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1// SPDX-License-Identifier: MIT
2/*
3 * Copyright 2019 Intel Corporation.
4 */
5
6#include "i915_drv.h"
7#include "intel_pch.h"
8
9/* Map PCH device id to PCH type, or PCH_NONE if unknown. */
10static enum intel_pch
11intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
12{
13 switch (id) {
14 case INTEL_PCH_IBX_DEVICE_ID_TYPE:
15 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
16 WARN_ON(!IS_GEN(dev_priv, 5));
17 return PCH_IBX;
18 case INTEL_PCH_CPT_DEVICE_ID_TYPE:
19 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
20 WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv));
21 return PCH_CPT;
22 case INTEL_PCH_PPT_DEVICE_ID_TYPE:
23 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
24 WARN_ON(!IS_GEN(dev_priv, 6) && !IS_IVYBRIDGE(dev_priv));
25 /* PantherPoint is CPT compatible */
26 return PCH_CPT;
27 case INTEL_PCH_LPT_DEVICE_ID_TYPE:
28 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
29 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
30 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
31 return PCH_LPT;
32 case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE:
33 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
34 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
35 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
36 return PCH_LPT;
37 case INTEL_PCH_WPT_DEVICE_ID_TYPE:
38 DRM_DEBUG_KMS("Found WildcatPoint PCH\n");
39 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
40 WARN_ON(IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
41 /* WildcatPoint is LPT compatible */
42 return PCH_LPT;
43 case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE:
44 DRM_DEBUG_KMS("Found WildcatPoint LP PCH\n");
45 WARN_ON(!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
46 WARN_ON(!IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
47 /* WildcatPoint is LPT compatible */
48 return PCH_LPT;
49 case INTEL_PCH_SPT_DEVICE_ID_TYPE:
50 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
51 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
52 return PCH_SPT;
53 case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE:
54 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
55 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
56 return PCH_SPT;
57 case INTEL_PCH_KBP_DEVICE_ID_TYPE:
58 DRM_DEBUG_KMS("Found Kaby Lake PCH (KBP)\n");
59 WARN_ON(!IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv) &&
60 !IS_COFFEELAKE(dev_priv));
61 /* KBP is SPT compatible */
62 return PCH_SPT;
63 case INTEL_PCH_CNP_DEVICE_ID_TYPE:
64 DRM_DEBUG_KMS("Found Cannon Lake PCH (CNP)\n");
65 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
66 return PCH_CNP;
67 case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE:
68 DRM_DEBUG_KMS("Found Cannon Lake LP PCH (CNP-LP)\n");
69 WARN_ON(!IS_CANNONLAKE(dev_priv) && !IS_COFFEELAKE(dev_priv));
70 return PCH_CNP;
71 case INTEL_PCH_CMP_DEVICE_ID_TYPE:
72 case INTEL_PCH_CMP2_DEVICE_ID_TYPE:
73 DRM_DEBUG_KMS("Found Comet Lake PCH (CMP)\n");
74 WARN_ON(!IS_COFFEELAKE(dev_priv));
75 /* CometPoint is CNP Compatible */
76 return PCH_CNP;
77 case INTEL_PCH_ICP_DEVICE_ID_TYPE:
78 DRM_DEBUG_KMS("Found Ice Lake PCH\n");
79 WARN_ON(!IS_ICELAKE(dev_priv));
80 return PCH_ICP;
81 case INTEL_PCH_MCC_DEVICE_ID_TYPE:
82 case INTEL_PCH_MCC2_DEVICE_ID_TYPE:
83 DRM_DEBUG_KMS("Found Mule Creek Canyon PCH\n");
84 WARN_ON(!IS_ELKHARTLAKE(dev_priv));
85 return PCH_MCC;
86 case INTEL_PCH_TGP_DEVICE_ID_TYPE:
87 DRM_DEBUG_KMS("Found Tiger Lake LP PCH\n");
88 WARN_ON(!IS_TIGERLAKE(dev_priv));
89 return PCH_TGP;
90 default:
91 return PCH_NONE;
92 }
93}
94
95static bool intel_is_virt_pch(unsigned short id,
96 unsigned short svendor, unsigned short sdevice)
97{
98 return (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
99 id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
100 (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
101 svendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
102 sdevice == PCI_SUBDEVICE_ID_QEMU));
103}
104
105static unsigned short
106intel_virt_detect_pch(const struct drm_i915_private *dev_priv)
107{
108 unsigned short id = 0;
109
110 /*
111 * In a virtualized passthrough environment we can be in a
112 * setup where the ISA bridge is not able to be passed through.
113 * In this case, a south bridge can be emulated and we have to
114 * make an educated guess as to which PCH is really there.
115 */
116
117 if (IS_TIGERLAKE(dev_priv))
118 id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
119 else if (IS_ELKHARTLAKE(dev_priv))
120 id = INTEL_PCH_MCC_DEVICE_ID_TYPE;
121 else if (IS_ICELAKE(dev_priv))
122 id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
123 else if (IS_CANNONLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
124 id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
125 else if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv))
126 id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
127 else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
128 id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
129 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
130 id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
131 else if (IS_GEN(dev_priv, 6) || IS_IVYBRIDGE(dev_priv))
132 id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
133 else if (IS_GEN(dev_priv, 5))
134 id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
135
136 if (id)
137 DRM_DEBUG_KMS("Assuming PCH ID %04x\n", id);
138 else
139 DRM_DEBUG_KMS("Assuming no PCH\n");
140
141 return id;
142}
143
144void intel_detect_pch(struct drm_i915_private *dev_priv)
145{
146 struct pci_dev *pch = NULL;
147
148 /*
149 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
150 * make graphics device passthrough work easy for VMM, that only
151 * need to expose ISA bridge to let driver know the real hardware
152 * underneath. This is a requirement from virtualization team.
153 *
154 * In some virtualized environments (e.g. XEN), there is irrelevant
155 * ISA bridge in the system. To work reliably, we should scan trhough
156 * all the ISA bridge devices and check for the first match, instead
157 * of only checking the first one.
158 */
159 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
160 unsigned short id;
161 enum intel_pch pch_type;
162
163 if (pch->vendor != PCI_VENDOR_ID_INTEL)
164 continue;
165
166 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
167
168 pch_type = intel_pch_type(dev_priv, id);
169 if (pch_type != PCH_NONE) {
170 dev_priv->pch_type = pch_type;
171 dev_priv->pch_id = id;
172 break;
173 } else if (intel_is_virt_pch(id, pch->subsystem_vendor,
174 pch->subsystem_device)) {
175 id = intel_virt_detect_pch(dev_priv);
176 pch_type = intel_pch_type(dev_priv, id);
177
178 /* Sanity check virtual PCH id */
179 if (WARN_ON(id && pch_type == PCH_NONE))
180 id = 0;
181
182 dev_priv->pch_type = pch_type;
183 dev_priv->pch_id = id;
184 break;
185 }
186 }
187
188 /*
189 * Use PCH_NOP (PCH but no South Display) for PCH platforms without
190 * display.
191 */
192 if (pch && !HAS_DISPLAY(dev_priv)) {
193 DRM_DEBUG_KMS("Display disabled, reverting to NOP PCH\n");
194 dev_priv->pch_type = PCH_NOP;
195 dev_priv->pch_id = 0;
196 }
197
198 if (!pch)
199 DRM_DEBUG_KMS("No PCH found.\n");
200
201 pci_dev_put(pch);
202}
1// SPDX-License-Identifier: MIT
2/*
3 * Copyright 2019 Intel Corporation.
4 */
5
6#include "i915_drv.h"
7#include "intel_pch.h"
8
9/* Map PCH device id to PCH type, or PCH_NONE if unknown. */
10static enum intel_pch
11intel_pch_type(const struct drm_i915_private *dev_priv, unsigned short id)
12{
13 switch (id) {
14 case INTEL_PCH_IBX_DEVICE_ID_TYPE:
15 drm_dbg_kms(&dev_priv->drm, "Found Ibex Peak PCH\n");
16 drm_WARN_ON(&dev_priv->drm, GRAPHICS_VER(dev_priv) != 5);
17 return PCH_IBX;
18 case INTEL_PCH_CPT_DEVICE_ID_TYPE:
19 drm_dbg_kms(&dev_priv->drm, "Found CougarPoint PCH\n");
20 drm_WARN_ON(&dev_priv->drm,
21 GRAPHICS_VER(dev_priv) != 6 && !IS_IVYBRIDGE(dev_priv));
22 return PCH_CPT;
23 case INTEL_PCH_PPT_DEVICE_ID_TYPE:
24 drm_dbg_kms(&dev_priv->drm, "Found PantherPoint PCH\n");
25 drm_WARN_ON(&dev_priv->drm,
26 GRAPHICS_VER(dev_priv) != 6 && !IS_IVYBRIDGE(dev_priv));
27 /* PantherPoint is CPT compatible */
28 return PCH_CPT;
29 case INTEL_PCH_LPT_DEVICE_ID_TYPE:
30 drm_dbg_kms(&dev_priv->drm, "Found LynxPoint PCH\n");
31 drm_WARN_ON(&dev_priv->drm,
32 !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
33 drm_WARN_ON(&dev_priv->drm,
34 IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
35 return PCH_LPT;
36 case INTEL_PCH_LPT_LP_DEVICE_ID_TYPE:
37 drm_dbg_kms(&dev_priv->drm, "Found LynxPoint LP PCH\n");
38 drm_WARN_ON(&dev_priv->drm,
39 !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
40 drm_WARN_ON(&dev_priv->drm,
41 !IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
42 return PCH_LPT;
43 case INTEL_PCH_WPT_DEVICE_ID_TYPE:
44 drm_dbg_kms(&dev_priv->drm, "Found WildcatPoint PCH\n");
45 drm_WARN_ON(&dev_priv->drm,
46 !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
47 drm_WARN_ON(&dev_priv->drm,
48 IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv));
49 /* WildcatPoint is LPT compatible */
50 return PCH_LPT;
51 case INTEL_PCH_WPT_LP_DEVICE_ID_TYPE:
52 drm_dbg_kms(&dev_priv->drm, "Found WildcatPoint LP PCH\n");
53 drm_WARN_ON(&dev_priv->drm,
54 !IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv));
55 drm_WARN_ON(&dev_priv->drm,
56 !IS_HSW_ULT(dev_priv) && !IS_BDW_ULT(dev_priv));
57 /* WildcatPoint is LPT compatible */
58 return PCH_LPT;
59 case INTEL_PCH_SPT_DEVICE_ID_TYPE:
60 drm_dbg_kms(&dev_priv->drm, "Found SunrisePoint PCH\n");
61 drm_WARN_ON(&dev_priv->drm,
62 !IS_SKYLAKE(dev_priv) && !IS_KABYLAKE(dev_priv));
63 return PCH_SPT;
64 case INTEL_PCH_SPT_LP_DEVICE_ID_TYPE:
65 drm_dbg_kms(&dev_priv->drm, "Found SunrisePoint LP PCH\n");
66 drm_WARN_ON(&dev_priv->drm,
67 !IS_SKYLAKE(dev_priv) &&
68 !IS_KABYLAKE(dev_priv) &&
69 !IS_COFFEELAKE(dev_priv) &&
70 !IS_COMETLAKE(dev_priv));
71 return PCH_SPT;
72 case INTEL_PCH_KBP_DEVICE_ID_TYPE:
73 drm_dbg_kms(&dev_priv->drm, "Found Kaby Lake PCH (KBP)\n");
74 drm_WARN_ON(&dev_priv->drm,
75 !IS_SKYLAKE(dev_priv) &&
76 !IS_KABYLAKE(dev_priv) &&
77 !IS_COFFEELAKE(dev_priv) &&
78 !IS_COMETLAKE(dev_priv));
79 /* KBP is SPT compatible */
80 return PCH_SPT;
81 case INTEL_PCH_CNP_DEVICE_ID_TYPE:
82 drm_dbg_kms(&dev_priv->drm, "Found Cannon Lake PCH (CNP)\n");
83 drm_WARN_ON(&dev_priv->drm,
84 !IS_CANNONLAKE(dev_priv) &&
85 !IS_COFFEELAKE(dev_priv) &&
86 !IS_COMETLAKE(dev_priv));
87 return PCH_CNP;
88 case INTEL_PCH_CNP_LP_DEVICE_ID_TYPE:
89 drm_dbg_kms(&dev_priv->drm,
90 "Found Cannon Lake LP PCH (CNP-LP)\n");
91 drm_WARN_ON(&dev_priv->drm,
92 !IS_CANNONLAKE(dev_priv) &&
93 !IS_COFFEELAKE(dev_priv) &&
94 !IS_COMETLAKE(dev_priv));
95 return PCH_CNP;
96 case INTEL_PCH_CMP_DEVICE_ID_TYPE:
97 case INTEL_PCH_CMP2_DEVICE_ID_TYPE:
98 drm_dbg_kms(&dev_priv->drm, "Found Comet Lake PCH (CMP)\n");
99 drm_WARN_ON(&dev_priv->drm,
100 !IS_COFFEELAKE(dev_priv) &&
101 !IS_COMETLAKE(dev_priv) &&
102 !IS_ROCKETLAKE(dev_priv));
103 /* CometPoint is CNP Compatible */
104 return PCH_CNP;
105 case INTEL_PCH_CMP_V_DEVICE_ID_TYPE:
106 drm_dbg_kms(&dev_priv->drm, "Found Comet Lake V PCH (CMP-V)\n");
107 drm_WARN_ON(&dev_priv->drm,
108 !IS_COFFEELAKE(dev_priv) &&
109 !IS_COMETLAKE(dev_priv));
110 /* Comet Lake V PCH is based on KBP, which is SPT compatible */
111 return PCH_SPT;
112 case INTEL_PCH_ICP_DEVICE_ID_TYPE:
113 drm_dbg_kms(&dev_priv->drm, "Found Ice Lake PCH\n");
114 drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv));
115 return PCH_ICP;
116 case INTEL_PCH_MCC_DEVICE_ID_TYPE:
117 drm_dbg_kms(&dev_priv->drm, "Found Mule Creek Canyon PCH\n");
118 drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
119 return PCH_MCC;
120 case INTEL_PCH_TGP_DEVICE_ID_TYPE:
121 case INTEL_PCH_TGP2_DEVICE_ID_TYPE:
122 drm_dbg_kms(&dev_priv->drm, "Found Tiger Lake LP PCH\n");
123 drm_WARN_ON(&dev_priv->drm, !IS_TIGERLAKE(dev_priv) &&
124 !IS_ROCKETLAKE(dev_priv) &&
125 !IS_GEN9_BC(dev_priv));
126 return PCH_TGP;
127 case INTEL_PCH_JSP_DEVICE_ID_TYPE:
128 case INTEL_PCH_JSP2_DEVICE_ID_TYPE:
129 drm_dbg_kms(&dev_priv->drm, "Found Jasper Lake PCH\n");
130 drm_WARN_ON(&dev_priv->drm, !IS_JSL_EHL(dev_priv));
131 return PCH_JSP;
132 case INTEL_PCH_ADP_DEVICE_ID_TYPE:
133 case INTEL_PCH_ADP2_DEVICE_ID_TYPE:
134 drm_dbg_kms(&dev_priv->drm, "Found Alder Lake PCH\n");
135 drm_WARN_ON(&dev_priv->drm, !IS_ALDERLAKE_S(dev_priv) &&
136 !IS_ALDERLAKE_P(dev_priv));
137 return PCH_ADP;
138 default:
139 return PCH_NONE;
140 }
141}
142
143static bool intel_is_virt_pch(unsigned short id,
144 unsigned short svendor, unsigned short sdevice)
145{
146 return (id == INTEL_PCH_P2X_DEVICE_ID_TYPE ||
147 id == INTEL_PCH_P3X_DEVICE_ID_TYPE ||
148 (id == INTEL_PCH_QEMU_DEVICE_ID_TYPE &&
149 svendor == PCI_SUBVENDOR_ID_REDHAT_QUMRANET &&
150 sdevice == PCI_SUBDEVICE_ID_QEMU));
151}
152
153static void
154intel_virt_detect_pch(const struct drm_i915_private *dev_priv,
155 unsigned short *pch_id, enum intel_pch *pch_type)
156{
157 unsigned short id = 0;
158
159 /*
160 * In a virtualized passthrough environment we can be in a
161 * setup where the ISA bridge is not able to be passed through.
162 * In this case, a south bridge can be emulated and we have to
163 * make an educated guess as to which PCH is really there.
164 */
165
166 if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv))
167 id = INTEL_PCH_ADP_DEVICE_ID_TYPE;
168 else if (IS_TIGERLAKE(dev_priv) || IS_ROCKETLAKE(dev_priv))
169 id = INTEL_PCH_TGP_DEVICE_ID_TYPE;
170 else if (IS_JSL_EHL(dev_priv))
171 id = INTEL_PCH_MCC_DEVICE_ID_TYPE;
172 else if (IS_ICELAKE(dev_priv))
173 id = INTEL_PCH_ICP_DEVICE_ID_TYPE;
174 else if (IS_CANNONLAKE(dev_priv) ||
175 IS_COFFEELAKE(dev_priv) ||
176 IS_COMETLAKE(dev_priv))
177 id = INTEL_PCH_CNP_DEVICE_ID_TYPE;
178 else if (IS_KABYLAKE(dev_priv) || IS_SKYLAKE(dev_priv))
179 id = INTEL_PCH_SPT_DEVICE_ID_TYPE;
180 else if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
181 id = INTEL_PCH_LPT_LP_DEVICE_ID_TYPE;
182 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
183 id = INTEL_PCH_LPT_DEVICE_ID_TYPE;
184 else if (GRAPHICS_VER(dev_priv) == 6 || IS_IVYBRIDGE(dev_priv))
185 id = INTEL_PCH_CPT_DEVICE_ID_TYPE;
186 else if (GRAPHICS_VER(dev_priv) == 5)
187 id = INTEL_PCH_IBX_DEVICE_ID_TYPE;
188
189 if (id)
190 drm_dbg_kms(&dev_priv->drm, "Assuming PCH ID %04x\n", id);
191 else
192 drm_dbg_kms(&dev_priv->drm, "Assuming no PCH\n");
193
194 *pch_type = intel_pch_type(dev_priv, id);
195
196 /* Sanity check virtual PCH id */
197 if (drm_WARN_ON(&dev_priv->drm,
198 id && *pch_type == PCH_NONE))
199 id = 0;
200
201 *pch_id = id;
202}
203
204void intel_detect_pch(struct drm_i915_private *dev_priv)
205{
206 struct pci_dev *pch = NULL;
207 unsigned short id;
208 enum intel_pch pch_type;
209
210 /* DG1 has south engine display on the same PCI device */
211 if (IS_DG1(dev_priv)) {
212 dev_priv->pch_type = PCH_DG1;
213 return;
214 }
215
216 /*
217 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
218 * make graphics device passthrough work easy for VMM, that only
219 * need to expose ISA bridge to let driver know the real hardware
220 * underneath. This is a requirement from virtualization team.
221 *
222 * In some virtualized environments (e.g. XEN), there is irrelevant
223 * ISA bridge in the system. To work reliably, we should scan trhough
224 * all the ISA bridge devices and check for the first match, instead
225 * of only checking the first one.
226 */
227 while ((pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, pch))) {
228 if (pch->vendor != PCI_VENDOR_ID_INTEL)
229 continue;
230
231 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
232
233 pch_type = intel_pch_type(dev_priv, id);
234 if (pch_type != PCH_NONE) {
235 dev_priv->pch_type = pch_type;
236 dev_priv->pch_id = id;
237 break;
238 } else if (intel_is_virt_pch(id, pch->subsystem_vendor,
239 pch->subsystem_device)) {
240 intel_virt_detect_pch(dev_priv, &id, &pch_type);
241 dev_priv->pch_type = pch_type;
242 dev_priv->pch_id = id;
243 break;
244 }
245 }
246
247 /*
248 * Use PCH_NOP (PCH but no South Display) for PCH platforms without
249 * display.
250 */
251 if (pch && !HAS_DISPLAY(dev_priv)) {
252 drm_dbg_kms(&dev_priv->drm,
253 "Display disabled, reverting to NOP PCH\n");
254 dev_priv->pch_type = PCH_NOP;
255 dev_priv->pch_id = 0;
256 } else if (!pch) {
257 if (run_as_guest() && HAS_DISPLAY(dev_priv)) {
258 intel_virt_detect_pch(dev_priv, &id, &pch_type);
259 dev_priv->pch_type = pch_type;
260 dev_priv->pch_id = id;
261 } else {
262 drm_dbg_kms(&dev_priv->drm, "No PCH found.\n");
263 }
264 }
265
266 pci_dev_put(pch);
267}