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1#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
2#ifndef DC_DSC_H_
3#define DC_DSC_H_
4/*
5 * Copyright 2019 Advanced Micro Devices, Inc.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
23 * OTHER DEALINGS IN THE SOFTWARE.
24 *
25 * Author: AMD
26 */
27
28/* put it here temporarily until linux has the new addresses official defined */
29/* DP Extended DSC Capabilities */
30#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0 0x0a0 /* DP 1.4a SCR */
31#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1
32#define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2
33
34struct dc_dsc_bw_range {
35 uint32_t min_kbps; /* Bandwidth if min_target_bpp_x16 is used */
36 uint32_t min_target_bpp_x16;
37 uint32_t max_kbps; /* Bandwidth if max_target_bpp_x16 is used */
38 uint32_t max_target_bpp_x16;
39 uint32_t stream_kbps; /* Uncompressed stream bandwidth */
40};
41
42
43bool dc_dsc_parse_dsc_dpcd(const uint8_t *dpcd_dsc_basic_data,
44 const uint8_t *dpcd_dsc_ext_data,
45 struct dsc_dec_dpcd_caps *dsc_sink_caps);
46
47bool dc_dsc_compute_bandwidth_range(
48 const struct dc *dc,
49 const uint32_t min_kbps,
50 const uint32_t max_kbps,
51 const struct dsc_dec_dpcd_caps *dsc_sink_caps,
52 const struct dc_crtc_timing *timing,
53 struct dc_dsc_bw_range *range);
54
55bool dc_dsc_compute_config(
56 const struct dc *dc,
57 const struct dsc_dec_dpcd_caps *dsc_sink_caps,
58 uint32_t target_bandwidth_kbps,
59 const struct dc_crtc_timing *timing,
60 struct dc_dsc_config *dsc_cfg);
61#endif
62#endif
1#ifndef DC_DSC_H_
2#define DC_DSC_H_
3/*
4 * Copyright 2019 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Author: AMD
25 */
26
27/* put it here temporarily until linux has the new addresses official defined */
28/* DP Extended DSC Capabilities */
29#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_0 0x0a0 /* DP 1.4a SCR */
30#define DP_DSC_BRANCH_OVERALL_THROUGHPUT_1 0x0a1
31#define DP_DSC_BRANCH_MAX_LINE_WIDTH 0x0a2
32#include "dc_types.h"
33
34struct dc_dsc_bw_range {
35 uint32_t min_kbps; /* Bandwidth if min_target_bpp_x16 is used */
36 uint32_t min_target_bpp_x16;
37 uint32_t max_kbps; /* Bandwidth if max_target_bpp_x16 is used */
38 uint32_t max_target_bpp_x16;
39 uint32_t stream_kbps; /* Uncompressed stream bandwidth */
40};
41
42struct display_stream_compressor {
43 const struct dsc_funcs *funcs;
44 struct dc_context *ctx;
45 int inst;
46};
47
48struct dc_dsc_policy {
49 bool use_min_slices_h;
50 int max_slices_h; // Maximum available if 0
51 int min_slice_height; // Must not be less than 8
52 uint32_t max_target_bpp;
53 uint32_t min_target_bpp;
54 uint32_t preferred_bpp_x16;
55 bool enable_dsc_when_not_needed;
56};
57
58bool dc_dsc_parse_dsc_dpcd(const struct dc *dc,
59 const uint8_t *dpcd_dsc_basic_data,
60 const uint8_t *dpcd_dsc_ext_data,
61 struct dsc_dec_dpcd_caps *dsc_sink_caps);
62
63bool dc_dsc_compute_bandwidth_range(
64 const struct display_stream_compressor *dsc,
65 uint32_t dsc_min_slice_height_override,
66 uint32_t min_bpp_x16,
67 uint32_t max_bpp_x16,
68 const struct dsc_dec_dpcd_caps *dsc_sink_caps,
69 const struct dc_crtc_timing *timing,
70 struct dc_dsc_bw_range *range);
71
72bool dc_dsc_compute_config(
73 const struct display_stream_compressor *dsc,
74 const struct dsc_dec_dpcd_caps *dsc_sink_caps,
75 uint32_t dsc_min_slice_height_override,
76 uint32_t max_target_bpp_limit_override,
77 uint32_t target_bandwidth_kbps,
78 const struct dc_crtc_timing *timing,
79 struct dc_dsc_config *dsc_cfg);
80
81uint32_t dc_dsc_stream_bandwidth_in_kbps(const struct dc_crtc_timing *timing,
82 uint32_t bpp_x16, uint32_t num_slices_h, bool is_dp);
83
84void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing,
85 uint32_t max_target_bpp_limit_override_x16,
86 struct dc_dsc_policy *policy);
87
88void dc_dsc_policy_set_max_target_bpp_limit(uint32_t limit);
89
90void dc_dsc_policy_set_enable_dsc_when_not_needed(bool enable);
91
92void dc_dsc_policy_set_disable_dsc_stream_overhead(bool disable);
93
94#endif