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v5.4
  1/*
  2 * Copyright 2019 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * based on nouveau_prime.c
 23 *
 24 * Authors: Alex Deucher
 25 */
 26
 27/**
 28 * DOC: PRIME Buffer Sharing
 29 *
 30 * The following callback implementations are used for :ref:`sharing GEM buffer
 31 * objects between different devices via PRIME <prime_buffer_sharing>`.
 32 */
 33
 34#include "amdgpu.h"
 35#include "amdgpu_display.h"
 36#include "amdgpu_gem.h"
 
 
 37#include <drm/amdgpu_drm.h>
 38#include <linux/dma-buf.h>
 39#include <linux/dma-fence-array.h>
 40
 41/**
 42 * amdgpu_gem_prime_get_sg_table - &drm_driver.gem_prime_get_sg_table
 43 * implementation
 44 * @obj: GEM buffer object (BO)
 45 *
 46 * Returns:
 47 * A scatter/gather table for the pinned pages of the BO's memory.
 48 */
 49struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj)
 50{
 51	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
 52	int npages = bo->tbo.num_pages;
 53
 54	return drm_prime_pages_to_sg(bo->tbo.ttm->pages, npages);
 55}
 56
 57/**
 58 * amdgpu_gem_prime_vmap - &dma_buf_ops.vmap implementation
 59 * @obj: GEM BO
 60 *
 61 * Sets up an in-kernel virtual mapping of the BO's memory.
 62 *
 63 * Returns:
 64 * The virtual address of the mapping or an error pointer.
 65 */
 66void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj)
 67{
 68	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
 69	int ret;
 70
 71	ret = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages,
 72			  &bo->dma_buf_vmap);
 73	if (ret)
 74		return ERR_PTR(ret);
 75
 76	return bo->dma_buf_vmap.virtual;
 77}
 78
 79/**
 80 * amdgpu_gem_prime_vunmap - &dma_buf_ops.vunmap implementation
 81 * @obj: GEM BO
 82 * @vaddr: Virtual address (unused)
 83 *
 84 * Tears down the in-kernel virtual mapping of the BO's memory.
 85 */
 86void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr)
 87{
 88	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
 89
 90	ttm_bo_kunmap(&bo->dma_buf_vmap);
 91}
 92
 93/**
 94 * amdgpu_gem_prime_mmap - &drm_driver.gem_prime_mmap implementation
 95 * @obj: GEM BO
 96 * @vma: Virtual memory area
 97 *
 98 * Sets up a userspace mapping of the BO's memory in the given
 99 * virtual memory area.
100 *
101 * Returns:
102 * 0 on success or a negative error code on failure.
103 */
104int amdgpu_gem_prime_mmap(struct drm_gem_object *obj,
105			  struct vm_area_struct *vma)
106{
107	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
108	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
109	unsigned asize = amdgpu_bo_size(bo);
110	int ret;
111
112	if (!vma->vm_file)
113		return -ENODEV;
114
115	if (adev == NULL)
116		return -ENODEV;
117
118	/* Check for valid size. */
119	if (asize < vma->vm_end - vma->vm_start)
120		return -EINVAL;
121
122	if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
123	    (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) {
124		return -EPERM;
125	}
126	vma->vm_pgoff += amdgpu_bo_mmap_offset(bo) >> PAGE_SHIFT;
127
128	/* prime mmap does not need to check access, so allow here */
129	ret = drm_vma_node_allow(&obj->vma_node, vma->vm_file->private_data);
130	if (ret)
131		return ret;
132
133	ret = ttm_bo_mmap(vma->vm_file, vma, &adev->mman.bdev);
134	drm_vma_node_revoke(&obj->vma_node, vma->vm_file->private_data);
135
136	return ret;
137}
138
139static int
140__dma_resv_make_exclusive(struct dma_resv *obj)
141{
142	struct dma_fence **fences;
143	unsigned int count;
144	int r;
145
146	if (!dma_resv_get_list(obj)) /* no shared fences to convert */
147		return 0;
148
149	r = dma_resv_get_fences_rcu(obj, NULL, &count, &fences);
150	if (r)
151		return r;
152
153	if (count == 0) {
154		/* Now that was unexpected. */
155	} else if (count == 1) {
156		dma_resv_add_excl_fence(obj, fences[0]);
157		dma_fence_put(fences[0]);
158		kfree(fences);
159	} else {
160		struct dma_fence_array *array;
161
162		array = dma_fence_array_create(count, fences,
163					       dma_fence_context_alloc(1), 0,
164					       false);
165		if (!array)
166			goto err_fences_put;
167
168		dma_resv_add_excl_fence(obj, &array->base);
169		dma_fence_put(&array->base);
170	}
171
172	return 0;
173
174err_fences_put:
175	while (count--)
176		dma_fence_put(fences[count]);
177	kfree(fences);
178	return -ENOMEM;
179}
180
181/**
182 * amdgpu_dma_buf_map_attach - &dma_buf_ops.attach implementation
183 * @dma_buf: Shared DMA buffer
184 * @attach: DMA-buf attachment
185 *
186 * Makes sure that the shared DMA buffer can be accessed by the target device.
187 * For now, simply pins it to the GTT domain, where it should be accessible by
188 * all DMA devices.
189 *
190 * Returns:
191 * 0 on success or a negative error code on failure.
192 */
193static int amdgpu_dma_buf_map_attach(struct dma_buf *dma_buf,
194				     struct dma_buf_attachment *attach)
195{
196	struct drm_gem_object *obj = dma_buf->priv;
197	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
198	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
199	long r;
200
201	r = drm_gem_map_attach(dma_buf, attach);
202	if (r)
203		return r;
 
 
 
 
 
 
204
205	r = amdgpu_bo_reserve(bo, false);
206	if (unlikely(r != 0))
207		goto error_detach;
208
 
 
 
 
 
 
 
 
 
 
 
209
210	if (attach->dev->driver != adev->dev->driver) {
211		/*
212		 * We only create shared fences for internal use, but importers
213		 * of the dmabuf rely on exclusive fences for implicitly
214		 * tracking write hazards. As any of the current fences may
215		 * correspond to a write, we need to convert all existing
216		 * fences on the reservation object into a single exclusive
217		 * fence.
218		 */
219		r = __dma_resv_make_exclusive(bo->tbo.base.resv);
220		if (r)
221			goto error_unreserve;
222	}
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
223
224	/* pin buffer into GTT */
225	r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
226	if (r)
227		goto error_unreserve;
228
229	if (attach->dev->driver != adev->dev->driver)
230		bo->prime_shared_count++;
 
 
 
 
 
 
 
231
232error_unreserve:
233	amdgpu_bo_unreserve(bo);
 
 
 
 
 
 
 
 
 
234
235error_detach:
236	if (r)
237		drm_gem_map_detach(dma_buf, attach);
238	return r;
239}
240
241/**
242 * amdgpu_dma_buf_map_detach - &dma_buf_ops.detach implementation
243 * @dma_buf: Shared DMA buffer
244 * @attach: DMA-buf attachment
 
245 *
246 * This is called when a shared DMA buffer no longer needs to be accessible by
247 * another device. For now, simply unpins the buffer from GTT.
 
 
 
 
 
248 */
249static void amdgpu_dma_buf_map_detach(struct dma_buf *dma_buf,
250				      struct dma_buf_attachment *attach)
251{
 
252	struct drm_gem_object *obj = dma_buf->priv;
253	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
254	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
255	int ret = 0;
 
256
257	ret = amdgpu_bo_reserve(bo, true);
258	if (unlikely(ret != 0))
259		goto error;
 
 
 
 
 
 
 
 
 
 
 
260
261	amdgpu_bo_unpin(bo);
262	if (attach->dev->driver != adev->dev->driver && bo->prime_shared_count)
263		bo->prime_shared_count--;
264	amdgpu_bo_unreserve(bo);
265
266error:
267	drm_gem_map_detach(dma_buf, attach);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
268}
269
270/**
271 * amdgpu_dma_buf_begin_cpu_access - &dma_buf_ops.begin_cpu_access implementation
272 * @dma_buf: Shared DMA buffer
273 * @direction: Direction of DMA transfer
274 *
275 * This is called before CPU access to the shared DMA buffer's memory. If it's
276 * a read access, the buffer is moved to the GTT domain if possible, for optimal
277 * CPU read performance.
278 *
279 * Returns:
280 * 0 on success or a negative error code on failure.
281 */
282static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf,
283					   enum dma_data_direction direction)
284{
285	struct amdgpu_bo *bo = gem_to_amdgpu_bo(dma_buf->priv);
286	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
287	struct ttm_operation_ctx ctx = { true, false };
288	u32 domain = amdgpu_display_supported_domains(adev, bo->flags);
289	int ret;
290	bool reads = (direction == DMA_BIDIRECTIONAL ||
291		      direction == DMA_FROM_DEVICE);
292
293	if (!reads || !(domain & AMDGPU_GEM_DOMAIN_GTT))
294		return 0;
295
296	/* move to gtt */
297	ret = amdgpu_bo_reserve(bo, false);
298	if (unlikely(ret != 0))
299		return ret;
300
301	if (!bo->pin_count && (bo->allowed_domains & AMDGPU_GEM_DOMAIN_GTT)) {
 
302		amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
303		ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
304	}
305
306	amdgpu_bo_unreserve(bo);
307	return ret;
308}
309
310const struct dma_buf_ops amdgpu_dmabuf_ops = {
311	.attach = amdgpu_dma_buf_map_attach,
312	.detach = amdgpu_dma_buf_map_detach,
313	.map_dma_buf = drm_gem_map_dma_buf,
314	.unmap_dma_buf = drm_gem_unmap_dma_buf,
 
 
315	.release = drm_gem_dmabuf_release,
316	.begin_cpu_access = amdgpu_dma_buf_begin_cpu_access,
317	.mmap = drm_gem_dmabuf_mmap,
318	.vmap = drm_gem_dmabuf_vmap,
319	.vunmap = drm_gem_dmabuf_vunmap,
320};
321
322/**
323 * amdgpu_gem_prime_export - &drm_driver.gem_prime_export implementation
324 * @dev: DRM device
325 * @gobj: GEM BO
326 * @flags: Flags such as DRM_CLOEXEC and DRM_RDWR.
327 *
328 * The main work is done by the &drm_gem_prime_export helper.
329 *
330 * Returns:
331 * Shared DMA buffer representing the GEM BO from the given device.
332 */
333struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj,
334					int flags)
335{
336	struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
337	struct dma_buf *buf;
338
339	if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
340	    bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
341		return ERR_PTR(-EPERM);
342
343	buf = drm_gem_prime_export(gobj, flags);
344	if (!IS_ERR(buf)) {
345		buf->file->f_mapping = gobj->dev->anon_inode->i_mapping;
346		buf->ops = &amdgpu_dmabuf_ops;
347	}
348
349	return buf;
350}
351
352/**
353 * amdgpu_gem_prime_import_sg_table - &drm_driver.gem_prime_import_sg_table
354 * implementation
355 * @dev: DRM device
356 * @attach: DMA-buf attachment
357 * @sg: Scatter/gather table
358 *
359 * Imports shared DMA buffer memory exported by another device.
360 *
361 * Returns:
362 * A new GEM BO of the given DRM device, representing the memory
363 * described by the given DMA-buf attachment and scatter/gather table.
364 */
365struct drm_gem_object *
366amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
367				 struct dma_buf_attachment *attach,
368				 struct sg_table *sg)
369{
370	struct dma_resv *resv = attach->dmabuf->resv;
371	struct amdgpu_device *adev = dev->dev_private;
 
372	struct amdgpu_bo *bo;
373	struct amdgpu_bo_param bp;
374	int ret;
375
376	memset(&bp, 0, sizeof(bp));
377	bp.size = attach->dmabuf->size;
378	bp.byte_align = PAGE_SIZE;
379	bp.domain = AMDGPU_GEM_DOMAIN_CPU;
380	bp.flags = 0;
381	bp.type = ttm_bo_type_sg;
382	bp.resv = resv;
383	dma_resv_lock(resv, NULL);
384	ret = amdgpu_bo_create(adev, &bp, &bo);
 
 
 
 
 
 
 
 
 
385	if (ret)
386		goto error;
387
388	bo->tbo.sg = sg;
389	bo->tbo.ttm->sg = sg;
390	bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
391	bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
392	if (attach->dmabuf->ops != &amdgpu_dmabuf_ops)
393		bo->prime_shared_count = 1;
394
395	dma_resv_unlock(resv);
396	return &bo->tbo.base;
397
398error:
399	dma_resv_unlock(resv);
400	return ERR_PTR(ret);
401}
402
403/**
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
404 * amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation
405 * @dev: DRM device
406 * @dma_buf: Shared DMA buffer
407 *
408 * The main work is done by the &drm_gem_prime_import helper, which in turn
409 * uses &amdgpu_gem_prime_import_sg_table.
410 *
411 * Returns:
412 * GEM BO representing the shared DMA buffer for the given device.
413 */
414struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev,
415					    struct dma_buf *dma_buf)
416{
 
417	struct drm_gem_object *obj;
418
419	if (dma_buf->ops == &amdgpu_dmabuf_ops) {
420		obj = dma_buf->priv;
421		if (obj->dev == dev) {
422			/*
423			 * Importing dmabuf exported from out own gem increases
424			 * refcount on gem itself instead of f_count of dmabuf.
425			 */
426			drm_gem_object_get(obj);
427			return obj;
428		}
429	}
430
431	return drm_gem_prime_import(dev, dma_buf);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
432}
v5.14.15
  1/*
  2 * Copyright 2019 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * based on nouveau_prime.c
 23 *
 24 * Authors: Alex Deucher
 25 */
 26
 27/**
 28 * DOC: PRIME Buffer Sharing
 29 *
 30 * The following callback implementations are used for :ref:`sharing GEM buffer
 31 * objects between different devices via PRIME <prime_buffer_sharing>`.
 32 */
 33
 34#include "amdgpu.h"
 35#include "amdgpu_display.h"
 36#include "amdgpu_gem.h"
 37#include "amdgpu_dma_buf.h"
 38#include "amdgpu_xgmi.h"
 39#include <drm/amdgpu_drm.h>
 40#include <linux/dma-buf.h>
 41#include <linux/dma-fence-array.h>
 42#include <linux/pci-p2pdma.h>
 43#include <linux/pm_runtime.h>
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 44
 45static int
 46__dma_resv_make_exclusive(struct dma_resv *obj)
 47{
 48	struct dma_fence **fences;
 49	unsigned int count;
 50	int r;
 51
 52	if (!dma_resv_shared_list(obj)) /* no shared fences to convert */
 53		return 0;
 54
 55	r = dma_resv_get_fences(obj, NULL, &count, &fences);
 56	if (r)
 57		return r;
 58
 59	if (count == 0) {
 60		/* Now that was unexpected. */
 61	} else if (count == 1) {
 62		dma_resv_add_excl_fence(obj, fences[0]);
 63		dma_fence_put(fences[0]);
 64		kfree(fences);
 65	} else {
 66		struct dma_fence_array *array;
 67
 68		array = dma_fence_array_create(count, fences,
 69					       dma_fence_context_alloc(1), 0,
 70					       false);
 71		if (!array)
 72			goto err_fences_put;
 73
 74		dma_resv_add_excl_fence(obj, &array->base);
 75		dma_fence_put(&array->base);
 76	}
 77
 78	return 0;
 79
 80err_fences_put:
 81	while (count--)
 82		dma_fence_put(fences[count]);
 83	kfree(fences);
 84	return -ENOMEM;
 85}
 86
 87/**
 88 * amdgpu_dma_buf_attach - &dma_buf_ops.attach implementation
 
 
 89 *
 90 * @dmabuf: DMA-buf where we attach to
 91 * @attach: attachment to add
 
 92 *
 93 * Add the attachment as user to the exported DMA-buf.
 
 94 */
 95static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf,
 96				 struct dma_buf_attachment *attach)
 97{
 98	struct drm_gem_object *obj = dmabuf->priv;
 99	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
100	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
101	int r;
102
103	if (pci_p2pdma_distance_many(adev->pdev, &attach->dev, 1, true) < 0)
104		attach->peer2peer = false;
105
106	if (attach->dev->driver == adev->dev->driver)
107		return 0;
108
109	r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
110	if (r < 0)
111		goto out;
112
113	r = amdgpu_bo_reserve(bo, false);
114	if (unlikely(r != 0))
115		goto out;
116
117	/*
118	 * We only create shared fences for internal use, but importers
119	 * of the dmabuf rely on exclusive fences for implicitly
120	 * tracking write hazards. As any of the current fences may
121	 * correspond to a write, we need to convert all existing
122	 * fences on the reservation object into a single exclusive
123	 * fence.
124	 */
125	r = __dma_resv_make_exclusive(bo->tbo.base.resv);
126	if (r)
127		goto out;
128
129	bo->prime_shared_count++;
130	amdgpu_bo_unreserve(bo);
131	return 0;
132
133out:
134	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
135	return r;
136}
137
138/**
139 * amdgpu_dma_buf_detach - &dma_buf_ops.detach implementation
140 *
141 * @dmabuf: DMA-buf where we remove the attachment from
142 * @attach: the attachment to remove
143 *
144 * Called when an attachment is removed from the DMA-buf.
145 */
146static void amdgpu_dma_buf_detach(struct dma_buf *dmabuf,
147				  struct dma_buf_attachment *attach)
148{
149	struct drm_gem_object *obj = dmabuf->priv;
150	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
151	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
152
153	if (attach->dev->driver != adev->dev->driver && bo->prime_shared_count)
154		bo->prime_shared_count--;
155
156	pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
157	pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
158}
159
160/**
161 * amdgpu_dma_buf_pin - &dma_buf_ops.pin implementation
162 *
163 * @attach: attachment to pin down
164 *
165 * Pin the BO which is backing the DMA-buf so that it can't move any more.
166 */
167static int amdgpu_dma_buf_pin(struct dma_buf_attachment *attach)
168{
169	struct drm_gem_object *obj = attach->dmabuf->priv;
170	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
171	int r;
172
173	/* pin buffer into GTT */
174	r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
175	if (r)
176		return r;
177
178	if (bo->tbo.moving) {
179		r = dma_fence_wait(bo->tbo.moving, true);
180		if (r) {
181			amdgpu_bo_unpin(bo);
182			return r;
183		}
184	}
185	return 0;
186}
187
188/**
189 * amdgpu_dma_buf_unpin - &dma_buf_ops.unpin implementation
190 *
191 * @attach: attachment to unpin
192 *
193 * Unpin a previously pinned BO to make it movable again.
194 */
195static void amdgpu_dma_buf_unpin(struct dma_buf_attachment *attach)
196{
197	struct drm_gem_object *obj = attach->dmabuf->priv;
198	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
199
200	amdgpu_bo_unpin(bo);
 
 
 
201}
202
203/**
204 * amdgpu_dma_buf_map - &dma_buf_ops.map_dma_buf implementation
 
205 * @attach: DMA-buf attachment
206 * @dir: DMA direction
207 *
208 * Makes sure that the shared DMA buffer can be accessed by the target device.
209 * For now, simply pins it to the GTT domain, where it should be accessible by
210 * all DMA devices.
211 *
212 * Returns:
213 * sg_table filled with the DMA addresses to use or ERR_PRT with negative error
214 * code.
215 */
216static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach,
217					   enum dma_data_direction dir)
218{
219	struct dma_buf *dma_buf = attach->dmabuf;
220	struct drm_gem_object *obj = dma_buf->priv;
221	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
222	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
223	struct sg_table *sgt;
224	long r;
225
226	if (!bo->tbo.pin_count) {
227		/* move buffer into GTT or VRAM */
228		struct ttm_operation_ctx ctx = { false, false };
229		unsigned domains = AMDGPU_GEM_DOMAIN_GTT;
230
231		if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM &&
232		    attach->peer2peer) {
233			bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
234			domains |= AMDGPU_GEM_DOMAIN_VRAM;
235		}
236		amdgpu_bo_placement_from_domain(bo, domains);
237		r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
238		if (r)
239			return ERR_PTR(r);
240
241	} else if (!(amdgpu_mem_type_to_domain(bo->tbo.resource->mem_type) &
242		     AMDGPU_GEM_DOMAIN_GTT)) {
243		return ERR_PTR(-EBUSY);
244	}
245
246	switch (bo->tbo.resource->mem_type) {
247	case TTM_PL_TT:
248		sgt = drm_prime_pages_to_sg(obj->dev,
249					    bo->tbo.ttm->pages,
250					    bo->tbo.ttm->num_pages);
251		if (IS_ERR(sgt))
252			return sgt;
253
254		if (dma_map_sgtable(attach->dev, sgt, dir,
255				    DMA_ATTR_SKIP_CPU_SYNC))
256			goto error_free;
257		break;
258
259	case TTM_PL_VRAM:
260		r = amdgpu_vram_mgr_alloc_sgt(adev, bo->tbo.resource, 0,
261					      bo->tbo.base.size, attach->dev,
262					      dir, &sgt);
263		if (r)
264			return ERR_PTR(r);
265		break;
266	default:
267		return ERR_PTR(-EINVAL);
268	}
269
270	return sgt;
271
272error_free:
273	sg_free_table(sgt);
274	kfree(sgt);
275	return ERR_PTR(-EBUSY);
276}
277
278/**
279 * amdgpu_dma_buf_unmap - &dma_buf_ops.unmap_dma_buf implementation
280 * @attach: DMA-buf attachment
281 * @sgt: sg_table to unmap
282 * @dir: DMA direction
283 *
284 * This is called when a shared DMA buffer no longer needs to be accessible by
285 * another device. For now, simply unpins the buffer from GTT.
286 */
287static void amdgpu_dma_buf_unmap(struct dma_buf_attachment *attach,
288				 struct sg_table *sgt,
289				 enum dma_data_direction dir)
290{
291	if (sgt->sgl->page_link) {
292		dma_unmap_sgtable(attach->dev, sgt, dir, 0);
293		sg_free_table(sgt);
294		kfree(sgt);
295	} else {
296		amdgpu_vram_mgr_free_sgt(attach->dev, dir, sgt);
297	}
298}
299
300/**
301 * amdgpu_dma_buf_begin_cpu_access - &dma_buf_ops.begin_cpu_access implementation
302 * @dma_buf: Shared DMA buffer
303 * @direction: Direction of DMA transfer
304 *
305 * This is called before CPU access to the shared DMA buffer's memory. If it's
306 * a read access, the buffer is moved to the GTT domain if possible, for optimal
307 * CPU read performance.
308 *
309 * Returns:
310 * 0 on success or a negative error code on failure.
311 */
312static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf,
313					   enum dma_data_direction direction)
314{
315	struct amdgpu_bo *bo = gem_to_amdgpu_bo(dma_buf->priv);
316	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
317	struct ttm_operation_ctx ctx = { true, false };
318	u32 domain = amdgpu_display_supported_domains(adev, bo->flags);
319	int ret;
320	bool reads = (direction == DMA_BIDIRECTIONAL ||
321		      direction == DMA_FROM_DEVICE);
322
323	if (!reads || !(domain & AMDGPU_GEM_DOMAIN_GTT))
324		return 0;
325
326	/* move to gtt */
327	ret = amdgpu_bo_reserve(bo, false);
328	if (unlikely(ret != 0))
329		return ret;
330
331	if (!bo->tbo.pin_count &&
332	    (bo->allowed_domains & AMDGPU_GEM_DOMAIN_GTT)) {
333		amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
334		ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
335	}
336
337	amdgpu_bo_unreserve(bo);
338	return ret;
339}
340
341const struct dma_buf_ops amdgpu_dmabuf_ops = {
342	.attach = amdgpu_dma_buf_attach,
343	.detach = amdgpu_dma_buf_detach,
344	.pin = amdgpu_dma_buf_pin,
345	.unpin = amdgpu_dma_buf_unpin,
346	.map_dma_buf = amdgpu_dma_buf_map,
347	.unmap_dma_buf = amdgpu_dma_buf_unmap,
348	.release = drm_gem_dmabuf_release,
349	.begin_cpu_access = amdgpu_dma_buf_begin_cpu_access,
350	.mmap = drm_gem_dmabuf_mmap,
351	.vmap = drm_gem_dmabuf_vmap,
352	.vunmap = drm_gem_dmabuf_vunmap,
353};
354
355/**
356 * amdgpu_gem_prime_export - &drm_driver.gem_prime_export implementation
 
357 * @gobj: GEM BO
358 * @flags: Flags such as DRM_CLOEXEC and DRM_RDWR.
359 *
360 * The main work is done by the &drm_gem_prime_export helper.
361 *
362 * Returns:
363 * Shared DMA buffer representing the GEM BO from the given device.
364 */
365struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj,
366					int flags)
367{
368	struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj);
369	struct dma_buf *buf;
370
371	if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) ||
372	    bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID)
373		return ERR_PTR(-EPERM);
374
375	buf = drm_gem_prime_export(gobj, flags);
376	if (!IS_ERR(buf))
 
377		buf->ops = &amdgpu_dmabuf_ops;
 
378
379	return buf;
380}
381
382/**
383 * amdgpu_dma_buf_create_obj - create BO for DMA-buf import
384 *
385 * @dev: DRM device
386 * @dma_buf: DMA-buf
 
387 *
388 * Creates an empty SG BO for DMA-buf import.
389 *
390 * Returns:
391 * A new GEM BO of the given DRM device, representing the memory
392 * described by the given DMA-buf attachment and scatter/gather table.
393 */
394static struct drm_gem_object *
395amdgpu_dma_buf_create_obj(struct drm_device *dev, struct dma_buf *dma_buf)
 
 
396{
397	struct dma_resv *resv = dma_buf->resv;
398	struct amdgpu_device *adev = drm_to_adev(dev);
399	struct drm_gem_object *gobj;
400	struct amdgpu_bo *bo;
401	uint64_t flags = 0;
402	int ret;
403
 
 
 
 
 
 
 
404	dma_resv_lock(resv, NULL);
405
406	if (dma_buf->ops == &amdgpu_dmabuf_ops) {
407		struct amdgpu_bo *other = gem_to_amdgpu_bo(dma_buf->priv);
408
409		flags |= other->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC;
410	}
411
412	ret = amdgpu_gem_object_create(adev, dma_buf->size, PAGE_SIZE,
413				       AMDGPU_GEM_DOMAIN_CPU, flags,
414				       ttm_bo_type_sg, resv, &gobj);
415	if (ret)
416		goto error;
417
418	bo = gem_to_amdgpu_bo(gobj);
 
419	bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
420	bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
421	if (dma_buf->ops != &amdgpu_dmabuf_ops)
422		bo->prime_shared_count = 1;
423
424	dma_resv_unlock(resv);
425	return gobj;
426
427error:
428	dma_resv_unlock(resv);
429	return ERR_PTR(ret);
430}
431
432/**
433 * amdgpu_dma_buf_move_notify - &attach.move_notify implementation
434 *
435 * @attach: the DMA-buf attachment
436 *
437 * Invalidate the DMA-buf attachment, making sure that the we re-create the
438 * mapping before the next use.
439 */
440static void
441amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach)
442{
443	struct drm_gem_object *obj = attach->importer_priv;
444	struct ww_acquire_ctx *ticket = dma_resv_locking_ctx(obj->resv);
445	struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
446	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
447	struct ttm_operation_ctx ctx = { false, false };
448	struct ttm_placement placement = {};
449	struct amdgpu_vm_bo_base *bo_base;
450	int r;
451
452	if (bo->tbo.resource->mem_type == TTM_PL_SYSTEM)
453		return;
454
455	r = ttm_bo_validate(&bo->tbo, &placement, &ctx);
456	if (r) {
457		DRM_ERROR("Failed to invalidate DMA-buf import (%d))\n", r);
458		return;
459	}
460
461	for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) {
462		struct amdgpu_vm *vm = bo_base->vm;
463		struct dma_resv *resv = vm->root.bo->tbo.base.resv;
464
465		if (ticket) {
466			/* When we get an error here it means that somebody
467			 * else is holding the VM lock and updating page tables
468			 * So we can just continue here.
469			 */
470			r = dma_resv_lock(resv, ticket);
471			if (r)
472				continue;
473
474		} else {
475			/* TODO: This is more problematic and we actually need
476			 * to allow page tables updates without holding the
477			 * lock.
478			 */
479			if (!dma_resv_trylock(resv))
480				continue;
481		}
482
483		r = amdgpu_vm_clear_freed(adev, vm, NULL);
484		if (!r)
485			r = amdgpu_vm_handle_moved(adev, vm);
486
487		if (r && r != -EBUSY)
488			DRM_ERROR("Failed to invalidate VM page tables (%d))\n",
489				  r);
490
491		dma_resv_unlock(resv);
492	}
493}
494
495static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops = {
496	.allow_peer2peer = true,
497	.move_notify = amdgpu_dma_buf_move_notify
498};
499
500/**
501 * amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation
502 * @dev: DRM device
503 * @dma_buf: Shared DMA buffer
504 *
505 * Import a dma_buf into a the driver and potentially create a new GEM object.
 
506 *
507 * Returns:
508 * GEM BO representing the shared DMA buffer for the given device.
509 */
510struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev,
511					       struct dma_buf *dma_buf)
512{
513	struct dma_buf_attachment *attach;
514	struct drm_gem_object *obj;
515
516	if (dma_buf->ops == &amdgpu_dmabuf_ops) {
517		obj = dma_buf->priv;
518		if (obj->dev == dev) {
519			/*
520			 * Importing dmabuf exported from out own gem increases
521			 * refcount on gem itself instead of f_count of dmabuf.
522			 */
523			drm_gem_object_get(obj);
524			return obj;
525		}
526	}
527
528	obj = amdgpu_dma_buf_create_obj(dev, dma_buf);
529	if (IS_ERR(obj))
530		return obj;
531
532	attach = dma_buf_dynamic_attach(dma_buf, dev->dev,
533					&amdgpu_dma_buf_attach_ops, obj);
534	if (IS_ERR(attach)) {
535		drm_gem_object_put(obj);
536		return ERR_CAST(attach);
537	}
538
539	get_dma_buf(dma_buf);
540	obj->import_attach = attach;
541	return obj;
542}
543
544/**
545 * amdgpu_dmabuf_is_xgmi_accessible - Check if xgmi available for P2P transfer
546 *
547 * @adev: amdgpu_device pointer of the importer
548 * @bo: amdgpu buffer object
549 *
550 * Returns:
551 * True if dmabuf accessible over xgmi, false otherwise.
552 */
553bool amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device *adev,
554				      struct amdgpu_bo *bo)
555{
556	struct drm_gem_object *obj = &bo->tbo.base;
557	struct drm_gem_object *gobj;
558
559	if (obj->import_attach) {
560		struct dma_buf *dma_buf = obj->import_attach->dmabuf;
561
562		if (dma_buf->ops != &amdgpu_dmabuf_ops)
563			/* No XGMI with non AMD GPUs */
564			return false;
565
566		gobj = dma_buf->priv;
567		bo = gem_to_amdgpu_bo(gobj);
568	}
569
570	if (amdgpu_xgmi_same_hive(adev, amdgpu_ttm_adev(bo->tbo.bdev)) &&
571			(bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM))
572		return true;
573
574	return false;
575}