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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Intel Transactional Synchronization Extensions (TSX) control.
4 *
5 * Copyright (C) 2019 Intel Corporation
6 *
7 * Author:
8 * Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
9 */
10
11#include <linux/cpufeature.h>
12
13#include <asm/cmdline.h>
14
15#include "cpu.h"
16
17enum tsx_ctrl_states tsx_ctrl_state __ro_after_init = TSX_CTRL_NOT_SUPPORTED;
18
19void tsx_disable(void)
20{
21 u64 tsx;
22
23 rdmsrl(MSR_IA32_TSX_CTRL, tsx);
24
25 /* Force all transactions to immediately abort */
26 tsx |= TSX_CTRL_RTM_DISABLE;
27
28 /*
29 * Ensure TSX support is not enumerated in CPUID.
30 * This is visible to userspace and will ensure they
31 * do not waste resources trying TSX transactions that
32 * will always abort.
33 */
34 tsx |= TSX_CTRL_CPUID_CLEAR;
35
36 wrmsrl(MSR_IA32_TSX_CTRL, tsx);
37}
38
39void tsx_enable(void)
40{
41 u64 tsx;
42
43 rdmsrl(MSR_IA32_TSX_CTRL, tsx);
44
45 /* Enable the RTM feature in the cpu */
46 tsx &= ~TSX_CTRL_RTM_DISABLE;
47
48 /*
49 * Ensure TSX support is enumerated in CPUID.
50 * This is visible to userspace and will ensure they
51 * can enumerate and use the TSX feature.
52 */
53 tsx &= ~TSX_CTRL_CPUID_CLEAR;
54
55 wrmsrl(MSR_IA32_TSX_CTRL, tsx);
56}
57
58static bool __init tsx_ctrl_is_supported(void)
59{
60 u64 ia32_cap = x86_read_arch_cap_msr();
61
62 /*
63 * TSX is controlled via MSR_IA32_TSX_CTRL. However, support for this
64 * MSR is enumerated by ARCH_CAP_TSX_MSR bit in MSR_IA32_ARCH_CAPABILITIES.
65 *
66 * TSX control (aka MSR_IA32_TSX_CTRL) is only available after a
67 * microcode update on CPUs that have their MSR_IA32_ARCH_CAPABILITIES
68 * bit MDS_NO=1. CPUs with MDS_NO=0 are not planned to get
69 * MSR_IA32_TSX_CTRL support even after a microcode update. Thus,
70 * tsx= cmdline requests will do nothing on CPUs without
71 * MSR_IA32_TSX_CTRL support.
72 */
73 return !!(ia32_cap & ARCH_CAP_TSX_CTRL_MSR);
74}
75
76static enum tsx_ctrl_states x86_get_tsx_auto_mode(void)
77{
78 if (boot_cpu_has_bug(X86_BUG_TAA))
79 return TSX_CTRL_DISABLE;
80
81 return TSX_CTRL_ENABLE;
82}
83
84void __init tsx_init(void)
85{
86 char arg[5] = {};
87 int ret;
88
89 if (!tsx_ctrl_is_supported())
90 return;
91
92 ret = cmdline_find_option(boot_command_line, "tsx", arg, sizeof(arg));
93 if (ret >= 0) {
94 if (!strcmp(arg, "on")) {
95 tsx_ctrl_state = TSX_CTRL_ENABLE;
96 } else if (!strcmp(arg, "off")) {
97 tsx_ctrl_state = TSX_CTRL_DISABLE;
98 } else if (!strcmp(arg, "auto")) {
99 tsx_ctrl_state = x86_get_tsx_auto_mode();
100 } else {
101 tsx_ctrl_state = TSX_CTRL_DISABLE;
102 pr_err("tsx: invalid option, defaulting to off\n");
103 }
104 } else {
105 /* tsx= not provided */
106 if (IS_ENABLED(CONFIG_X86_INTEL_TSX_MODE_AUTO))
107 tsx_ctrl_state = x86_get_tsx_auto_mode();
108 else if (IS_ENABLED(CONFIG_X86_INTEL_TSX_MODE_OFF))
109 tsx_ctrl_state = TSX_CTRL_DISABLE;
110 else
111 tsx_ctrl_state = TSX_CTRL_ENABLE;
112 }
113
114 if (tsx_ctrl_state == TSX_CTRL_DISABLE) {
115 tsx_disable();
116
117 /*
118 * tsx_disable() will change the state of the
119 * RTM CPUID bit. Clear it here since it is now
120 * expected to be not set.
121 */
122 setup_clear_cpu_cap(X86_FEATURE_RTM);
123 } else if (tsx_ctrl_state == TSX_CTRL_ENABLE) {
124
125 /*
126 * HW defaults TSX to be enabled at bootup.
127 * We may still need the TSX enable support
128 * during init for special cases like
129 * kexec after TSX is disabled.
130 */
131 tsx_enable();
132
133 /*
134 * tsx_enable() will change the state of the
135 * RTM CPUID bit. Force it here since it is now
136 * expected to be set.
137 */
138 setup_force_cpu_cap(X86_FEATURE_RTM);
139 }
140}
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Intel Transactional Synchronization Extensions (TSX) control.
4 *
5 * Copyright (C) 2019-2021 Intel Corporation
6 *
7 * Author:
8 * Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
9 */
10
11#include <linux/cpufeature.h>
12
13#include <asm/cmdline.h>
14
15#include "cpu.h"
16
17#undef pr_fmt
18#define pr_fmt(fmt) "tsx: " fmt
19
20enum tsx_ctrl_states tsx_ctrl_state __ro_after_init = TSX_CTRL_NOT_SUPPORTED;
21
22void tsx_disable(void)
23{
24 u64 tsx;
25
26 rdmsrl(MSR_IA32_TSX_CTRL, tsx);
27
28 /* Force all transactions to immediately abort */
29 tsx |= TSX_CTRL_RTM_DISABLE;
30
31 /*
32 * Ensure TSX support is not enumerated in CPUID.
33 * This is visible to userspace and will ensure they
34 * do not waste resources trying TSX transactions that
35 * will always abort.
36 */
37 tsx |= TSX_CTRL_CPUID_CLEAR;
38
39 wrmsrl(MSR_IA32_TSX_CTRL, tsx);
40}
41
42void tsx_enable(void)
43{
44 u64 tsx;
45
46 rdmsrl(MSR_IA32_TSX_CTRL, tsx);
47
48 /* Enable the RTM feature in the cpu */
49 tsx &= ~TSX_CTRL_RTM_DISABLE;
50
51 /*
52 * Ensure TSX support is enumerated in CPUID.
53 * This is visible to userspace and will ensure they
54 * can enumerate and use the TSX feature.
55 */
56 tsx &= ~TSX_CTRL_CPUID_CLEAR;
57
58 wrmsrl(MSR_IA32_TSX_CTRL, tsx);
59}
60
61static bool __init tsx_ctrl_is_supported(void)
62{
63 u64 ia32_cap = x86_read_arch_cap_msr();
64
65 /*
66 * TSX is controlled via MSR_IA32_TSX_CTRL. However, support for this
67 * MSR is enumerated by ARCH_CAP_TSX_MSR bit in MSR_IA32_ARCH_CAPABILITIES.
68 *
69 * TSX control (aka MSR_IA32_TSX_CTRL) is only available after a
70 * microcode update on CPUs that have their MSR_IA32_ARCH_CAPABILITIES
71 * bit MDS_NO=1. CPUs with MDS_NO=0 are not planned to get
72 * MSR_IA32_TSX_CTRL support even after a microcode update. Thus,
73 * tsx= cmdline requests will do nothing on CPUs without
74 * MSR_IA32_TSX_CTRL support.
75 */
76 return !!(ia32_cap & ARCH_CAP_TSX_CTRL_MSR);
77}
78
79static enum tsx_ctrl_states x86_get_tsx_auto_mode(void)
80{
81 if (boot_cpu_has_bug(X86_BUG_TAA))
82 return TSX_CTRL_DISABLE;
83
84 return TSX_CTRL_ENABLE;
85}
86
87void tsx_clear_cpuid(void)
88{
89 u64 msr;
90
91 /*
92 * MSR_TFA_TSX_CPUID_CLEAR bit is only present when both CPUID
93 * bits RTM_ALWAYS_ABORT and TSX_FORCE_ABORT are present.
94 */
95 if (boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT) &&
96 boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)) {
97 rdmsrl(MSR_TSX_FORCE_ABORT, msr);
98 msr |= MSR_TFA_TSX_CPUID_CLEAR;
99 wrmsrl(MSR_TSX_FORCE_ABORT, msr);
100 }
101}
102
103void __init tsx_init(void)
104{
105 char arg[5] = {};
106 int ret;
107
108 /*
109 * Hardware will always abort a TSX transaction if both CPUID bits
110 * RTM_ALWAYS_ABORT and TSX_FORCE_ABORT are set. In this case, it is
111 * better not to enumerate CPUID.RTM and CPUID.HLE bits. Clear them
112 * here.
113 */
114 if (boot_cpu_has(X86_FEATURE_RTM_ALWAYS_ABORT) &&
115 boot_cpu_has(X86_FEATURE_TSX_FORCE_ABORT)) {
116 tsx_ctrl_state = TSX_CTRL_RTM_ALWAYS_ABORT;
117 tsx_clear_cpuid();
118 setup_clear_cpu_cap(X86_FEATURE_RTM);
119 setup_clear_cpu_cap(X86_FEATURE_HLE);
120 return;
121 }
122
123 if (!tsx_ctrl_is_supported()) {
124 tsx_ctrl_state = TSX_CTRL_NOT_SUPPORTED;
125 return;
126 }
127
128 ret = cmdline_find_option(boot_command_line, "tsx", arg, sizeof(arg));
129 if (ret >= 0) {
130 if (!strcmp(arg, "on")) {
131 tsx_ctrl_state = TSX_CTRL_ENABLE;
132 } else if (!strcmp(arg, "off")) {
133 tsx_ctrl_state = TSX_CTRL_DISABLE;
134 } else if (!strcmp(arg, "auto")) {
135 tsx_ctrl_state = x86_get_tsx_auto_mode();
136 } else {
137 tsx_ctrl_state = TSX_CTRL_DISABLE;
138 pr_err("invalid option, defaulting to off\n");
139 }
140 } else {
141 /* tsx= not provided */
142 if (IS_ENABLED(CONFIG_X86_INTEL_TSX_MODE_AUTO))
143 tsx_ctrl_state = x86_get_tsx_auto_mode();
144 else if (IS_ENABLED(CONFIG_X86_INTEL_TSX_MODE_OFF))
145 tsx_ctrl_state = TSX_CTRL_DISABLE;
146 else
147 tsx_ctrl_state = TSX_CTRL_ENABLE;
148 }
149
150 if (tsx_ctrl_state == TSX_CTRL_DISABLE) {
151 tsx_disable();
152
153 /*
154 * tsx_disable() will change the state of the RTM and HLE CPUID
155 * bits. Clear them here since they are now expected to be not
156 * set.
157 */
158 setup_clear_cpu_cap(X86_FEATURE_RTM);
159 setup_clear_cpu_cap(X86_FEATURE_HLE);
160 } else if (tsx_ctrl_state == TSX_CTRL_ENABLE) {
161
162 /*
163 * HW defaults TSX to be enabled at bootup.
164 * We may still need the TSX enable support
165 * during init for special cases like
166 * kexec after TSX is disabled.
167 */
168 tsx_enable();
169
170 /*
171 * tsx_enable() will change the state of the RTM and HLE CPUID
172 * bits. Force them here since they are now expected to be set.
173 */
174 setup_force_cpu_cap(X86_FEATURE_RTM);
175 setup_force_cpu_cap(X86_FEATURE_HLE);
176 }
177}