1/*
   2 * Copyright 2013 Maxime Ripard
   3 *
   4 * Maxime Ripard <maxime.ripard@free-electrons.com>
   5 *
   6 * This file is dual-licensed: you can use it either under the terms
   7 * of the GPL or the X11 license, at your option. Note that this dual
   8 * licensing only applies to this file, and not this project as a
   9 * whole.
  10 *
  11 *  a) This file is free software; you can redistribute it and/or
  12 *     modify it under the terms of the GNU General Public License as
  13 *     published by the Free Software Foundation; either version 2 of the
  14 *     License, or (at your option) any later version.
  15 *
  16 *     This file is distributed in the hope that it will be useful,
  17 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 *     GNU General Public License for more details.
  20 *
  21 * Or, alternatively,
  22 *
  23 *  b) Permission is hereby granted, free of charge, to any person
  24 *     obtaining a copy of this software and associated documentation
  25 *     files (the "Software"), to deal in the Software without
  26 *     restriction, including without limitation the rights to use,
  27 *     copy, modify, merge, publish, distribute, sublicense, and/or
  28 *     sell copies of the Software, and to permit persons to whom the
  29 *     Software is furnished to do so, subject to the following
  30 *     conditions:
  31 *
  32 *     The above copyright notice and this permission notice shall be
  33 *     included in all copies or substantial portions of the Software.
  34 *
  35 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42 *     OTHER DEALINGS IN THE SOFTWARE.
  43 */
  44
  45#include <dt-bindings/interrupt-controller/arm-gic.h>
  46#include <dt-bindings/thermal/thermal.h>
  47#include <dt-bindings/dma/sun4i-a10.h>
  48#include <dt-bindings/clock/sun7i-a20-ccu.h>
  49#include <dt-bindings/reset/sun4i-a10-ccu.h>
 
  50
  51/ {
  52	interrupt-parent = <&gic>;
  53	#address-cells = <1>;
  54	#size-cells = <1>;
  55
  56	aliases {
  57		ethernet0 = &gmac;
  58	};
  59
  60	chosen {
  61		#address-cells = <1>;
  62		#size-cells = <1>;
  63		ranges;
  64
  65		framebuffer-lcd0-hdmi {
  66			compatible = "allwinner,simple-framebuffer",
  67				     "simple-framebuffer";
  68			allwinner,pipeline = "de_be0-lcd0-hdmi";
  69			clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_HDMI0>,
  70				 <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
  71				 <&ccu CLK_TCON0_CH1>, <&ccu CLK_DRAM_DE_BE0>,
  72				 <&ccu CLK_HDMI>;
  73			status = "disabled";
  74		};
  75
  76		framebuffer-lcd0 {
  77			compatible = "allwinner,simple-framebuffer",
  78				     "simple-framebuffer";
  79			allwinner,pipeline = "de_be0-lcd0";
  80			clocks = <&ccu CLK_AHB_LCD0>, <&ccu CLK_AHB_DE_BE0>,
  81				 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH0>,
  82				 <&ccu CLK_DRAM_DE_BE0>;
  83			status = "disabled";
  84		};
  85
  86		framebuffer-lcd0-tve0 {
  87			compatible = "allwinner,simple-framebuffer",
  88				     "simple-framebuffer";
  89			allwinner,pipeline = "de_be0-lcd0-tve0";
  90			clocks = <&ccu CLK_AHB_TVE0>, <&ccu CLK_AHB_LCD0>,
  91				 <&ccu CLK_AHB_DE_BE0>,
  92				 <&ccu CLK_DE_BE0>, <&ccu CLK_TCON0_CH1>,
  93				 <&ccu CLK_DRAM_TVE0>, <&ccu CLK_DRAM_DE_BE0>;
  94			status = "disabled";
  95		};
  96	};
  97
  98	cpus {
  99		#address-cells = <1>;
 100		#size-cells = <0>;
 101
 102		cpu0: cpu@0 {
 103			compatible = "arm,cortex-a7";
 104			device_type = "cpu";
 105			reg = <0>;
 106			clocks = <&ccu CLK_CPU>;
 107			clock-latency = <244144>; /* 8 32k periods */
 108			operating-points = <
 109				/* kHz	  uV */
 110				960000	1400000
 111				912000	1400000
 112				864000	1300000
 113				720000	1200000
 114				528000	1100000
 115				312000	1000000
 116				144000	1000000
 117				>;
 118			#cooling-cells = <2>;
 119		};
 120
 121		cpu1: cpu@1 {
 122			compatible = "arm,cortex-a7";
 123			device_type = "cpu";
 124			reg = <1>;
 125			clocks = <&ccu CLK_CPU>;
 126			clock-latency = <244144>; /* 8 32k periods */
 127			operating-points = <
 128				/* kHz	  uV */
 129				960000	1400000
 130				912000	1400000
 131				864000	1300000
 132				720000	1200000
 133				528000	1100000
 134				312000	1000000
 135				144000	1000000
 136				>;
 137			#cooling-cells = <2>;
 138		};
 139	};
 140
 141	thermal-zones {
 142		cpu_thermal {
 143			/* milliseconds */
 144			polling-delay-passive = <250>;
 145			polling-delay = <1000>;
 146			thermal-sensors = <&rtp>;
 147
 148			cooling-maps {
 149				map0 {
 150					trip = <&cpu_alert0>;
 151					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 152							 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 153				};
 154			};
 155
 156			trips {
 157				cpu_alert0: cpu_alert0 {
 158					/* milliCelsius */
 159					temperature = <75000>;
 160					hysteresis = <2000>;
 161					type = "passive";
 162				};
 163
 164				cpu_crit: cpu_crit {
 165					/* milliCelsius */
 166					temperature = <100000>;
 167					hysteresis = <2000>;
 168					type = "critical";
 169				};
 170			};
 171		};
 172	};
 173
 174	reserved-memory {
 175		#address-cells = <1>;
 176		#size-cells = <1>;
 177		ranges;
 178
 179		/* Address must be kept in the lower 256 MiBs of DRAM for VE. */
 180		default-pool {
 181			compatible = "shared-dma-pool";
 182			size = <0x6000000>;
 183			alloc-ranges = <0x4a000000 0x6000000>;
 184			reusable;
 185			linux,cma-default;
 186		};
 187	};
 188
 189	timer {
 190		compatible = "arm,armv7-timer";
 191		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 192			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 193			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 194			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 195	};
 196
 197	pmu {
 198		compatible = "arm,cortex-a7-pmu";
 199		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 200			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
 201	};
 202
 203	clocks {
 204		#address-cells = <1>;
 205		#size-cells = <1>;
 206		ranges;
 207
 208		osc24M: clk-24M {
 209			#clock-cells = <0>;
 210			compatible = "fixed-clock";
 211			clock-frequency = <24000000>;
 212			clock-output-names = "osc24M";
 213		};
 214
 215		osc32k: clk-32k {
 216			#clock-cells = <0>;
 217			compatible = "fixed-clock";
 218			clock-frequency = <32768>;
 219			clock-output-names = "osc32k";
 220		};
 221
 222		/*
 223		 * The following two are dummy clocks, placeholders
 224		 * used in the gmac_tx clock. The gmac driver will
 225		 * choose one parent depending on the PHY interface
 226		 * mode, using clk_set_rate auto-reparenting.
 227		 *
 228		 * The actual TX clock rate is not controlled by the
 229		 * gmac_tx clock.
 230		 */
 231		mii_phy_tx_clk: clk-mii-phy-tx {
 232			#clock-cells = <0>;
 233			compatible = "fixed-clock";
 234			clock-frequency = <25000000>;
 235			clock-output-names = "mii_phy_tx";
 236		};
 237
 238		gmac_int_tx_clk: clk-gmac-int-tx {
 239			#clock-cells = <0>;
 240			compatible = "fixed-clock";
 241			clock-frequency = <125000000>;
 242			clock-output-names = "gmac_int_tx";
 243		};
 244
 245		gmac_tx_clk: clk@1c20164 {
 246			#clock-cells = <0>;
 247			compatible = "allwinner,sun7i-a20-gmac-clk";
 248			reg = <0x01c20164 0x4>;
 249			clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 250			clock-output-names = "gmac_tx";
 251		};
 252	};
 253
 254
 255	de: display-engine {
 256		compatible = "allwinner,sun7i-a20-display-engine";
 257		allwinner,pipelines = <&fe0>, <&fe1>;
 258		status = "disabled";
 259	};
 260
 261	soc {
 262		compatible = "simple-bus";
 263		#address-cells = <1>;
 264		#size-cells = <1>;
 265		ranges;
 266
 267		system-control@1c00000 {
 268			compatible = "allwinner,sun7i-a20-system-control",
 269				     "allwinner,sun4i-a10-system-control";
 270			reg = <0x01c00000 0x30>;
 271			#address-cells = <1>;
 272			#size-cells = <1>;
 273			ranges;
 274
 275			sram_a: sram@0 {
 276				compatible = "mmio-sram";
 277				reg = <0x00000000 0xc000>;
 278				#address-cells = <1>;
 279				#size-cells = <1>;
 280				ranges = <0 0x00000000 0xc000>;
 281
 282				emac_sram: sram-section@8000 {
 283					compatible = "allwinner,sun7i-a20-sram-a3-a4",
 284						     "allwinner,sun4i-a10-sram-a3-a4";
 285					reg = <0x8000 0x4000>;
 286					status = "disabled";
 287				};
 288			};
 289
 290			sram_d: sram@10000 {
 291				compatible = "mmio-sram";
 292				reg = <0x00010000 0x1000>;
 293				#address-cells = <1>;
 294				#size-cells = <1>;
 295				ranges = <0 0x00010000 0x1000>;
 296
 297				otg_sram: sram-section@0 {
 298					compatible = "allwinner,sun7i-a20-sram-d",
 299						     "allwinner,sun4i-a10-sram-d";
 300					reg = <0x0000 0x1000>;
 301					status = "disabled";
 302				};
 303			};
 304
 305			sram_c: sram@1d00000 {
 306				compatible = "mmio-sram";
 307				reg = <0x01d00000 0xd0000>;
 308				#address-cells = <1>;
 309				#size-cells = <1>;
 310				ranges = <0 0x01d00000 0xd0000>;
 311
 312				ve_sram: sram-section@0 {
 313					compatible = "allwinner,sun7i-a20-sram-c1",
 314						     "allwinner,sun4i-a10-sram-c1";
 315					reg = <0x000000 0x80000>;
 316				};
 317			};
 318		};
 319
 320		nmi_intc: interrupt-controller@1c00030 {
 321			compatible = "allwinner,sun7i-a20-sc-nmi";
 322			interrupt-controller;
 323			#interrupt-cells = <2>;
 324			reg = <0x01c00030 0x0c>;
 325			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 326		};
 327
 328		dma: dma-controller@1c02000 {
 329			compatible = "allwinner,sun4i-a10-dma";
 330			reg = <0x01c02000 0x1000>;
 331			interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
 332			clocks = <&ccu CLK_AHB_DMA>;
 333			#dma-cells = <2>;
 334		};
 335
 336		nfc: nand-controller@1c03000 {
 337			compatible = "allwinner,sun4i-a10-nand";
 338			reg = <0x01c03000 0x1000>;
 339			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
 340			clocks = <&ccu CLK_AHB_NAND>, <&ccu CLK_NAND>;
 341			clock-names = "ahb", "mod";
 342			dmas = <&dma SUN4I_DMA_DEDICATED 3>;
 343			dma-names = "rxtx";
 344			status = "disabled";
 345			#address-cells = <1>;
 346			#size-cells = <0>;
 347		};
 348
 349		spi0: spi@1c05000 {
 350			compatible = "allwinner,sun4i-a10-spi";
 351			reg = <0x01c05000 0x1000>;
 352			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 353			clocks = <&ccu CLK_AHB_SPI0>, <&ccu CLK_SPI0>;
 354			clock-names = "ahb", "mod";
 355			dmas = <&dma SUN4I_DMA_DEDICATED 27>,
 356			       <&dma SUN4I_DMA_DEDICATED 26>;
 357			dma-names = "rx", "tx";
 358			status = "disabled";
 359			#address-cells = <1>;
 360			#size-cells = <0>;
 361			num-cs = <4>;
 362		};
 363
 364		spi1: spi@1c06000 {
 365			compatible = "allwinner,sun4i-a10-spi";
 366			reg = <0x01c06000 0x1000>;
 367			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 368			clocks = <&ccu CLK_AHB_SPI1>, <&ccu CLK_SPI1>;
 369			clock-names = "ahb", "mod";
 370			dmas = <&dma SUN4I_DMA_DEDICATED 9>,
 371			       <&dma SUN4I_DMA_DEDICATED 8>;
 372			dma-names = "rx", "tx";
 373			status = "disabled";
 374			#address-cells = <1>;
 375			#size-cells = <0>;
 376			num-cs = <1>;
 377		};
 378
 379		csi0: csi@1c09000 {
 380			compatible = "allwinner,sun7i-a20-csi0";
 381			reg = <0x01c09000 0x1000>;
 382			interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 383			clocks = <&ccu CLK_AHB_CSI0>, <&ccu CLK_CSI_SCLK>, <&ccu CLK_DRAM_CSI0>;
 384			clock-names = "bus", "isp", "ram";
 385			resets = <&ccu RST_CSI0>;
 386			status = "disabled";
 387		};
 388
 389		emac: ethernet@1c0b000 {
 390			compatible = "allwinner,sun4i-a10-emac";
 391			reg = <0x01c0b000 0x1000>;
 392			interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
 393			clocks = <&ccu CLK_AHB_EMAC>;
 394			allwinner,sram = <&emac_sram 1>;
 395			status = "disabled";
 396		};
 397
 398		mdio: mdio@1c0b080 {
 399			compatible = "allwinner,sun4i-a10-mdio";
 400			reg = <0x01c0b080 0x14>;
 401			status = "disabled";
 402			#address-cells = <1>;
 403			#size-cells = <0>;
 404		};
 405
 406		tcon0: lcd-controller@1c0c000 {
 407			compatible = "allwinner,sun7i-a20-tcon";
 
 408			reg = <0x01c0c000 0x1000>;
 409			interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
 410			resets = <&ccu RST_TCON0>;
 411			reset-names = "lcd";
 412			clocks = <&ccu CLK_AHB_LCD0>,
 413				 <&ccu CLK_TCON0_CH0>,
 414				 <&ccu CLK_TCON0_CH1>;
 415			clock-names = "ahb",
 416				      "tcon-ch0",
 417				      "tcon-ch1";
 418			clock-output-names = "tcon0-pixel-clock";
 419			#clock-cells = <0>;
 420			dmas = <&dma SUN4I_DMA_DEDICATED 14>;
 421
 422			ports {
 423				#address-cells = <1>;
 424				#size-cells = <0>;
 425
 426				tcon0_in: port@0 {
 427					#address-cells = <1>;
 428					#size-cells = <0>;
 429					reg = <0>;
 430
 431					tcon0_in_be0: endpoint@0 {
 432						reg = <0>;
 433						remote-endpoint = <&be0_out_tcon0>;
 434					};
 435
 436					tcon0_in_be1: endpoint@1 {
 437						reg = <1>;
 438						remote-endpoint = <&be1_out_tcon0>;
 439					};
 440				};
 441
 442				tcon0_out: port@1 {
 443					#address-cells = <1>;
 444					#size-cells = <0>;
 445					reg = <1>;
 446
 447					tcon0_out_hdmi: endpoint@1 {
 448						reg = <1>;
 449						remote-endpoint = <&hdmi_in_tcon0>;
 450						allwinner,tcon-channel = <1>;
 451					};
 452				};
 453			};
 454		};
 455
 456		tcon1: lcd-controller@1c0d000 {
 457			compatible = "allwinner,sun7i-a20-tcon";
 
 458			reg = <0x01c0d000 0x1000>;
 459			interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
 460			resets = <&ccu RST_TCON1>;
 461			reset-names = "lcd";
 462			clocks = <&ccu CLK_AHB_LCD1>,
 463				 <&ccu CLK_TCON1_CH0>,
 464				 <&ccu CLK_TCON1_CH1>;
 465			clock-names = "ahb",
 466				      "tcon-ch0",
 467				      "tcon-ch1";
 468			clock-output-names = "tcon1-pixel-clock";
 469			#clock-cells = <0>;
 470			dmas = <&dma SUN4I_DMA_DEDICATED 15>;
 471
 472			ports {
 473				#address-cells = <1>;
 474				#size-cells = <0>;
 475
 476				tcon1_in: port@0 {
 477					#address-cells = <1>;
 478					#size-cells = <0>;
 479					reg = <0>;
 480
 481					tcon1_in_be0: endpoint@0 {
 482						reg = <0>;
 483						remote-endpoint = <&be0_out_tcon1>;
 484					};
 485
 486					tcon1_in_be1: endpoint@1 {
 487						reg = <1>;
 488						remote-endpoint = <&be1_out_tcon1>;
 489					};
 490				};
 491
 492				tcon1_out: port@1 {
 493					#address-cells = <1>;
 494					#size-cells = <0>;
 495					reg = <1>;
 496
 497					tcon1_out_hdmi: endpoint@1 {
 498						reg = <1>;
 499						remote-endpoint = <&hdmi_in_tcon1>;
 500						allwinner,tcon-channel = <1>;
 501					};
 502				};
 503			};
 504		};
 505
 506		video-codec@1c0e000 {
 507			compatible = "allwinner,sun7i-a20-video-engine";
 508			reg = <0x01c0e000 0x1000>;
 509			clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
 510				 <&ccu CLK_DRAM_VE>;
 511			clock-names = "ahb", "mod", "ram";
 512			resets = <&ccu RST_VE>;
 513			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
 514			allwinner,sram = <&ve_sram 1>;
 515		};
 516
 517		mmc0: mmc@1c0f000 {
 518			compatible = "allwinner,sun7i-a20-mmc";
 519			reg = <0x01c0f000 0x1000>;
 520			clocks = <&ccu CLK_AHB_MMC0>,
 521				 <&ccu CLK_MMC0>,
 522				 <&ccu CLK_MMC0_OUTPUT>,
 523				 <&ccu CLK_MMC0_SAMPLE>;
 524			clock-names = "ahb",
 525				      "mmc",
 526				      "output",
 527				      "sample";
 528			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 529			pinctrl-names = "default";
 530			pinctrl-0 = <&mmc0_pins>;
 531			status = "disabled";
 532			#address-cells = <1>;
 533			#size-cells = <0>;
 534		};
 535
 536		mmc1: mmc@1c10000 {
 537			compatible = "allwinner,sun7i-a20-mmc";
 538			reg = <0x01c10000 0x1000>;
 539			clocks = <&ccu CLK_AHB_MMC1>,
 540				 <&ccu CLK_MMC1>,
 541				 <&ccu CLK_MMC1_OUTPUT>,
 542				 <&ccu CLK_MMC1_SAMPLE>;
 543			clock-names = "ahb",
 544				      "mmc",
 545				      "output",
 546				      "sample";
 547			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
 548			status = "disabled";
 549			#address-cells = <1>;
 550			#size-cells = <0>;
 551		};
 552
 553		mmc2: mmc@1c11000 {
 554			compatible = "allwinner,sun7i-a20-mmc";
 555			reg = <0x01c11000 0x1000>;
 556			clocks = <&ccu CLK_AHB_MMC2>,
 557				 <&ccu CLK_MMC2>,
 558				 <&ccu CLK_MMC2_OUTPUT>,
 559				 <&ccu CLK_MMC2_SAMPLE>;
 560			clock-names = "ahb",
 561				      "mmc",
 562				      "output",
 563				      "sample";
 564			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
 565			pinctrl-names = "default";
 566			pinctrl-0 = <&mmc2_pins>;
 567			status = "disabled";
 568			#address-cells = <1>;
 569			#size-cells = <0>;
 570		};
 571
 572		mmc3: mmc@1c12000 {
 573			compatible = "allwinner,sun7i-a20-mmc";
 574			reg = <0x01c12000 0x1000>;
 575			clocks = <&ccu CLK_AHB_MMC3>,
 576				 <&ccu CLK_MMC3>,
 577				 <&ccu CLK_MMC3_OUTPUT>,
 578				 <&ccu CLK_MMC3_SAMPLE>;
 579			clock-names = "ahb",
 580				      "mmc",
 581				      "output",
 582				      "sample";
 583			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
 584			pinctrl-names = "default";
 585			pinctrl-0 = <&mmc3_pins>;
 586			status = "disabled";
 587			#address-cells = <1>;
 588			#size-cells = <0>;
 589		};
 590
 591		usb_otg: usb@1c13000 {
 592			compatible = "allwinner,sun4i-a10-musb";
 593			reg = <0x01c13000 0x0400>;
 594			clocks = <&ccu CLK_AHB_OTG>;
 595			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
 596			interrupt-names = "mc";
 597			phys = <&usbphy 0>;
 598			phy-names = "usb";
 599			extcon = <&usbphy 0>;
 600			allwinner,sram = <&otg_sram 1>;
 601			dr_mode = "otg";
 602			status = "disabled";
 603		};
 604
 605		usbphy: phy@1c13400 {
 606			#phy-cells = <1>;
 607			compatible = "allwinner,sun7i-a20-usb-phy";
 608			reg = <0x01c13400 0x10>, <0x01c14800 0x4>, <0x01c1c800 0x4>;
 609			reg-names = "phy_ctrl", "pmu1", "pmu2";
 610			clocks = <&ccu CLK_USB_PHY>;
 611			clock-names = "usb_phy";
 612			resets = <&ccu RST_USB_PHY0>,
 613				 <&ccu RST_USB_PHY1>,
 614				 <&ccu RST_USB_PHY2>;
 615			reset-names = "usb0_reset", "usb1_reset", "usb2_reset";
 616			status = "disabled";
 617		};
 618
 619		ehci0: usb@1c14000 {
 620			compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
 621			reg = <0x01c14000 0x100>;
 622			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
 623			clocks = <&ccu CLK_AHB_EHCI0>;
 624			phys = <&usbphy 1>;
 625			phy-names = "usb";
 626			status = "disabled";
 627		};
 628
 629		ohci0: usb@1c14400 {
 630			compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
 631			reg = <0x01c14400 0x100>;
 632			interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
 633			clocks = <&ccu CLK_USB_OHCI0>, <&ccu CLK_AHB_OHCI0>;
 634			phys = <&usbphy 1>;
 635			phy-names = "usb";
 636			status = "disabled";
 637		};
 638
 639		crypto: crypto-engine@1c15000 {
 640			compatible = "allwinner,sun7i-a20-crypto",
 641				     "allwinner,sun4i-a10-crypto";
 642			reg = <0x01c15000 0x1000>;
 643			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
 644			clocks = <&ccu CLK_AHB_SS>, <&ccu CLK_SS>;
 645			clock-names = "ahb", "mod";
 646		};
 647
 648		hdmi: hdmi@1c16000 {
 649			compatible = "allwinner,sun7i-a20-hdmi",
 650				     "allwinner,sun5i-a10s-hdmi";
 651			reg = <0x01c16000 0x1000>;
 652			interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
 653			clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
 654				 <&ccu CLK_PLL_VIDEO0_2X>,
 655				 <&ccu CLK_PLL_VIDEO1_2X>;
 656			clock-names = "ahb", "mod", "pll-0", "pll-1";
 657			dmas = <&dma SUN4I_DMA_NORMAL 16>,
 658			       <&dma SUN4I_DMA_NORMAL 16>,
 659			       <&dma SUN4I_DMA_DEDICATED 24>;
 660			dma-names = "ddc-tx", "ddc-rx", "audio-tx";
 661			status = "disabled";
 662
 663			ports {
 664				#address-cells = <1>;
 665				#size-cells = <0>;
 666
 667				hdmi_in: port@0 {
 668					#address-cells = <1>;
 669					#size-cells = <0>;
 670					reg = <0>;
 671
 672					hdmi_in_tcon0: endpoint@0 {
 673						reg = <0>;
 674						remote-endpoint = <&tcon0_out_hdmi>;
 675					};
 676
 677					hdmi_in_tcon1: endpoint@1 {
 678						reg = <1>;
 679						remote-endpoint = <&tcon1_out_hdmi>;
 680					};
 681				};
 682
 683				hdmi_out: port@1 {
 684					reg = <1>;
 685				};
 686			};
 687		};
 688
 689		spi2: spi@1c17000 {
 690			compatible = "allwinner,sun4i-a10-spi";
 691			reg = <0x01c17000 0x1000>;
 692			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 693			clocks = <&ccu CLK_AHB_SPI2>, <&ccu CLK_SPI2>;
 694			clock-names = "ahb", "mod";
 695			dmas = <&dma SUN4I_DMA_DEDICATED 29>,
 696			       <&dma SUN4I_DMA_DEDICATED 28>;
 697			dma-names = "rx", "tx";
 698			status = "disabled";
 699			#address-cells = <1>;
 700			#size-cells = <0>;
 701			num-cs = <1>;
 702		};
 703
 704		ahci: sata@1c18000 {
 705			compatible = "allwinner,sun4i-a10-ahci";
 706			reg = <0x01c18000 0x1000>;
 707			interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
 708			clocks = <&ccu CLK_AHB_SATA>, <&ccu CLK_SATA>;
 709			status = "disabled";
 710		};
 711
 712		ehci1: usb@1c1c000 {
 713			compatible = "allwinner,sun7i-a20-ehci", "generic-ehci";
 714			reg = <0x01c1c000 0x100>;
 715			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
 716			clocks = <&ccu CLK_AHB_EHCI1>;
 717			phys = <&usbphy 2>;
 718			phy-names = "usb";
 719			status = "disabled";
 720		};
 721
 722		ohci1: usb@1c1c400 {
 723			compatible = "allwinner,sun7i-a20-ohci", "generic-ohci";
 724			reg = <0x01c1c400 0x100>;
 725			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 726			clocks = <&ccu CLK_USB_OHCI1>, <&ccu CLK_AHB_OHCI1>;
 727			phys = <&usbphy 2>;
 728			phy-names = "usb";
 729			status = "disabled";
 730		};
 731
 
 
 
 
 
 
 
 
 
 
 
 732		spi3: spi@1c1f000 {
 733			compatible = "allwinner,sun4i-a10-spi";
 734			reg = <0x01c1f000 0x1000>;
 735			interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 736			clocks = <&ccu CLK_AHB_SPI3>, <&ccu CLK_SPI3>;
 737			clock-names = "ahb", "mod";
 738			dmas = <&dma SUN4I_DMA_DEDICATED 31>,
 739			       <&dma SUN4I_DMA_DEDICATED 30>;
 740			dma-names = "rx", "tx";
 741			status = "disabled";
 742			#address-cells = <1>;
 743			#size-cells = <0>;
 744			num-cs = <1>;
 745		};
 746
 747		ccu: clock@1c20000 {
 748			compatible = "allwinner,sun7i-a20-ccu";
 749			reg = <0x01c20000 0x400>;
 750			clocks = <&osc24M>, <&osc32k>;
 751			clock-names = "hosc", "losc";
 752			#clock-cells = <1>;
 753			#reset-cells = <1>;
 754		};
 755
 756		pio: pinctrl@1c20800 {
 757			compatible = "allwinner,sun7i-a20-pinctrl";
 758			reg = <0x01c20800 0x400>;
 759			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 760			clocks = <&ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
 761			clock-names = "apb", "hosc", "losc";
 762			gpio-controller;
 763			interrupt-controller;
 764			#interrupt-cells = <3>;
 765			#gpio-cells = <3>;
 766
 767			/omit-if-no-ref/
 768			can_pa_pins: can-pa-pins {
 769				pins = "PA16", "PA17";
 770				function = "can";
 771			};
 772
 773			/omit-if-no-ref/
 774			can_ph_pins: can-ph-pins {
 775				pins = "PH20", "PH21";
 776				function = "can";
 777			};
 778
 779			/omit-if-no-ref/
 780			clk_out_a_pin: clk-out-a-pin {
 781				pins = "PI12";
 782				function = "clk_out_a";
 783			};
 784
 785			/omit-if-no-ref/
 786			clk_out_b_pin: clk-out-b-pin {
 787				pins = "PI13";
 788				function = "clk_out_b";
 789			};
 790
 791			/omit-if-no-ref/
 792			csi0_8bits_pins: csi-8bits-pins {
 793				pins = "PE0", "PE2", "PE3", "PE4", "PE5",
 794				       "PE6", "PE7", "PE8", "PE9", "PE10",
 795				       "PE11";
 796				function = "csi0";
 797			};
 798
 799			/omit-if-no-ref/
 800			csi0_clk_pin: csi-clk-pin {
 801				pins = "PE1";
 802				function = "csi0";
 803			};
 804
 805			/omit-if-no-ref/
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 806			emac_pa_pins: emac-pa-pins {
 807				pins = "PA0", "PA1", "PA2",
 808				       "PA3", "PA4", "PA5", "PA6",
 809				       "PA7", "PA8", "PA9", "PA10",
 810				       "PA11", "PA12", "PA13", "PA14",
 811				       "PA15", "PA16";
 812				function = "emac";
 813			};
 814
 815			/omit-if-no-ref/
 816			emac_ph_pins: emac-ph-pins {
 817				pins = "PH8", "PH9", "PH10", "PH11",
 818				       "PH14", "PH15", "PH16", "PH17",
 819				       "PH18", "PH19", "PH20", "PH21",
 820				       "PH22", "PH23", "PH24", "PH25",
 821				       "PH26";
 822				function = "emac";
 823			};
 824
 825			/omit-if-no-ref/
 826			gmac_mii_pins: gmac-mii-pins {
 827				pins = "PA0", "PA1", "PA2",
 828				       "PA3", "PA4", "PA5", "PA6",
 829				       "PA7", "PA8", "PA9", "PA10",
 830				       "PA11", "PA12", "PA13", "PA14",
 831				       "PA15", "PA16";
 832				function = "gmac";
 833			};
 834
 835			/omit-if-no-ref/
 836			gmac_rgmii_pins: gmac-rgmii-pins {
 837				pins = "PA0", "PA1", "PA2",
 838				       "PA3", "PA4", "PA5", "PA6",
 839				        "PA7", "PA8", "PA10",
 840				       "PA11", "PA12", "PA13",
 841				       "PA15", "PA16";
 842				function = "gmac";
 843				/*
 844				 * data lines in RGMII mode use DDR mode
 845				 * and need a higher signal drive strength
 846				 */
 847				drive-strength = <40>;
 848			};
 849
 850			/omit-if-no-ref/
 851			i2c0_pins: i2c0-pins {
 852				pins = "PB0", "PB1";
 853				function = "i2c0";
 854			};
 855
 856			/omit-if-no-ref/
 857			i2c1_pins: i2c1-pins {
 858				pins = "PB18", "PB19";
 859				function = "i2c1";
 860			};
 861
 862			/omit-if-no-ref/
 863			i2c2_pins: i2c2-pins {
 864				pins = "PB20", "PB21";
 865				function = "i2c2";
 866			};
 867
 868			/omit-if-no-ref/
 869			i2c3_pins: i2c3-pins {
 870				pins = "PI0", "PI1";
 871				function = "i2c3";
 872			};
 873
 874			/omit-if-no-ref/
 875			ir0_rx_pin: ir0-rx-pin {
 876				pins = "PB4";
 877				function = "ir0";
 878			};
 879
 880			/omit-if-no-ref/
 881			ir0_tx_pin: ir0-tx-pin {
 882				pins = "PB3";
 883				function = "ir0";
 884			};
 885
 886			/omit-if-no-ref/
 887			ir1_rx_pin: ir1-rx-pin {
 888				pins = "PB23";
 889				function = "ir1";
 890			};
 891
 892			/omit-if-no-ref/
 893			ir1_tx_pin: ir1-tx-pin {
 894				pins = "PB22";
 895				function = "ir1";
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 896			};
 897
 898			/omit-if-no-ref/
 899			mmc0_pins: mmc0-pins {
 900				pins = "PF0", "PF1", "PF2",
 901				       "PF3", "PF4", "PF5";
 902				function = "mmc0";
 903				drive-strength = <30>;
 904				bias-pull-up;
 905			};
 906
 907			/omit-if-no-ref/
 908			mmc2_pins: mmc2-pins {
 909				pins = "PC6", "PC7", "PC8",
 910				       "PC9", "PC10", "PC11";
 911				function = "mmc2";
 912				drive-strength = <30>;
 913				bias-pull-up;
 914			};
 915
 916			/omit-if-no-ref/
 917			mmc3_pins: mmc3-pins {
 918				pins = "PI4", "PI5", "PI6",
 919				       "PI7", "PI8", "PI9";
 920				function = "mmc3";
 921				drive-strength = <30>;
 922				bias-pull-up;
 923			};
 924
 925			/omit-if-no-ref/
 926			ps2_0_pins: ps2-0-pins {
 927				pins = "PI20", "PI21";
 928				function = "ps2";
 929			};
 930
 931			/omit-if-no-ref/
 932			ps2_1_ph_pins: ps2-1-ph-pins {
 933				pins = "PH12", "PH13";
 934				function = "ps2";
 935			};
 936
 937			/omit-if-no-ref/
 938			pwm0_pin: pwm0-pin {
 939				pins = "PB2";
 940				function = "pwm";
 941			};
 942
 943			/omit-if-no-ref/
 944			pwm1_pin: pwm1-pin {
 945				pins = "PI3";
 946				function = "pwm";
 947			};
 948
 949			/omit-if-no-ref/
 950			spdif_tx_pin: spdif-tx-pin {
 951				pins = "PB13";
 952				function = "spdif";
 953				bias-pull-up;
 954			};
 955
 956			/omit-if-no-ref/
 957			spi0_pi_pins: spi0-pi-pins {
 958				pins = "PI11", "PI12", "PI13";
 959				function = "spi0";
 960			};
 961
 962			/omit-if-no-ref/
 963			spi0_cs0_pi_pin: spi0-cs0-pi-pin {
 964				pins = "PI10";
 965				function = "spi0";
 966			};
 967
 968			/omit-if-no-ref/
 969			spi0_cs1_pi_pin: spi0-cs1-pi-pin {
 970				pins = "PI14";
 971				function = "spi0";
 972			};
 973
 974			/omit-if-no-ref/
 975			spi1_pi_pins: spi1-pi-pins {
 976				pins = "PI17", "PI18", "PI19";
 977				function = "spi1";
 978			};
 979
 980			/omit-if-no-ref/
 981			spi1_cs0_pi_pin: spi1-cs0-pi-pin {
 982				pins = "PI16";
 983				function = "spi1";
 984			};
 985
 986			/omit-if-no-ref/
 987			spi2_pb_pins: spi2-pb-pins {
 988				pins = "PB15", "PB16", "PB17";
 989				function = "spi2";
 990			};
 991
 992			/omit-if-no-ref/
 993			spi2_cs0_pb_pin: spi2-cs0-pb-pin {
 994				pins = "PB14";
 995				function = "spi2";
 996			};
 997
 998			/omit-if-no-ref/
 999			spi2_pc_pins: spi2-pc-pins {
1000				pins = "PC20", "PC21", "PC22";
1001				function = "spi2";
1002			};
1003
1004			/omit-if-no-ref/
1005			spi2_cs0_pc_pin: spi2-cs0-pc-pin {
1006				pins = "PC19";
1007				function = "spi2";
1008			};
1009
1010			/omit-if-no-ref/
1011			uart0_pb_pins: uart0-pb-pins {
1012				pins = "PB22", "PB23";
1013				function = "uart0";
1014			};
1015
1016			/omit-if-no-ref/
1017			uart0_pf_pins: uart0-pf-pins {
1018				pins = "PF2", "PF4";
1019				function = "uart0";
1020			};
1021
1022			/omit-if-no-ref/
1023			uart1_pa_pins: uart1-pa-pins {
1024				pins = "PA10", "PA11";
1025				function = "uart1";
1026			};
1027
1028			/omit-if-no-ref/
1029			uart1_cts_rts_pa_pins: uart1-cts-rts-pa-pins {
1030				pins = "PA12", "PA13";
1031				function = "uart1";
1032			};
1033
1034			/omit-if-no-ref/
1035			uart2_pa_pins: uart2-pa-pins {
1036				pins = "PA2", "PA3";
1037				function = "uart2";
1038			};
1039
1040			/omit-if-no-ref/
1041			uart2_cts_rts_pa_pins: uart2-cts-rts-pa-pins {
1042				pins = "PA0", "PA1";
1043				function = "uart2";
1044			};
1045
1046			/omit-if-no-ref/
1047			uart2_pi_pins: uart2-pi-pins {
1048				pins = "PI18", "PI19";
1049				function = "uart2";
1050			};
1051
1052			/omit-if-no-ref/
1053			uart2_cts_rts_pi_pins: uart2-cts-rts-pi-pins {
1054				pins = "PI16", "PI17";
1055				function = "uart2";
1056			};
1057
1058			/omit-if-no-ref/
1059			uart3_pg_pins: uart3-pg-pins {
1060				pins = "PG6", "PG7";
1061				function = "uart3";
1062			};
1063
1064			/omit-if-no-ref/
1065			uart3_cts_rts_pg_pins: uart3-cts-rts-pg-pins {
1066				pins = "PG8", "PG9";
1067				function = "uart3";
1068			};
1069
1070			/omit-if-no-ref/
1071			uart3_ph_pins: uart3-ph-pins {
1072				pins = "PH0", "PH1";
1073				function = "uart3";
1074			};
1075
1076			/omit-if-no-ref/
1077			uart3_cts_rts_ph_pins: uart3-cts-rts-ph-pins {
1078				pins = "PH2", "PH3";
1079				function = "uart3";
1080			};
1081
1082			/omit-if-no-ref/
1083			uart4_pg_pins: uart4-pg-pins {
1084				pins = "PG10", "PG11";
1085				function = "uart4";
1086			};
1087
1088			/omit-if-no-ref/
1089			uart4_ph_pins: uart4-ph-pins {
1090				pins = "PH4", "PH5";
1091				function = "uart4";
1092			};
1093
1094			/omit-if-no-ref/
1095			uart5_ph_pins: uart5-ph-pins {
1096				pins = "PH6", "PH7";
1097				function = "uart5";
1098			};
1099
1100			/omit-if-no-ref/
1101			uart5_pi_pins: uart5-pi-pins {
1102				pins = "PI10", "PI11";
1103				function = "uart5";
1104			};
1105
1106			/omit-if-no-ref/
1107			uart6_pa_pins: uart6-pa-pins {
1108				pins = "PA12", "PA13";
1109				function = "uart6";
1110			};
1111
1112			/omit-if-no-ref/
1113			uart6_pi_pins: uart6-pi-pins {
1114				pins = "PI12", "PI13";
1115				function = "uart6";
1116			};
1117
1118			/omit-if-no-ref/
1119			uart7_pa_pins: uart7-pa-pins {
1120				pins = "PA14", "PA15";
1121				function = "uart7";
1122			};
1123
1124			/omit-if-no-ref/
1125			uart7_pi_pins: uart7-pi-pins {
1126				pins = "PI20", "PI21";
1127				function = "uart7";
1128			};
1129		};
1130
1131		timer@1c20c00 {
1132			compatible = "allwinner,sun4i-a10-timer";
1133			reg = <0x01c20c00 0x90>;
1134			interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
1135				     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
1136				     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
1137				     <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
1138				     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
1139				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
1140			clocks = <&osc24M>;
1141		};
1142
1143		wdt: watchdog@1c20c90 {
1144			compatible = "allwinner,sun4i-a10-wdt";
1145			reg = <0x01c20c90 0x10>;
1146			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1147			clocks = <&osc24M>;
1148		};
1149
1150		rtc: rtc@1c20d00 {
1151			compatible = "allwinner,sun7i-a20-rtc";
1152			reg = <0x01c20d00 0x20>;
1153			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
1154		};
1155
1156		pwm: pwm@1c20e00 {
1157			compatible = "allwinner,sun7i-a20-pwm";
1158			reg = <0x01c20e00 0xc>;
1159			clocks = <&osc24M>;
1160			#pwm-cells = <3>;
1161			status = "disabled";
1162		};
1163
1164		spdif: spdif@1c21000 {
1165			#sound-dai-cells = <0>;
1166			compatible = "allwinner,sun4i-a10-spdif";
1167			reg = <0x01c21000 0x400>;
1168			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1169			clocks = <&ccu CLK_APB0_SPDIF>, <&ccu CLK_SPDIF>;
1170			clock-names = "apb", "spdif";
1171			dmas = <&dma SUN4I_DMA_NORMAL 2>,
1172			       <&dma SUN4I_DMA_NORMAL 2>;
1173			dma-names = "rx", "tx";
1174			status = "disabled";
1175		};
1176
1177		ir0: ir@1c21800 {
1178			compatible = "allwinner,sun4i-a10-ir";
1179			clocks = <&ccu CLK_APB0_IR0>, <&ccu CLK_IR0>;
1180			clock-names = "apb", "ir";
1181			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1182			reg = <0x01c21800 0x40>;
1183			status = "disabled";
1184		};
1185
1186		ir1: ir@1c21c00 {
1187			compatible = "allwinner,sun4i-a10-ir";
1188			clocks = <&ccu CLK_APB0_IR1>, <&ccu CLK_IR1>;
1189			clock-names = "apb", "ir";
1190			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1191			reg = <0x01c21c00 0x40>;
1192			status = "disabled";
1193		};
1194
1195		i2s1: i2s@1c22000 {
1196			#sound-dai-cells = <0>;
1197			compatible = "allwinner,sun4i-a10-i2s";
1198			reg = <0x01c22000 0x400>;
1199			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
1200			clocks = <&ccu CLK_APB0_I2S1>, <&ccu CLK_I2S1>;
1201			clock-names = "apb", "mod";
1202			dmas = <&dma SUN4I_DMA_NORMAL 4>,
1203			       <&dma SUN4I_DMA_NORMAL 4>;
1204			dma-names = "rx", "tx";
1205			status = "disabled";
1206		};
1207
1208		i2s0: i2s@1c22400 {
1209			#sound-dai-cells = <0>;
1210			compatible = "allwinner,sun4i-a10-i2s";
1211			reg = <0x01c22400 0x400>;
1212			interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
1213			clocks = <&ccu CLK_APB0_I2S0>, <&ccu CLK_I2S0>;
1214			clock-names = "apb", "mod";
1215			dmas = <&dma SUN4I_DMA_NORMAL 3>,
1216			       <&dma SUN4I_DMA_NORMAL 3>;
1217			dma-names = "rx", "tx";
1218			status = "disabled";
1219		};
1220
1221		lradc: lradc@1c22800 {
1222			compatible = "allwinner,sun4i-a10-lradc-keys";
1223			reg = <0x01c22800 0x100>;
1224			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1225			status = "disabled";
1226		};
1227
1228		codec: codec@1c22c00 {
1229			#sound-dai-cells = <0>;
1230			compatible = "allwinner,sun7i-a20-codec";
1231			reg = <0x01c22c00 0x40>;
1232			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1233			clocks = <&ccu CLK_APB0_CODEC>, <&ccu CLK_CODEC>;
1234			clock-names = "apb", "codec";
1235			dmas = <&dma SUN4I_DMA_NORMAL 19>,
1236			       <&dma SUN4I_DMA_NORMAL 19>;
1237			dma-names = "rx", "tx";
1238			status = "disabled";
1239		};
1240
1241		sid: eeprom@1c23800 {
1242			compatible = "allwinner,sun7i-a20-sid";
1243			reg = <0x01c23800 0x200>;
1244		};
1245
1246		i2s2: i2s@1c24400 {
1247			#sound-dai-cells = <0>;
1248			compatible = "allwinner,sun4i-a10-i2s";
1249			reg = <0x01c24400 0x400>;
1250			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1251			clocks = <&ccu CLK_APB0_I2S2>, <&ccu CLK_I2S2>;
1252			clock-names = "apb", "mod";
1253			dmas = <&dma SUN4I_DMA_NORMAL 6>,
1254			       <&dma SUN4I_DMA_NORMAL 6>;
1255			dma-names = "rx", "tx";
1256			status = "disabled";
1257		};
1258
1259		rtp: rtp@1c25000 {
1260			compatible = "allwinner,sun5i-a13-ts";
1261			reg = <0x01c25000 0x100>;
1262			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
1263			#thermal-sensor-cells = <0>;
1264		};
1265
1266		uart0: serial@1c28000 {
1267			compatible = "snps,dw-apb-uart";
1268			reg = <0x01c28000 0x400>;
1269			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
1270			reg-shift = <2>;
1271			reg-io-width = <4>;
1272			clocks = <&ccu CLK_APB1_UART0>;
1273			status = "disabled";
1274		};
1275
1276		uart1: serial@1c28400 {
1277			compatible = "snps,dw-apb-uart";
1278			reg = <0x01c28400 0x400>;
1279			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
1280			reg-shift = <2>;
1281			reg-io-width = <4>;
1282			clocks = <&ccu CLK_APB1_UART1>;
1283			status = "disabled";
1284		};
1285
1286		uart2: serial@1c28800 {
1287			compatible = "snps,dw-apb-uart";
1288			reg = <0x01c28800 0x400>;
1289			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1290			reg-shift = <2>;
1291			reg-io-width = <4>;
1292			clocks = <&ccu CLK_APB1_UART2>;
1293			status = "disabled";
1294		};
1295
1296		uart3: serial@1c28c00 {
1297			compatible = "snps,dw-apb-uart";
1298			reg = <0x01c28c00 0x400>;
1299			interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
1300			reg-shift = <2>;
1301			reg-io-width = <4>;
1302			clocks = <&ccu CLK_APB1_UART3>;
1303			status = "disabled";
1304		};
1305
1306		uart4: serial@1c29000 {
1307			compatible = "snps,dw-apb-uart";
1308			reg = <0x01c29000 0x400>;
1309			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
1310			reg-shift = <2>;
1311			reg-io-width = <4>;
1312			clocks = <&ccu CLK_APB1_UART4>;
1313			status = "disabled";
1314		};
1315
1316		uart5: serial@1c29400 {
1317			compatible = "snps,dw-apb-uart";
1318			reg = <0x01c29400 0x400>;
1319			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
1320			reg-shift = <2>;
1321			reg-io-width = <4>;
1322			clocks = <&ccu CLK_APB1_UART5>;
1323			status = "disabled";
1324		};
1325
1326		uart6: serial@1c29800 {
1327			compatible = "snps,dw-apb-uart";
1328			reg = <0x01c29800 0x400>;
1329			interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1330			reg-shift = <2>;
1331			reg-io-width = <4>;
1332			clocks = <&ccu CLK_APB1_UART6>;
1333			status = "disabled";
1334		};
1335
1336		uart7: serial@1c29c00 {
1337			compatible = "snps,dw-apb-uart";
1338			reg = <0x01c29c00 0x400>;
1339			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1340			reg-shift = <2>;
1341			reg-io-width = <4>;
1342			clocks = <&ccu CLK_APB1_UART7>;
1343			status = "disabled";
1344		};
1345
1346		ps20: ps2@1c2a000 {
1347			compatible = "allwinner,sun4i-a10-ps2";
1348			reg = <0x01c2a000 0x400>;
1349			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1350			clocks = <&ccu CLK_APB1_PS20>;
1351			status = "disabled";
1352		};
1353
1354		ps21: ps2@1c2a400 {
1355			compatible = "allwinner,sun4i-a10-ps2";
1356			reg = <0x01c2a400 0x400>;
1357			interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
1358			clocks = <&ccu CLK_APB1_PS21>;
1359			status = "disabled";
1360		};
1361
1362		i2c0: i2c@1c2ac00 {
1363			compatible = "allwinner,sun7i-a20-i2c",
1364				     "allwinner,sun4i-a10-i2c";
1365			reg = <0x01c2ac00 0x400>;
1366			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
1367			clocks = <&ccu CLK_APB1_I2C0>;
1368			pinctrl-names = "default";
1369			pinctrl-0 = <&i2c0_pins>;
1370			status = "disabled";
1371			#address-cells = <1>;
1372			#size-cells = <0>;
1373		};
1374
1375		i2c1: i2c@1c2b000 {
1376			compatible = "allwinner,sun7i-a20-i2c",
1377				     "allwinner,sun4i-a10-i2c";
1378			reg = <0x01c2b000 0x400>;
1379			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
1380			clocks = <&ccu CLK_APB1_I2C1>;
1381			pinctrl-names = "default";
1382			pinctrl-0 = <&i2c1_pins>;
1383			status = "disabled";
1384			#address-cells = <1>;
1385			#size-cells = <0>;
1386		};
1387
1388		i2c2: i2c@1c2b400 {
1389			compatible = "allwinner,sun7i-a20-i2c",
1390				     "allwinner,sun4i-a10-i2c";
1391			reg = <0x01c2b400 0x400>;
1392			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1393			clocks = <&ccu CLK_APB1_I2C2>;
1394			pinctrl-names = "default";
1395			pinctrl-0 = <&i2c2_pins>;
1396			status = "disabled";
1397			#address-cells = <1>;
1398			#size-cells = <0>;
1399		};
1400
1401		i2c3: i2c@1c2b800 {
1402			compatible = "allwinner,sun7i-a20-i2c",
1403				     "allwinner,sun4i-a10-i2c";
1404			reg = <0x01c2b800 0x400>;
1405			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1406			clocks = <&ccu CLK_APB1_I2C3>;
1407			pinctrl-names = "default";
1408			pinctrl-0 = <&i2c3_pins>;
1409			status = "disabled";
1410			#address-cells = <1>;
1411			#size-cells = <0>;
1412		};
1413
1414		can0: can@1c2bc00 {
1415			compatible = "allwinner,sun7i-a20-can",
1416				     "allwinner,sun4i-a10-can";
1417			reg = <0x01c2bc00 0x400>;
1418			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
1419			clocks = <&ccu CLK_APB1_CAN>;
1420			status = "disabled";
1421		};
1422
1423		i2c4: i2c@1c2c000 {
1424			compatible = "allwinner,sun7i-a20-i2c",
1425				     "allwinner,sun4i-a10-i2c";
1426			reg = <0x01c2c000 0x400>;
1427			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1428			clocks = <&ccu CLK_APB1_I2C4>;
1429			status = "disabled";
1430			#address-cells = <1>;
1431			#size-cells = <0>;
1432		};
1433
1434		mali: gpu@1c40000 {
1435			compatible = "allwinner,sun7i-a20-mali", "arm,mali-400";
1436			reg = <0x01c40000 0x10000>;
1437			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1438				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1439				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1440				     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
1441				     <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
1442				     <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
1443				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
1444			interrupt-names = "gp",
1445					  "gpmmu",
1446					  "pp0",
1447					  "ppmmu0",
1448					  "pp1",
1449					  "ppmmu1",
1450					  "pmu";
1451			clocks = <&ccu CLK_AHB_GPU>, <&ccu CLK_GPU>;
1452			clock-names = "bus", "core";
1453			resets = <&ccu RST_GPU>;
1454
1455			assigned-clocks = <&ccu CLK_GPU>;
1456			assigned-clock-rates = <384000000>;
1457		};
1458
1459		gmac: ethernet@1c50000 {
1460			compatible = "allwinner,sun7i-a20-gmac";
1461			reg = <0x01c50000 0x10000>;
1462			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
1463			interrupt-names = "macirq";
1464			clocks = <&ccu CLK_AHB_GMAC>, <&gmac_tx_clk>;
1465			clock-names = "stmmaceth", "allwinner_gmac_tx";
1466			snps,pbl = <2>;
1467			snps,fixed-burst;
1468			snps,force_sf_dma_mode;
1469			status = "disabled";
1470
1471			gmac_mdio: mdio {
1472				compatible = "snps,dwmac-mdio";
1473				#address-cells = <1>;
1474				#size-cells = <0>;
1475			};
1476		};
1477
1478		hstimer@1c60000 {
1479			compatible = "allwinner,sun7i-a20-hstimer";
1480			reg = <0x01c60000 0x1000>;
1481			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
1482				     <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
1483				     <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
1484				     <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1485			clocks = <&ccu CLK_AHB_HSTIMER>;
1486		};
1487
1488		gic: interrupt-controller@1c81000 {
1489			compatible = "arm,gic-400";
1490			reg = <0x01c81000 0x1000>,
1491			      <0x01c82000 0x2000>,
1492			      <0x01c84000 0x2000>,
1493			      <0x01c86000 0x2000>;
1494			interrupt-controller;
1495			#interrupt-cells = <3>;
1496			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
1497		};
1498
1499		fe0: display-frontend@1e00000 {
1500			compatible = "allwinner,sun7i-a20-display-frontend";
1501			reg = <0x01e00000 0x20000>;
1502			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1503			clocks = <&ccu CLK_AHB_DE_FE0>, <&ccu CLK_DE_FE0>,
1504				 <&ccu CLK_DRAM_DE_FE0>;
1505			clock-names = "ahb", "mod",
1506				      "ram";
1507			resets = <&ccu RST_DE_FE0>;
1508
1509			ports {
1510				#address-cells = <1>;
1511				#size-cells = <0>;
1512
1513				fe0_out: port@1 {
1514					#address-cells = <1>;
1515					#size-cells = <0>;
1516					reg = <1>;
1517
1518					fe0_out_be0: endpoint@0 {
1519						reg = <0>;
1520						remote-endpoint = <&be0_in_fe0>;
1521					};
1522
1523					fe0_out_be1: endpoint@1 {
1524						reg = <1>;
1525						remote-endpoint = <&be1_in_fe0>;
1526					};
1527				};
1528			};
1529		};
1530
1531		fe1: display-frontend@1e20000 {
1532			compatible = "allwinner,sun7i-a20-display-frontend";
1533			reg = <0x01e20000 0x20000>;
1534			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1535			clocks = <&ccu CLK_AHB_DE_FE1>, <&ccu CLK_DE_FE1>,
1536				 <&ccu CLK_DRAM_DE_FE1>;
1537			clock-names = "ahb", "mod",
1538				      "ram";
1539			resets = <&ccu RST_DE_FE1>;
1540
1541			ports {
1542				#address-cells = <1>;
1543				#size-cells = <0>;
1544
1545				fe1_out: port@1 {
1546					#address-cells = <1>;
1547					#size-cells = <0>;
1548					reg = <1>;
1549
1550					fe1_out_be0: endpoint@0 {
1551						reg = <0>;
1552						remote-endpoint = <&be0_in_fe1>;
1553					};
1554
1555					fe1_out_be1: endpoint@1 {
1556						reg = <1>;
1557						remote-endpoint = <&be1_in_fe1>;
1558					};
1559				};
1560			};
1561		};
1562
1563		be1: display-backend@1e40000 {
1564			compatible = "allwinner,sun7i-a20-display-backend";
1565			reg = <0x01e40000 0x10000>;
1566			interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1567			clocks = <&ccu CLK_AHB_DE_BE1>, <&ccu CLK_DE_BE1>,
1568				 <&ccu CLK_DRAM_DE_BE1>;
1569			clock-names = "ahb", "mod",
1570				      "ram";
1571			resets = <&ccu RST_DE_BE1>;
1572
1573			ports {
1574				#address-cells = <1>;
1575				#size-cells = <0>;
1576
1577				be1_in: port@0 {
1578					#address-cells = <1>;
1579					#size-cells = <0>;
1580					reg = <0>;
1581
1582					be1_in_fe0: endpoint@0 {
1583						reg = <0>;
1584						remote-endpoint = <&fe0_out_be1>;
1585					};
1586
1587					be1_in_fe1: endpoint@1 {
1588						reg = <1>;
1589						remote-endpoint = <&fe1_out_be1>;
1590					};
1591				};
1592
1593				be1_out: port@1 {
1594					#address-cells = <1>;
1595					#size-cells = <0>;
1596					reg = <1>;
1597
1598					be1_out_tcon0: endpoint@0 {
1599						reg = <0>;
1600						remote-endpoint = <&tcon0_in_be1>;
1601					};
1602
1603					be1_out_tcon1: endpoint@1 {
1604						reg = <1>;
1605						remote-endpoint = <&tcon1_in_be1>;
1606					};
1607				};
1608			};
1609		};
1610
1611		be0: display-backend@1e60000 {
1612			compatible = "allwinner,sun7i-a20-display-backend";
1613			reg = <0x01e60000 0x10000>;
1614			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1615			clocks = <&ccu CLK_AHB_DE_BE0>, <&ccu CLK_DE_BE0>,
1616				 <&ccu CLK_DRAM_DE_BE0>;
1617			clock-names = "ahb", "mod",
1618				      "ram";
1619			resets = <&ccu RST_DE_BE0>;
1620
1621			ports {
1622				#address-cells = <1>;
1623				#size-cells = <0>;
1624
1625				be0_in: port@0 {
1626					#address-cells = <1>;
1627					#size-cells = <0>;
1628					reg = <0>;
1629
1630					be0_in_fe0: endpoint@0 {
1631						reg = <0>;
1632						remote-endpoint = <&fe0_out_be0>;
1633					};
1634
1635					be0_in_fe1: endpoint@1 {
1636						reg = <1>;
1637						remote-endpoint = <&fe1_out_be0>;
1638					};
1639				};
1640
1641				be0_out: port@1 {
1642					#address-cells = <1>;
1643					#size-cells = <0>;
1644					reg = <1>;
1645
1646					be0_out_tcon0: endpoint@0 {
1647						reg = <0>;
1648						remote-endpoint = <&tcon0_in_be0>;
1649					};
1650
1651					be0_out_tcon1: endpoint@1 {
1652						reg = <1>;
1653						remote-endpoint = <&tcon1_in_be0>;
1654					};
1655				};
1656			};
1657		};
1658	};
1659};