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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
4 *
5 * Based on "omap4.dtsi"
6 */
7
8#include <dt-bindings/bus/ti-sysc.h>
9#include <dt-bindings/clock/dra7.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/pinctrl/dra.h>
12#include <dt-bindings/clock/dra7.h>
13
14#define MAX_SOURCES 400
15
16/ {
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 compatible = "ti,dra7xx";
21 interrupt-parent = <&crossbar_mpu>;
22 chosen { };
23
24 aliases {
25 i2c0 = &i2c1;
26 i2c1 = &i2c2;
27 i2c2 = &i2c3;
28 i2c3 = &i2c4;
29 i2c4 = &i2c5;
30 serial0 = &uart1;
31 serial1 = &uart2;
32 serial2 = &uart3;
33 serial3 = &uart4;
34 serial4 = &uart5;
35 serial5 = &uart6;
36 serial6 = &uart7;
37 serial7 = &uart8;
38 serial8 = &uart9;
39 serial9 = &uart10;
40 ethernet0 = &cpsw_emac0;
41 ethernet1 = &cpsw_emac1;
42 d_can0 = &dcan1;
43 d_can1 = &dcan2;
44 spi0 = &qspi;
45 };
46
47 timer {
48 compatible = "arm,armv7-timer";
49 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
52 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
53 interrupt-parent = <&gic>;
54 };
55
56 gic: interrupt-controller@48211000 {
57 compatible = "arm,cortex-a15-gic";
58 interrupt-controller;
59 #interrupt-cells = <3>;
60 reg = <0x0 0x48211000 0x0 0x1000>,
61 <0x0 0x48212000 0x0 0x2000>,
62 <0x0 0x48214000 0x0 0x2000>,
63 <0x0 0x48216000 0x0 0x2000>;
64 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
65 interrupt-parent = <&gic>;
66 };
67
68 wakeupgen: interrupt-controller@48281000 {
69 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
70 interrupt-controller;
71 #interrupt-cells = <3>;
72 reg = <0x0 0x48281000 0x0 0x1000>;
73 interrupt-parent = <&gic>;
74 };
75
76 cpus {
77 #address-cells = <1>;
78 #size-cells = <0>;
79
80 cpu0: cpu@0 {
81 device_type = "cpu";
82 compatible = "arm,cortex-a15";
83 reg = <0>;
84
85 operating-points-v2 = <&cpu0_opp_table>;
86
87 clocks = <&dpll_mpu_ck>;
88 clock-names = "cpu";
89
90 clock-latency = <300000>; /* From omap-cpufreq driver */
91
92 /* cooling options */
93 #cooling-cells = <2>; /* min followed by max */
94
95 vbb-supply = <&abb_mpu>;
96 };
97 };
98
99 cpu0_opp_table: opp-table {
100 compatible = "operating-points-v2-ti-cpu";
101 syscon = <&scm_wkup>;
102
103 opp_nom-1000000000 {
104 opp-hz = /bits/ 64 <1000000000>;
105 opp-microvolt = <1060000 850000 1150000>,
106 <1060000 850000 1150000>;
107 opp-supported-hw = <0xFF 0x01>;
108 opp-suspend;
109 };
110
111 opp_od-1176000000 {
112 opp-hz = /bits/ 64 <1176000000>;
113 opp-microvolt = <1160000 885000 1160000>,
114 <1160000 885000 1160000>;
115
116 opp-supported-hw = <0xFF 0x02>;
117 };
118
119 opp_high@1500000000 {
120 opp-hz = /bits/ 64 <1500000000>;
121 opp-microvolt = <1210000 950000 1250000>,
122 <1210000 950000 1250000>;
123 opp-supported-hw = <0xFF 0x04>;
124 };
125 };
126
127 /*
128 * The soc node represents the soc top level view. It is used for IPs
129 * that are not memory mapped in the MPU view or for the MPU itself.
130 */
131 soc {
132 compatible = "ti,omap-infra";
133 mpu {
134 compatible = "ti,omap5-mpu";
135 ti,hwmods = "mpu";
136 };
137 };
138
139 /*
140 * XXX: Use a flat representation of the SOC interconnect.
141 * The real OMAP interconnect network is quite complex.
142 * Since it will not bring real advantage to represent that in DT for
143 * the moment, just use a fake OCP bus entry to represent the whole bus
144 * hierarchy.
145 */
146 ocp {
147 compatible = "ti,dra7-l3-noc", "simple-bus";
148 #address-cells = <1>;
149 #size-cells = <1>;
150 ranges = <0x0 0x0 0x0 0xc0000000>;
151 ti,hwmods = "l3_main_1", "l3_main_2";
152 reg = <0x0 0x44000000 0x0 0x1000000>,
153 <0x0 0x45000000 0x0 0x1000>;
154 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
155 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
156
157 l4_cfg: interconnect@4a000000 {
158 };
159 l4_wkup: interconnect@4ae00000 {
160 };
161 l4_per1: interconnect@48000000 {
162 };
163 l4_per2: interconnect@48400000 {
164 };
165 l4_per3: interconnect@48800000 {
166 };
167
168 axi@0 {
169 compatible = "simple-bus";
170 #size-cells = <1>;
171 #address-cells = <1>;
172 ranges = <0x51000000 0x51000000 0x3000
173 0x0 0x20000000 0x10000000>;
174 /**
175 * To enable PCI endpoint mode, disable the pcie1_rc
176 * node and enable pcie1_ep mode.
177 */
178 pcie1_rc: pcie@51000000 {
179 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
180 reg-names = "rc_dbics", "ti_conf", "config";
181 interrupts = <0 232 0x4>, <0 233 0x4>;
182 #address-cells = <3>;
183 #size-cells = <2>;
184 device_type = "pci";
185 ranges = <0x81000000 0 0 0x03000 0 0x00010000
186 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
187 bus-range = <0x00 0xff>;
188 #interrupt-cells = <1>;
189 num-lanes = <1>;
190 linux,pci-domain = <0>;
191 ti,hwmods = "pcie1";
192 phys = <&pcie1_phy>;
193 phy-names = "pcie-phy0";
194 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
195 interrupt-map-mask = <0 0 0 7>;
196 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
197 <0 0 0 2 &pcie1_intc 2>,
198 <0 0 0 3 &pcie1_intc 3>,
199 <0 0 0 4 &pcie1_intc 4>;
200 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
201 status = "disabled";
202 pcie1_intc: interrupt-controller {
203 interrupt-controller;
204 #address-cells = <0>;
205 #interrupt-cells = <1>;
206 };
207 };
208
209 pcie1_ep: pcie_ep@51000000 {
210 reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;
211 reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
212 interrupts = <0 232 0x4>;
213 num-lanes = <1>;
214 num-ib-windows = <4>;
215 num-ob-windows = <16>;
216 ti,hwmods = "pcie1";
217 phys = <&pcie1_phy>;
218 phy-names = "pcie-phy0";
219 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
220 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
221 status = "disabled";
222 };
223 };
224
225 axi@1 {
226 compatible = "simple-bus";
227 #size-cells = <1>;
228 #address-cells = <1>;
229 ranges = <0x51800000 0x51800000 0x3000
230 0x0 0x30000000 0x10000000>;
231 status = "disabled";
232 pcie2_rc: pcie@51800000 {
233 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
234 reg-names = "rc_dbics", "ti_conf", "config";
235 interrupts = <0 355 0x4>, <0 356 0x4>;
236 #address-cells = <3>;
237 #size-cells = <2>;
238 device_type = "pci";
239 ranges = <0x81000000 0 0 0x03000 0 0x00010000
240 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
241 bus-range = <0x00 0xff>;
242 #interrupt-cells = <1>;
243 num-lanes = <1>;
244 linux,pci-domain = <1>;
245 ti,hwmods = "pcie2";
246 phys = <&pcie2_phy>;
247 phy-names = "pcie-phy0";
248 interrupt-map-mask = <0 0 0 7>;
249 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
250 <0 0 0 2 &pcie2_intc 2>,
251 <0 0 0 3 &pcie2_intc 3>,
252 <0 0 0 4 &pcie2_intc 4>;
253 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
254 pcie2_intc: interrupt-controller {
255 interrupt-controller;
256 #address-cells = <0>;
257 #interrupt-cells = <1>;
258 };
259 };
260 };
261
262 ocmcram1: ocmcram@40300000 {
263 compatible = "mmio-sram";
264 reg = <0x40300000 0x80000>;
265 ranges = <0x0 0x40300000 0x80000>;
266 #address-cells = <1>;
267 #size-cells = <1>;
268 /*
269 * This is a placeholder for an optional reserved
270 * region for use by secure software. The size
271 * of this region is not known until runtime so it
272 * is set as zero to either be updated to reserve
273 * space or left unchanged to leave all SRAM for use.
274 * On HS parts that that require the reserved region
275 * either the bootloader can update the size to
276 * the required amount or the node can be overridden
277 * from the board dts file for the secure platform.
278 */
279 sram-hs@0 {
280 compatible = "ti,secure-ram";
281 reg = <0x0 0x0>;
282 };
283 };
284
285 /*
286 * NOTE: ocmcram2 and ocmcram3 are not available on all
287 * DRA7xx and AM57xx variants. Confirm availability in
288 * the data manual for the exact part number in use
289 * before enabling these nodes in the board dts file.
290 */
291 ocmcram2: ocmcram@40400000 {
292 status = "disabled";
293 compatible = "mmio-sram";
294 reg = <0x40400000 0x100000>;
295 ranges = <0x0 0x40400000 0x100000>;
296 #address-cells = <1>;
297 #size-cells = <1>;
298 };
299
300 ocmcram3: ocmcram@40500000 {
301 status = "disabled";
302 compatible = "mmio-sram";
303 reg = <0x40500000 0x100000>;
304 ranges = <0x0 0x40500000 0x100000>;
305 #address-cells = <1>;
306 #size-cells = <1>;
307 };
308
309 bandgap: bandgap@4a0021e0 {
310 reg = <0x4a0021e0 0xc
311 0x4a00232c 0xc
312 0x4a002380 0x2c
313 0x4a0023C0 0x3c
314 0x4a002564 0x8
315 0x4a002574 0x50>;
316 compatible = "ti,dra752-bandgap";
317 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
318 #thermal-sensor-cells = <1>;
319 };
320
321 dsp1_system: dsp_system@40d00000 {
322 compatible = "syscon";
323 reg = <0x40d00000 0x100>;
324 };
325
326 dra7_iodelay_core: padconf@4844a000 {
327 compatible = "ti,dra7-iodelay";
328 reg = <0x4844a000 0x0d1c>;
329 #address-cells = <1>;
330 #size-cells = <0>;
331 #pinctrl-cells = <2>;
332 };
333
334 edma: edma@43300000 {
335 compatible = "ti,edma3-tpcc";
336 ti,hwmods = "tpcc";
337 reg = <0x43300000 0x100000>;
338 reg-names = "edma3_cc";
339 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
340 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
342 interrupt-names = "edma3_ccint", "edma3_mperr",
343 "edma3_ccerrint";
344 dma-requests = <64>;
345 #dma-cells = <2>;
346
347 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
348
349 /*
350 * memcpy is disabled, can be enabled with:
351 * ti,edma-memcpy-channels = <20 21>;
352 * for example. Note that these channels need to be
353 * masked in the xbar as well.
354 */
355 };
356
357 edma_tptc0: tptc@43400000 {
358 compatible = "ti,edma3-tptc";
359 ti,hwmods = "tptc0";
360 reg = <0x43400000 0x100000>;
361 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
362 interrupt-names = "edma3_tcerrint";
363 };
364
365 edma_tptc1: tptc@43500000 {
366 compatible = "ti,edma3-tptc";
367 ti,hwmods = "tptc1";
368 reg = <0x43500000 0x100000>;
369 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
370 interrupt-names = "edma3_tcerrint";
371 };
372
373 dmm@4e000000 {
374 compatible = "ti,omap5-dmm";
375 reg = <0x4e000000 0x800>;
376 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
377 ti,hwmods = "dmm";
378 };
379
380 mmu0_dsp1: mmu@40d01000 {
381 compatible = "ti,dra7-dsp-iommu";
382 reg = <0x40d01000 0x100>;
383 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
384 ti,hwmods = "mmu0_dsp1";
385 #iommu-cells = <0>;
386 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
387 status = "disabled";
388 };
389
390 mmu1_dsp1: mmu@40d02000 {
391 compatible = "ti,dra7-dsp-iommu";
392 reg = <0x40d02000 0x100>;
393 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
394 ti,hwmods = "mmu1_dsp1";
395 #iommu-cells = <0>;
396 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
397 status = "disabled";
398 };
399
400 mmu_ipu1: mmu@58882000 {
401 compatible = "ti,dra7-iommu";
402 reg = <0x58882000 0x100>;
403 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
404 ti,hwmods = "mmu_ipu1";
405 #iommu-cells = <0>;
406 ti,iommu-bus-err-back;
407 status = "disabled";
408 };
409
410 mmu_ipu2: mmu@55082000 {
411 compatible = "ti,dra7-iommu";
412 reg = <0x55082000 0x100>;
413 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
414 ti,hwmods = "mmu_ipu2";
415 #iommu-cells = <0>;
416 ti,iommu-bus-err-back;
417 status = "disabled";
418 };
419
420 abb_mpu: regulator-abb-mpu {
421 compatible = "ti,abb-v3";
422 regulator-name = "abb_mpu";
423 #address-cells = <0>;
424 #size-cells = <0>;
425 clocks = <&sys_clkin1>;
426 ti,settling-time = <50>;
427 ti,clock-cycles = <16>;
428
429 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
430 <0x4ae06014 0x4>, <0x4a003b20 0xc>,
431 <0x4ae0c158 0x4>;
432 reg-names = "setup-address", "control-address",
433 "int-address", "efuse-address",
434 "ldo-address";
435 ti,tranxdone-status-mask = <0x80>;
436 /* LDOVBBMPU_FBB_MUX_CTRL */
437 ti,ldovbb-override-mask = <0x400>;
438 /* LDOVBBMPU_FBB_VSET_OUT */
439 ti,ldovbb-vset-mask = <0x1F>;
440
441 /*
442 * NOTE: only FBB mode used but actual vset will
443 * determine final biasing
444 */
445 ti,abb_info = <
446 /*uV ABB efuse rbb_m fbb_m vset_m*/
447 1060000 0 0x0 0 0x02000000 0x01F00000
448 1160000 0 0x4 0 0x02000000 0x01F00000
449 1210000 0 0x8 0 0x02000000 0x01F00000
450 >;
451 };
452
453 abb_ivahd: regulator-abb-ivahd {
454 compatible = "ti,abb-v3";
455 regulator-name = "abb_ivahd";
456 #address-cells = <0>;
457 #size-cells = <0>;
458 clocks = <&sys_clkin1>;
459 ti,settling-time = <50>;
460 ti,clock-cycles = <16>;
461
462 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
463 <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
464 <0x4a002470 0x4>;
465 reg-names = "setup-address", "control-address",
466 "int-address", "efuse-address",
467 "ldo-address";
468 ti,tranxdone-status-mask = <0x40000000>;
469 /* LDOVBBIVA_FBB_MUX_CTRL */
470 ti,ldovbb-override-mask = <0x400>;
471 /* LDOVBBIVA_FBB_VSET_OUT */
472 ti,ldovbb-vset-mask = <0x1F>;
473
474 /*
475 * NOTE: only FBB mode used but actual vset will
476 * determine final biasing
477 */
478 ti,abb_info = <
479 /*uV ABB efuse rbb_m fbb_m vset_m*/
480 1055000 0 0x0 0 0x02000000 0x01F00000
481 1150000 0 0x4 0 0x02000000 0x01F00000
482 1250000 0 0x8 0 0x02000000 0x01F00000
483 >;
484 };
485
486 abb_dspeve: regulator-abb-dspeve {
487 compatible = "ti,abb-v3";
488 regulator-name = "abb_dspeve";
489 #address-cells = <0>;
490 #size-cells = <0>;
491 clocks = <&sys_clkin1>;
492 ti,settling-time = <50>;
493 ti,clock-cycles = <16>;
494
495 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
496 <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
497 <0x4a00246c 0x4>;
498 reg-names = "setup-address", "control-address",
499 "int-address", "efuse-address",
500 "ldo-address";
501 ti,tranxdone-status-mask = <0x20000000>;
502 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
503 ti,ldovbb-override-mask = <0x400>;
504 /* LDOVBBDSPEVE_FBB_VSET_OUT */
505 ti,ldovbb-vset-mask = <0x1F>;
506
507 /*
508 * NOTE: only FBB mode used but actual vset will
509 * determine final biasing
510 */
511 ti,abb_info = <
512 /*uV ABB efuse rbb_m fbb_m vset_m*/
513 1055000 0 0x0 0 0x02000000 0x01F00000
514 1150000 0 0x4 0 0x02000000 0x01F00000
515 1250000 0 0x8 0 0x02000000 0x01F00000
516 >;
517 };
518
519 abb_gpu: regulator-abb-gpu {
520 compatible = "ti,abb-v3";
521 regulator-name = "abb_gpu";
522 #address-cells = <0>;
523 #size-cells = <0>;
524 clocks = <&sys_clkin1>;
525 ti,settling-time = <50>;
526 ti,clock-cycles = <16>;
527
528 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
529 <0x4ae06010 0x4>, <0x4a003b08 0xc>,
530 <0x4ae0c154 0x4>;
531 reg-names = "setup-address", "control-address",
532 "int-address", "efuse-address",
533 "ldo-address";
534 ti,tranxdone-status-mask = <0x10000000>;
535 /* LDOVBBGPU_FBB_MUX_CTRL */
536 ti,ldovbb-override-mask = <0x400>;
537 /* LDOVBBGPU_FBB_VSET_OUT */
538 ti,ldovbb-vset-mask = <0x1F>;
539
540 /*
541 * NOTE: only FBB mode used but actual vset will
542 * determine final biasing
543 */
544 ti,abb_info = <
545 /*uV ABB efuse rbb_m fbb_m vset_m*/
546 1090000 0 0x0 0 0x02000000 0x01F00000
547 1210000 0 0x4 0 0x02000000 0x01F00000
548 1280000 0 0x8 0 0x02000000 0x01F00000
549 >;
550 };
551
552 qspi: spi@4b300000 {
553 compatible = "ti,dra7xxx-qspi";
554 reg = <0x4b300000 0x100>,
555 <0x5c000000 0x4000000>;
556 reg-names = "qspi_base", "qspi_mmap";
557 syscon-chipselects = <&scm_conf 0x558>;
558 #address-cells = <1>;
559 #size-cells = <0>;
560 ti,hwmods = "qspi";
561 clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>;
562 clock-names = "fck";
563 num-cs = <4>;
564 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
565 status = "disabled";
566 };
567
568 /* OCP2SCP3 */
569 sata: sata@4a141100 {
570 compatible = "snps,dwc-ahci";
571 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
572 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
573 phys = <&sata_phy>;
574 phy-names = "sata-phy";
575 clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;
576 ti,hwmods = "sata";
577 ports-implemented = <0x1>;
578 };
579
580 /* OCP2SCP1 */
581 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
582 gpmc: gpmc@50000000 {
583 compatible = "ti,am3352-gpmc";
584 ti,hwmods = "gpmc";
585 reg = <0x50000000 0x37c>; /* device IO registers */
586 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
587 dmas = <&edma_xbar 4 0>;
588 dma-names = "rxtx";
589 gpmc,num-cs = <8>;
590 gpmc,num-waitpins = <2>;
591 #address-cells = <2>;
592 #size-cells = <1>;
593 interrupt-controller;
594 #interrupt-cells = <2>;
595 gpio-controller;
596 #gpio-cells = <2>;
597 status = "disabled";
598 };
599
600 crossbar_mpu: crossbar@4a002a48 {
601 compatible = "ti,irq-crossbar";
602 reg = <0x4a002a48 0x130>;
603 interrupt-controller;
604 interrupt-parent = <&wakeupgen>;
605 #interrupt-cells = <3>;
606 ti,max-irqs = <160>;
607 ti,max-crossbar-sources = <MAX_SOURCES>;
608 ti,reg-size = <2>;
609 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
610 ti,irqs-skip = <10 133 139 140>;
611 ti,irqs-safe-map = <0>;
612 };
613
614 dss: dss@58000000 {
615 compatible = "ti,dra7-dss";
616 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
617 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
618 status = "disabled";
619 ti,hwmods = "dss_core";
620 /* CTRL_CORE_DSS_PLL_CONTROL */
621 syscon-pll-ctrl = <&scm_conf 0x538>;
622 #address-cells = <1>;
623 #size-cells = <1>;
624 ranges;
625
626 dispc@58001000 {
627 compatible = "ti,dra7-dispc";
628 reg = <0x58001000 0x1000>;
629 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
630 ti,hwmods = "dss_dispc";
631 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
632 clock-names = "fck";
633 /* CTRL_CORE_SMA_SW_1 */
634 syscon-pol = <&scm_conf 0x534>;
635 };
636
637 hdmi: encoder@58060000 {
638 compatible = "ti,dra7-hdmi";
639 reg = <0x58040000 0x200>,
640 <0x58040200 0x80>,
641 <0x58040300 0x80>,
642 <0x58060000 0x19000>;
643 reg-names = "wp", "pll", "phy", "core";
644 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
645 status = "disabled";
646 ti,hwmods = "dss_hdmi";
647 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
648 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>;
649 clock-names = "fck", "sys_clk";
650 dmas = <&sdma_xbar 76>;
651 dma-names = "audio_tx";
652 };
653 };
654
655 aes1: aes@4b500000 {
656 compatible = "ti,omap4-aes";
657 ti,hwmods = "aes1";
658 reg = <0x4b500000 0xa0>;
659 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
660 dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
661 dma-names = "tx", "rx";
662 clocks = <&l3_iclk_div>;
663 clock-names = "fck";
664 };
665
666 aes2: aes@4b700000 {
667 compatible = "ti,omap4-aes";
668 ti,hwmods = "aes2";
669 reg = <0x4b700000 0xa0>;
670 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
671 dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
672 dma-names = "tx", "rx";
673 clocks = <&l3_iclk_div>;
674 clock-names = "fck";
675 };
676
677 des: des@480a5000 {
678 compatible = "ti,omap4-des";
679 ti,hwmods = "des";
680 reg = <0x480a5000 0xa0>;
681 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
682 dmas = <&sdma_xbar 117>, <&sdma_xbar 116>;
683 dma-names = "tx", "rx";
684 clocks = <&l3_iclk_div>;
685 clock-names = "fck";
686 };
687
688 sham: sham@53100000 {
689 compatible = "ti,omap5-sham";
690 ti,hwmods = "sham";
691 reg = <0x4b101000 0x300>;
692 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
693 dmas = <&edma_xbar 119 0>;
694 dma-names = "rx";
695 clocks = <&l3_iclk_div>;
696 clock-names = "fck";
697 };
698
699 opp_supply_mpu: opp-supply@4a003b20 {
700 compatible = "ti,omap5-opp-supply";
701 reg = <0x4a003b20 0xc>;
702 ti,efuse-settings = <
703 /* uV offset */
704 1060000 0x0
705 1160000 0x4
706 1210000 0x8
707 >;
708 ti,absolute-max-voltage-uv = <1500000>;
709 };
710
711 };
712
713 thermal_zones: thermal-zones {
714 #include "omap4-cpu-thermal.dtsi"
715 #include "omap5-gpu-thermal.dtsi"
716 #include "omap5-core-thermal.dtsi"
717 #include "dra7-dspeve-thermal.dtsi"
718 #include "dra7-iva-thermal.dtsi"
719 };
720
721};
722
723&cpu_thermal {
724 polling-delay = <500>; /* milliseconds */
725 coefficients = <0 2000>;
726};
727
728&gpu_thermal {
729 coefficients = <0 2000>;
730};
731
732&core_thermal {
733 coefficients = <0 2000>;
734};
735
736&dspeve_thermal {
737 coefficients = <0 2000>;
738};
739
740&iva_thermal {
741 coefficients = <0 2000>;
742};
743
744&cpu_crit {
745 temperature = <120000>; /* milli Celsius */
746};
747
748&core_crit {
749 temperature = <120000>; /* milli Celsius */
750};
751
752&gpu_crit {
753 temperature = <120000>; /* milli Celsius */
754};
755
756&dspeve_crit {
757 temperature = <120000>; /* milli Celsius */
758};
759
760&iva_crit {
761 temperature = <120000>; /* milli Celsius */
762};
763
764#include "dra7-l4.dtsi"
765#include "dra7xx-clocks.dtsi"
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com/
4 *
5 * Based on "omap4.dtsi"
6 */
7
8#include <dt-bindings/bus/ti-sysc.h>
9#include <dt-bindings/clock/dra7.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/pinctrl/dra.h>
12#include <dt-bindings/clock/dra7.h>
13
14#define MAX_SOURCES 400
15
16/ {
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 compatible = "ti,dra7xx";
21 interrupt-parent = <&crossbar_mpu>;
22 chosen { };
23
24 aliases {
25 i2c0 = &i2c1;
26 i2c1 = &i2c2;
27 i2c2 = &i2c3;
28 i2c3 = &i2c4;
29 i2c4 = &i2c5;
30 serial0 = &uart1;
31 serial1 = &uart2;
32 serial2 = &uart3;
33 serial3 = &uart4;
34 serial4 = &uart5;
35 serial5 = &uart6;
36 serial6 = &uart7;
37 serial7 = &uart8;
38 serial8 = &uart9;
39 serial9 = &uart10;
40 ethernet0 = &cpsw_port1;
41 ethernet1 = &cpsw_port2;
42 d_can0 = &dcan1;
43 d_can1 = &dcan2;
44 spi0 = &qspi;
45 };
46
47 timer {
48 compatible = "arm,armv7-timer";
49 status = "disabled"; /* See ARM architected timer wrap erratum i940 */
50 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
52 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
53 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
54 interrupt-parent = <&gic>;
55 };
56
57 gic: interrupt-controller@48211000 {
58 compatible = "arm,cortex-a15-gic";
59 interrupt-controller;
60 #interrupt-cells = <3>;
61 reg = <0x0 0x48211000 0x0 0x1000>,
62 <0x0 0x48212000 0x0 0x2000>,
63 <0x0 0x48214000 0x0 0x2000>,
64 <0x0 0x48216000 0x0 0x2000>;
65 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
66 interrupt-parent = <&gic>;
67 };
68
69 wakeupgen: interrupt-controller@48281000 {
70 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
71 interrupt-controller;
72 #interrupt-cells = <3>;
73 reg = <0x0 0x48281000 0x0 0x1000>;
74 interrupt-parent = <&gic>;
75 };
76
77 cpus {
78 #address-cells = <1>;
79 #size-cells = <0>;
80
81 cpu0: cpu@0 {
82 device_type = "cpu";
83 compatible = "arm,cortex-a15";
84 reg = <0>;
85
86 operating-points-v2 = <&cpu0_opp_table>;
87
88 clocks = <&dpll_mpu_ck>;
89 clock-names = "cpu";
90
91 clock-latency = <300000>; /* From omap-cpufreq driver */
92
93 /* cooling options */
94 #cooling-cells = <2>; /* min followed by max */
95
96 vbb-supply = <&abb_mpu>;
97 };
98 };
99
100 cpu0_opp_table: opp-table {
101 compatible = "operating-points-v2-ti-cpu";
102 syscon = <&scm_wkup>;
103
104 opp_nom-1000000000 {
105 opp-hz = /bits/ 64 <1000000000>;
106 opp-microvolt = <1060000 850000 1150000>,
107 <1060000 850000 1150000>;
108 opp-supported-hw = <0xFF 0x01>;
109 opp-suspend;
110 };
111
112 opp_od-1176000000 {
113 opp-hz = /bits/ 64 <1176000000>;
114 opp-microvolt = <1160000 885000 1160000>,
115 <1160000 885000 1160000>;
116
117 opp-supported-hw = <0xFF 0x02>;
118 };
119
120 opp_high@1500000000 {
121 opp-hz = /bits/ 64 <1500000000>;
122 opp-microvolt = <1210000 950000 1250000>,
123 <1210000 950000 1250000>;
124 opp-supported-hw = <0xFF 0x04>;
125 };
126 };
127
128 /*
129 * XXX: Use a flat representation of the SOC interconnect.
130 * The real OMAP interconnect network is quite complex.
131 * Since it will not bring real advantage to represent that in DT for
132 * the moment, just use a fake OCP bus entry to represent the whole bus
133 * hierarchy.
134 */
135 ocp: ocp {
136 compatible = "simple-pm-bus";
137 power-domains = <&prm_core>;
138 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_L3_MAIN_1_CLKCTRL 0>,
139 <&l3instr_clkctrl DRA7_L3INSTR_L3_MAIN_2_CLKCTRL 0>;
140 #address-cells = <1>;
141 #size-cells = <1>;
142 ranges = <0x0 0x0 0x0 0xc0000000>;
143 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
144
145 l3-noc@44000000 {
146 compatible = "ti,dra7-l3-noc";
147 reg = <0x44000000 0x1000>,
148 <0x45000000 0x1000>;
149 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
150 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
151 };
152
153 l4_cfg: interconnect@4a000000 {
154 };
155 l4_wkup: interconnect@4ae00000 {
156 };
157 l4_per1: interconnect@48000000 {
158 };
159
160 target-module@48210000 {
161 compatible = "ti,sysc-omap4-simple", "ti,sysc";
162 power-domains = <&prm_mpu>;
163 clocks = <&mpu_clkctrl DRA7_MPU_CLKCTRL 0>;
164 clock-names = "fck";
165 #address-cells = <1>;
166 #size-cells = <1>;
167 ranges = <0 0x48210000 0x1f0000>;
168
169 mpu {
170 compatible = "ti,omap5-mpu";
171 };
172 };
173
174 l4_per2: interconnect@48400000 {
175 };
176 l4_per3: interconnect@48800000 {
177 };
178
179 /*
180 * Register access seems to have complex dependencies and also
181 * seems to need an enabled phy. See the TRM chapter for "Table
182 * 26-678. Main Sequence PCIe Controller Global Initialization"
183 * and also dra7xx_pcie_probe().
184 */
185 axi0: target-module@51000000 {
186 compatible = "ti,sysc-omap4", "ti,sysc";
187 power-domains = <&prm_l3init>;
188 resets = <&prm_l3init 0>;
189 reset-names = "rstctrl";
190 clocks = <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 0>,
191 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>,
192 <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>;
193 clock-names = "fck", "phy-clk", "phy-clk-div";
194 #size-cells = <1>;
195 #address-cells = <1>;
196 ranges = <0x51000000 0x51000000 0x3000>,
197 <0x20000000 0x20000000 0x10000000>;
198 dma-ranges;
199 /**
200 * To enable PCI endpoint mode, disable the pcie1_rc
201 * node and enable pcie1_ep mode.
202 */
203 pcie1_rc: pcie@51000000 {
204 reg = <0x51000000 0x2000>,
205 <0x51002000 0x14c>,
206 <0x20001000 0x2000>;
207 reg-names = "rc_dbics", "ti_conf", "config";
208 interrupts = <0 232 0x4>, <0 233 0x4>;
209 #address-cells = <3>;
210 #size-cells = <2>;
211 device_type = "pci";
212 ranges = <0x81000000 0 0x00000000 0x20003000 0 0x00010000>,
213 <0x82000000 0 0x20013000 0x20013000 0 0x0ffed000>;
214 bus-range = <0x00 0xff>;
215 #interrupt-cells = <1>;
216 num-lanes = <1>;
217 linux,pci-domain = <0>;
218 phys = <&pcie1_phy>;
219 phy-names = "pcie-phy0";
220 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
221 interrupt-map-mask = <0 0 0 7>;
222 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
223 <0 0 0 2 &pcie1_intc 2>,
224 <0 0 0 3 &pcie1_intc 3>,
225 <0 0 0 4 &pcie1_intc 4>;
226 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
227 status = "disabled";
228 pcie1_intc: interrupt-controller {
229 interrupt-controller;
230 #address-cells = <0>;
231 #interrupt-cells = <1>;
232 };
233 };
234
235 pcie1_ep: pcie_ep@51000000 {
236 reg = <0x51000000 0x28>,
237 <0x51002000 0x14c>,
238 <0x51001000 0x28>,
239 <0x20001000 0x10000000>;
240 reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
241 interrupts = <0 232 0x4>;
242 num-lanes = <1>;
243 num-ib-windows = <4>;
244 num-ob-windows = <16>;
245 phys = <&pcie1_phy>;
246 phy-names = "pcie-phy0";
247 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
248 ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
249 status = "disabled";
250 };
251 };
252
253 /*
254 * Register access seems to have complex dependencies and also
255 * seems to need an enabled phy. See the TRM chapter for "Table
256 * 26-678. Main Sequence PCIe Controller Global Initialization"
257 * and also dra7xx_pcie_probe().
258 */
259 axi1: target-module@51800000 {
260 compatible = "ti,sysc-omap4", "ti,sysc";
261 clocks = <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 0>,
262 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>,
263 <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>;
264 clock-names = "fck", "phy-clk", "phy-clk-div";
265 power-domains = <&prm_l3init>;
266 resets = <&prm_l3init 1>;
267 reset-names = "rstctrl";
268 #size-cells = <1>;
269 #address-cells = <1>;
270 ranges = <0x51800000 0x51800000 0x3000>,
271 <0x30000000 0x30000000 0x10000000>;
272 dma-ranges;
273 status = "disabled";
274 pcie2_rc: pcie@51800000 {
275 reg = <0x51800000 0x2000>,
276 <0x51802000 0x14c>,
277 <0x30001000 0x2000>;
278 reg-names = "rc_dbics", "ti_conf", "config";
279 interrupts = <0 355 0x4>, <0 356 0x4>;
280 #address-cells = <3>;
281 #size-cells = <2>;
282 device_type = "pci";
283 ranges = <0x81000000 0 0x00000000 0x30003000 0 0x00010000>,
284 <0x82000000 0 0x30013000 0x30013000 0 0x0ffed000>;
285 bus-range = <0x00 0xff>;
286 #interrupt-cells = <1>;
287 num-lanes = <1>;
288 linux,pci-domain = <1>;
289 phys = <&pcie2_phy>;
290 phy-names = "pcie-phy0";
291 interrupt-map-mask = <0 0 0 7>;
292 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
293 <0 0 0 2 &pcie2_intc 2>,
294 <0 0 0 3 &pcie2_intc 3>,
295 <0 0 0 4 &pcie2_intc 4>;
296 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
297 pcie2_intc: interrupt-controller {
298 interrupt-controller;
299 #address-cells = <0>;
300 #interrupt-cells = <1>;
301 };
302 };
303 };
304
305 ocmcram1: ocmcram@40300000 {
306 compatible = "mmio-sram";
307 reg = <0x40300000 0x80000>;
308 ranges = <0x0 0x40300000 0x80000>;
309 #address-cells = <1>;
310 #size-cells = <1>;
311 /*
312 * This is a placeholder for an optional reserved
313 * region for use by secure software. The size
314 * of this region is not known until runtime so it
315 * is set as zero to either be updated to reserve
316 * space or left unchanged to leave all SRAM for use.
317 * On HS parts that that require the reserved region
318 * either the bootloader can update the size to
319 * the required amount or the node can be overridden
320 * from the board dts file for the secure platform.
321 */
322 sram-hs@0 {
323 compatible = "ti,secure-ram";
324 reg = <0x0 0x0>;
325 };
326 };
327
328 /*
329 * NOTE: ocmcram2 and ocmcram3 are not available on all
330 * DRA7xx and AM57xx variants. Confirm availability in
331 * the data manual for the exact part number in use
332 * before enabling these nodes in the board dts file.
333 */
334 ocmcram2: ocmcram@40400000 {
335 status = "disabled";
336 compatible = "mmio-sram";
337 reg = <0x40400000 0x100000>;
338 ranges = <0x0 0x40400000 0x100000>;
339 #address-cells = <1>;
340 #size-cells = <1>;
341 };
342
343 ocmcram3: ocmcram@40500000 {
344 status = "disabled";
345 compatible = "mmio-sram";
346 reg = <0x40500000 0x100000>;
347 ranges = <0x0 0x40500000 0x100000>;
348 #address-cells = <1>;
349 #size-cells = <1>;
350 };
351
352 bandgap: bandgap@4a0021e0 {
353 reg = <0x4a0021e0 0xc
354 0x4a00232c 0xc
355 0x4a002380 0x2c
356 0x4a0023C0 0x3c
357 0x4a002564 0x8
358 0x4a002574 0x50>;
359 compatible = "ti,dra752-bandgap";
360 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
361 #thermal-sensor-cells = <1>;
362 };
363
364 dsp1_system: dsp_system@40d00000 {
365 compatible = "syscon";
366 reg = <0x40d00000 0x100>;
367 };
368
369 dra7_iodelay_core: padconf@4844a000 {
370 compatible = "ti,dra7-iodelay";
371 reg = <0x4844a000 0x0d1c>;
372 #address-cells = <1>;
373 #size-cells = <0>;
374 #pinctrl-cells = <2>;
375 };
376
377 target-module@43300000 {
378 compatible = "ti,sysc-omap4", "ti,sysc";
379 reg = <0x43300000 0x4>,
380 <0x43300010 0x4>;
381 reg-names = "rev", "sysc";
382 ti,sysc-midle = <SYSC_IDLE_FORCE>,
383 <SYSC_IDLE_NO>,
384 <SYSC_IDLE_SMART>;
385 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
386 <SYSC_IDLE_NO>,
387 <SYSC_IDLE_SMART>;
388 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPCC_CLKCTRL 0>;
389 clock-names = "fck";
390 #address-cells = <1>;
391 #size-cells = <1>;
392 ranges = <0x0 0x43300000 0x100000>;
393
394 edma: dma@0 {
395 compatible = "ti,edma3-tpcc";
396 reg = <0 0x100000>;
397 reg-names = "edma3_cc";
398 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
399 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
400 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
401 interrupt-names = "edma3_ccint", "edma3_mperr",
402 "edma3_ccerrint";
403 dma-requests = <64>;
404 #dma-cells = <2>;
405
406 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
407
408 /*
409 * memcpy is disabled, can be enabled with:
410 * ti,edma-memcpy-channels = <20 21>;
411 * for example. Note that these channels need to be
412 * masked in the xbar as well.
413 */
414 };
415 };
416
417 target-module@43400000 {
418 compatible = "ti,sysc-omap4", "ti,sysc";
419 reg = <0x43400000 0x4>,
420 <0x43400010 0x4>;
421 reg-names = "rev", "sysc";
422 ti,sysc-midle = <SYSC_IDLE_FORCE>,
423 <SYSC_IDLE_NO>,
424 <SYSC_IDLE_SMART>;
425 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
426 <SYSC_IDLE_NO>,
427 <SYSC_IDLE_SMART>;
428 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC0_CLKCTRL 0>;
429 clock-names = "fck";
430 #address-cells = <1>;
431 #size-cells = <1>;
432 ranges = <0x0 0x43400000 0x100000>;
433
434 edma_tptc0: dma@0 {
435 compatible = "ti,edma3-tptc";
436 reg = <0 0x100000>;
437 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
438 interrupt-names = "edma3_tcerrint";
439 };
440 };
441
442 target-module@43500000 {
443 compatible = "ti,sysc-omap4", "ti,sysc";
444 reg = <0x43500000 0x4>,
445 <0x43500010 0x4>;
446 reg-names = "rev", "sysc";
447 ti,sysc-midle = <SYSC_IDLE_FORCE>,
448 <SYSC_IDLE_NO>,
449 <SYSC_IDLE_SMART>;
450 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
451 <SYSC_IDLE_NO>,
452 <SYSC_IDLE_SMART>;
453 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_TPTC1_CLKCTRL 0>;
454 clock-names = "fck";
455 #address-cells = <1>;
456 #size-cells = <1>;
457 ranges = <0x0 0x43500000 0x100000>;
458
459 edma_tptc1: dma@0 {
460 compatible = "ti,edma3-tptc";
461 reg = <0 0x100000>;
462 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
463 interrupt-names = "edma3_tcerrint";
464 };
465 };
466
467 target-module@4e000000 {
468 compatible = "ti,sysc-omap2", "ti,sysc";
469 reg = <0x4e000000 0x4>,
470 <0x4e000010 0x4>;
471 reg-names = "rev", "sysc";
472 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
473 <SYSC_IDLE_NO>,
474 <SYSC_IDLE_SMART>;
475 ranges = <0x0 0x4e000000 0x2000000>;
476 #size-cells = <1>;
477 #address-cells = <1>;
478
479 dmm@0 {
480 compatible = "ti,omap5-dmm";
481 reg = <0 0x800>;
482 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
483 };
484 };
485
486 ipu1: ipu@58820000 {
487 compatible = "ti,dra7-ipu";
488 reg = <0x58820000 0x10000>;
489 reg-names = "l2ram";
490 iommus = <&mmu_ipu1>;
491 status = "disabled";
492 resets = <&prm_ipu 0>, <&prm_ipu 1>;
493 clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
494 firmware-name = "dra7-ipu1-fw.xem4";
495 };
496
497 ipu2: ipu@55020000 {
498 compatible = "ti,dra7-ipu";
499 reg = <0x55020000 0x10000>;
500 reg-names = "l2ram";
501 iommus = <&mmu_ipu2>;
502 status = "disabled";
503 resets = <&prm_core 0>, <&prm_core 1>;
504 clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
505 firmware-name = "dra7-ipu2-fw.xem4";
506 };
507
508 dsp1: dsp@40800000 {
509 compatible = "ti,dra7-dsp";
510 reg = <0x40800000 0x48000>,
511 <0x40e00000 0x8000>,
512 <0x40f00000 0x8000>;
513 reg-names = "l2ram", "l1pram", "l1dram";
514 ti,bootreg = <&scm_conf 0x55c 10>;
515 iommus = <&mmu0_dsp1>, <&mmu1_dsp1>;
516 status = "disabled";
517 resets = <&prm_dsp1 0>;
518 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
519 firmware-name = "dra7-dsp1-fw.xe66";
520 };
521
522 target-module@40d01000 {
523 compatible = "ti,sysc-omap2", "ti,sysc";
524 reg = <0x40d01000 0x4>,
525 <0x40d01010 0x4>,
526 <0x40d01014 0x4>;
527 reg-names = "rev", "sysc", "syss";
528 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
529 <SYSC_IDLE_NO>,
530 <SYSC_IDLE_SMART>;
531 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
532 SYSC_OMAP2_SOFTRESET |
533 SYSC_OMAP2_AUTOIDLE)>;
534 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
535 clock-names = "fck";
536 resets = <&prm_dsp1 1>;
537 reset-names = "rstctrl";
538 ranges = <0x0 0x40d01000 0x1000>;
539 #size-cells = <1>;
540 #address-cells = <1>;
541
542 mmu0_dsp1: mmu@0 {
543 compatible = "ti,dra7-dsp-iommu";
544 reg = <0x0 0x100>;
545 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
546 #iommu-cells = <0>;
547 ti,syscon-mmuconfig = <&dsp1_system 0x0>;
548 };
549 };
550
551 target-module@40d02000 {
552 compatible = "ti,sysc-omap2", "ti,sysc";
553 reg = <0x40d02000 0x4>,
554 <0x40d02010 0x4>,
555 <0x40d02014 0x4>;
556 reg-names = "rev", "sysc", "syss";
557 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
558 <SYSC_IDLE_NO>,
559 <SYSC_IDLE_SMART>;
560 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
561 SYSC_OMAP2_SOFTRESET |
562 SYSC_OMAP2_AUTOIDLE)>;
563 clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
564 clock-names = "fck";
565 resets = <&prm_dsp1 1>;
566 reset-names = "rstctrl";
567 ranges = <0x0 0x40d02000 0x1000>;
568 #size-cells = <1>;
569 #address-cells = <1>;
570
571 mmu1_dsp1: mmu@0 {
572 compatible = "ti,dra7-dsp-iommu";
573 reg = <0x0 0x100>;
574 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
575 #iommu-cells = <0>;
576 ti,syscon-mmuconfig = <&dsp1_system 0x1>;
577 };
578 };
579
580 target-module@58882000 {
581 compatible = "ti,sysc-omap2", "ti,sysc";
582 reg = <0x58882000 0x4>,
583 <0x58882010 0x4>,
584 <0x58882014 0x4>;
585 reg-names = "rev", "sysc", "syss";
586 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
587 <SYSC_IDLE_NO>,
588 <SYSC_IDLE_SMART>;
589 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
590 SYSC_OMAP2_SOFTRESET |
591 SYSC_OMAP2_AUTOIDLE)>;
592 clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
593 clock-names = "fck";
594 resets = <&prm_ipu 2>;
595 reset-names = "rstctrl";
596 #address-cells = <1>;
597 #size-cells = <1>;
598 ranges = <0x0 0x58882000 0x100>;
599
600 mmu_ipu1: mmu@0 {
601 compatible = "ti,dra7-iommu";
602 reg = <0x0 0x100>;
603 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
604 #iommu-cells = <0>;
605 ti,iommu-bus-err-back;
606 };
607 };
608
609 target-module@55082000 {
610 compatible = "ti,sysc-omap2", "ti,sysc";
611 reg = <0x55082000 0x4>,
612 <0x55082010 0x4>,
613 <0x55082014 0x4>;
614 reg-names = "rev", "sysc", "syss";
615 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
616 <SYSC_IDLE_NO>,
617 <SYSC_IDLE_SMART>;
618 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
619 SYSC_OMAP2_SOFTRESET |
620 SYSC_OMAP2_AUTOIDLE)>;
621 clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
622 clock-names = "fck";
623 resets = <&prm_core 2>;
624 reset-names = "rstctrl";
625 #address-cells = <1>;
626 #size-cells = <1>;
627 ranges = <0x0 0x55082000 0x100>;
628
629 mmu_ipu2: mmu@0 {
630 compatible = "ti,dra7-iommu";
631 reg = <0x0 0x100>;
632 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
633 #iommu-cells = <0>;
634 ti,iommu-bus-err-back;
635 };
636 };
637
638 abb_mpu: regulator-abb-mpu {
639 compatible = "ti,abb-v3";
640 regulator-name = "abb_mpu";
641 #address-cells = <0>;
642 #size-cells = <0>;
643 clocks = <&sys_clkin1>;
644 ti,settling-time = <50>;
645 ti,clock-cycles = <16>;
646
647 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
648 <0x4ae06014 0x4>, <0x4a003b20 0xc>,
649 <0x4ae0c158 0x4>;
650 reg-names = "setup-address", "control-address",
651 "int-address", "efuse-address",
652 "ldo-address";
653 ti,tranxdone-status-mask = <0x80>;
654 /* LDOVBBMPU_FBB_MUX_CTRL */
655 ti,ldovbb-override-mask = <0x400>;
656 /* LDOVBBMPU_FBB_VSET_OUT */
657 ti,ldovbb-vset-mask = <0x1F>;
658
659 /*
660 * NOTE: only FBB mode used but actual vset will
661 * determine final biasing
662 */
663 ti,abb_info = <
664 /*uV ABB efuse rbb_m fbb_m vset_m*/
665 1060000 0 0x0 0 0x02000000 0x01F00000
666 1160000 0 0x4 0 0x02000000 0x01F00000
667 1210000 0 0x8 0 0x02000000 0x01F00000
668 >;
669 };
670
671 abb_ivahd: regulator-abb-ivahd {
672 compatible = "ti,abb-v3";
673 regulator-name = "abb_ivahd";
674 #address-cells = <0>;
675 #size-cells = <0>;
676 clocks = <&sys_clkin1>;
677 ti,settling-time = <50>;
678 ti,clock-cycles = <16>;
679
680 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
681 <0x4ae06010 0x4>, <0x4a0025cc 0xc>,
682 <0x4a002470 0x4>;
683 reg-names = "setup-address", "control-address",
684 "int-address", "efuse-address",
685 "ldo-address";
686 ti,tranxdone-status-mask = <0x40000000>;
687 /* LDOVBBIVA_FBB_MUX_CTRL */
688 ti,ldovbb-override-mask = <0x400>;
689 /* LDOVBBIVA_FBB_VSET_OUT */
690 ti,ldovbb-vset-mask = <0x1F>;
691
692 /*
693 * NOTE: only FBB mode used but actual vset will
694 * determine final biasing
695 */
696 ti,abb_info = <
697 /*uV ABB efuse rbb_m fbb_m vset_m*/
698 1055000 0 0x0 0 0x02000000 0x01F00000
699 1150000 0 0x4 0 0x02000000 0x01F00000
700 1250000 0 0x8 0 0x02000000 0x01F00000
701 >;
702 };
703
704 abb_dspeve: regulator-abb-dspeve {
705 compatible = "ti,abb-v3";
706 regulator-name = "abb_dspeve";
707 #address-cells = <0>;
708 #size-cells = <0>;
709 clocks = <&sys_clkin1>;
710 ti,settling-time = <50>;
711 ti,clock-cycles = <16>;
712
713 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
714 <0x4ae06010 0x4>, <0x4a0025e0 0xc>,
715 <0x4a00246c 0x4>;
716 reg-names = "setup-address", "control-address",
717 "int-address", "efuse-address",
718 "ldo-address";
719 ti,tranxdone-status-mask = <0x20000000>;
720 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
721 ti,ldovbb-override-mask = <0x400>;
722 /* LDOVBBDSPEVE_FBB_VSET_OUT */
723 ti,ldovbb-vset-mask = <0x1F>;
724
725 /*
726 * NOTE: only FBB mode used but actual vset will
727 * determine final biasing
728 */
729 ti,abb_info = <
730 /*uV ABB efuse rbb_m fbb_m vset_m*/
731 1055000 0 0x0 0 0x02000000 0x01F00000
732 1150000 0 0x4 0 0x02000000 0x01F00000
733 1250000 0 0x8 0 0x02000000 0x01F00000
734 >;
735 };
736
737 abb_gpu: regulator-abb-gpu {
738 compatible = "ti,abb-v3";
739 regulator-name = "abb_gpu";
740 #address-cells = <0>;
741 #size-cells = <0>;
742 clocks = <&sys_clkin1>;
743 ti,settling-time = <50>;
744 ti,clock-cycles = <16>;
745
746 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
747 <0x4ae06010 0x4>, <0x4a003b08 0xc>,
748 <0x4ae0c154 0x4>;
749 reg-names = "setup-address", "control-address",
750 "int-address", "efuse-address",
751 "ldo-address";
752 ti,tranxdone-status-mask = <0x10000000>;
753 /* LDOVBBGPU_FBB_MUX_CTRL */
754 ti,ldovbb-override-mask = <0x400>;
755 /* LDOVBBGPU_FBB_VSET_OUT */
756 ti,ldovbb-vset-mask = <0x1F>;
757
758 /*
759 * NOTE: only FBB mode used but actual vset will
760 * determine final biasing
761 */
762 ti,abb_info = <
763 /*uV ABB efuse rbb_m fbb_m vset_m*/
764 1090000 0 0x0 0 0x02000000 0x01F00000
765 1210000 0 0x4 0 0x02000000 0x01F00000
766 1280000 0 0x8 0 0x02000000 0x01F00000
767 >;
768 };
769
770 target-module@4b300000 {
771 compatible = "ti,sysc-omap4", "ti,sysc";
772 reg = <0x4b300000 0x4>,
773 <0x4b300010 0x4>;
774 reg-names = "rev", "sysc";
775 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
776 <SYSC_IDLE_NO>,
777 <SYSC_IDLE_SMART>,
778 <SYSC_IDLE_SMART_WKUP>;
779 clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 0>;
780 clock-names = "fck";
781 #address-cells = <1>;
782 #size-cells = <1>;
783 ranges = <0x0 0x4b300000 0x1000>,
784 <0x5c000000 0x5c000000 0x4000000>;
785
786 qspi: spi@0 {
787 compatible = "ti,dra7xxx-qspi";
788 reg = <0 0x100>,
789 <0x5c000000 0x4000000>;
790 reg-names = "qspi_base", "qspi_mmap";
791 syscon-chipselects = <&scm_conf 0x558>;
792 #address-cells = <1>;
793 #size-cells = <0>;
794 clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>;
795 clock-names = "fck";
796 num-cs = <4>;
797 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
798 status = "disabled";
799 };
800 };
801
802 /* OCP2SCP1 */
803 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
804
805 target-module@50000000 {
806 compatible = "ti,sysc-omap2", "ti,sysc";
807 reg = <0x50000000 4>,
808 <0x50000010 4>,
809 <0x50000014 4>;
810 reg-names = "rev", "sysc", "syss";
811 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
812 <SYSC_IDLE_NO>,
813 <SYSC_IDLE_SMART>;
814 ti,syss-mask = <1>;
815 clocks = <&l3main1_clkctrl DRA7_L3MAIN1_GPMC_CLKCTRL 0>;
816 clock-names = "fck";
817 #address-cells = <1>;
818 #size-cells = <1>;
819 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
820 <0x00000000 0x00000000 0x40000000>; /* data */
821
822 gpmc: gpmc@50000000 {
823 compatible = "ti,am3352-gpmc";
824 reg = <0x50000000 0x37c>; /* device IO registers */
825 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
826 dmas = <&edma_xbar 4 0>;
827 dma-names = "rxtx";
828 gpmc,num-cs = <8>;
829 gpmc,num-waitpins = <2>;
830 #address-cells = <2>;
831 #size-cells = <1>;
832 interrupt-controller;
833 #interrupt-cells = <2>;
834 gpio-controller;
835 #gpio-cells = <2>;
836 status = "disabled";
837 };
838 };
839
840 target-module@56000000 {
841 compatible = "ti,sysc-omap4", "ti,sysc";
842 reg = <0x5600fe00 0x4>,
843 <0x5600fe10 0x4>;
844 reg-names = "rev", "sysc";
845 ti,sysc-midle = <SYSC_IDLE_FORCE>,
846 <SYSC_IDLE_NO>,
847 <SYSC_IDLE_SMART>;
848 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
849 <SYSC_IDLE_NO>,
850 <SYSC_IDLE_SMART>;
851 clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>;
852 clock-names = "fck";
853 #address-cells = <1>;
854 #size-cells = <1>;
855 ranges = <0 0x56000000 0x2000000>;
856 };
857
858 crossbar_mpu: crossbar@4a002a48 {
859 compatible = "ti,irq-crossbar";
860 reg = <0x4a002a48 0x130>;
861 interrupt-controller;
862 interrupt-parent = <&wakeupgen>;
863 #interrupt-cells = <3>;
864 ti,max-irqs = <160>;
865 ti,max-crossbar-sources = <MAX_SOURCES>;
866 ti,reg-size = <2>;
867 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
868 ti,irqs-skip = <10 133 139 140>;
869 ti,irqs-safe-map = <0>;
870 };
871
872 target-module@58000000 {
873 compatible = "ti,sysc-omap2", "ti,sysc";
874 reg = <0x58000000 4>,
875 <0x58000014 4>;
876 reg-names = "rev", "syss";
877 ti,syss-mask = <1>;
878 clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 0>,
879 <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>,
880 <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 10>,
881 <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 11>;
882 clock-names = "fck", "hdmi_clk", "sys_clk", "tv_clk";
883 #address-cells = <1>;
884 #size-cells = <1>;
885 ranges = <0 0x58000000 0x800000>;
886
887 dss: dss@0 {
888 compatible = "ti,dra7-dss";
889 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
890 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
891 status = "disabled";
892 /* CTRL_CORE_DSS_PLL_CONTROL */
893 syscon-pll-ctrl = <&scm_conf 0x538>;
894 #address-cells = <1>;
895 #size-cells = <1>;
896 ranges = <0 0 0x800000>;
897
898 target-module@1000 {
899 compatible = "ti,sysc-omap2", "ti,sysc";
900 reg = <0x1000 0x4>,
901 <0x1010 0x4>,
902 <0x1014 0x4>;
903 reg-names = "rev", "sysc", "syss";
904 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
905 <SYSC_IDLE_NO>,
906 <SYSC_IDLE_SMART>;
907 ti,sysc-midle = <SYSC_IDLE_FORCE>,
908 <SYSC_IDLE_NO>,
909 <SYSC_IDLE_SMART>;
910 ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
911 SYSC_OMAP2_ENAWAKEUP |
912 SYSC_OMAP2_SOFTRESET |
913 SYSC_OMAP2_AUTOIDLE)>;
914 ti,syss-mask = <1>;
915 clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>;
916 clock-names = "fck";
917 #address-cells = <1>;
918 #size-cells = <1>;
919 ranges = <0 0x1000 0x1000>;
920
921 dispc@0 {
922 compatible = "ti,dra7-dispc";
923 reg = <0 0x1000>;
924 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
925 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
926 clock-names = "fck";
927 /* CTRL_CORE_SMA_SW_1 */
928 syscon-pol = <&scm_conf 0x534>;
929 };
930 };
931
932 target-module@40000 {
933 compatible = "ti,sysc-omap4", "ti,sysc";
934 reg = <0x40000 0x4>,
935 <0x40010 0x4>;
936 reg-names = "rev", "sysc";
937 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
938 <SYSC_IDLE_NO>,
939 <SYSC_IDLE_SMART>,
940 <SYSC_IDLE_SMART_WKUP>;
941 ti,sysc-mask = <(SYSC_OMAP4_SOFTRESET)>;
942 clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>,
943 <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>;
944 clock-names = "fck", "dss_clk";
945 #address-cells = <1>;
946 #size-cells = <1>;
947 ranges = <0 0x40000 0x40000>;
948
949 hdmi: encoder@0 {
950 compatible = "ti,dra7-hdmi";
951 reg = <0 0x200>,
952 <0x200 0x80>,
953 <0x300 0x80>,
954 <0x20000 0x19000>;
955 reg-names = "wp", "pll", "phy", "core";
956 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
957 status = "disabled";
958 clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
959 <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>;
960 clock-names = "fck", "sys_clk";
961 dmas = <&sdma_xbar 76>;
962 dma-names = "audio_tx";
963 };
964 };
965 };
966 };
967
968 aes1_target: target-module@4b500000 {
969 compatible = "ti,sysc-omap2", "ti,sysc";
970 reg = <0x4b500080 0x4>,
971 <0x4b500084 0x4>,
972 <0x4b500088 0x4>;
973 reg-names = "rev", "sysc", "syss";
974 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
975 SYSC_OMAP2_AUTOIDLE)>;
976 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
977 <SYSC_IDLE_NO>,
978 <SYSC_IDLE_SMART>,
979 <SYSC_IDLE_SMART_WKUP>;
980 ti,syss-mask = <1>;
981 /* Domains (P, C): per_pwrdm, l4sec_clkdm */
982 clocks = <&l4sec_clkctrl DRA7_L4SEC_AES1_CLKCTRL 0>;
983 clock-names = "fck";
984 #address-cells = <1>;
985 #size-cells = <1>;
986 ranges = <0x0 0x4b500000 0x1000>;
987
988 aes1: aes@0 {
989 compatible = "ti,omap4-aes";
990 reg = <0 0xa0>;
991 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
992 dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
993 dma-names = "tx", "rx";
994 clocks = <&l3_iclk_div>;
995 clock-names = "fck";
996 };
997 };
998
999 aes2_target: target-module@4b700000 {
1000 compatible = "ti,sysc-omap2", "ti,sysc";
1001 reg = <0x4b700080 0x4>,
1002 <0x4b700084 0x4>,
1003 <0x4b700088 0x4>;
1004 reg-names = "rev", "sysc", "syss";
1005 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
1006 SYSC_OMAP2_AUTOIDLE)>;
1007 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1008 <SYSC_IDLE_NO>,
1009 <SYSC_IDLE_SMART>,
1010 <SYSC_IDLE_SMART_WKUP>;
1011 ti,syss-mask = <1>;
1012 /* Domains (P, C): per_pwrdm, l4sec_clkdm */
1013 clocks = <&l4sec_clkctrl DRA7_L4SEC_AES2_CLKCTRL 0>;
1014 clock-names = "fck";
1015 #address-cells = <1>;
1016 #size-cells = <1>;
1017 ranges = <0x0 0x4b700000 0x1000>;
1018
1019 aes2: aes@0 {
1020 compatible = "ti,omap4-aes";
1021 reg = <0 0xa0>;
1022 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
1023 dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
1024 dma-names = "tx", "rx";
1025 clocks = <&l3_iclk_div>;
1026 clock-names = "fck";
1027 };
1028 };
1029
1030 sham1_target: target-module@4b101000 {
1031 compatible = "ti,sysc-omap3-sham", "ti,sysc";
1032 reg = <0x4b101100 0x4>,
1033 <0x4b101110 0x4>,
1034 <0x4b101114 0x4>;
1035 reg-names = "rev", "sysc", "syss";
1036 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
1037 SYSC_OMAP2_AUTOIDLE)>;
1038 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1039 <SYSC_IDLE_NO>,
1040 <SYSC_IDLE_SMART>;
1041 ti,syss-mask = <1>;
1042 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
1043 clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM_CLKCTRL 0>;
1044 clock-names = "fck";
1045 #address-cells = <1>;
1046 #size-cells = <1>;
1047 ranges = <0x0 0x4b101000 0x1000>;
1048
1049 sham1: sham@0 {
1050 compatible = "ti,omap5-sham";
1051 reg = <0 0x300>;
1052 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1053 dmas = <&edma_xbar 119 0>;
1054 dma-names = "rx";
1055 clocks = <&l3_iclk_div>;
1056 clock-names = "fck";
1057 };
1058 };
1059
1060 sham2_target: target-module@42701000 {
1061 compatible = "ti,sysc-omap3-sham", "ti,sysc";
1062 reg = <0x42701100 0x4>,
1063 <0x42701110 0x4>,
1064 <0x42701114 0x4>;
1065 reg-names = "rev", "sysc", "syss";
1066 ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
1067 SYSC_OMAP2_AUTOIDLE)>;
1068 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1069 <SYSC_IDLE_NO>,
1070 <SYSC_IDLE_SMART>;
1071 ti,syss-mask = <1>;
1072 /* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
1073 clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM2_CLKCTRL 0>;
1074 clock-names = "fck";
1075 #address-cells = <1>;
1076 #size-cells = <1>;
1077 ranges = <0x0 0x42701000 0x1000>;
1078
1079 sham2: sham@0 {
1080 compatible = "ti,omap5-sham";
1081 reg = <0 0x300>;
1082 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
1083 dmas = <&edma_xbar 165 0>;
1084 dma-names = "rx";
1085 clocks = <&l3_iclk_div>;
1086 clock-names = "fck";
1087 };
1088 };
1089
1090 iva_hd_target: target-module@5a000000 {
1091 compatible = "ti,sysc-omap4", "ti,sysc";
1092 reg = <0x5a05a400 0x4>,
1093 <0x5a05a410 0x4>;
1094 reg-names = "rev", "sysc";
1095 ti,sysc-midle = <SYSC_IDLE_FORCE>,
1096 <SYSC_IDLE_NO>,
1097 <SYSC_IDLE_SMART>;
1098 ti,sysc-sidle = <SYSC_IDLE_FORCE>,
1099 <SYSC_IDLE_NO>,
1100 <SYSC_IDLE_SMART>;
1101 power-domains = <&prm_iva>;
1102 resets = <&prm_iva 2>;
1103 reset-names = "rstctrl";
1104 clocks = <&iva_clkctrl DRA7_IVA_CLKCTRL 0>;
1105 clock-names = "fck";
1106 #address-cells = <1>;
1107 #size-cells = <1>;
1108 ranges = <0x5a000000 0x5a000000 0x1000000>,
1109 <0x5b000000 0x5b000000 0x1000000>;
1110
1111 iva {
1112 compatible = "ti,ivahd";
1113 };
1114 };
1115
1116 opp_supply_mpu: opp-supply@4a003b20 {
1117 compatible = "ti,omap5-opp-supply";
1118 reg = <0x4a003b20 0xc>;
1119 ti,efuse-settings = <
1120 /* uV offset */
1121 1060000 0x0
1122 1160000 0x4
1123 1210000 0x8
1124 >;
1125 ti,absolute-max-voltage-uv = <1500000>;
1126 };
1127
1128 };
1129
1130 thermal_zones: thermal-zones {
1131 #include "omap4-cpu-thermal.dtsi"
1132 #include "omap5-gpu-thermal.dtsi"
1133 #include "omap5-core-thermal.dtsi"
1134 #include "dra7-dspeve-thermal.dtsi"
1135 #include "dra7-iva-thermal.dtsi"
1136 };
1137
1138};
1139
1140&cpu_thermal {
1141 polling-delay = <500>; /* milliseconds */
1142 coefficients = <0 2000>;
1143};
1144
1145&gpu_thermal {
1146 coefficients = <0 2000>;
1147};
1148
1149&core_thermal {
1150 coefficients = <0 2000>;
1151};
1152
1153&dspeve_thermal {
1154 coefficients = <0 2000>;
1155};
1156
1157&iva_thermal {
1158 coefficients = <0 2000>;
1159};
1160
1161&cpu_crit {
1162 temperature = <120000>; /* milli Celsius */
1163};
1164
1165&core_crit {
1166 temperature = <120000>; /* milli Celsius */
1167};
1168
1169&gpu_crit {
1170 temperature = <120000>; /* milli Celsius */
1171};
1172
1173&dspeve_crit {
1174 temperature = <120000>; /* milli Celsius */
1175};
1176
1177&iva_crit {
1178 temperature = <120000>; /* milli Celsius */
1179};
1180
1181#include "dra7-l4.dtsi"
1182#include "dra7xx-clocks.dtsi"
1183
1184&prm {
1185 prm_mpu: prm@300 {
1186 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1187 reg = <0x300 0x100>;
1188 #power-domain-cells = <0>;
1189 };
1190
1191 prm_dsp1: prm@400 {
1192 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1193 reg = <0x400 0x100>;
1194 #reset-cells = <1>;
1195 #power-domain-cells = <0>;
1196 };
1197
1198 prm_ipu: prm@500 {
1199 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1200 reg = <0x500 0x100>;
1201 #reset-cells = <1>;
1202 #power-domain-cells = <0>;
1203 };
1204
1205 prm_coreaon: prm@628 {
1206 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1207 reg = <0x628 0xd8>;
1208 #power-domain-cells = <0>;
1209 };
1210
1211 prm_core: prm@700 {
1212 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1213 reg = <0x700 0x100>;
1214 #reset-cells = <1>;
1215 #power-domain-cells = <0>;
1216 };
1217
1218 prm_iva: prm@f00 {
1219 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1220 reg = <0xf00 0x100>;
1221 #reset-cells = <1>;
1222 #power-domain-cells = <0>;
1223 };
1224
1225 prm_cam: prm@1000 {
1226 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1227 reg = <0x1000 0x100>;
1228 #power-domain-cells = <0>;
1229 };
1230
1231 prm_dss: prm@1100 {
1232 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1233 reg = <0x1100 0x100>;
1234 #power-domain-cells = <0>;
1235 };
1236
1237 prm_gpu: prm@1200 {
1238 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1239 reg = <0x1200 0x100>;
1240 #power-domain-cells = <0>;
1241 };
1242
1243 prm_l3init: prm@1300 {
1244 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1245 reg = <0x1300 0x100>;
1246 #reset-cells = <1>;
1247 #power-domain-cells = <0>;
1248 };
1249
1250 prm_l4per: prm@1400 {
1251 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1252 reg = <0x1400 0x100>;
1253 #power-domain-cells = <0>;
1254 };
1255
1256 prm_custefuse: prm@1600 {
1257 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1258 reg = <0x1600 0x100>;
1259 #power-domain-cells = <0>;
1260 };
1261
1262 prm_wkupaon: prm@1724 {
1263 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1264 reg = <0x1724 0x100>;
1265 #power-domain-cells = <0>;
1266 };
1267
1268 prm_dsp2: prm@1b00 {
1269 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1270 reg = <0x1b00 0x40>;
1271 #reset-cells = <1>;
1272 #power-domain-cells = <0>;
1273 };
1274
1275 prm_eve1: prm@1b40 {
1276 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1277 reg = <0x1b40 0x40>;
1278 #power-domain-cells = <0>;
1279 };
1280
1281 prm_eve2: prm@1b80 {
1282 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1283 reg = <0x1b80 0x40>;
1284 #power-domain-cells = <0>;
1285 };
1286
1287 prm_eve3: prm@1bc0 {
1288 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1289 reg = <0x1bc0 0x40>;
1290 #power-domain-cells = <0>;
1291 };
1292
1293 prm_eve4: prm@1c00 {
1294 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1295 reg = <0x1c00 0x60>;
1296 #power-domain-cells = <0>;
1297 };
1298
1299 prm_rtc: prm@1c60 {
1300 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1301 reg = <0x1c60 0x20>;
1302 #power-domain-cells = <0>;
1303 };
1304
1305 prm_vpe: prm@1c80 {
1306 compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
1307 reg = <0x1c80 0x80>;
1308 #power-domain-cells = <0>;
1309 };
1310};
1311
1312/* Preferred always-on timer for clockevent */
1313&timer1_target {
1314 ti,no-reset-on-init;
1315 ti,no-idle;
1316 timer@0 {
1317 assigned-clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>;
1318 assigned-clock-parents = <&sys_32k_ck>;
1319 };
1320};
1321
1322/* Local timers, see ARM architected timer wrap erratum i940 */
1323&timer3_target {
1324 ti,no-reset-on-init;
1325 ti,no-idle;
1326 timer@0 {
1327 assigned-clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>;
1328 assigned-clock-parents = <&timer_sys_clk_div>;
1329 };
1330};
1331
1332&timer4_target {
1333 ti,no-reset-on-init;
1334 ti,no-idle;
1335 timer@0 {
1336 assigned-clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>;
1337 assigned-clock-parents = <&timer_sys_clk_div>;
1338 };
1339};