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1perf-list(1)
2============
3
4NAME
5----
6perf-list - List all symbolic event types
7
8SYNOPSIS
9--------
10[verse]
11'perf list' [--no-desc] [--long-desc]
12 [hw|sw|cache|tracepoint|pmu|sdt|metric|metricgroup|event_glob]
13
14DESCRIPTION
15-----------
16This command displays the symbolic event types which can be selected in the
17various perf commands with the -e option.
18
19OPTIONS
20-------
21-d::
22--desc::
23Print extra event descriptions. (default)
24
25--no-desc::
26Don't print descriptions.
27
28-v::
29--long-desc::
30Print longer event descriptions.
31
32--debug::
33Enable debugging output.
34
35--details::
36Print how named events are resolved internally into perf events, and also
37any extra expressions computed by perf stat.
38
39[[EVENT_MODIFIERS]]
40EVENT MODIFIERS
41---------------
42
43Events can optionally have a modifier by appending a colon and one or
44more modifiers. Modifiers allow the user to restrict the events to be
45counted. The following modifiers exist:
46
47 u - user-space counting
48 k - kernel counting
49 h - hypervisor counting
50 I - non idle counting
51 G - guest counting (in KVM guests)
52 H - host counting (not in KVM guests)
53 p - precise level
54 P - use maximum detected precise level
55 S - read sample value (PERF_SAMPLE_READ)
56 D - pin the event to the PMU
57 W - group is weak and will fallback to non-group if not schedulable,
58
59The 'p' modifier can be used for specifying how precise the instruction
60address should be. The 'p' modifier can be specified multiple times:
61
62 0 - SAMPLE_IP can have arbitrary skid
63 1 - SAMPLE_IP must have constant skid
64 2 - SAMPLE_IP requested to have 0 skid
65 3 - SAMPLE_IP must have 0 skid, or uses randomization to avoid
66 sample shadowing effects.
67
68For Intel systems precise event sampling is implemented with PEBS
69which supports up to precise-level 2, and precise level 3 for
70some special cases
71
72On AMD systems it is implemented using IBS (up to precise-level 2).
73The precise modifier works with event types 0x76 (cpu-cycles, CPU
74clocks not halted) and 0xC1 (micro-ops retired). Both events map to
75IBS execution sampling (IBS op) with the IBS Op Counter Control bit
76(IbsOpCntCtl) set respectively (see AMD64 Architecture Programmer’s
77Manual Volume 2: System Programming, 13.3 Instruction-Based
78Sampling). Examples to use IBS:
79
80 perf record -a -e cpu-cycles:p ... # use ibs op counting cycles
81 perf record -a -e r076:p ... # same as -e cpu-cycles:p
82 perf record -a -e r0C1:p ... # use ibs op counting micro-ops
83
84RAW HARDWARE EVENT DESCRIPTOR
85-----------------------------
86Even when an event is not available in a symbolic form within perf right now,
87it can be encoded in a per processor specific way.
88
89For instance For x86 CPUs NNN represents the raw register encoding with the
90layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout
91of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344,
92Figure 13-7 Performance Event-Select Register (PerfEvtSeln)).
93
94Note: Only the following bit fields can be set in x86 counter
95registers: event, umask, edge, inv, cmask. Esp. guest/host only and
96OS/user mode flags must be setup using <<EVENT_MODIFIERS, EVENT
97MODIFIERS>>.
98
99Example:
100
101If the Intel docs for a QM720 Core i7 describe an event as:
102
103 Event Umask Event Mask
104 Num. Value Mnemonic Description Comment
105
106 A8H 01H LSD.UOPS Counts the number of micro-ops Use cmask=1 and
107 delivered by loop stream detector invert to count
108 cycles
109
110raw encoding of 0x1A8 can be used:
111
112 perf stat -e r1a8 -a sleep 1
113 perf record -e r1a8 ...
114
115You should refer to the processor specific documentation for getting these
116details. Some of them are referenced in the SEE ALSO section below.
117
118ARBITRARY PMUS
119--------------
120
121perf also supports an extended syntax for specifying raw parameters
122to PMUs. Using this typically requires looking up the specific event
123in the CPU vendor specific documentation.
124
125The available PMUs and their raw parameters can be listed with
126
127 ls /sys/devices/*/format
128
129For example the raw event "LSD.UOPS" core pmu event above could
130be specified as
131
132 perf stat -e cpu/event=0xa8,umask=0x1,name=LSD.UOPS_CYCLES,cmask=0x1/ ...
133
134 or using extended name syntax
135
136 perf stat -e cpu/event=0xa8,umask=0x1,cmask=0x1,name=\'LSD.UOPS_CYCLES:cmask=0x1\'/ ...
137
138PER SOCKET PMUS
139---------------
140
141Some PMUs are not associated with a core, but with a whole CPU socket.
142Events on these PMUs generally cannot be sampled, but only counted globally
143with perf stat -a. They can be bound to one logical CPU, but will measure
144all the CPUs in the same socket.
145
146This example measures memory bandwidth every second
147on the first memory controller on socket 0 of a Intel Xeon system
148
149 perf stat -C 0 -a uncore_imc_0/cas_count_read/,uncore_imc_0/cas_count_write/ -I 1000 ...
150
151Each memory controller has its own PMU. Measuring the complete system
152bandwidth would require specifying all imc PMUs (see perf list output),
153and adding the values together. To simplify creation of multiple events,
154prefix and glob matching is supported in the PMU name, and the prefix
155'uncore_' is also ignored when performing the match. So the command above
156can be expanded to all memory controllers by using the syntaxes:
157
158 perf stat -C 0 -a imc/cas_count_read/,imc/cas_count_write/ -I 1000 ...
159 perf stat -C 0 -a *imc*/cas_count_read/,*imc*/cas_count_write/ -I 1000 ...
160
161This example measures the combined core power every second
162
163 perf stat -I 1000 -e power/energy-cores/ -a
164
165ACCESS RESTRICTIONS
166-------------------
167
168For non root users generally only context switched PMU events are available.
169This is normally only the events in the cpu PMU, the predefined events
170like cycles and instructions and some software events.
171
172Other PMUs and global measurements are normally root only.
173Some event qualifiers, such as "any", are also root only.
174
175This can be overridden by setting the kernel.perf_event_paranoid
176sysctl to -1, which allows non root to use these events.
177
178For accessing trace point events perf needs to have read access to
179/sys/kernel/debug/tracing, even when perf_event_paranoid is in a relaxed
180setting.
181
182TRACING
183-------
184
185Some PMUs control advanced hardware tracing capabilities, such as Intel PT,
186that allows low overhead execution tracing. These are described in a separate
187intel-pt.txt document.
188
189PARAMETERIZED EVENTS
190--------------------
191
192Some pmu events listed by 'perf-list' will be displayed with '?' in them. For
193example:
194
195 hv_gpci/dtbp_ptitc,phys_processor_idx=?/
196
197This means that when provided as an event, a value for '?' must
198also be supplied. For example:
199
200 perf stat -C 0 -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ...
201
202EVENT QUALIFIERS:
203
204It is also possible to add extra qualifiers to an event:
205
206percore:
207
208Sums up the event counts for all hardware threads in a core, e.g.:
209
210
211 perf stat -e cpu/event=0,umask=0x3,percore=1/
212
213
214EVENT GROUPS
215------------
216
217Perf supports time based multiplexing of events, when the number of events
218active exceeds the number of hardware performance counters. Multiplexing
219can cause measurement errors when the workload changes its execution
220profile.
221
222When metrics are computed using formulas from event counts, it is useful to
223ensure some events are always measured together as a group to minimize multiplexing
224errors. Event groups can be specified using { }.
225
226 perf stat -e '{instructions,cycles}' ...
227
228The number of available performance counters depend on the CPU. A group
229cannot contain more events than available counters.
230For example Intel Core CPUs typically have four generic performance counters
231for the core, plus three fixed counters for instructions, cycles and
232ref-cycles. Some special events have restrictions on which counter they
233can schedule, and may not support multiple instances in a single group.
234When too many events are specified in the group some of them will not
235be measured.
236
237Globally pinned events can limit the number of counters available for
238other groups. On x86 systems, the NMI watchdog pins a counter by default.
239The nmi watchdog can be disabled as root with
240
241 echo 0 > /proc/sys/kernel/nmi_watchdog
242
243Events from multiple different PMUs cannot be mixed in a group, with
244some exceptions for software events.
245
246LEADER SAMPLING
247---------------
248
249perf also supports group leader sampling using the :S specifier.
250
251 perf record -e '{cycles,instructions}:S' ...
252 perf report --group
253
254Normally all events in an event group sample, but with :S only
255the first event (the leader) samples, and it only reads the values of the
256other events in the group.
257
258OPTIONS
259-------
260
261Without options all known events will be listed.
262
263To limit the list use:
264
265. 'hw' or 'hardware' to list hardware events such as cache-misses, etc.
266
267. 'sw' or 'software' to list software events such as context switches, etc.
268
269. 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc.
270
271. 'tracepoint' to list all tracepoint events, alternatively use
272 'subsys_glob:event_glob' to filter by tracepoint subsystems such as sched,
273 block, etc.
274
275. 'pmu' to print the kernel supplied PMU events.
276
277. 'sdt' to list all Statically Defined Tracepoint events.
278
279. 'metric' to list metrics
280
281. 'metricgroup' to list metricgroups with metrics.
282
283. If none of the above is matched, it will apply the supplied glob to all
284 events, printing the ones that match.
285
286. As a last resort, it will do a substring search in all event names.
287
288One or more types can be used at the same time, listing the events for the
289types specified.
290
291Support raw format:
292
293. '--raw-dump', shows the raw-dump of all the events.
294. '--raw-dump [hw|sw|cache|tracepoint|pmu|event_glob]', shows the raw-dump of
295 a certain kind of events.
296
297SEE ALSO
298--------
299linkperf:perf-stat[1], linkperf:perf-top[1],
300linkperf:perf-record[1],
301http://www.intel.com/sdm/[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide],
302http://support.amd.com/us/Processor_TechDocs/24593_APM_v2.pdf[AMD64 Architecture Programmer’s Manual Volume 2: System Programming]
1perf-list(1)
2============
3
4NAME
5----
6perf-list - List all symbolic event types
7
8SYNOPSIS
9--------
10[verse]
11'perf list' [hw|sw|cache|tracepoint|pmu|event_glob]
12
13DESCRIPTION
14-----------
15This command displays the symbolic event types which can be selected in the
16various perf commands with the -e option.
17
18[[EVENT_MODIFIERS]]
19EVENT MODIFIERS
20---------------
21
22Events can optionally have a modifier by appending a colon and one or
23more modifiers. Modifiers allow the user to restrict the events to be
24counted. The following modifiers exist:
25
26 u - user-space counting
27 k - kernel counting
28 h - hypervisor counting
29 I - non idle counting
30 G - guest counting (in KVM guests)
31 H - host counting (not in KVM guests)
32 p - precise level
33 P - use maximum detected precise level
34 S - read sample value (PERF_SAMPLE_READ)
35 D - pin the event to the PMU
36
37The 'p' modifier can be used for specifying how precise the instruction
38address should be. The 'p' modifier can be specified multiple times:
39
40 0 - SAMPLE_IP can have arbitrary skid
41 1 - SAMPLE_IP must have constant skid
42 2 - SAMPLE_IP requested to have 0 skid
43 3 - SAMPLE_IP must have 0 skid, or uses randomization to avoid
44 sample shadowing effects.
45
46For Intel systems precise event sampling is implemented with PEBS
47which supports up to precise-level 2, and precise level 3 for
48some special cases
49
50On AMD systems it is implemented using IBS (up to precise-level 2).
51The precise modifier works with event types 0x76 (cpu-cycles, CPU
52clocks not halted) and 0xC1 (micro-ops retired). Both events map to
53IBS execution sampling (IBS op) with the IBS Op Counter Control bit
54(IbsOpCntCtl) set respectively (see AMD64 Architecture Programmer’s
55Manual Volume 2: System Programming, 13.3 Instruction-Based
56Sampling). Examples to use IBS:
57
58 perf record -a -e cpu-cycles:p ... # use ibs op counting cycles
59 perf record -a -e r076:p ... # same as -e cpu-cycles:p
60 perf record -a -e r0C1:p ... # use ibs op counting micro-ops
61
62RAW HARDWARE EVENT DESCRIPTOR
63-----------------------------
64Even when an event is not available in a symbolic form within perf right now,
65it can be encoded in a per processor specific way.
66
67For instance For x86 CPUs NNN represents the raw register encoding with the
68layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide] Figure 30-1 Layout
69of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344,
70Figure 13-7 Performance Event-Select Register (PerfEvtSeln)).
71
72Note: Only the following bit fields can be set in x86 counter
73registers: event, umask, edge, inv, cmask. Esp. guest/host only and
74OS/user mode flags must be setup using <<EVENT_MODIFIERS, EVENT
75MODIFIERS>>.
76
77Example:
78
79If the Intel docs for a QM720 Core i7 describe an event as:
80
81 Event Umask Event Mask
82 Num. Value Mnemonic Description Comment
83
84 A8H 01H LSD.UOPS Counts the number of micro-ops Use cmask=1 and
85 delivered by loop stream detector invert to count
86 cycles
87
88raw encoding of 0x1A8 can be used:
89
90 perf stat -e r1a8 -a sleep 1
91 perf record -e r1a8 ...
92
93You should refer to the processor specific documentation for getting these
94details. Some of them are referenced in the SEE ALSO section below.
95
96PARAMETERIZED EVENTS
97--------------------
98
99Some pmu events listed by 'perf-list' will be displayed with '?' in them. For
100example:
101
102 hv_gpci/dtbp_ptitc,phys_processor_idx=?/
103
104This means that when provided as an event, a value for '?' must
105also be supplied. For example:
106
107 perf stat -C 0 -e 'hv_gpci/dtbp_ptitc,phys_processor_idx=0x2/' ...
108
109OPTIONS
110-------
111
112Without options all known events will be listed.
113
114To limit the list use:
115
116. 'hw' or 'hardware' to list hardware events such as cache-misses, etc.
117
118. 'sw' or 'software' to list software events such as context switches, etc.
119
120. 'cache' or 'hwcache' to list hardware cache events such as L1-dcache-loads, etc.
121
122. 'tracepoint' to list all tracepoint events, alternatively use
123 'subsys_glob:event_glob' to filter by tracepoint subsystems such as sched,
124 block, etc.
125
126. 'pmu' to print the kernel supplied PMU events.
127
128. If none of the above is matched, it will apply the supplied glob to all
129 events, printing the ones that match.
130
131. As a last resort, it will do a substring search in all event names.
132
133One or more types can be used at the same time, listing the events for the
134types specified.
135
136Support raw format:
137
138. '--raw-dump', shows the raw-dump of all the events.
139. '--raw-dump [hw|sw|cache|tracepoint|pmu|event_glob]', shows the raw-dump of
140 a certain kind of events.
141
142SEE ALSO
143--------
144linkperf:perf-stat[1], linkperf:perf-top[1],
145linkperf:perf-record[1],
146http://www.intel.com/Assets/PDF/manual/253669.pdf[Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide],
147http://support.amd.com/us/Processor_TechDocs/24593_APM_v2.pdf[AMD64 Architecture Programmer’s Manual Volume 2: System Programming]