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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Cadence UART driver (found in Xilinx Zynq)
4 *
5 * 2011 - 2014 (C) Xilinx Inc.
6 *
7 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
8 * still shows in the naming of this file, the kconfig symbols and some symbols
9 * in the code.
10 */
11
12#if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
13#define SUPPORT_SYSRQ
14#endif
15
16#include <linux/platform_device.h>
17#include <linux/serial.h>
18#include <linux/console.h>
19#include <linux/serial_core.h>
20#include <linux/slab.h>
21#include <linux/tty.h>
22#include <linux/tty_flip.h>
23#include <linux/clk.h>
24#include <linux/irq.h>
25#include <linux/io.h>
26#include <linux/of.h>
27#include <linux/module.h>
28#include <linux/pm_runtime.h>
29#include <linux/iopoll.h>
30
31#define CDNS_UART_TTY_NAME "ttyPS"
32#define CDNS_UART_NAME "xuartps"
33#define CDNS_UART_FIFO_SIZE 64 /* FIFO size */
34#define CDNS_UART_REGISTER_SPACE 0x1000
35#define TX_TIMEOUT 500000
36
37/* Rx Trigger level */
38static int rx_trigger_level = 56;
39static int uartps_major;
40module_param(rx_trigger_level, uint, 0444);
41MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
42
43/* Rx Timeout */
44static int rx_timeout = 10;
45module_param(rx_timeout, uint, 0444);
46MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
47
48/* Register offsets for the UART. */
49#define CDNS_UART_CR 0x00 /* Control Register */
50#define CDNS_UART_MR 0x04 /* Mode Register */
51#define CDNS_UART_IER 0x08 /* Interrupt Enable */
52#define CDNS_UART_IDR 0x0C /* Interrupt Disable */
53#define CDNS_UART_IMR 0x10 /* Interrupt Mask */
54#define CDNS_UART_ISR 0x14 /* Interrupt Status */
55#define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */
56#define CDNS_UART_RXTOUT 0x1C /* RX Timeout */
57#define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */
58#define CDNS_UART_MODEMCR 0x24 /* Modem Control */
59#define CDNS_UART_MODEMSR 0x28 /* Modem Status */
60#define CDNS_UART_SR 0x2C /* Channel Status */
61#define CDNS_UART_FIFO 0x30 /* FIFO */
62#define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */
63#define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */
64#define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */
65#define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */
66#define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */
67#define CDNS_UART_RXBS 0x48 /* RX FIFO byte status register */
68
69/* Control Register Bit Definitions */
70#define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */
71#define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */
72#define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */
73#define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */
74#define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */
75#define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */
76#define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */
77#define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */
78#define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
79#define CDNS_UART_RXBS_PARITY 0x00000001 /* Parity error status */
80#define CDNS_UART_RXBS_FRAMING 0x00000002 /* Framing error status */
81#define CDNS_UART_RXBS_BRK 0x00000004 /* Overrun error status */
82
83/*
84 * Mode Register:
85 * The mode register (MR) defines the mode of transfer as well as the data
86 * format. If this register is modified during transmission or reception,
87 * data validity cannot be guaranteed.
88 */
89#define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
90#define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
91#define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */
92#define CDNS_UART_MR_CHMODE_MASK 0x00000300 /* Mask for mode bits */
93
94#define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
95#define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
96
97#define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
98#define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
99#define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
100#define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
101#define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
102
103#define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
104#define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
105#define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
106
107/*
108 * Interrupt Registers:
109 * Interrupt control logic uses the interrupt enable register (IER) and the
110 * interrupt disable register (IDR) to set the value of the bits in the
111 * interrupt mask register (IMR). The IMR determines whether to pass an
112 * interrupt to the interrupt status register (ISR).
113 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
114 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
115 * Reading either IER or IDR returns 0x00.
116 * All four registers have the same bit definitions.
117 */
118#define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
119#define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */
120#define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */
121#define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
122#define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
123#define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
124#define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
125#define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
126#define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
127#define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
128#define CDNS_UART_IXR_RXMASK 0x000021e7 /* Valid RX bit mask */
129
130 /*
131 * Do not enable parity error interrupt for the following
132 * reason: When parity error interrupt is enabled, each Rx
133 * parity error always results in 2 events. The first one
134 * being parity error interrupt and the second one with a
135 * proper Rx interrupt with the incoming data. Disabling
136 * parity error interrupt ensures better handling of parity
137 * error events. With this change, for a parity error case, we
138 * get a Rx interrupt with parity error set in ISR register
139 * and we still handle parity errors in the desired way.
140 */
141
142#define CDNS_UART_RX_IRQS (CDNS_UART_IXR_FRAMING | \
143 CDNS_UART_IXR_OVERRUN | \
144 CDNS_UART_IXR_RXTRIG | \
145 CDNS_UART_IXR_TOUT)
146
147/* Goes in read_status_mask for break detection as the HW doesn't do it*/
148#define CDNS_UART_IXR_BRK 0x00002000
149
150#define CDNS_UART_RXBS_SUPPORT BIT(1)
151/*
152 * Modem Control register:
153 * The read/write Modem Control register controls the interface with the modem
154 * or data set, or a peripheral device emulating a modem.
155 */
156#define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */
157#define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */
158#define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */
159
160/*
161 * Channel Status Register:
162 * The channel status register (CSR) is provided to enable the control logic
163 * to monitor the status of bits in the channel interrupt status register,
164 * even if these are masked out by the interrupt mask register.
165 */
166#define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
167#define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
168#define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
169#define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */
170#define CDNS_UART_SR_TACTIVE 0x00000800 /* TX state machine active */
171
172/* baud dividers min/max values */
173#define CDNS_UART_BDIV_MIN 4
174#define CDNS_UART_BDIV_MAX 255
175#define CDNS_UART_CD_MAX 65535
176#define UART_AUTOSUSPEND_TIMEOUT 3000
177
178/**
179 * struct cdns_uart - device data
180 * @port: Pointer to the UART port
181 * @uartclk: Reference clock
182 * @pclk: APB clock
183 * @cdns_uart_driver: Pointer to UART driver
184 * @baud: Current baud rate
185 * @id: Port ID
186 * @clk_rate_change_nb: Notifier block for clock changes
187 * @quirks: Flags for RXBS support.
188 */
189struct cdns_uart {
190 struct uart_port *port;
191 struct clk *uartclk;
192 struct clk *pclk;
193 struct uart_driver *cdns_uart_driver;
194 unsigned int baud;
195 int id;
196 struct notifier_block clk_rate_change_nb;
197 u32 quirks;
198 bool cts_override;
199};
200struct cdns_platform_data {
201 u32 quirks;
202};
203#define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
204 clk_rate_change_nb)
205
206/**
207 * cdns_uart_handle_rx - Handle the received bytes along with Rx errors.
208 * @dev_id: Id of the UART port
209 * @isrstatus: The interrupt status register value as read
210 * Return: None
211 */
212static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus)
213{
214 struct uart_port *port = (struct uart_port *)dev_id;
215 struct cdns_uart *cdns_uart = port->private_data;
216 unsigned int data;
217 unsigned int rxbs_status = 0;
218 unsigned int status_mask;
219 unsigned int framerrprocessed = 0;
220 char status = TTY_NORMAL;
221 bool is_rxbs_support;
222
223 is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
224
225 while ((readl(port->membase + CDNS_UART_SR) &
226 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
227 if (is_rxbs_support)
228 rxbs_status = readl(port->membase + CDNS_UART_RXBS);
229 data = readl(port->membase + CDNS_UART_FIFO);
230 port->icount.rx++;
231 /*
232 * There is no hardware break detection in Zynq, so we interpret
233 * framing error with all-zeros data as a break sequence.
234 * Most of the time, there's another non-zero byte at the
235 * end of the sequence.
236 */
237 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) {
238 if (!data) {
239 port->read_status_mask |= CDNS_UART_IXR_BRK;
240 framerrprocessed = 1;
241 continue;
242 }
243 }
244 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) {
245 port->icount.brk++;
246 status = TTY_BREAK;
247 if (uart_handle_break(port))
248 continue;
249 }
250
251 isrstatus &= port->read_status_mask;
252 isrstatus &= ~port->ignore_status_mask;
253 status_mask = port->read_status_mask;
254 status_mask &= ~port->ignore_status_mask;
255
256 if (data &&
257 (port->read_status_mask & CDNS_UART_IXR_BRK)) {
258 port->read_status_mask &= ~CDNS_UART_IXR_BRK;
259 port->icount.brk++;
260 if (uart_handle_break(port))
261 continue;
262 }
263
264 if (uart_handle_sysrq_char(port, data))
265 continue;
266
267 if (is_rxbs_support) {
268 if ((rxbs_status & CDNS_UART_RXBS_PARITY)
269 && (status_mask & CDNS_UART_IXR_PARITY)) {
270 port->icount.parity++;
271 status = TTY_PARITY;
272 }
273 if ((rxbs_status & CDNS_UART_RXBS_FRAMING)
274 && (status_mask & CDNS_UART_IXR_PARITY)) {
275 port->icount.frame++;
276 status = TTY_FRAME;
277 }
278 } else {
279 if (isrstatus & CDNS_UART_IXR_PARITY) {
280 port->icount.parity++;
281 status = TTY_PARITY;
282 }
283 if ((isrstatus & CDNS_UART_IXR_FRAMING) &&
284 !framerrprocessed) {
285 port->icount.frame++;
286 status = TTY_FRAME;
287 }
288 }
289 if (isrstatus & CDNS_UART_IXR_OVERRUN) {
290 port->icount.overrun++;
291 tty_insert_flip_char(&port->state->port, 0,
292 TTY_OVERRUN);
293 }
294 tty_insert_flip_char(&port->state->port, data, status);
295 isrstatus = 0;
296 }
297 spin_unlock(&port->lock);
298 tty_flip_buffer_push(&port->state->port);
299 spin_lock(&port->lock);
300}
301
302/**
303 * cdns_uart_handle_tx - Handle the bytes to be Txed.
304 * @dev_id: Id of the UART port
305 * Return: None
306 */
307static void cdns_uart_handle_tx(void *dev_id)
308{
309 struct uart_port *port = (struct uart_port *)dev_id;
310 unsigned int numbytes;
311
312 if (uart_circ_empty(&port->state->xmit)) {
313 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
314 } else {
315 numbytes = port->fifosize;
316 while (numbytes && !uart_circ_empty(&port->state->xmit) &&
317 !(readl(port->membase + CDNS_UART_SR) &
318 CDNS_UART_SR_TXFULL)) {
319 /*
320 * Get the data from the UART circular buffer
321 * and write it to the cdns_uart's TX_FIFO
322 * register.
323 */
324 writel(
325 port->state->xmit.buf[port->state->xmit.tail],
326 port->membase + CDNS_UART_FIFO);
327
328 port->icount.tx++;
329
330 /*
331 * Adjust the tail of the UART buffer and wrap
332 * the buffer if it reaches limit.
333 */
334 port->state->xmit.tail =
335 (port->state->xmit.tail + 1) &
336 (UART_XMIT_SIZE - 1);
337
338 numbytes--;
339 }
340
341 if (uart_circ_chars_pending(
342 &port->state->xmit) < WAKEUP_CHARS)
343 uart_write_wakeup(port);
344 }
345}
346
347/**
348 * cdns_uart_isr - Interrupt handler
349 * @irq: Irq number
350 * @dev_id: Id of the port
351 *
352 * Return: IRQHANDLED
353 */
354static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
355{
356 struct uart_port *port = (struct uart_port *)dev_id;
357 unsigned int isrstatus;
358
359 spin_lock(&port->lock);
360
361 /* Read the interrupt status register to determine which
362 * interrupt(s) is/are active and clear them.
363 */
364 isrstatus = readl(port->membase + CDNS_UART_ISR);
365 writel(isrstatus, port->membase + CDNS_UART_ISR);
366
367 if (isrstatus & CDNS_UART_IXR_TXEMPTY) {
368 cdns_uart_handle_tx(dev_id);
369 isrstatus &= ~CDNS_UART_IXR_TXEMPTY;
370 }
371
372 /*
373 * Skip RX processing if RX is disabled as RXEMPTY will never be set
374 * as read bytes will not be removed from the FIFO.
375 */
376 if (isrstatus & CDNS_UART_IXR_RXMASK &&
377 !(readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS))
378 cdns_uart_handle_rx(dev_id, isrstatus);
379
380 spin_unlock(&port->lock);
381 return IRQ_HANDLED;
382}
383
384/**
385 * cdns_uart_calc_baud_divs - Calculate baud rate divisors
386 * @clk: UART module input clock
387 * @baud: Desired baud rate
388 * @rbdiv: BDIV value (return value)
389 * @rcd: CD value (return value)
390 * @div8: Value for clk_sel bit in mod (return value)
391 * Return: baud rate, requested baud when possible, or actual baud when there
392 * was too much error, zero if no valid divisors are found.
393 *
394 * Formula to obtain baud rate is
395 * baud_tx/rx rate = clk/CD * (BDIV + 1)
396 * input_clk = (Uart User Defined Clock or Apb Clock)
397 * depends on UCLKEN in MR Reg
398 * clk = input_clk or input_clk/8;
399 * depends on CLKS in MR reg
400 * CD and BDIV depends on values in
401 * baud rate generate register
402 * baud rate clock divisor register
403 */
404static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
405 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
406{
407 u32 cd, bdiv;
408 unsigned int calc_baud;
409 unsigned int bestbaud = 0;
410 unsigned int bauderror;
411 unsigned int besterror = ~0;
412
413 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
414 *div8 = 1;
415 clk /= 8;
416 } else {
417 *div8 = 0;
418 }
419
420 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
421 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
422 if (cd < 1 || cd > CDNS_UART_CD_MAX)
423 continue;
424
425 calc_baud = clk / (cd * (bdiv + 1));
426
427 if (baud > calc_baud)
428 bauderror = baud - calc_baud;
429 else
430 bauderror = calc_baud - baud;
431
432 if (besterror > bauderror) {
433 *rbdiv = bdiv;
434 *rcd = cd;
435 bestbaud = calc_baud;
436 besterror = bauderror;
437 }
438 }
439 /* use the values when percent error is acceptable */
440 if (((besterror * 100) / baud) < 3)
441 bestbaud = baud;
442
443 return bestbaud;
444}
445
446/**
447 * cdns_uart_set_baud_rate - Calculate and set the baud rate
448 * @port: Handle to the uart port structure
449 * @baud: Baud rate to set
450 * Return: baud rate, requested baud when possible, or actual baud when there
451 * was too much error, zero if no valid divisors are found.
452 */
453static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
454 unsigned int baud)
455{
456 unsigned int calc_baud;
457 u32 cd = 0, bdiv = 0;
458 u32 mreg;
459 int div8;
460 struct cdns_uart *cdns_uart = port->private_data;
461
462 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
463 &div8);
464
465 /* Write new divisors to hardware */
466 mreg = readl(port->membase + CDNS_UART_MR);
467 if (div8)
468 mreg |= CDNS_UART_MR_CLKSEL;
469 else
470 mreg &= ~CDNS_UART_MR_CLKSEL;
471 writel(mreg, port->membase + CDNS_UART_MR);
472 writel(cd, port->membase + CDNS_UART_BAUDGEN);
473 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
474 cdns_uart->baud = baud;
475
476 return calc_baud;
477}
478
479#ifdef CONFIG_COMMON_CLK
480/**
481 * cdns_uart_clk_notitifer_cb - Clock notifier callback
482 * @nb: Notifier block
483 * @event: Notify event
484 * @data: Notifier data
485 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
486 */
487static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
488 unsigned long event, void *data)
489{
490 u32 ctrl_reg;
491 struct uart_port *port;
492 int locked = 0;
493 struct clk_notifier_data *ndata = data;
494 unsigned long flags = 0;
495 struct cdns_uart *cdns_uart = to_cdns_uart(nb);
496
497 port = cdns_uart->port;
498 if (port->suspended)
499 return NOTIFY_OK;
500
501 switch (event) {
502 case PRE_RATE_CHANGE:
503 {
504 u32 bdiv, cd;
505 int div8;
506
507 /*
508 * Find out if current baud-rate can be achieved with new clock
509 * frequency.
510 */
511 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
512 &bdiv, &cd, &div8)) {
513 dev_warn(port->dev, "clock rate change rejected\n");
514 return NOTIFY_BAD;
515 }
516
517 spin_lock_irqsave(&cdns_uart->port->lock, flags);
518
519 /* Disable the TX and RX to set baud rate */
520 ctrl_reg = readl(port->membase + CDNS_UART_CR);
521 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
522 writel(ctrl_reg, port->membase + CDNS_UART_CR);
523
524 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
525
526 return NOTIFY_OK;
527 }
528 case POST_RATE_CHANGE:
529 /*
530 * Set clk dividers to generate correct baud with new clock
531 * frequency.
532 */
533
534 spin_lock_irqsave(&cdns_uart->port->lock, flags);
535
536 locked = 1;
537 port->uartclk = ndata->new_rate;
538
539 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
540 cdns_uart->baud);
541 /* fall through */
542 case ABORT_RATE_CHANGE:
543 if (!locked)
544 spin_lock_irqsave(&cdns_uart->port->lock, flags);
545
546 /* Set TX/RX Reset */
547 ctrl_reg = readl(port->membase + CDNS_UART_CR);
548 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
549 writel(ctrl_reg, port->membase + CDNS_UART_CR);
550
551 while (readl(port->membase + CDNS_UART_CR) &
552 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
553 cpu_relax();
554
555 /*
556 * Clear the RX disable and TX disable bits and then set the TX
557 * enable bit and RX enable bit to enable the transmitter and
558 * receiver.
559 */
560 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
561 ctrl_reg = readl(port->membase + CDNS_UART_CR);
562 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
563 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
564 writel(ctrl_reg, port->membase + CDNS_UART_CR);
565
566 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
567
568 return NOTIFY_OK;
569 default:
570 return NOTIFY_DONE;
571 }
572}
573#endif
574
575/**
576 * cdns_uart_start_tx - Start transmitting bytes
577 * @port: Handle to the uart port structure
578 */
579static void cdns_uart_start_tx(struct uart_port *port)
580{
581 unsigned int status;
582
583 if (uart_tx_stopped(port))
584 return;
585
586 /*
587 * Set the TX enable bit and clear the TX disable bit to enable the
588 * transmitter.
589 */
590 status = readl(port->membase + CDNS_UART_CR);
591 status &= ~CDNS_UART_CR_TX_DIS;
592 status |= CDNS_UART_CR_TX_EN;
593 writel(status, port->membase + CDNS_UART_CR);
594
595 if (uart_circ_empty(&port->state->xmit))
596 return;
597
598 cdns_uart_handle_tx(port);
599
600 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
601 /* Enable the TX Empty interrupt */
602 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER);
603}
604
605/**
606 * cdns_uart_stop_tx - Stop TX
607 * @port: Handle to the uart port structure
608 */
609static void cdns_uart_stop_tx(struct uart_port *port)
610{
611 unsigned int regval;
612
613 regval = readl(port->membase + CDNS_UART_CR);
614 regval |= CDNS_UART_CR_TX_DIS;
615 /* Disable the transmitter */
616 writel(regval, port->membase + CDNS_UART_CR);
617}
618
619/**
620 * cdns_uart_stop_rx - Stop RX
621 * @port: Handle to the uart port structure
622 */
623static void cdns_uart_stop_rx(struct uart_port *port)
624{
625 unsigned int regval;
626
627 /* Disable RX IRQs */
628 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
629
630 /* Disable the receiver */
631 regval = readl(port->membase + CDNS_UART_CR);
632 regval |= CDNS_UART_CR_RX_DIS;
633 writel(regval, port->membase + CDNS_UART_CR);
634}
635
636/**
637 * cdns_uart_tx_empty - Check whether TX is empty
638 * @port: Handle to the uart port structure
639 *
640 * Return: TIOCSER_TEMT on success, 0 otherwise
641 */
642static unsigned int cdns_uart_tx_empty(struct uart_port *port)
643{
644 unsigned int status;
645
646 status = readl(port->membase + CDNS_UART_SR) &
647 CDNS_UART_SR_TXEMPTY;
648 return status ? TIOCSER_TEMT : 0;
649}
650
651/**
652 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
653 * transmitting char breaks
654 * @port: Handle to the uart port structure
655 * @ctl: Value based on which start or stop decision is taken
656 */
657static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
658{
659 unsigned int status;
660 unsigned long flags;
661
662 spin_lock_irqsave(&port->lock, flags);
663
664 status = readl(port->membase + CDNS_UART_CR);
665
666 if (ctl == -1)
667 writel(CDNS_UART_CR_STARTBRK | status,
668 port->membase + CDNS_UART_CR);
669 else {
670 if ((status & CDNS_UART_CR_STOPBRK) == 0)
671 writel(CDNS_UART_CR_STOPBRK | status,
672 port->membase + CDNS_UART_CR);
673 }
674 spin_unlock_irqrestore(&port->lock, flags);
675}
676
677/**
678 * cdns_uart_set_termios - termios operations, handling data length, parity,
679 * stop bits, flow control, baud rate
680 * @port: Handle to the uart port structure
681 * @termios: Handle to the input termios structure
682 * @old: Values of the previously saved termios structure
683 */
684static void cdns_uart_set_termios(struct uart_port *port,
685 struct ktermios *termios, struct ktermios *old)
686{
687 unsigned int cval = 0;
688 unsigned int baud, minbaud, maxbaud;
689 unsigned long flags;
690 unsigned int ctrl_reg, mode_reg, val;
691 int err;
692
693 /* Wait for the transmit FIFO to empty before making changes */
694 if (!(readl(port->membase + CDNS_UART_CR) &
695 CDNS_UART_CR_TX_DIS)) {
696 err = readl_poll_timeout(port->membase + CDNS_UART_SR,
697 val, (val & CDNS_UART_SR_TXEMPTY),
698 1000, TX_TIMEOUT);
699 if (err) {
700 dev_err(port->dev, "timed out waiting for tx empty");
701 return;
702 }
703 }
704 spin_lock_irqsave(&port->lock, flags);
705
706 /* Disable the TX and RX to set baud rate */
707 ctrl_reg = readl(port->membase + CDNS_UART_CR);
708 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
709 writel(ctrl_reg, port->membase + CDNS_UART_CR);
710
711 /*
712 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
713 * min and max baud should be calculated here based on port->uartclk.
714 * this way we get a valid baud and can safely call set_baud()
715 */
716 minbaud = port->uartclk /
717 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
718 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
719 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
720 baud = cdns_uart_set_baud_rate(port, baud);
721 if (tty_termios_baud_rate(termios))
722 tty_termios_encode_baud_rate(termios, baud, baud);
723
724 /* Update the per-port timeout. */
725 uart_update_timeout(port, termios->c_cflag, baud);
726
727 /* Set TX/RX Reset */
728 ctrl_reg = readl(port->membase + CDNS_UART_CR);
729 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
730 writel(ctrl_reg, port->membase + CDNS_UART_CR);
731
732 while (readl(port->membase + CDNS_UART_CR) &
733 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
734 cpu_relax();
735
736 /*
737 * Clear the RX disable and TX disable bits and then set the TX enable
738 * bit and RX enable bit to enable the transmitter and receiver.
739 */
740 ctrl_reg = readl(port->membase + CDNS_UART_CR);
741 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
742 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
743 writel(ctrl_reg, port->membase + CDNS_UART_CR);
744
745 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
746
747 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
748 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
749 port->ignore_status_mask = 0;
750
751 if (termios->c_iflag & INPCK)
752 port->read_status_mask |= CDNS_UART_IXR_PARITY |
753 CDNS_UART_IXR_FRAMING;
754
755 if (termios->c_iflag & IGNPAR)
756 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
757 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
758
759 /* ignore all characters if CREAD is not set */
760 if ((termios->c_cflag & CREAD) == 0)
761 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
762 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
763 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
764
765 mode_reg = readl(port->membase + CDNS_UART_MR);
766
767 /* Handling Data Size */
768 switch (termios->c_cflag & CSIZE) {
769 case CS6:
770 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
771 break;
772 case CS7:
773 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
774 break;
775 default:
776 case CS8:
777 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
778 termios->c_cflag &= ~CSIZE;
779 termios->c_cflag |= CS8;
780 break;
781 }
782
783 /* Handling Parity and Stop Bits length */
784 if (termios->c_cflag & CSTOPB)
785 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
786 else
787 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
788
789 if (termios->c_cflag & PARENB) {
790 /* Mark or Space parity */
791 if (termios->c_cflag & CMSPAR) {
792 if (termios->c_cflag & PARODD)
793 cval |= CDNS_UART_MR_PARITY_MARK;
794 else
795 cval |= CDNS_UART_MR_PARITY_SPACE;
796 } else {
797 if (termios->c_cflag & PARODD)
798 cval |= CDNS_UART_MR_PARITY_ODD;
799 else
800 cval |= CDNS_UART_MR_PARITY_EVEN;
801 }
802 } else {
803 cval |= CDNS_UART_MR_PARITY_NONE;
804 }
805 cval |= mode_reg & 1;
806 writel(cval, port->membase + CDNS_UART_MR);
807
808 spin_unlock_irqrestore(&port->lock, flags);
809}
810
811/**
812 * cdns_uart_startup - Called when an application opens a cdns_uart port
813 * @port: Handle to the uart port structure
814 *
815 * Return: 0 on success, negative errno otherwise
816 */
817static int cdns_uart_startup(struct uart_port *port)
818{
819 struct cdns_uart *cdns_uart = port->private_data;
820 bool is_brk_support;
821 int ret;
822 unsigned long flags;
823 unsigned int status = 0;
824
825 is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
826
827 spin_lock_irqsave(&port->lock, flags);
828
829 /* Disable the TX and RX */
830 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
831 port->membase + CDNS_UART_CR);
832
833 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
834 * no break chars.
835 */
836 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
837 port->membase + CDNS_UART_CR);
838
839 while (readl(port->membase + CDNS_UART_CR) &
840 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
841 cpu_relax();
842
843 /*
844 * Clear the RX disable bit and then set the RX enable bit to enable
845 * the receiver.
846 */
847 status = readl(port->membase + CDNS_UART_CR);
848 status &= ~CDNS_UART_CR_RX_DIS;
849 status |= CDNS_UART_CR_RX_EN;
850 writel(status, port->membase + CDNS_UART_CR);
851
852 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
853 * no parity.
854 */
855 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
856 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
857 port->membase + CDNS_UART_MR);
858
859 /*
860 * Set the RX FIFO Trigger level to use most of the FIFO, but it
861 * can be tuned with a module parameter
862 */
863 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
864
865 /*
866 * Receive Timeout register is enabled but it
867 * can be tuned with a module parameter
868 */
869 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
870
871 /* Clear out any pending interrupts before enabling them */
872 writel(readl(port->membase + CDNS_UART_ISR),
873 port->membase + CDNS_UART_ISR);
874
875 spin_unlock_irqrestore(&port->lock, flags);
876
877 ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);
878 if (ret) {
879 dev_err(port->dev, "request_irq '%d' failed with %d\n",
880 port->irq, ret);
881 return ret;
882 }
883
884 /* Set the Interrupt Registers with desired interrupts */
885 if (is_brk_support)
886 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK,
887 port->membase + CDNS_UART_IER);
888 else
889 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
890
891 return 0;
892}
893
894/**
895 * cdns_uart_shutdown - Called when an application closes a cdns_uart port
896 * @port: Handle to the uart port structure
897 */
898static void cdns_uart_shutdown(struct uart_port *port)
899{
900 int status;
901 unsigned long flags;
902
903 spin_lock_irqsave(&port->lock, flags);
904
905 /* Disable interrupts */
906 status = readl(port->membase + CDNS_UART_IMR);
907 writel(status, port->membase + CDNS_UART_IDR);
908 writel(0xffffffff, port->membase + CDNS_UART_ISR);
909
910 /* Disable the TX and RX */
911 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
912 port->membase + CDNS_UART_CR);
913
914 spin_unlock_irqrestore(&port->lock, flags);
915
916 free_irq(port->irq, port);
917}
918
919/**
920 * cdns_uart_type - Set UART type to cdns_uart port
921 * @port: Handle to the uart port structure
922 *
923 * Return: string on success, NULL otherwise
924 */
925static const char *cdns_uart_type(struct uart_port *port)
926{
927 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
928}
929
930/**
931 * cdns_uart_verify_port - Verify the port params
932 * @port: Handle to the uart port structure
933 * @ser: Handle to the structure whose members are compared
934 *
935 * Return: 0 on success, negative errno otherwise.
936 */
937static int cdns_uart_verify_port(struct uart_port *port,
938 struct serial_struct *ser)
939{
940 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
941 return -EINVAL;
942 if (port->irq != ser->irq)
943 return -EINVAL;
944 if (ser->io_type != UPIO_MEM)
945 return -EINVAL;
946 if (port->iobase != ser->port)
947 return -EINVAL;
948 if (ser->hub6 != 0)
949 return -EINVAL;
950 return 0;
951}
952
953/**
954 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
955 * called when the driver adds a cdns_uart port via
956 * uart_add_one_port()
957 * @port: Handle to the uart port structure
958 *
959 * Return: 0 on success, negative errno otherwise.
960 */
961static int cdns_uart_request_port(struct uart_port *port)
962{
963 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
964 CDNS_UART_NAME)) {
965 return -ENOMEM;
966 }
967
968 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
969 if (!port->membase) {
970 dev_err(port->dev, "Unable to map registers\n");
971 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
972 return -ENOMEM;
973 }
974 return 0;
975}
976
977/**
978 * cdns_uart_release_port - Release UART port
979 * @port: Handle to the uart port structure
980 *
981 * Release the memory region attached to a cdns_uart port. Called when the
982 * driver removes a cdns_uart port via uart_remove_one_port().
983 */
984static void cdns_uart_release_port(struct uart_port *port)
985{
986 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
987 iounmap(port->membase);
988 port->membase = NULL;
989}
990
991/**
992 * cdns_uart_config_port - Configure UART port
993 * @port: Handle to the uart port structure
994 * @flags: If any
995 */
996static void cdns_uart_config_port(struct uart_port *port, int flags)
997{
998 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
999 port->type = PORT_XUARTPS;
1000}
1001
1002/**
1003 * cdns_uart_get_mctrl - Get the modem control state
1004 * @port: Handle to the uart port structure
1005 *
1006 * Return: the modem control state
1007 */
1008static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
1009{
1010 struct cdns_uart *cdns_uart_data = port->private_data;
1011
1012 if (cdns_uart_data->cts_override)
1013 return 0;
1014
1015 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
1016}
1017
1018static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1019{
1020 u32 val;
1021 u32 mode_reg;
1022 struct cdns_uart *cdns_uart_data = port->private_data;
1023
1024 if (cdns_uart_data->cts_override)
1025 return;
1026
1027 val = readl(port->membase + CDNS_UART_MODEMCR);
1028 mode_reg = readl(port->membase + CDNS_UART_MR);
1029
1030 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR |
1031 CDNS_UART_MODEMCR_FCM);
1032 mode_reg &= ~CDNS_UART_MR_CHMODE_MASK;
1033
1034 if (mctrl & TIOCM_RTS || mctrl & TIOCM_DTR)
1035 val |= CDNS_UART_MODEMCR_FCM;
1036 if (mctrl & TIOCM_LOOP)
1037 mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP;
1038 else
1039 mode_reg |= CDNS_UART_MR_CHMODE_NORM;
1040
1041 writel(val, port->membase + CDNS_UART_MODEMCR);
1042 writel(mode_reg, port->membase + CDNS_UART_MR);
1043}
1044
1045#ifdef CONFIG_CONSOLE_POLL
1046static int cdns_uart_poll_get_char(struct uart_port *port)
1047{
1048 int c;
1049 unsigned long flags;
1050
1051 spin_lock_irqsave(&port->lock, flags);
1052
1053 /* Check if FIFO is empty */
1054 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
1055 c = NO_POLL_CHAR;
1056 else /* Read a character */
1057 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
1058
1059 spin_unlock_irqrestore(&port->lock, flags);
1060
1061 return c;
1062}
1063
1064static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
1065{
1066 unsigned long flags;
1067
1068 spin_lock_irqsave(&port->lock, flags);
1069
1070 /* Wait until FIFO is empty */
1071 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1072 cpu_relax();
1073
1074 /* Write a character */
1075 writel(c, port->membase + CDNS_UART_FIFO);
1076
1077 /* Wait until FIFO is empty */
1078 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1079 cpu_relax();
1080
1081 spin_unlock_irqrestore(&port->lock, flags);
1082}
1083#endif
1084
1085static void cdns_uart_pm(struct uart_port *port, unsigned int state,
1086 unsigned int oldstate)
1087{
1088 switch (state) {
1089 case UART_PM_STATE_OFF:
1090 pm_runtime_mark_last_busy(port->dev);
1091 pm_runtime_put_autosuspend(port->dev);
1092 break;
1093 default:
1094 pm_runtime_get_sync(port->dev);
1095 break;
1096 }
1097}
1098
1099static const struct uart_ops cdns_uart_ops = {
1100 .set_mctrl = cdns_uart_set_mctrl,
1101 .get_mctrl = cdns_uart_get_mctrl,
1102 .start_tx = cdns_uart_start_tx,
1103 .stop_tx = cdns_uart_stop_tx,
1104 .stop_rx = cdns_uart_stop_rx,
1105 .tx_empty = cdns_uart_tx_empty,
1106 .break_ctl = cdns_uart_break_ctl,
1107 .set_termios = cdns_uart_set_termios,
1108 .startup = cdns_uart_startup,
1109 .shutdown = cdns_uart_shutdown,
1110 .pm = cdns_uart_pm,
1111 .type = cdns_uart_type,
1112 .verify_port = cdns_uart_verify_port,
1113 .request_port = cdns_uart_request_port,
1114 .release_port = cdns_uart_release_port,
1115 .config_port = cdns_uart_config_port,
1116#ifdef CONFIG_CONSOLE_POLL
1117 .poll_get_char = cdns_uart_poll_get_char,
1118 .poll_put_char = cdns_uart_poll_put_char,
1119#endif
1120};
1121
1122#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1123/**
1124 * cdns_uart_console_putchar - write the character to the FIFO buffer
1125 * @port: Handle to the uart port structure
1126 * @ch: Character to be written
1127 */
1128static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1129{
1130 while (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)
1131 cpu_relax();
1132 writel(ch, port->membase + CDNS_UART_FIFO);
1133}
1134
1135static void cdns_early_write(struct console *con, const char *s,
1136 unsigned n)
1137{
1138 struct earlycon_device *dev = con->data;
1139
1140 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1141}
1142
1143static int __init cdns_early_console_setup(struct earlycon_device *device,
1144 const char *opt)
1145{
1146 struct uart_port *port = &device->port;
1147
1148 if (!port->membase)
1149 return -ENODEV;
1150
1151 /* initialise control register */
1152 writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST,
1153 port->membase + CDNS_UART_CR);
1154
1155 /* only set baud if specified on command line - otherwise
1156 * assume it has been initialized by a boot loader.
1157 */
1158 if (port->uartclk && device->baud) {
1159 u32 cd = 0, bdiv = 0;
1160 u32 mr;
1161 int div8;
1162
1163 cdns_uart_calc_baud_divs(port->uartclk, device->baud,
1164 &bdiv, &cd, &div8);
1165 mr = CDNS_UART_MR_PARITY_NONE;
1166 if (div8)
1167 mr |= CDNS_UART_MR_CLKSEL;
1168
1169 writel(mr, port->membase + CDNS_UART_MR);
1170 writel(cd, port->membase + CDNS_UART_BAUDGEN);
1171 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
1172 }
1173
1174 device->con->write = cdns_early_write;
1175
1176 return 0;
1177}
1178OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);
1179OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);
1180OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);
1181OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup);
1182
1183
1184/* Static pointer to console port */
1185static struct uart_port *console_port;
1186
1187/**
1188 * cdns_uart_console_write - perform write operation
1189 * @co: Console handle
1190 * @s: Pointer to character array
1191 * @count: No of characters
1192 */
1193static void cdns_uart_console_write(struct console *co, const char *s,
1194 unsigned int count)
1195{
1196 struct uart_port *port = console_port;
1197 unsigned long flags = 0;
1198 unsigned int imr, ctrl;
1199 int locked = 1;
1200
1201 if (port->sysrq)
1202 locked = 0;
1203 else if (oops_in_progress)
1204 locked = spin_trylock_irqsave(&port->lock, flags);
1205 else
1206 spin_lock_irqsave(&port->lock, flags);
1207
1208 /* save and disable interrupt */
1209 imr = readl(port->membase + CDNS_UART_IMR);
1210 writel(imr, port->membase + CDNS_UART_IDR);
1211
1212 /*
1213 * Make sure that the tx part is enabled. Set the TX enable bit and
1214 * clear the TX disable bit to enable the transmitter.
1215 */
1216 ctrl = readl(port->membase + CDNS_UART_CR);
1217 ctrl &= ~CDNS_UART_CR_TX_DIS;
1218 ctrl |= CDNS_UART_CR_TX_EN;
1219 writel(ctrl, port->membase + CDNS_UART_CR);
1220
1221 uart_console_write(port, s, count, cdns_uart_console_putchar);
1222 while ((readl(port->membase + CDNS_UART_SR) &
1223 (CDNS_UART_SR_TXEMPTY | CDNS_UART_SR_TACTIVE)) !=
1224 CDNS_UART_SR_TXEMPTY)
1225 cpu_relax();
1226
1227 /* restore interrupt state */
1228 writel(imr, port->membase + CDNS_UART_IER);
1229
1230 if (locked)
1231 spin_unlock_irqrestore(&port->lock, flags);
1232}
1233
1234/**
1235 * cdns_uart_console_setup - Initialize the uart to default config
1236 * @co: Console handle
1237 * @options: Initial settings of uart
1238 *
1239 * Return: 0 on success, negative errno otherwise.
1240 */
1241static int cdns_uart_console_setup(struct console *co, char *options)
1242{
1243 struct uart_port *port = console_port;
1244
1245 int baud = 9600;
1246 int bits = 8;
1247 int parity = 'n';
1248 int flow = 'n';
1249
1250 if (!port->membase) {
1251 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1252 co->index);
1253 return -ENODEV;
1254 }
1255
1256 if (options)
1257 uart_parse_options(options, &baud, &parity, &bits, &flow);
1258
1259 return uart_set_options(port, co, baud, parity, bits, flow);
1260}
1261#endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1262
1263#ifdef CONFIG_PM_SLEEP
1264/**
1265 * cdns_uart_suspend - suspend event
1266 * @device: Pointer to the device structure
1267 *
1268 * Return: 0
1269 */
1270static int cdns_uart_suspend(struct device *device)
1271{
1272 struct uart_port *port = dev_get_drvdata(device);
1273 struct cdns_uart *cdns_uart = port->private_data;
1274 int may_wake;
1275
1276 may_wake = device_may_wakeup(device);
1277
1278 if (console_suspend_enabled && uart_console(port) && may_wake) {
1279 unsigned long flags = 0;
1280
1281 spin_lock_irqsave(&port->lock, flags);
1282 /* Empty the receive FIFO 1st before making changes */
1283 while (!(readl(port->membase + CDNS_UART_SR) &
1284 CDNS_UART_SR_RXEMPTY))
1285 readl(port->membase + CDNS_UART_FIFO);
1286 /* set RX trigger level to 1 */
1287 writel(1, port->membase + CDNS_UART_RXWM);
1288 /* disable RX timeout interrups */
1289 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1290 spin_unlock_irqrestore(&port->lock, flags);
1291 }
1292
1293 /*
1294 * Call the API provided in serial_core.c file which handles
1295 * the suspend.
1296 */
1297 return uart_suspend_port(cdns_uart->cdns_uart_driver, port);
1298}
1299
1300/**
1301 * cdns_uart_resume - Resume after a previous suspend
1302 * @device: Pointer to the device structure
1303 *
1304 * Return: 0
1305 */
1306static int cdns_uart_resume(struct device *device)
1307{
1308 struct uart_port *port = dev_get_drvdata(device);
1309 struct cdns_uart *cdns_uart = port->private_data;
1310 unsigned long flags = 0;
1311 u32 ctrl_reg;
1312 int may_wake;
1313
1314 may_wake = device_may_wakeup(device);
1315
1316 if (console_suspend_enabled && uart_console(port) && !may_wake) {
1317 clk_enable(cdns_uart->pclk);
1318 clk_enable(cdns_uart->uartclk);
1319
1320 spin_lock_irqsave(&port->lock, flags);
1321
1322 /* Set TX/RX Reset */
1323 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1324 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1325 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1326 while (readl(port->membase + CDNS_UART_CR) &
1327 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1328 cpu_relax();
1329
1330 /* restore rx timeout value */
1331 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1332 /* Enable Tx/Rx */
1333 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1334 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1335 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1336 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1337
1338 clk_disable(cdns_uart->uartclk);
1339 clk_disable(cdns_uart->pclk);
1340 spin_unlock_irqrestore(&port->lock, flags);
1341 } else {
1342 spin_lock_irqsave(&port->lock, flags);
1343 /* restore original rx trigger level */
1344 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1345 /* enable RX timeout interrupt */
1346 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
1347 spin_unlock_irqrestore(&port->lock, flags);
1348 }
1349
1350 return uart_resume_port(cdns_uart->cdns_uart_driver, port);
1351}
1352#endif /* ! CONFIG_PM_SLEEP */
1353static int __maybe_unused cdns_runtime_suspend(struct device *dev)
1354{
1355 struct uart_port *port = dev_get_drvdata(dev);
1356 struct cdns_uart *cdns_uart = port->private_data;
1357
1358 clk_disable(cdns_uart->uartclk);
1359 clk_disable(cdns_uart->pclk);
1360 return 0;
1361};
1362
1363static int __maybe_unused cdns_runtime_resume(struct device *dev)
1364{
1365 struct uart_port *port = dev_get_drvdata(dev);
1366 struct cdns_uart *cdns_uart = port->private_data;
1367
1368 clk_enable(cdns_uart->pclk);
1369 clk_enable(cdns_uart->uartclk);
1370 return 0;
1371};
1372
1373static const struct dev_pm_ops cdns_uart_dev_pm_ops = {
1374 SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume)
1375 SET_RUNTIME_PM_OPS(cdns_runtime_suspend,
1376 cdns_runtime_resume, NULL)
1377};
1378
1379static const struct cdns_platform_data zynqmp_uart_def = {
1380 .quirks = CDNS_UART_RXBS_SUPPORT, };
1381
1382/* Match table for of_platform binding */
1383static const struct of_device_id cdns_uart_of_match[] = {
1384 { .compatible = "xlnx,xuartps", },
1385 { .compatible = "cdns,uart-r1p8", },
1386 { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def },
1387 { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def },
1388 {}
1389};
1390MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1391
1392/*
1393 * Maximum number of instances without alias IDs but if there is alias
1394 * which target "< MAX_UART_INSTANCES" range this ID can't be used.
1395 */
1396#define MAX_UART_INSTANCES 32
1397
1398/* Stores static aliases list */
1399static DECLARE_BITMAP(alias_bitmap, MAX_UART_INSTANCES);
1400static int alias_bitmap_initialized;
1401
1402/* Stores actual bitmap of allocated IDs with alias IDs together */
1403static DECLARE_BITMAP(bitmap, MAX_UART_INSTANCES);
1404/* Protect bitmap operations to have unique IDs */
1405static DEFINE_MUTEX(bitmap_lock);
1406
1407static int cdns_get_id(struct platform_device *pdev)
1408{
1409 int id, ret;
1410
1411 mutex_lock(&bitmap_lock);
1412
1413 /* Alias list is stable that's why get alias bitmap only once */
1414 if (!alias_bitmap_initialized) {
1415 ret = of_alias_get_alias_list(cdns_uart_of_match, "serial",
1416 alias_bitmap, MAX_UART_INSTANCES);
1417 if (ret && ret != -EOVERFLOW) {
1418 mutex_unlock(&bitmap_lock);
1419 return ret;
1420 }
1421
1422 alias_bitmap_initialized++;
1423 }
1424
1425 /* Make sure that alias ID is not taken by instance without alias */
1426 bitmap_or(bitmap, bitmap, alias_bitmap, MAX_UART_INSTANCES);
1427
1428 dev_dbg(&pdev->dev, "Alias bitmap: %*pb\n",
1429 MAX_UART_INSTANCES, bitmap);
1430
1431 /* Look for a serialN alias */
1432 id = of_alias_get_id(pdev->dev.of_node, "serial");
1433 if (id < 0) {
1434 dev_warn(&pdev->dev,
1435 "No serial alias passed. Using the first free id\n");
1436
1437 /*
1438 * Start with id 0 and check if there is no serial0 alias
1439 * which points to device which is compatible with this driver.
1440 * If alias exists then try next free position.
1441 */
1442 id = 0;
1443
1444 for (;;) {
1445 dev_info(&pdev->dev, "Checking id %d\n", id);
1446 id = find_next_zero_bit(bitmap, MAX_UART_INSTANCES, id);
1447
1448 /* No free empty instance */
1449 if (id == MAX_UART_INSTANCES) {
1450 dev_err(&pdev->dev, "No free ID\n");
1451 mutex_unlock(&bitmap_lock);
1452 return -EINVAL;
1453 }
1454
1455 dev_dbg(&pdev->dev, "The empty id is %d\n", id);
1456 /* Check if ID is empty */
1457 if (!test_and_set_bit(id, bitmap)) {
1458 /* Break the loop if bit is taken */
1459 dev_dbg(&pdev->dev,
1460 "Selected ID %d allocation passed\n",
1461 id);
1462 break;
1463 }
1464 dev_dbg(&pdev->dev,
1465 "Selected ID %d allocation failed\n", id);
1466 /* if taking bit fails then try next one */
1467 id++;
1468 }
1469 }
1470
1471 mutex_unlock(&bitmap_lock);
1472
1473 return id;
1474}
1475
1476/**
1477 * cdns_uart_probe - Platform driver probe
1478 * @pdev: Pointer to the platform device structure
1479 *
1480 * Return: 0 on success, negative errno otherwise
1481 */
1482static int cdns_uart_probe(struct platform_device *pdev)
1483{
1484 int rc, irq;
1485 struct uart_port *port;
1486 struct resource *res;
1487 struct cdns_uart *cdns_uart_data;
1488 const struct of_device_id *match;
1489 struct uart_driver *cdns_uart_uart_driver;
1490 char *driver_name;
1491#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1492 struct console *cdns_uart_console;
1493#endif
1494
1495 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1496 GFP_KERNEL);
1497 if (!cdns_uart_data)
1498 return -ENOMEM;
1499 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
1500 if (!port)
1501 return -ENOMEM;
1502
1503 cdns_uart_uart_driver = devm_kzalloc(&pdev->dev,
1504 sizeof(*cdns_uart_uart_driver),
1505 GFP_KERNEL);
1506 if (!cdns_uart_uart_driver)
1507 return -ENOMEM;
1508
1509 cdns_uart_data->id = cdns_get_id(pdev);
1510 if (cdns_uart_data->id < 0)
1511 return cdns_uart_data->id;
1512
1513 /* There is a need to use unique driver name */
1514 driver_name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%s%d",
1515 CDNS_UART_NAME, cdns_uart_data->id);
1516 if (!driver_name) {
1517 rc = -ENOMEM;
1518 goto err_out_id;
1519 }
1520
1521 cdns_uart_uart_driver->owner = THIS_MODULE;
1522 cdns_uart_uart_driver->driver_name = driver_name;
1523 cdns_uart_uart_driver->dev_name = CDNS_UART_TTY_NAME;
1524 cdns_uart_uart_driver->major = uartps_major;
1525 cdns_uart_uart_driver->minor = cdns_uart_data->id;
1526 cdns_uart_uart_driver->nr = 1;
1527
1528#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1529 cdns_uart_console = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_console),
1530 GFP_KERNEL);
1531 if (!cdns_uart_console) {
1532 rc = -ENOMEM;
1533 goto err_out_id;
1534 }
1535
1536 strncpy(cdns_uart_console->name, CDNS_UART_TTY_NAME,
1537 sizeof(cdns_uart_console->name));
1538 cdns_uart_console->index = cdns_uart_data->id;
1539 cdns_uart_console->write = cdns_uart_console_write;
1540 cdns_uart_console->device = uart_console_device;
1541 cdns_uart_console->setup = cdns_uart_console_setup;
1542 cdns_uart_console->flags = CON_PRINTBUFFER;
1543 cdns_uart_console->data = cdns_uart_uart_driver;
1544 cdns_uart_uart_driver->cons = cdns_uart_console;
1545#endif
1546
1547 rc = uart_register_driver(cdns_uart_uart_driver);
1548 if (rc < 0) {
1549 dev_err(&pdev->dev, "Failed to register driver\n");
1550 goto err_out_id;
1551 }
1552
1553 cdns_uart_data->cdns_uart_driver = cdns_uart_uart_driver;
1554
1555 /*
1556 * Setting up proper name_base needs to be done after uart
1557 * registration because tty_driver structure is not filled.
1558 * name_base is 0 by default.
1559 */
1560 cdns_uart_uart_driver->tty_driver->name_base = cdns_uart_data->id;
1561
1562 match = of_match_node(cdns_uart_of_match, pdev->dev.of_node);
1563 if (match && match->data) {
1564 const struct cdns_platform_data *data = match->data;
1565
1566 cdns_uart_data->quirks = data->quirks;
1567 }
1568
1569 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1570 if (PTR_ERR(cdns_uart_data->pclk) == -EPROBE_DEFER) {
1571 rc = PTR_ERR(cdns_uart_data->pclk);
1572 goto err_out_unregister_driver;
1573 }
1574
1575 if (IS_ERR(cdns_uart_data->pclk)) {
1576 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1577 if (IS_ERR(cdns_uart_data->pclk)) {
1578 rc = PTR_ERR(cdns_uart_data->pclk);
1579 goto err_out_unregister_driver;
1580 }
1581 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1582 }
1583
1584 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1585 if (PTR_ERR(cdns_uart_data->uartclk) == -EPROBE_DEFER) {
1586 rc = PTR_ERR(cdns_uart_data->uartclk);
1587 goto err_out_unregister_driver;
1588 }
1589
1590 if (IS_ERR(cdns_uart_data->uartclk)) {
1591 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1592 if (IS_ERR(cdns_uart_data->uartclk)) {
1593 rc = PTR_ERR(cdns_uart_data->uartclk);
1594 goto err_out_unregister_driver;
1595 }
1596 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1597 }
1598
1599 rc = clk_prepare_enable(cdns_uart_data->pclk);
1600 if (rc) {
1601 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1602 goto err_out_unregister_driver;
1603 }
1604 rc = clk_prepare_enable(cdns_uart_data->uartclk);
1605 if (rc) {
1606 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1607 goto err_out_clk_dis_pclk;
1608 }
1609
1610 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1611 if (!res) {
1612 rc = -ENODEV;
1613 goto err_out_clk_disable;
1614 }
1615
1616 irq = platform_get_irq(pdev, 0);
1617 if (irq <= 0) {
1618 rc = -ENXIO;
1619 goto err_out_clk_disable;
1620 }
1621
1622#ifdef CONFIG_COMMON_CLK
1623 cdns_uart_data->clk_rate_change_nb.notifier_call =
1624 cdns_uart_clk_notifier_cb;
1625 if (clk_notifier_register(cdns_uart_data->uartclk,
1626 &cdns_uart_data->clk_rate_change_nb))
1627 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1628#endif
1629
1630 /* At this point, we've got an empty uart_port struct, initialize it */
1631 spin_lock_init(&port->lock);
1632 port->type = PORT_UNKNOWN;
1633 port->iotype = UPIO_MEM32;
1634 port->flags = UPF_BOOT_AUTOCONF;
1635 port->ops = &cdns_uart_ops;
1636 port->fifosize = CDNS_UART_FIFO_SIZE;
1637
1638 /*
1639 * Register the port.
1640 * This function also registers this device with the tty layer
1641 * and triggers invocation of the config_port() entry point.
1642 */
1643 port->mapbase = res->start;
1644 port->irq = irq;
1645 port->dev = &pdev->dev;
1646 port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1647 port->private_data = cdns_uart_data;
1648 cdns_uart_data->port = port;
1649 platform_set_drvdata(pdev, port);
1650
1651 pm_runtime_use_autosuspend(&pdev->dev);
1652 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
1653 pm_runtime_set_active(&pdev->dev);
1654 pm_runtime_enable(&pdev->dev);
1655 device_init_wakeup(port->dev, true);
1656
1657#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1658 /*
1659 * If console hasn't been found yet try to assign this port
1660 * because it is required to be assigned for console setup function.
1661 * If register_console() don't assign value, then console_port pointer
1662 * is cleanup.
1663 */
1664 if (!console_port)
1665 console_port = port;
1666#endif
1667
1668 rc = uart_add_one_port(cdns_uart_uart_driver, port);
1669 if (rc) {
1670 dev_err(&pdev->dev,
1671 "uart_add_one_port() failed; err=%i\n", rc);
1672 goto err_out_pm_disable;
1673 }
1674
1675#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1676 /* This is not port which is used for console that's why clean it up */
1677 if (console_port == port &&
1678 !(cdns_uart_uart_driver->cons->flags & CON_ENABLED))
1679 console_port = NULL;
1680#endif
1681
1682 uartps_major = cdns_uart_uart_driver->tty_driver->major;
1683 cdns_uart_data->cts_override = of_property_read_bool(pdev->dev.of_node,
1684 "cts-override");
1685 return 0;
1686
1687err_out_pm_disable:
1688 pm_runtime_disable(&pdev->dev);
1689 pm_runtime_set_suspended(&pdev->dev);
1690 pm_runtime_dont_use_autosuspend(&pdev->dev);
1691#ifdef CONFIG_COMMON_CLK
1692 clk_notifier_unregister(cdns_uart_data->uartclk,
1693 &cdns_uart_data->clk_rate_change_nb);
1694#endif
1695err_out_clk_disable:
1696 clk_disable_unprepare(cdns_uart_data->uartclk);
1697err_out_clk_dis_pclk:
1698 clk_disable_unprepare(cdns_uart_data->pclk);
1699err_out_unregister_driver:
1700 uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
1701err_out_id:
1702 mutex_lock(&bitmap_lock);
1703 if (cdns_uart_data->id < MAX_UART_INSTANCES)
1704 clear_bit(cdns_uart_data->id, bitmap);
1705 mutex_unlock(&bitmap_lock);
1706 return rc;
1707}
1708
1709/**
1710 * cdns_uart_remove - called when the platform driver is unregistered
1711 * @pdev: Pointer to the platform device structure
1712 *
1713 * Return: 0 on success, negative errno otherwise
1714 */
1715static int cdns_uart_remove(struct platform_device *pdev)
1716{
1717 struct uart_port *port = platform_get_drvdata(pdev);
1718 struct cdns_uart *cdns_uart_data = port->private_data;
1719 int rc;
1720
1721 /* Remove the cdns_uart port from the serial core */
1722#ifdef CONFIG_COMMON_CLK
1723 clk_notifier_unregister(cdns_uart_data->uartclk,
1724 &cdns_uart_data->clk_rate_change_nb);
1725#endif
1726 rc = uart_remove_one_port(cdns_uart_data->cdns_uart_driver, port);
1727 port->mapbase = 0;
1728 mutex_lock(&bitmap_lock);
1729 if (cdns_uart_data->id < MAX_UART_INSTANCES)
1730 clear_bit(cdns_uart_data->id, bitmap);
1731 mutex_unlock(&bitmap_lock);
1732 clk_disable_unprepare(cdns_uart_data->uartclk);
1733 clk_disable_unprepare(cdns_uart_data->pclk);
1734 pm_runtime_disable(&pdev->dev);
1735 pm_runtime_set_suspended(&pdev->dev);
1736 pm_runtime_dont_use_autosuspend(&pdev->dev);
1737 device_init_wakeup(&pdev->dev, false);
1738
1739#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1740 if (console_port == port)
1741 console_port = NULL;
1742#endif
1743
1744 /* If this is last instance major number should be initialized */
1745 mutex_lock(&bitmap_lock);
1746 if (bitmap_empty(bitmap, MAX_UART_INSTANCES))
1747 uartps_major = 0;
1748 mutex_unlock(&bitmap_lock);
1749
1750 uart_unregister_driver(cdns_uart_data->cdns_uart_driver);
1751 return rc;
1752}
1753
1754static struct platform_driver cdns_uart_platform_driver = {
1755 .probe = cdns_uart_probe,
1756 .remove = cdns_uart_remove,
1757 .driver = {
1758 .name = CDNS_UART_NAME,
1759 .of_match_table = cdns_uart_of_match,
1760 .pm = &cdns_uart_dev_pm_ops,
1761 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_XILINX_PS_UART),
1762 },
1763};
1764
1765static int __init cdns_uart_init(void)
1766{
1767 /* Register the platform driver */
1768 return platform_driver_register(&cdns_uart_platform_driver);
1769}
1770
1771static void __exit cdns_uart_exit(void)
1772{
1773 /* Unregister the platform driver */
1774 platform_driver_unregister(&cdns_uart_platform_driver);
1775}
1776
1777arch_initcall(cdns_uart_init);
1778module_exit(cdns_uart_exit);
1779
1780MODULE_DESCRIPTION("Driver for Cadence UART");
1781MODULE_AUTHOR("Xilinx Inc.");
1782MODULE_LICENSE("GPL");
1/*
2 * Cadence UART driver (found in Xilinx Zynq)
3 *
4 * 2011 - 2014 (C) Xilinx Inc.
5 *
6 * This program is free software; you can redistribute it
7 * and/or modify it under the terms of the GNU General Public
8 * License as published by the Free Software Foundation;
9 * either version 2 of the License, or (at your option) any
10 * later version.
11 *
12 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
13 * still shows in the naming of this file, the kconfig symbols and some symbols
14 * in the code.
15 */
16
17#if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
18#define SUPPORT_SYSRQ
19#endif
20
21#include <linux/platform_device.h>
22#include <linux/serial.h>
23#include <linux/console.h>
24#include <linux/serial_core.h>
25#include <linux/slab.h>
26#include <linux/tty.h>
27#include <linux/tty_flip.h>
28#include <linux/clk.h>
29#include <linux/irq.h>
30#include <linux/io.h>
31#include <linux/of.h>
32#include <linux/module.h>
33
34#define CDNS_UART_TTY_NAME "ttyPS"
35#define CDNS_UART_NAME "xuartps"
36#define CDNS_UART_MAJOR 0 /* use dynamic node allocation */
37#define CDNS_UART_MINOR 0 /* works best with devtmpfs */
38#define CDNS_UART_NR_PORTS 2
39#define CDNS_UART_FIFO_SIZE 64 /* FIFO size */
40#define CDNS_UART_REGISTER_SPACE 0x1000
41
42/* Rx Trigger level */
43static int rx_trigger_level = 56;
44module_param(rx_trigger_level, uint, S_IRUGO);
45MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
46
47/* Rx Timeout */
48static int rx_timeout = 10;
49module_param(rx_timeout, uint, S_IRUGO);
50MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
51
52/* Register offsets for the UART. */
53#define CDNS_UART_CR 0x00 /* Control Register */
54#define CDNS_UART_MR 0x04 /* Mode Register */
55#define CDNS_UART_IER 0x08 /* Interrupt Enable */
56#define CDNS_UART_IDR 0x0C /* Interrupt Disable */
57#define CDNS_UART_IMR 0x10 /* Interrupt Mask */
58#define CDNS_UART_ISR 0x14 /* Interrupt Status */
59#define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */
60#define CDNS_UART_RXTOUT 0x1C /* RX Timeout */
61#define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */
62#define CDNS_UART_MODEMCR 0x24 /* Modem Control */
63#define CDNS_UART_MODEMSR 0x28 /* Modem Status */
64#define CDNS_UART_SR 0x2C /* Channel Status */
65#define CDNS_UART_FIFO 0x30 /* FIFO */
66#define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */
67#define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */
68#define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */
69#define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */
70#define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */
71
72/* Control Register Bit Definitions */
73#define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */
74#define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */
75#define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */
76#define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */
77#define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */
78#define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */
79#define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */
80#define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */
81#define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
82
83/*
84 * Mode Register:
85 * The mode register (MR) defines the mode of transfer as well as the data
86 * format. If this register is modified during transmission or reception,
87 * data validity cannot be guaranteed.
88 */
89#define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
90#define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
91#define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */
92
93#define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
94#define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
95
96#define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
97#define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
98#define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
99#define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
100#define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
101
102#define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
103#define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
104#define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
105
106/*
107 * Interrupt Registers:
108 * Interrupt control logic uses the interrupt enable register (IER) and the
109 * interrupt disable register (IDR) to set the value of the bits in the
110 * interrupt mask register (IMR). The IMR determines whether to pass an
111 * interrupt to the interrupt status register (ISR).
112 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
113 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
114 * Reading either IER or IDR returns 0x00.
115 * All four registers have the same bit definitions.
116 */
117#define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
118#define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */
119#define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */
120#define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
121#define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
122#define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
123#define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
124#define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
125#define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
126#define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
127#define CDNS_UART_IXR_MASK 0x00001FFF /* Valid bit mask */
128
129#define CDNS_UART_RX_IRQS (CDNS_UART_IXR_PARITY | CDNS_UART_IXR_FRAMING | \
130 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_RXTRIG | \
131 CDNS_UART_IXR_TOUT)
132
133/* Goes in read_status_mask for break detection as the HW doesn't do it*/
134#define CDNS_UART_IXR_BRK 0x80000000
135
136/*
137 * Modem Control register:
138 * The read/write Modem Control register controls the interface with the modem
139 * or data set, or a peripheral device emulating a modem.
140 */
141#define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */
142#define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */
143#define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */
144
145/*
146 * Channel Status Register:
147 * The channel status register (CSR) is provided to enable the control logic
148 * to monitor the status of bits in the channel interrupt status register,
149 * even if these are masked out by the interrupt mask register.
150 */
151#define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
152#define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
153#define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
154#define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */
155
156/* baud dividers min/max values */
157#define CDNS_UART_BDIV_MIN 4
158#define CDNS_UART_BDIV_MAX 255
159#define CDNS_UART_CD_MAX 65535
160
161/**
162 * struct cdns_uart - device data
163 * @port: Pointer to the UART port
164 * @uartclk: Reference clock
165 * @pclk: APB clock
166 * @baud: Current baud rate
167 * @clk_rate_change_nb: Notifier block for clock changes
168 */
169struct cdns_uart {
170 struct uart_port *port;
171 struct clk *uartclk;
172 struct clk *pclk;
173 unsigned int baud;
174 struct notifier_block clk_rate_change_nb;
175};
176#define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
177 clk_rate_change_nb);
178
179static void cdns_uart_handle_rx(struct uart_port *port, unsigned int isrstatus)
180{
181 /*
182 * There is no hardware break detection, so we interpret framing
183 * error with all-zeros data as a break sequence. Most of the time,
184 * there's another non-zero byte at the end of the sequence.
185 */
186 if (isrstatus & CDNS_UART_IXR_FRAMING) {
187 while (!(readl(port->membase + CDNS_UART_SR) &
188 CDNS_UART_SR_RXEMPTY)) {
189 if (!readl(port->membase + CDNS_UART_FIFO)) {
190 port->read_status_mask |= CDNS_UART_IXR_BRK;
191 isrstatus &= ~CDNS_UART_IXR_FRAMING;
192 }
193 }
194 writel(CDNS_UART_IXR_FRAMING, port->membase + CDNS_UART_ISR);
195 }
196
197 /* drop byte with parity error if IGNPAR specified */
198 if (isrstatus & port->ignore_status_mask & CDNS_UART_IXR_PARITY)
199 isrstatus &= ~(CDNS_UART_IXR_RXTRIG | CDNS_UART_IXR_TOUT);
200
201 isrstatus &= port->read_status_mask;
202 isrstatus &= ~port->ignore_status_mask;
203
204 if (!(isrstatus & (CDNS_UART_IXR_TOUT | CDNS_UART_IXR_RXTRIG)))
205 return;
206
207 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)) {
208 u32 data;
209 char status = TTY_NORMAL;
210
211 data = readl(port->membase + CDNS_UART_FIFO);
212
213 /* Non-NULL byte after BREAK is garbage (99%) */
214 if (data && (port->read_status_mask & CDNS_UART_IXR_BRK)) {
215 port->read_status_mask &= ~CDNS_UART_IXR_BRK;
216 port->icount.brk++;
217 if (uart_handle_break(port))
218 continue;
219 }
220
221 if (uart_handle_sysrq_char(port, data))
222 continue;
223
224 port->icount.rx++;
225
226 if (isrstatus & CDNS_UART_IXR_PARITY) {
227 port->icount.parity++;
228 status = TTY_PARITY;
229 } else if (isrstatus & CDNS_UART_IXR_FRAMING) {
230 port->icount.frame++;
231 status = TTY_FRAME;
232 } else if (isrstatus & CDNS_UART_IXR_OVERRUN) {
233 port->icount.overrun++;
234 }
235
236 uart_insert_char(port, isrstatus, CDNS_UART_IXR_OVERRUN,
237 data, status);
238 }
239 tty_flip_buffer_push(&port->state->port);
240}
241
242static void cdns_uart_handle_tx(struct uart_port *port)
243{
244 unsigned int numbytes;
245
246 if (uart_circ_empty(&port->state->xmit)) {
247 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
248 return;
249 }
250
251 numbytes = port->fifosize;
252 while (numbytes && !uart_circ_empty(&port->state->xmit) &&
253 !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) {
254 /*
255 * Get the data from the UART circular buffer
256 * and write it to the cdns_uart's TX_FIFO
257 * register.
258 */
259 writel(port->state->xmit.buf[port->state->xmit.tail],
260 port->membase + CDNS_UART_FIFO);
261 port->icount.tx++;
262
263 /*
264 * Adjust the tail of the UART buffer and wrap
265 * the buffer if it reaches limit.
266 */
267 port->state->xmit.tail =
268 (port->state->xmit.tail + 1) & (UART_XMIT_SIZE - 1);
269
270 numbytes--;
271 }
272
273 if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS)
274 uart_write_wakeup(port);
275}
276
277/**
278 * cdns_uart_isr - Interrupt handler
279 * @irq: Irq number
280 * @dev_id: Id of the port
281 *
282 * Return: IRQHANDLED
283 */
284static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
285{
286 struct uart_port *port = (struct uart_port *)dev_id;
287 unsigned long flags;
288 unsigned int isrstatus;
289
290 spin_lock_irqsave(&port->lock, flags);
291
292 /* Read the interrupt status register to determine which
293 * interrupt(s) is/are active.
294 */
295 isrstatus = readl(port->membase + CDNS_UART_ISR);
296
297 if (isrstatus & CDNS_UART_RX_IRQS)
298 cdns_uart_handle_rx(port, isrstatus);
299
300 if ((isrstatus & CDNS_UART_IXR_TXEMPTY) == CDNS_UART_IXR_TXEMPTY)
301 cdns_uart_handle_tx(port);
302
303 writel(isrstatus, port->membase + CDNS_UART_ISR);
304
305 /* be sure to release the lock and tty before leaving */
306 spin_unlock_irqrestore(&port->lock, flags);
307
308 return IRQ_HANDLED;
309}
310
311/**
312 * cdns_uart_calc_baud_divs - Calculate baud rate divisors
313 * @clk: UART module input clock
314 * @baud: Desired baud rate
315 * @rbdiv: BDIV value (return value)
316 * @rcd: CD value (return value)
317 * @div8: Value for clk_sel bit in mod (return value)
318 * Return: baud rate, requested baud when possible, or actual baud when there
319 * was too much error, zero if no valid divisors are found.
320 *
321 * Formula to obtain baud rate is
322 * baud_tx/rx rate = clk/CD * (BDIV + 1)
323 * input_clk = (Uart User Defined Clock or Apb Clock)
324 * depends on UCLKEN in MR Reg
325 * clk = input_clk or input_clk/8;
326 * depends on CLKS in MR reg
327 * CD and BDIV depends on values in
328 * baud rate generate register
329 * baud rate clock divisor register
330 */
331static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
332 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
333{
334 u32 cd, bdiv;
335 unsigned int calc_baud;
336 unsigned int bestbaud = 0;
337 unsigned int bauderror;
338 unsigned int besterror = ~0;
339
340 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
341 *div8 = 1;
342 clk /= 8;
343 } else {
344 *div8 = 0;
345 }
346
347 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
348 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
349 if (cd < 1 || cd > CDNS_UART_CD_MAX)
350 continue;
351
352 calc_baud = clk / (cd * (bdiv + 1));
353
354 if (baud > calc_baud)
355 bauderror = baud - calc_baud;
356 else
357 bauderror = calc_baud - baud;
358
359 if (besterror > bauderror) {
360 *rbdiv = bdiv;
361 *rcd = cd;
362 bestbaud = calc_baud;
363 besterror = bauderror;
364 }
365 }
366 /* use the values when percent error is acceptable */
367 if (((besterror * 100) / baud) < 3)
368 bestbaud = baud;
369
370 return bestbaud;
371}
372
373/**
374 * cdns_uart_set_baud_rate - Calculate and set the baud rate
375 * @port: Handle to the uart port structure
376 * @baud: Baud rate to set
377 * Return: baud rate, requested baud when possible, or actual baud when there
378 * was too much error, zero if no valid divisors are found.
379 */
380static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
381 unsigned int baud)
382{
383 unsigned int calc_baud;
384 u32 cd = 0, bdiv = 0;
385 u32 mreg;
386 int div8;
387 struct cdns_uart *cdns_uart = port->private_data;
388
389 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
390 &div8);
391
392 /* Write new divisors to hardware */
393 mreg = readl(port->membase + CDNS_UART_MR);
394 if (div8)
395 mreg |= CDNS_UART_MR_CLKSEL;
396 else
397 mreg &= ~CDNS_UART_MR_CLKSEL;
398 writel(mreg, port->membase + CDNS_UART_MR);
399 writel(cd, port->membase + CDNS_UART_BAUDGEN);
400 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
401 cdns_uart->baud = baud;
402
403 return calc_baud;
404}
405
406#ifdef CONFIG_COMMON_CLK
407/**
408 * cdns_uart_clk_notitifer_cb - Clock notifier callback
409 * @nb: Notifier block
410 * @event: Notify event
411 * @data: Notifier data
412 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
413 */
414static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
415 unsigned long event, void *data)
416{
417 u32 ctrl_reg;
418 struct uart_port *port;
419 int locked = 0;
420 struct clk_notifier_data *ndata = data;
421 unsigned long flags = 0;
422 struct cdns_uart *cdns_uart = to_cdns_uart(nb);
423
424 port = cdns_uart->port;
425 if (port->suspended)
426 return NOTIFY_OK;
427
428 switch (event) {
429 case PRE_RATE_CHANGE:
430 {
431 u32 bdiv, cd;
432 int div8;
433
434 /*
435 * Find out if current baud-rate can be achieved with new clock
436 * frequency.
437 */
438 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
439 &bdiv, &cd, &div8)) {
440 dev_warn(port->dev, "clock rate change rejected\n");
441 return NOTIFY_BAD;
442 }
443
444 spin_lock_irqsave(&cdns_uart->port->lock, flags);
445
446 /* Disable the TX and RX to set baud rate */
447 ctrl_reg = readl(port->membase + CDNS_UART_CR);
448 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
449 writel(ctrl_reg, port->membase + CDNS_UART_CR);
450
451 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
452
453 return NOTIFY_OK;
454 }
455 case POST_RATE_CHANGE:
456 /*
457 * Set clk dividers to generate correct baud with new clock
458 * frequency.
459 */
460
461 spin_lock_irqsave(&cdns_uart->port->lock, flags);
462
463 locked = 1;
464 port->uartclk = ndata->new_rate;
465
466 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
467 cdns_uart->baud);
468 /* fall through */
469 case ABORT_RATE_CHANGE:
470 if (!locked)
471 spin_lock_irqsave(&cdns_uart->port->lock, flags);
472
473 /* Set TX/RX Reset */
474 ctrl_reg = readl(port->membase + CDNS_UART_CR);
475 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
476 writel(ctrl_reg, port->membase + CDNS_UART_CR);
477
478 while (readl(port->membase + CDNS_UART_CR) &
479 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
480 cpu_relax();
481
482 /*
483 * Clear the RX disable and TX disable bits and then set the TX
484 * enable bit and RX enable bit to enable the transmitter and
485 * receiver.
486 */
487 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
488 ctrl_reg = readl(port->membase + CDNS_UART_CR);
489 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
490 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
491 writel(ctrl_reg, port->membase + CDNS_UART_CR);
492
493 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
494
495 return NOTIFY_OK;
496 default:
497 return NOTIFY_DONE;
498 }
499}
500#endif
501
502/**
503 * cdns_uart_start_tx - Start transmitting bytes
504 * @port: Handle to the uart port structure
505 */
506static void cdns_uart_start_tx(struct uart_port *port)
507{
508 unsigned int status;
509
510 if (uart_tx_stopped(port))
511 return;
512
513 /*
514 * Set the TX enable bit and clear the TX disable bit to enable the
515 * transmitter.
516 */
517 status = readl(port->membase + CDNS_UART_CR);
518 status &= ~CDNS_UART_CR_TX_DIS;
519 status |= CDNS_UART_CR_TX_EN;
520 writel(status, port->membase + CDNS_UART_CR);
521
522 if (uart_circ_empty(&port->state->xmit))
523 return;
524
525 cdns_uart_handle_tx(port);
526
527 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
528 /* Enable the TX Empty interrupt */
529 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER);
530}
531
532/**
533 * cdns_uart_stop_tx - Stop TX
534 * @port: Handle to the uart port structure
535 */
536static void cdns_uart_stop_tx(struct uart_port *port)
537{
538 unsigned int regval;
539
540 regval = readl(port->membase + CDNS_UART_CR);
541 regval |= CDNS_UART_CR_TX_DIS;
542 /* Disable the transmitter */
543 writel(regval, port->membase + CDNS_UART_CR);
544}
545
546/**
547 * cdns_uart_stop_rx - Stop RX
548 * @port: Handle to the uart port structure
549 */
550static void cdns_uart_stop_rx(struct uart_port *port)
551{
552 unsigned int regval;
553
554 /* Disable RX IRQs */
555 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
556
557 /* Disable the receiver */
558 regval = readl(port->membase + CDNS_UART_CR);
559 regval |= CDNS_UART_CR_RX_DIS;
560 writel(regval, port->membase + CDNS_UART_CR);
561}
562
563/**
564 * cdns_uart_tx_empty - Check whether TX is empty
565 * @port: Handle to the uart port structure
566 *
567 * Return: TIOCSER_TEMT on success, 0 otherwise
568 */
569static unsigned int cdns_uart_tx_empty(struct uart_port *port)
570{
571 unsigned int status;
572
573 status = readl(port->membase + CDNS_UART_SR) &
574 CDNS_UART_SR_TXEMPTY;
575 return status ? TIOCSER_TEMT : 0;
576}
577
578/**
579 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
580 * transmitting char breaks
581 * @port: Handle to the uart port structure
582 * @ctl: Value based on which start or stop decision is taken
583 */
584static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
585{
586 unsigned int status;
587 unsigned long flags;
588
589 spin_lock_irqsave(&port->lock, flags);
590
591 status = readl(port->membase + CDNS_UART_CR);
592
593 if (ctl == -1)
594 writel(CDNS_UART_CR_STARTBRK | status,
595 port->membase + CDNS_UART_CR);
596 else {
597 if ((status & CDNS_UART_CR_STOPBRK) == 0)
598 writel(CDNS_UART_CR_STOPBRK | status,
599 port->membase + CDNS_UART_CR);
600 }
601 spin_unlock_irqrestore(&port->lock, flags);
602}
603
604/**
605 * cdns_uart_set_termios - termios operations, handling data length, parity,
606 * stop bits, flow control, baud rate
607 * @port: Handle to the uart port structure
608 * @termios: Handle to the input termios structure
609 * @old: Values of the previously saved termios structure
610 */
611static void cdns_uart_set_termios(struct uart_port *port,
612 struct ktermios *termios, struct ktermios *old)
613{
614 unsigned int cval = 0;
615 unsigned int baud, minbaud, maxbaud;
616 unsigned long flags;
617 unsigned int ctrl_reg, mode_reg;
618
619 spin_lock_irqsave(&port->lock, flags);
620
621 /* Wait for the transmit FIFO to empty before making changes */
622 if (!(readl(port->membase + CDNS_UART_CR) &
623 CDNS_UART_CR_TX_DIS)) {
624 while (!(readl(port->membase + CDNS_UART_SR) &
625 CDNS_UART_SR_TXEMPTY)) {
626 cpu_relax();
627 }
628 }
629
630 /* Disable the TX and RX to set baud rate */
631 ctrl_reg = readl(port->membase + CDNS_UART_CR);
632 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
633 writel(ctrl_reg, port->membase + CDNS_UART_CR);
634
635 /*
636 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
637 * min and max baud should be calculated here based on port->uartclk.
638 * this way we get a valid baud and can safely call set_baud()
639 */
640 minbaud = port->uartclk /
641 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
642 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
643 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
644 baud = cdns_uart_set_baud_rate(port, baud);
645 if (tty_termios_baud_rate(termios))
646 tty_termios_encode_baud_rate(termios, baud, baud);
647
648 /* Update the per-port timeout. */
649 uart_update_timeout(port, termios->c_cflag, baud);
650
651 /* Set TX/RX Reset */
652 ctrl_reg = readl(port->membase + CDNS_UART_CR);
653 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
654 writel(ctrl_reg, port->membase + CDNS_UART_CR);
655
656 /*
657 * Clear the RX disable and TX disable bits and then set the TX enable
658 * bit and RX enable bit to enable the transmitter and receiver.
659 */
660 ctrl_reg = readl(port->membase + CDNS_UART_CR);
661 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
662 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
663 writel(ctrl_reg, port->membase + CDNS_UART_CR);
664
665 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
666
667 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
668 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
669 port->ignore_status_mask = 0;
670
671 if (termios->c_iflag & INPCK)
672 port->read_status_mask |= CDNS_UART_IXR_PARITY |
673 CDNS_UART_IXR_FRAMING;
674
675 if (termios->c_iflag & IGNPAR)
676 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
677 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
678
679 /* ignore all characters if CREAD is not set */
680 if ((termios->c_cflag & CREAD) == 0)
681 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
682 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
683 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
684
685 mode_reg = readl(port->membase + CDNS_UART_MR);
686
687 /* Handling Data Size */
688 switch (termios->c_cflag & CSIZE) {
689 case CS6:
690 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
691 break;
692 case CS7:
693 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
694 break;
695 default:
696 case CS8:
697 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
698 termios->c_cflag &= ~CSIZE;
699 termios->c_cflag |= CS8;
700 break;
701 }
702
703 /* Handling Parity and Stop Bits length */
704 if (termios->c_cflag & CSTOPB)
705 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
706 else
707 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
708
709 if (termios->c_cflag & PARENB) {
710 /* Mark or Space parity */
711 if (termios->c_cflag & CMSPAR) {
712 if (termios->c_cflag & PARODD)
713 cval |= CDNS_UART_MR_PARITY_MARK;
714 else
715 cval |= CDNS_UART_MR_PARITY_SPACE;
716 } else {
717 if (termios->c_cflag & PARODD)
718 cval |= CDNS_UART_MR_PARITY_ODD;
719 else
720 cval |= CDNS_UART_MR_PARITY_EVEN;
721 }
722 } else {
723 cval |= CDNS_UART_MR_PARITY_NONE;
724 }
725 cval |= mode_reg & 1;
726 writel(cval, port->membase + CDNS_UART_MR);
727
728 spin_unlock_irqrestore(&port->lock, flags);
729}
730
731/**
732 * cdns_uart_startup - Called when an application opens a cdns_uart port
733 * @port: Handle to the uart port structure
734 *
735 * Return: 0 on success, negative errno otherwise
736 */
737static int cdns_uart_startup(struct uart_port *port)
738{
739 int ret;
740 unsigned long flags;
741 unsigned int status = 0;
742
743 spin_lock_irqsave(&port->lock, flags);
744
745 /* Disable the TX and RX */
746 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
747 port->membase + CDNS_UART_CR);
748
749 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
750 * no break chars.
751 */
752 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
753 port->membase + CDNS_UART_CR);
754
755 /*
756 * Clear the RX disable bit and then set the RX enable bit to enable
757 * the receiver.
758 */
759 status = readl(port->membase + CDNS_UART_CR);
760 status &= CDNS_UART_CR_RX_DIS;
761 status |= CDNS_UART_CR_RX_EN;
762 writel(status, port->membase + CDNS_UART_CR);
763
764 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
765 * no parity.
766 */
767 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
768 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
769 port->membase + CDNS_UART_MR);
770
771 /*
772 * Set the RX FIFO Trigger level to use most of the FIFO, but it
773 * can be tuned with a module parameter
774 */
775 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
776
777 /*
778 * Receive Timeout register is enabled but it
779 * can be tuned with a module parameter
780 */
781 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
782
783 /* Clear out any pending interrupts before enabling them */
784 writel(readl(port->membase + CDNS_UART_ISR),
785 port->membase + CDNS_UART_ISR);
786
787 spin_unlock_irqrestore(&port->lock, flags);
788
789 ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);
790 if (ret) {
791 dev_err(port->dev, "request_irq '%d' failed with %d\n",
792 port->irq, ret);
793 return ret;
794 }
795
796 /* Set the Interrupt Registers with desired interrupts */
797 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
798
799 return 0;
800}
801
802/**
803 * cdns_uart_shutdown - Called when an application closes a cdns_uart port
804 * @port: Handle to the uart port structure
805 */
806static void cdns_uart_shutdown(struct uart_port *port)
807{
808 int status;
809 unsigned long flags;
810
811 spin_lock_irqsave(&port->lock, flags);
812
813 /* Disable interrupts */
814 status = readl(port->membase + CDNS_UART_IMR);
815 writel(status, port->membase + CDNS_UART_IDR);
816 writel(0xffffffff, port->membase + CDNS_UART_ISR);
817
818 /* Disable the TX and RX */
819 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
820 port->membase + CDNS_UART_CR);
821
822 spin_unlock_irqrestore(&port->lock, flags);
823
824 free_irq(port->irq, port);
825}
826
827/**
828 * cdns_uart_type - Set UART type to cdns_uart port
829 * @port: Handle to the uart port structure
830 *
831 * Return: string on success, NULL otherwise
832 */
833static const char *cdns_uart_type(struct uart_port *port)
834{
835 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
836}
837
838/**
839 * cdns_uart_verify_port - Verify the port params
840 * @port: Handle to the uart port structure
841 * @ser: Handle to the structure whose members are compared
842 *
843 * Return: 0 on success, negative errno otherwise.
844 */
845static int cdns_uart_verify_port(struct uart_port *port,
846 struct serial_struct *ser)
847{
848 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
849 return -EINVAL;
850 if (port->irq != ser->irq)
851 return -EINVAL;
852 if (ser->io_type != UPIO_MEM)
853 return -EINVAL;
854 if (port->iobase != ser->port)
855 return -EINVAL;
856 if (ser->hub6 != 0)
857 return -EINVAL;
858 return 0;
859}
860
861/**
862 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
863 * called when the driver adds a cdns_uart port via
864 * uart_add_one_port()
865 * @port: Handle to the uart port structure
866 *
867 * Return: 0 on success, negative errno otherwise.
868 */
869static int cdns_uart_request_port(struct uart_port *port)
870{
871 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
872 CDNS_UART_NAME)) {
873 return -ENOMEM;
874 }
875
876 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
877 if (!port->membase) {
878 dev_err(port->dev, "Unable to map registers\n");
879 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
880 return -ENOMEM;
881 }
882 return 0;
883}
884
885/**
886 * cdns_uart_release_port - Release UART port
887 * @port: Handle to the uart port structure
888 *
889 * Release the memory region attached to a cdns_uart port. Called when the
890 * driver removes a cdns_uart port via uart_remove_one_port().
891 */
892static void cdns_uart_release_port(struct uart_port *port)
893{
894 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
895 iounmap(port->membase);
896 port->membase = NULL;
897}
898
899/**
900 * cdns_uart_config_port - Configure UART port
901 * @port: Handle to the uart port structure
902 * @flags: If any
903 */
904static void cdns_uart_config_port(struct uart_port *port, int flags)
905{
906 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
907 port->type = PORT_XUARTPS;
908}
909
910/**
911 * cdns_uart_get_mctrl - Get the modem control state
912 * @port: Handle to the uart port structure
913 *
914 * Return: the modem control state
915 */
916static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
917{
918 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
919}
920
921static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
922{
923 u32 val;
924
925 val = readl(port->membase + CDNS_UART_MODEMCR);
926
927 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR);
928
929 if (mctrl & TIOCM_RTS)
930 val |= CDNS_UART_MODEMCR_RTS;
931 if (mctrl & TIOCM_DTR)
932 val |= CDNS_UART_MODEMCR_DTR;
933
934 writel(val, port->membase + CDNS_UART_MODEMCR);
935}
936
937#ifdef CONFIG_CONSOLE_POLL
938static int cdns_uart_poll_get_char(struct uart_port *port)
939{
940 int c;
941 unsigned long flags;
942
943 spin_lock_irqsave(&port->lock, flags);
944
945 /* Check if FIFO is empty */
946 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
947 c = NO_POLL_CHAR;
948 else /* Read a character */
949 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
950
951 spin_unlock_irqrestore(&port->lock, flags);
952
953 return c;
954}
955
956static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
957{
958 unsigned long flags;
959
960 spin_lock_irqsave(&port->lock, flags);
961
962 /* Wait until FIFO is empty */
963 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
964 cpu_relax();
965
966 /* Write a character */
967 writel(c, port->membase + CDNS_UART_FIFO);
968
969 /* Wait until FIFO is empty */
970 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
971 cpu_relax();
972
973 spin_unlock_irqrestore(&port->lock, flags);
974
975 return;
976}
977#endif
978
979static struct uart_ops cdns_uart_ops = {
980 .set_mctrl = cdns_uart_set_mctrl,
981 .get_mctrl = cdns_uart_get_mctrl,
982 .start_tx = cdns_uart_start_tx,
983 .stop_tx = cdns_uart_stop_tx,
984 .stop_rx = cdns_uart_stop_rx,
985 .tx_empty = cdns_uart_tx_empty,
986 .break_ctl = cdns_uart_break_ctl,
987 .set_termios = cdns_uart_set_termios,
988 .startup = cdns_uart_startup,
989 .shutdown = cdns_uart_shutdown,
990 .type = cdns_uart_type,
991 .verify_port = cdns_uart_verify_port,
992 .request_port = cdns_uart_request_port,
993 .release_port = cdns_uart_release_port,
994 .config_port = cdns_uart_config_port,
995#ifdef CONFIG_CONSOLE_POLL
996 .poll_get_char = cdns_uart_poll_get_char,
997 .poll_put_char = cdns_uart_poll_put_char,
998#endif
999};
1000
1001static struct uart_port cdns_uart_port[CDNS_UART_NR_PORTS];
1002
1003/**
1004 * cdns_uart_get_port - Configure the port from platform device resource info
1005 * @id: Port id
1006 *
1007 * Return: a pointer to a uart_port or NULL for failure
1008 */
1009static struct uart_port *cdns_uart_get_port(int id)
1010{
1011 struct uart_port *port;
1012
1013 /* Try the given port id if failed use default method */
1014 if (cdns_uart_port[id].mapbase != 0) {
1015 /* Find the next unused port */
1016 for (id = 0; id < CDNS_UART_NR_PORTS; id++)
1017 if (cdns_uart_port[id].mapbase == 0)
1018 break;
1019 }
1020
1021 if (id >= CDNS_UART_NR_PORTS)
1022 return NULL;
1023
1024 port = &cdns_uart_port[id];
1025
1026 /* At this point, we've got an empty uart_port struct, initialize it */
1027 spin_lock_init(&port->lock);
1028 port->membase = NULL;
1029 port->irq = 0;
1030 port->type = PORT_UNKNOWN;
1031 port->iotype = UPIO_MEM32;
1032 port->flags = UPF_BOOT_AUTOCONF;
1033 port->ops = &cdns_uart_ops;
1034 port->fifosize = CDNS_UART_FIFO_SIZE;
1035 port->line = id;
1036 port->dev = NULL;
1037 return port;
1038}
1039
1040#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1041/**
1042 * cdns_uart_console_wait_tx - Wait for the TX to be full
1043 * @port: Handle to the uart port structure
1044 */
1045static void cdns_uart_console_wait_tx(struct uart_port *port)
1046{
1047 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1048 barrier();
1049}
1050
1051/**
1052 * cdns_uart_console_putchar - write the character to the FIFO buffer
1053 * @port: Handle to the uart port structure
1054 * @ch: Character to be written
1055 */
1056static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1057{
1058 cdns_uart_console_wait_tx(port);
1059 writel(ch, port->membase + CDNS_UART_FIFO);
1060}
1061
1062static void __init cdns_early_write(struct console *con, const char *s,
1063 unsigned n)
1064{
1065 struct earlycon_device *dev = con->data;
1066
1067 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1068}
1069
1070static int __init cdns_early_console_setup(struct earlycon_device *device,
1071 const char *opt)
1072{
1073 if (!device->port.membase)
1074 return -ENODEV;
1075
1076 device->con->write = cdns_early_write;
1077
1078 return 0;
1079}
1080OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);
1081OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);
1082OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);
1083
1084/**
1085 * cdns_uart_console_write - perform write operation
1086 * @co: Console handle
1087 * @s: Pointer to character array
1088 * @count: No of characters
1089 */
1090static void cdns_uart_console_write(struct console *co, const char *s,
1091 unsigned int count)
1092{
1093 struct uart_port *port = &cdns_uart_port[co->index];
1094 unsigned long flags;
1095 unsigned int imr, ctrl;
1096 int locked = 1;
1097
1098 if (port->sysrq)
1099 locked = 0;
1100 else if (oops_in_progress)
1101 locked = spin_trylock_irqsave(&port->lock, flags);
1102 else
1103 spin_lock_irqsave(&port->lock, flags);
1104
1105 /* save and disable interrupt */
1106 imr = readl(port->membase + CDNS_UART_IMR);
1107 writel(imr, port->membase + CDNS_UART_IDR);
1108
1109 /*
1110 * Make sure that the tx part is enabled. Set the TX enable bit and
1111 * clear the TX disable bit to enable the transmitter.
1112 */
1113 ctrl = readl(port->membase + CDNS_UART_CR);
1114 ctrl &= ~CDNS_UART_CR_TX_DIS;
1115 ctrl |= CDNS_UART_CR_TX_EN;
1116 writel(ctrl, port->membase + CDNS_UART_CR);
1117
1118 uart_console_write(port, s, count, cdns_uart_console_putchar);
1119 cdns_uart_console_wait_tx(port);
1120
1121 writel(ctrl, port->membase + CDNS_UART_CR);
1122
1123 /* restore interrupt state */
1124 writel(imr, port->membase + CDNS_UART_IER);
1125
1126 if (locked)
1127 spin_unlock_irqrestore(&port->lock, flags);
1128}
1129
1130/**
1131 * cdns_uart_console_setup - Initialize the uart to default config
1132 * @co: Console handle
1133 * @options: Initial settings of uart
1134 *
1135 * Return: 0 on success, negative errno otherwise.
1136 */
1137static int __init cdns_uart_console_setup(struct console *co, char *options)
1138{
1139 struct uart_port *port = &cdns_uart_port[co->index];
1140 int baud = 9600;
1141 int bits = 8;
1142 int parity = 'n';
1143 int flow = 'n';
1144
1145 if (co->index < 0 || co->index >= CDNS_UART_NR_PORTS)
1146 return -EINVAL;
1147
1148 if (!port->membase) {
1149 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1150 co->index);
1151 return -ENODEV;
1152 }
1153
1154 if (options)
1155 uart_parse_options(options, &baud, &parity, &bits, &flow);
1156
1157 return uart_set_options(port, co, baud, parity, bits, flow);
1158}
1159
1160static struct uart_driver cdns_uart_uart_driver;
1161
1162static struct console cdns_uart_console = {
1163 .name = CDNS_UART_TTY_NAME,
1164 .write = cdns_uart_console_write,
1165 .device = uart_console_device,
1166 .setup = cdns_uart_console_setup,
1167 .flags = CON_PRINTBUFFER,
1168 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1169 .data = &cdns_uart_uart_driver,
1170};
1171
1172/**
1173 * cdns_uart_console_init - Initialization call
1174 *
1175 * Return: 0 on success, negative errno otherwise
1176 */
1177static int __init cdns_uart_console_init(void)
1178{
1179 register_console(&cdns_uart_console);
1180 return 0;
1181}
1182
1183console_initcall(cdns_uart_console_init);
1184
1185#endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1186
1187static struct uart_driver cdns_uart_uart_driver = {
1188 .owner = THIS_MODULE,
1189 .driver_name = CDNS_UART_NAME,
1190 .dev_name = CDNS_UART_TTY_NAME,
1191 .major = CDNS_UART_MAJOR,
1192 .minor = CDNS_UART_MINOR,
1193 .nr = CDNS_UART_NR_PORTS,
1194#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1195 .cons = &cdns_uart_console,
1196#endif
1197};
1198
1199#ifdef CONFIG_PM_SLEEP
1200/**
1201 * cdns_uart_suspend - suspend event
1202 * @device: Pointer to the device structure
1203 *
1204 * Return: 0
1205 */
1206static int cdns_uart_suspend(struct device *device)
1207{
1208 struct uart_port *port = dev_get_drvdata(device);
1209 struct tty_struct *tty;
1210 struct device *tty_dev;
1211 int may_wake = 0;
1212
1213 /* Get the tty which could be NULL so don't assume it's valid */
1214 tty = tty_port_tty_get(&port->state->port);
1215 if (tty) {
1216 tty_dev = tty->dev;
1217 may_wake = device_may_wakeup(tty_dev);
1218 tty_kref_put(tty);
1219 }
1220
1221 /*
1222 * Call the API provided in serial_core.c file which handles
1223 * the suspend.
1224 */
1225 uart_suspend_port(&cdns_uart_uart_driver, port);
1226 if (console_suspend_enabled && !may_wake) {
1227 struct cdns_uart *cdns_uart = port->private_data;
1228
1229 clk_disable(cdns_uart->uartclk);
1230 clk_disable(cdns_uart->pclk);
1231 } else {
1232 unsigned long flags = 0;
1233
1234 spin_lock_irqsave(&port->lock, flags);
1235 /* Empty the receive FIFO 1st before making changes */
1236 while (!(readl(port->membase + CDNS_UART_SR) &
1237 CDNS_UART_SR_RXEMPTY))
1238 readl(port->membase + CDNS_UART_FIFO);
1239 /* set RX trigger level to 1 */
1240 writel(1, port->membase + CDNS_UART_RXWM);
1241 /* disable RX timeout interrups */
1242 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1243 spin_unlock_irqrestore(&port->lock, flags);
1244 }
1245
1246 return 0;
1247}
1248
1249/**
1250 * cdns_uart_resume - Resume after a previous suspend
1251 * @device: Pointer to the device structure
1252 *
1253 * Return: 0
1254 */
1255static int cdns_uart_resume(struct device *device)
1256{
1257 struct uart_port *port = dev_get_drvdata(device);
1258 unsigned long flags = 0;
1259 u32 ctrl_reg;
1260 struct tty_struct *tty;
1261 struct device *tty_dev;
1262 int may_wake = 0;
1263
1264 /* Get the tty which could be NULL so don't assume it's valid */
1265 tty = tty_port_tty_get(&port->state->port);
1266 if (tty) {
1267 tty_dev = tty->dev;
1268 may_wake = device_may_wakeup(tty_dev);
1269 tty_kref_put(tty);
1270 }
1271
1272 if (console_suspend_enabled && !may_wake) {
1273 struct cdns_uart *cdns_uart = port->private_data;
1274
1275 clk_enable(cdns_uart->pclk);
1276 clk_enable(cdns_uart->uartclk);
1277
1278 spin_lock_irqsave(&port->lock, flags);
1279
1280 /* Set TX/RX Reset */
1281 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1282 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1283 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1284 while (readl(port->membase + CDNS_UART_CR) &
1285 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1286 cpu_relax();
1287
1288 /* restore rx timeout value */
1289 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1290 /* Enable Tx/Rx */
1291 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1292 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1293 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1294 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1295
1296 spin_unlock_irqrestore(&port->lock, flags);
1297 } else {
1298 spin_lock_irqsave(&port->lock, flags);
1299 /* restore original rx trigger level */
1300 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1301 /* enable RX timeout interrupt */
1302 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
1303 spin_unlock_irqrestore(&port->lock, flags);
1304 }
1305
1306 return uart_resume_port(&cdns_uart_uart_driver, port);
1307}
1308#endif /* ! CONFIG_PM_SLEEP */
1309
1310static SIMPLE_DEV_PM_OPS(cdns_uart_dev_pm_ops, cdns_uart_suspend,
1311 cdns_uart_resume);
1312
1313/**
1314 * cdns_uart_probe - Platform driver probe
1315 * @pdev: Pointer to the platform device structure
1316 *
1317 * Return: 0 on success, negative errno otherwise
1318 */
1319static int cdns_uart_probe(struct platform_device *pdev)
1320{
1321 int rc, id, irq;
1322 struct uart_port *port;
1323 struct resource *res;
1324 struct cdns_uart *cdns_uart_data;
1325
1326 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1327 GFP_KERNEL);
1328 if (!cdns_uart_data)
1329 return -ENOMEM;
1330
1331 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1332 if (IS_ERR(cdns_uart_data->pclk)) {
1333 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1334 if (!IS_ERR(cdns_uart_data->pclk))
1335 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1336 }
1337 if (IS_ERR(cdns_uart_data->pclk)) {
1338 dev_err(&pdev->dev, "pclk clock not found.\n");
1339 return PTR_ERR(cdns_uart_data->pclk);
1340 }
1341
1342 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1343 if (IS_ERR(cdns_uart_data->uartclk)) {
1344 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1345 if (!IS_ERR(cdns_uart_data->uartclk))
1346 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1347 }
1348 if (IS_ERR(cdns_uart_data->uartclk)) {
1349 dev_err(&pdev->dev, "uart_clk clock not found.\n");
1350 return PTR_ERR(cdns_uart_data->uartclk);
1351 }
1352
1353 rc = clk_prepare_enable(cdns_uart_data->pclk);
1354 if (rc) {
1355 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1356 return rc;
1357 }
1358 rc = clk_prepare_enable(cdns_uart_data->uartclk);
1359 if (rc) {
1360 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1361 goto err_out_clk_dis_pclk;
1362 }
1363
1364 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1365 if (!res) {
1366 rc = -ENODEV;
1367 goto err_out_clk_disable;
1368 }
1369
1370 irq = platform_get_irq(pdev, 0);
1371 if (irq <= 0) {
1372 rc = -ENXIO;
1373 goto err_out_clk_disable;
1374 }
1375
1376#ifdef CONFIG_COMMON_CLK
1377 cdns_uart_data->clk_rate_change_nb.notifier_call =
1378 cdns_uart_clk_notifier_cb;
1379 if (clk_notifier_register(cdns_uart_data->uartclk,
1380 &cdns_uart_data->clk_rate_change_nb))
1381 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1382#endif
1383 /* Look for a serialN alias */
1384 id = of_alias_get_id(pdev->dev.of_node, "serial");
1385 if (id < 0)
1386 id = 0;
1387
1388 /* Initialize the port structure */
1389 port = cdns_uart_get_port(id);
1390
1391 if (!port) {
1392 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1393 rc = -ENODEV;
1394 goto err_out_notif_unreg;
1395 }
1396
1397 /*
1398 * Register the port.
1399 * This function also registers this device with the tty layer
1400 * and triggers invocation of the config_port() entry point.
1401 */
1402 port->mapbase = res->start;
1403 port->irq = irq;
1404 port->dev = &pdev->dev;
1405 port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1406 port->private_data = cdns_uart_data;
1407 cdns_uart_data->port = port;
1408 platform_set_drvdata(pdev, port);
1409
1410 rc = uart_add_one_port(&cdns_uart_uart_driver, port);
1411 if (rc) {
1412 dev_err(&pdev->dev,
1413 "uart_add_one_port() failed; err=%i\n", rc);
1414 goto err_out_notif_unreg;
1415 }
1416
1417 return 0;
1418
1419err_out_notif_unreg:
1420#ifdef CONFIG_COMMON_CLK
1421 clk_notifier_unregister(cdns_uart_data->uartclk,
1422 &cdns_uart_data->clk_rate_change_nb);
1423#endif
1424err_out_clk_disable:
1425 clk_disable_unprepare(cdns_uart_data->uartclk);
1426err_out_clk_dis_pclk:
1427 clk_disable_unprepare(cdns_uart_data->pclk);
1428
1429 return rc;
1430}
1431
1432/**
1433 * cdns_uart_remove - called when the platform driver is unregistered
1434 * @pdev: Pointer to the platform device structure
1435 *
1436 * Return: 0 on success, negative errno otherwise
1437 */
1438static int cdns_uart_remove(struct platform_device *pdev)
1439{
1440 struct uart_port *port = platform_get_drvdata(pdev);
1441 struct cdns_uart *cdns_uart_data = port->private_data;
1442 int rc;
1443
1444 /* Remove the cdns_uart port from the serial core */
1445#ifdef CONFIG_COMMON_CLK
1446 clk_notifier_unregister(cdns_uart_data->uartclk,
1447 &cdns_uart_data->clk_rate_change_nb);
1448#endif
1449 rc = uart_remove_one_port(&cdns_uart_uart_driver, port);
1450 port->mapbase = 0;
1451 clk_disable_unprepare(cdns_uart_data->uartclk);
1452 clk_disable_unprepare(cdns_uart_data->pclk);
1453 return rc;
1454}
1455
1456/* Match table for of_platform binding */
1457static const struct of_device_id cdns_uart_of_match[] = {
1458 { .compatible = "xlnx,xuartps", },
1459 { .compatible = "cdns,uart-r1p8", },
1460 {}
1461};
1462MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1463
1464static struct platform_driver cdns_uart_platform_driver = {
1465 .probe = cdns_uart_probe,
1466 .remove = cdns_uart_remove,
1467 .driver = {
1468 .name = CDNS_UART_NAME,
1469 .of_match_table = cdns_uart_of_match,
1470 .pm = &cdns_uart_dev_pm_ops,
1471 },
1472};
1473
1474static int __init cdns_uart_init(void)
1475{
1476 int retval = 0;
1477
1478 /* Register the cdns_uart driver with the serial core */
1479 retval = uart_register_driver(&cdns_uart_uart_driver);
1480 if (retval)
1481 return retval;
1482
1483 /* Register the platform driver */
1484 retval = platform_driver_register(&cdns_uart_platform_driver);
1485 if (retval)
1486 uart_unregister_driver(&cdns_uart_uart_driver);
1487
1488 return retval;
1489}
1490
1491static void __exit cdns_uart_exit(void)
1492{
1493 /* Unregister the platform driver */
1494 platform_driver_unregister(&cdns_uart_platform_driver);
1495
1496 /* Unregister the cdns_uart driver */
1497 uart_unregister_driver(&cdns_uart_uart_driver);
1498}
1499
1500module_init(cdns_uart_init);
1501module_exit(cdns_uart_exit);
1502
1503MODULE_DESCRIPTION("Driver for Cadence UART");
1504MODULE_AUTHOR("Xilinx Inc.");
1505MODULE_LICENSE("GPL");