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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * drivers/net/phy/lxt.c
4 *
5 * Driver for Intel LXT PHYs
6 *
7 * Author: Andy Fleming
8 *
9 * Copyright (c) 2004 Freescale Semiconductor, Inc.
10 */
11#include <linux/kernel.h>
12#include <linux/string.h>
13#include <linux/errno.h>
14#include <linux/unistd.h>
15#include <linux/interrupt.h>
16#include <linux/init.h>
17#include <linux/delay.h>
18#include <linux/netdevice.h>
19#include <linux/etherdevice.h>
20#include <linux/skbuff.h>
21#include <linux/spinlock.h>
22#include <linux/mm.h>
23#include <linux/module.h>
24#include <linux/mii.h>
25#include <linux/ethtool.h>
26#include <linux/phy.h>
27
28#include <asm/io.h>
29#include <asm/irq.h>
30#include <linux/uaccess.h>
31
32/* The Level one LXT970 is used by many boards */
33
34#define MII_LXT970_IER 17 /* Interrupt Enable Register */
35
36#define MII_LXT970_IER_IEN 0x0002
37
38#define MII_LXT970_ISR 18 /* Interrupt Status Register */
39
40#define MII_LXT970_CONFIG 19 /* Configuration Register */
41
42/* ------------------------------------------------------------------------- */
43/* The Level one LXT971 is used on some of my custom boards */
44
45/* register definitions for the 971 */
46#define MII_LXT971_IER 18 /* Interrupt Enable Register */
47#define MII_LXT971_IER_IEN 0x00f2
48
49#define MII_LXT971_ISR 19 /* Interrupt Status Register */
50
51/* register definitions for the 973 */
52#define MII_LXT973_PCR 16 /* Port Configuration Register */
53#define PCR_FIBER_SELECT 1
54
55MODULE_DESCRIPTION("Intel LXT PHY driver");
56MODULE_AUTHOR("Andy Fleming");
57MODULE_LICENSE("GPL");
58
59static int lxt970_ack_interrupt(struct phy_device *phydev)
60{
61 int err;
62
63 err = phy_read(phydev, MII_BMSR);
64
65 if (err < 0)
66 return err;
67
68 err = phy_read(phydev, MII_LXT970_ISR);
69
70 if (err < 0)
71 return err;
72
73 return 0;
74}
75
76static int lxt970_config_intr(struct phy_device *phydev)
77{
78 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
79 return phy_write(phydev, MII_LXT970_IER, MII_LXT970_IER_IEN);
80 else
81 return phy_write(phydev, MII_LXT970_IER, 0);
82}
83
84static int lxt970_config_init(struct phy_device *phydev)
85{
86 return phy_write(phydev, MII_LXT970_CONFIG, 0);
87}
88
89
90static int lxt971_ack_interrupt(struct phy_device *phydev)
91{
92 int err = phy_read(phydev, MII_LXT971_ISR);
93
94 if (err < 0)
95 return err;
96
97 return 0;
98}
99
100static int lxt971_config_intr(struct phy_device *phydev)
101{
102 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
103 return phy_write(phydev, MII_LXT971_IER, MII_LXT971_IER_IEN);
104 else
105 return phy_write(phydev, MII_LXT971_IER, 0);
106}
107
108/*
109 * A2 version of LXT973 chip has an ERRATA: it randomly return the contents
110 * of the previous even register when you read a odd register regularly
111 */
112
113static int lxt973a2_update_link(struct phy_device *phydev)
114{
115 int status;
116 int control;
117 int retry = 8; /* we try 8 times */
118
119 /* Do a fake read */
120 status = phy_read(phydev, MII_BMSR);
121
122 if (status < 0)
123 return status;
124
125 control = phy_read(phydev, MII_BMCR);
126 if (control < 0)
127 return control;
128
129 do {
130 /* Read link and autonegotiation status */
131 status = phy_read(phydev, MII_BMSR);
132 } while (status >= 0 && retry-- && status == control);
133
134 if (status < 0)
135 return status;
136
137 if ((status & BMSR_LSTATUS) == 0)
138 phydev->link = 0;
139 else
140 phydev->link = 1;
141
142 return 0;
143}
144
145static int lxt973a2_read_status(struct phy_device *phydev)
146{
147 int adv;
148 int err;
149 int lpa;
150
151 /* Update the link, but return if there was an error */
152 err = lxt973a2_update_link(phydev);
153 if (err)
154 return err;
155
156 if (AUTONEG_ENABLE == phydev->autoneg) {
157 int retry = 1;
158
159 adv = phy_read(phydev, MII_ADVERTISE);
160
161 if (adv < 0)
162 return adv;
163
164 do {
165 lpa = phy_read(phydev, MII_LPA);
166
167 if (lpa < 0)
168 return lpa;
169
170 /* If both registers are equal, it is suspect but not
171 * impossible, hence a new try
172 */
173 } while (lpa == adv && retry--);
174
175 mii_lpa_to_linkmode_lpa_t(phydev->lp_advertising, lpa);
176
177 lpa &= adv;
178
179 phydev->speed = SPEED_10;
180 phydev->duplex = DUPLEX_HALF;
181 phydev->pause = phydev->asym_pause = 0;
182
183 if (lpa & (LPA_100FULL | LPA_100HALF)) {
184 phydev->speed = SPEED_100;
185
186 if (lpa & LPA_100FULL)
187 phydev->duplex = DUPLEX_FULL;
188 } else {
189 if (lpa & LPA_10FULL)
190 phydev->duplex = DUPLEX_FULL;
191 }
192
193 if (phydev->duplex == DUPLEX_FULL) {
194 phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
195 phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
196 }
197 } else {
198 int bmcr = phy_read(phydev, MII_BMCR);
199
200 if (bmcr < 0)
201 return bmcr;
202
203 if (bmcr & BMCR_FULLDPLX)
204 phydev->duplex = DUPLEX_FULL;
205 else
206 phydev->duplex = DUPLEX_HALF;
207
208 if (bmcr & BMCR_SPEED1000)
209 phydev->speed = SPEED_1000;
210 else if (bmcr & BMCR_SPEED100)
211 phydev->speed = SPEED_100;
212 else
213 phydev->speed = SPEED_10;
214
215 phydev->pause = phydev->asym_pause = 0;
216 linkmode_zero(phydev->lp_advertising);
217 }
218
219 return 0;
220}
221
222static int lxt973_probe(struct phy_device *phydev)
223{
224 int val = phy_read(phydev, MII_LXT973_PCR);
225
226 if (val & PCR_FIBER_SELECT) {
227 /*
228 * If fiber is selected, then the only correct setting
229 * is 100Mbps, full duplex, and auto negotiation off.
230 */
231 val = phy_read(phydev, MII_BMCR);
232 val |= (BMCR_SPEED100 | BMCR_FULLDPLX);
233 val &= ~BMCR_ANENABLE;
234 phy_write(phydev, MII_BMCR, val);
235 /* Remember that the port is in fiber mode. */
236 phydev->priv = lxt973_probe;
237 } else {
238 phydev->priv = NULL;
239 }
240 return 0;
241}
242
243static int lxt973_config_aneg(struct phy_device *phydev)
244{
245 /* Do nothing if port is in fiber mode. */
246 return phydev->priv ? 0 : genphy_config_aneg(phydev);
247}
248
249static struct phy_driver lxt97x_driver[] = {
250{
251 .phy_id = 0x78100000,
252 .name = "LXT970",
253 .phy_id_mask = 0xfffffff0,
254 /* PHY_BASIC_FEATURES */
255 .config_init = lxt970_config_init,
256 .ack_interrupt = lxt970_ack_interrupt,
257 .config_intr = lxt970_config_intr,
258}, {
259 .phy_id = 0x001378e0,
260 .name = "LXT971",
261 .phy_id_mask = 0xfffffff0,
262 /* PHY_BASIC_FEATURES */
263 .ack_interrupt = lxt971_ack_interrupt,
264 .config_intr = lxt971_config_intr,
265 .suspend = genphy_suspend,
266 .resume = genphy_resume,
267}, {
268 .phy_id = 0x00137a10,
269 .name = "LXT973-A2",
270 .phy_id_mask = 0xffffffff,
271 /* PHY_BASIC_FEATURES */
272 .flags = 0,
273 .probe = lxt973_probe,
274 .config_aneg = lxt973_config_aneg,
275 .read_status = lxt973a2_read_status,
276 .suspend = genphy_suspend,
277 .resume = genphy_resume,
278}, {
279 .phy_id = 0x00137a10,
280 .name = "LXT973",
281 .phy_id_mask = 0xfffffff0,
282 /* PHY_BASIC_FEATURES */
283 .flags = 0,
284 .probe = lxt973_probe,
285 .config_aneg = lxt973_config_aneg,
286 .suspend = genphy_suspend,
287 .resume = genphy_resume,
288} };
289
290module_phy_driver(lxt97x_driver);
291
292static struct mdio_device_id __maybe_unused lxt_tbl[] = {
293 { 0x78100000, 0xfffffff0 },
294 { 0x001378e0, 0xfffffff0 },
295 { 0x00137a10, 0xfffffff0 },
296 { }
297};
298
299MODULE_DEVICE_TABLE(mdio, lxt_tbl);
1/*
2 * drivers/net/phy/lxt.c
3 *
4 * Driver for Intel LXT PHYs
5 *
6 * Author: Andy Fleming
7 *
8 * Copyright (c) 2004 Freescale Semiconductor, Inc.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 *
15 */
16#include <linux/kernel.h>
17#include <linux/string.h>
18#include <linux/errno.h>
19#include <linux/unistd.h>
20#include <linux/interrupt.h>
21#include <linux/init.h>
22#include <linux/delay.h>
23#include <linux/netdevice.h>
24#include <linux/etherdevice.h>
25#include <linux/skbuff.h>
26#include <linux/spinlock.h>
27#include <linux/mm.h>
28#include <linux/module.h>
29#include <linux/mii.h>
30#include <linux/ethtool.h>
31#include <linux/phy.h>
32
33#include <asm/io.h>
34#include <asm/irq.h>
35#include <asm/uaccess.h>
36
37/* The Level one LXT970 is used by many boards */
38
39#define MII_LXT970_IER 17 /* Interrupt Enable Register */
40
41#define MII_LXT970_IER_IEN 0x0002
42
43#define MII_LXT970_ISR 18 /* Interrupt Status Register */
44
45#define MII_LXT970_CONFIG 19 /* Configuration Register */
46
47/* ------------------------------------------------------------------------- */
48/* The Level one LXT971 is used on some of my custom boards */
49
50/* register definitions for the 971 */
51#define MII_LXT971_IER 18 /* Interrupt Enable Register */
52#define MII_LXT971_IER_IEN 0x00f2
53
54#define MII_LXT971_ISR 19 /* Interrupt Status Register */
55
56/* register definitions for the 973 */
57#define MII_LXT973_PCR 16 /* Port Configuration Register */
58#define PCR_FIBER_SELECT 1
59
60MODULE_DESCRIPTION("Intel LXT PHY driver");
61MODULE_AUTHOR("Andy Fleming");
62MODULE_LICENSE("GPL");
63
64static int lxt970_ack_interrupt(struct phy_device *phydev)
65{
66 int err;
67
68 err = phy_read(phydev, MII_BMSR);
69
70 if (err < 0)
71 return err;
72
73 err = phy_read(phydev, MII_LXT970_ISR);
74
75 if (err < 0)
76 return err;
77
78 return 0;
79}
80
81static int lxt970_config_intr(struct phy_device *phydev)
82{
83 int err;
84
85 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
86 err = phy_write(phydev, MII_LXT970_IER, MII_LXT970_IER_IEN);
87 else
88 err = phy_write(phydev, MII_LXT970_IER, 0);
89
90 return err;
91}
92
93static int lxt970_config_init(struct phy_device *phydev)
94{
95 int err;
96
97 err = phy_write(phydev, MII_LXT970_CONFIG, 0);
98
99 return err;
100}
101
102
103static int lxt971_ack_interrupt(struct phy_device *phydev)
104{
105 int err = phy_read(phydev, MII_LXT971_ISR);
106
107 if (err < 0)
108 return err;
109
110 return 0;
111}
112
113static int lxt971_config_intr(struct phy_device *phydev)
114{
115 int err;
116
117 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
118 err = phy_write(phydev, MII_LXT971_IER, MII_LXT971_IER_IEN);
119 else
120 err = phy_write(phydev, MII_LXT971_IER, 0);
121
122 return err;
123}
124
125/*
126 * A2 version of LXT973 chip has an ERRATA: it randomly return the contents
127 * of the previous even register when you read a odd register regularly
128 */
129
130static int lxt973a2_update_link(struct phy_device *phydev)
131{
132 int status;
133 int control;
134 int retry = 8; /* we try 8 times */
135
136 /* Do a fake read */
137 status = phy_read(phydev, MII_BMSR);
138
139 if (status < 0)
140 return status;
141
142 control = phy_read(phydev, MII_BMCR);
143 if (control < 0)
144 return control;
145
146 do {
147 /* Read link and autonegotiation status */
148 status = phy_read(phydev, MII_BMSR);
149 } while (status >= 0 && retry-- && status == control);
150
151 if (status < 0)
152 return status;
153
154 if ((status & BMSR_LSTATUS) == 0)
155 phydev->link = 0;
156 else
157 phydev->link = 1;
158
159 return 0;
160}
161
162static int lxt973a2_read_status(struct phy_device *phydev)
163{
164 int adv;
165 int err;
166 int lpa;
167 int lpagb = 0;
168
169 /* Update the link, but return if there was an error */
170 err = lxt973a2_update_link(phydev);
171 if (err)
172 return err;
173
174 if (AUTONEG_ENABLE == phydev->autoneg) {
175 int retry = 1;
176
177 adv = phy_read(phydev, MII_ADVERTISE);
178
179 if (adv < 0)
180 return adv;
181
182 do {
183 lpa = phy_read(phydev, MII_LPA);
184
185 if (lpa < 0)
186 return lpa;
187
188 /* If both registers are equal, it is suspect but not
189 * impossible, hence a new try
190 */
191 } while (lpa == adv && retry--);
192
193 lpa &= adv;
194
195 phydev->speed = SPEED_10;
196 phydev->duplex = DUPLEX_HALF;
197 phydev->pause = phydev->asym_pause = 0;
198
199 if (lpagb & (LPA_1000FULL | LPA_1000HALF)) {
200 phydev->speed = SPEED_1000;
201
202 if (lpagb & LPA_1000FULL)
203 phydev->duplex = DUPLEX_FULL;
204 } else if (lpa & (LPA_100FULL | LPA_100HALF)) {
205 phydev->speed = SPEED_100;
206
207 if (lpa & LPA_100FULL)
208 phydev->duplex = DUPLEX_FULL;
209 } else {
210 if (lpa & LPA_10FULL)
211 phydev->duplex = DUPLEX_FULL;
212 }
213
214 if (phydev->duplex == DUPLEX_FULL) {
215 phydev->pause = lpa & LPA_PAUSE_CAP ? 1 : 0;
216 phydev->asym_pause = lpa & LPA_PAUSE_ASYM ? 1 : 0;
217 }
218 } else {
219 int bmcr = phy_read(phydev, MII_BMCR);
220
221 if (bmcr < 0)
222 return bmcr;
223
224 if (bmcr & BMCR_FULLDPLX)
225 phydev->duplex = DUPLEX_FULL;
226 else
227 phydev->duplex = DUPLEX_HALF;
228
229 if (bmcr & BMCR_SPEED1000)
230 phydev->speed = SPEED_1000;
231 else if (bmcr & BMCR_SPEED100)
232 phydev->speed = SPEED_100;
233 else
234 phydev->speed = SPEED_10;
235
236 phydev->pause = phydev->asym_pause = 0;
237 }
238
239 return 0;
240}
241
242static int lxt973_probe(struct phy_device *phydev)
243{
244 int val = phy_read(phydev, MII_LXT973_PCR);
245
246 if (val & PCR_FIBER_SELECT) {
247 /*
248 * If fiber is selected, then the only correct setting
249 * is 100Mbps, full duplex, and auto negotiation off.
250 */
251 val = phy_read(phydev, MII_BMCR);
252 val |= (BMCR_SPEED100 | BMCR_FULLDPLX);
253 val &= ~BMCR_ANENABLE;
254 phy_write(phydev, MII_BMCR, val);
255 /* Remember that the port is in fiber mode. */
256 phydev->priv = lxt973_probe;
257 } else {
258 phydev->priv = NULL;
259 }
260 return 0;
261}
262
263static int lxt973_config_aneg(struct phy_device *phydev)
264{
265 /* Do nothing if port is in fiber mode. */
266 return phydev->priv ? 0 : genphy_config_aneg(phydev);
267}
268
269static struct phy_driver lxt97x_driver[] = {
270{
271 .phy_id = 0x78100000,
272 .name = "LXT970",
273 .phy_id_mask = 0xfffffff0,
274 .features = PHY_BASIC_FEATURES,
275 .flags = PHY_HAS_INTERRUPT,
276 .config_init = lxt970_config_init,
277 .config_aneg = genphy_config_aneg,
278 .read_status = genphy_read_status,
279 .ack_interrupt = lxt970_ack_interrupt,
280 .config_intr = lxt970_config_intr,
281}, {
282 .phy_id = 0x001378e0,
283 .name = "LXT971",
284 .phy_id_mask = 0xfffffff0,
285 .features = PHY_BASIC_FEATURES,
286 .flags = PHY_HAS_INTERRUPT,
287 .config_aneg = genphy_config_aneg,
288 .read_status = genphy_read_status,
289 .ack_interrupt = lxt971_ack_interrupt,
290 .config_intr = lxt971_config_intr,
291}, {
292 .phy_id = 0x00137a10,
293 .name = "LXT973-A2",
294 .phy_id_mask = 0xffffffff,
295 .features = PHY_BASIC_FEATURES,
296 .flags = 0,
297 .probe = lxt973_probe,
298 .config_aneg = lxt973_config_aneg,
299 .read_status = lxt973a2_read_status,
300}, {
301 .phy_id = 0x00137a10,
302 .name = "LXT973",
303 .phy_id_mask = 0xfffffff0,
304 .features = PHY_BASIC_FEATURES,
305 .flags = 0,
306 .probe = lxt973_probe,
307 .config_aneg = lxt973_config_aneg,
308 .read_status = genphy_read_status,
309} };
310
311module_phy_driver(lxt97x_driver);
312
313static struct mdio_device_id __maybe_unused lxt_tbl[] = {
314 { 0x78100000, 0xfffffff0 },
315 { 0x001378e0, 0xfffffff0 },
316 { 0x00137a10, 0xfffffff0 },
317 { }
318};
319
320MODULE_DEVICE_TABLE(mdio, lxt_tbl);