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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Broadcom Starfighter 2 DSA switch driver
4 *
5 * Copyright (C) 2014, Broadcom Corporation
6 */
7
8#include <linux/list.h>
9#include <linux/module.h>
10#include <linux/netdevice.h>
11#include <linux/interrupt.h>
12#include <linux/platform_device.h>
13#include <linux/phy.h>
14#include <linux/phy_fixed.h>
15#include <linux/phylink.h>
16#include <linux/mii.h>
17#include <linux/of.h>
18#include <linux/of_irq.h>
19#include <linux/of_address.h>
20#include <linux/of_net.h>
21#include <linux/of_mdio.h>
22#include <net/dsa.h>
23#include <linux/ethtool.h>
24#include <linux/if_bridge.h>
25#include <linux/brcmphy.h>
26#include <linux/etherdevice.h>
27#include <linux/platform_data/b53.h>
28
29#include "bcm_sf2.h"
30#include "bcm_sf2_regs.h"
31#include "b53/b53_priv.h"
32#include "b53/b53_regs.h"
33
34static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
35{
36 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
37 unsigned int i;
38 u32 reg, offset;
39
40 /* Enable the port memories */
41 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
42 reg &= ~P_TXQ_PSM_VDD(port);
43 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
44
45 /* Enable forwarding */
46 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
47
48 /* Enable IMP port in dumb mode */
49 reg = core_readl(priv, CORE_SWITCH_CTRL);
50 reg |= MII_DUMB_FWDG_EN;
51 core_writel(priv, reg, CORE_SWITCH_CTRL);
52
53 /* Configure Traffic Class to QoS mapping, allow each priority to map
54 * to a different queue number
55 */
56 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
57 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
58 reg |= i << (PRT_TO_QID_SHIFT * i);
59 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
60
61 b53_brcm_hdr_setup(ds, port);
62
63 if (port == 8) {
64 if (priv->type == BCM7445_DEVICE_ID)
65 offset = CORE_STS_OVERRIDE_IMP;
66 else
67 offset = CORE_STS_OVERRIDE_IMP2;
68
69 /* Force link status for IMP port */
70 reg = core_readl(priv, offset);
71 reg |= (MII_SW_OR | LINK_STS);
72 core_writel(priv, reg, offset);
73
74 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
75 reg = core_readl(priv, CORE_IMP_CTL);
76 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
77 reg &= ~(RX_DIS | TX_DIS);
78 core_writel(priv, reg, CORE_IMP_CTL);
79 } else {
80 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
81 reg &= ~(RX_DIS | TX_DIS);
82 core_writel(priv, reg, CORE_G_PCTL_PORT(port));
83 }
84}
85
86static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
87{
88 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
89 u32 reg;
90
91 reg = reg_readl(priv, REG_SPHY_CNTRL);
92 if (enable) {
93 reg |= PHY_RESET;
94 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS);
95 reg_writel(priv, reg, REG_SPHY_CNTRL);
96 udelay(21);
97 reg = reg_readl(priv, REG_SPHY_CNTRL);
98 reg &= ~PHY_RESET;
99 } else {
100 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
101 reg_writel(priv, reg, REG_SPHY_CNTRL);
102 mdelay(1);
103 reg |= CK25_DIS;
104 }
105 reg_writel(priv, reg, REG_SPHY_CNTRL);
106
107 /* Use PHY-driven LED signaling */
108 if (!enable) {
109 reg = reg_readl(priv, REG_LED_CNTRL(0));
110 reg |= SPDLNK_SRC_SEL;
111 reg_writel(priv, reg, REG_LED_CNTRL(0));
112 }
113}
114
115static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
116 int port)
117{
118 unsigned int off;
119
120 switch (port) {
121 case 7:
122 off = P7_IRQ_OFF;
123 break;
124 case 0:
125 /* Port 0 interrupts are located on the first bank */
126 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
127 return;
128 default:
129 off = P_IRQ_OFF(port);
130 break;
131 }
132
133 intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
134}
135
136static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
137 int port)
138{
139 unsigned int off;
140
141 switch (port) {
142 case 7:
143 off = P7_IRQ_OFF;
144 break;
145 case 0:
146 /* Port 0 interrupts are located on the first bank */
147 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
148 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
149 return;
150 default:
151 off = P_IRQ_OFF(port);
152 break;
153 }
154
155 intrl2_1_mask_set(priv, P_IRQ_MASK(off));
156 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
157}
158
159static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
160 struct phy_device *phy)
161{
162 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
163 unsigned int i;
164 u32 reg;
165
166 if (!dsa_is_user_port(ds, port))
167 return 0;
168
169 /* Clear the memory power down */
170 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
171 reg &= ~P_TXQ_PSM_VDD(port);
172 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
173
174 /* Enable learning */
175 reg = core_readl(priv, CORE_DIS_LEARN);
176 reg &= ~BIT(port);
177 core_writel(priv, reg, CORE_DIS_LEARN);
178
179 /* Enable Broadcom tags for that port if requested */
180 if (priv->brcm_tag_mask & BIT(port))
181 b53_brcm_hdr_setup(ds, port);
182
183 /* Configure Traffic Class to QoS mapping, allow each priority to map
184 * to a different queue number
185 */
186 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
187 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
188 reg |= i << (PRT_TO_QID_SHIFT * i);
189 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
190
191 /* Re-enable the GPHY and re-apply workarounds */
192 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
193 bcm_sf2_gphy_enable_set(ds, true);
194 if (phy) {
195 /* if phy_stop() has been called before, phy
196 * will be in halted state, and phy_start()
197 * will call resume.
198 *
199 * the resume path does not configure back
200 * autoneg settings, and since we hard reset
201 * the phy manually here, we need to reset the
202 * state machine also.
203 */
204 phy->state = PHY_READY;
205 phy_init_hw(phy);
206 }
207 }
208
209 /* Enable MoCA port interrupts to get notified */
210 if (port == priv->moca_port)
211 bcm_sf2_port_intr_enable(priv, port);
212
213 /* Set per-queue pause threshold to 32 */
214 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port));
215
216 /* Set ACB threshold to 24 */
217 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) {
218 reg = acb_readl(priv, ACB_QUEUE_CFG(port *
219 SF2_NUM_EGRESS_QUEUES + i));
220 reg &= ~XOFF_THRESHOLD_MASK;
221 reg |= 24;
222 acb_writel(priv, reg, ACB_QUEUE_CFG(port *
223 SF2_NUM_EGRESS_QUEUES + i));
224 }
225
226 return b53_enable_port(ds, port, phy);
227}
228
229static void bcm_sf2_port_disable(struct dsa_switch *ds, int port)
230{
231 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
232 u32 reg;
233
234 /* Disable learning while in WoL mode */
235 if (priv->wol_ports_mask & (1 << port)) {
236 reg = core_readl(priv, CORE_DIS_LEARN);
237 reg |= BIT(port);
238 core_writel(priv, reg, CORE_DIS_LEARN);
239 return;
240 }
241
242 if (port == priv->moca_port)
243 bcm_sf2_port_intr_disable(priv, port);
244
245 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
246 bcm_sf2_gphy_enable_set(ds, false);
247
248 b53_disable_port(ds, port);
249
250 /* Power down the port memory */
251 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
252 reg |= P_TXQ_PSM_VDD(port);
253 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
254}
255
256
257static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
258 int regnum, u16 val)
259{
260 int ret = 0;
261 u32 reg;
262
263 reg = reg_readl(priv, REG_SWITCH_CNTRL);
264 reg |= MDIO_MASTER_SEL;
265 reg_writel(priv, reg, REG_SWITCH_CNTRL);
266
267 /* Page << 8 | offset */
268 reg = 0x70;
269 reg <<= 2;
270 core_writel(priv, addr, reg);
271
272 /* Page << 8 | offset */
273 reg = 0x80 << 8 | regnum << 1;
274 reg <<= 2;
275
276 if (op)
277 ret = core_readl(priv, reg);
278 else
279 core_writel(priv, val, reg);
280
281 reg = reg_readl(priv, REG_SWITCH_CNTRL);
282 reg &= ~MDIO_MASTER_SEL;
283 reg_writel(priv, reg, REG_SWITCH_CNTRL);
284
285 return ret & 0xffff;
286}
287
288static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
289{
290 struct bcm_sf2_priv *priv = bus->priv;
291
292 /* Intercept reads from Broadcom pseudo-PHY address, else, send
293 * them to our master MDIO bus controller
294 */
295 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
296 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
297 else
298 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum);
299}
300
301static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
302 u16 val)
303{
304 struct bcm_sf2_priv *priv = bus->priv;
305
306 /* Intercept writes to the Broadcom pseudo-PHY address, else,
307 * send them to our master MDIO bus controller
308 */
309 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
310 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
311 else
312 return mdiobus_write_nested(priv->master_mii_bus, addr,
313 regnum, val);
314}
315
316static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
317{
318 struct dsa_switch *ds = dev_id;
319 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
320
321 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
322 ~priv->irq0_mask;
323 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
324
325 return IRQ_HANDLED;
326}
327
328static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
329{
330 struct dsa_switch *ds = dev_id;
331 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
332
333 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
334 ~priv->irq1_mask;
335 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
336
337 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) {
338 priv->port_sts[7].link = true;
339 dsa_port_phylink_mac_change(ds, 7, true);
340 }
341 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) {
342 priv->port_sts[7].link = false;
343 dsa_port_phylink_mac_change(ds, 7, false);
344 }
345
346 return IRQ_HANDLED;
347}
348
349static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
350{
351 unsigned int timeout = 1000;
352 u32 reg;
353
354 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
355 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
356 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
357
358 do {
359 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
360 if (!(reg & SOFTWARE_RESET))
361 break;
362
363 usleep_range(1000, 2000);
364 } while (timeout-- > 0);
365
366 if (timeout == 0)
367 return -ETIMEDOUT;
368
369 return 0;
370}
371
372static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
373{
374 intrl2_0_mask_set(priv, 0xffffffff);
375 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
376 intrl2_1_mask_set(priv, 0xffffffff);
377 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
378}
379
380static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
381 struct device_node *dn)
382{
383 struct device_node *port;
384 int mode;
385 unsigned int port_num;
386
387 priv->moca_port = -1;
388
389 for_each_available_child_of_node(dn, port) {
390 if (of_property_read_u32(port, "reg", &port_num))
391 continue;
392
393 /* Internal PHYs get assigned a specific 'phy-mode' property
394 * value: "internal" to help flag them before MDIO probing
395 * has completed, since they might be turned off at that
396 * time
397 */
398 mode = of_get_phy_mode(port);
399 if (mode < 0)
400 continue;
401
402 if (mode == PHY_INTERFACE_MODE_INTERNAL)
403 priv->int_phy_mask |= 1 << port_num;
404
405 if (mode == PHY_INTERFACE_MODE_MOCA)
406 priv->moca_port = port_num;
407
408 if (of_property_read_bool(port, "brcm,use-bcm-hdr"))
409 priv->brcm_tag_mask |= 1 << port_num;
410 }
411}
412
413static int bcm_sf2_mdio_register(struct dsa_switch *ds)
414{
415 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
416 struct device_node *dn;
417 static int index;
418 int err;
419
420 /* Find our integrated MDIO bus node */
421 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
422 priv->master_mii_bus = of_mdio_find_bus(dn);
423 if (!priv->master_mii_bus)
424 return -EPROBE_DEFER;
425
426 get_device(&priv->master_mii_bus->dev);
427 priv->master_mii_dn = dn;
428
429 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev);
430 if (!priv->slave_mii_bus)
431 return -ENOMEM;
432
433 priv->slave_mii_bus->priv = priv;
434 priv->slave_mii_bus->name = "sf2 slave mii";
435 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
436 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
437 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
438 index++);
439 priv->slave_mii_bus->dev.of_node = dn;
440
441 /* Include the pseudo-PHY address to divert reads towards our
442 * workaround. This is only required for 7445D0, since 7445E0
443 * disconnects the internal switch pseudo-PHY such that we can use the
444 * regular SWITCH_MDIO master controller instead.
445 *
446 * Here we flag the pseudo PHY as needing special treatment and would
447 * otherwise make all other PHY read/writes go to the master MDIO bus
448 * controller that comes with this switch backed by the "mdio-unimac"
449 * driver.
450 */
451 if (of_machine_is_compatible("brcm,bcm7445d0"))
452 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR);
453 else
454 priv->indir_phy_mask = 0;
455
456 ds->phys_mii_mask = priv->indir_phy_mask;
457 ds->slave_mii_bus = priv->slave_mii_bus;
458 priv->slave_mii_bus->parent = ds->dev->parent;
459 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
460
461 err = of_mdiobus_register(priv->slave_mii_bus, dn);
462 if (err && dn)
463 of_node_put(dn);
464
465 return err;
466}
467
468static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
469{
470 mdiobus_unregister(priv->slave_mii_bus);
471 of_node_put(priv->master_mii_dn);
472}
473
474static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
475{
476 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
477
478 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
479 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
480 * the REG_PHY_REVISION register layout is.
481 */
482
483 return priv->hw_params.gphy_rev;
484}
485
486static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port,
487 unsigned long *supported,
488 struct phylink_link_state *state)
489{
490 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
491 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
492
493 if (!phy_interface_mode_is_rgmii(state->interface) &&
494 state->interface != PHY_INTERFACE_MODE_MII &&
495 state->interface != PHY_INTERFACE_MODE_REVMII &&
496 state->interface != PHY_INTERFACE_MODE_GMII &&
497 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
498 state->interface != PHY_INTERFACE_MODE_MOCA) {
499 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
500 if (port != core_readl(priv, CORE_IMP0_PRT_ID))
501 dev_err(ds->dev,
502 "Unsupported interface: %d for port %d\n",
503 state->interface, port);
504 return;
505 }
506
507 /* Allow all the expected bits */
508 phylink_set(mask, Autoneg);
509 phylink_set_port_modes(mask);
510 phylink_set(mask, Pause);
511 phylink_set(mask, Asym_Pause);
512
513 /* With the exclusion of MII and Reverse MII, we support Gigabit,
514 * including Half duplex
515 */
516 if (state->interface != PHY_INTERFACE_MODE_MII &&
517 state->interface != PHY_INTERFACE_MODE_REVMII) {
518 phylink_set(mask, 1000baseT_Full);
519 phylink_set(mask, 1000baseT_Half);
520 }
521
522 phylink_set(mask, 10baseT_Half);
523 phylink_set(mask, 10baseT_Full);
524 phylink_set(mask, 100baseT_Half);
525 phylink_set(mask, 100baseT_Full);
526
527 bitmap_and(supported, supported, mask,
528 __ETHTOOL_LINK_MODE_MASK_NBITS);
529 bitmap_and(state->advertising, state->advertising, mask,
530 __ETHTOOL_LINK_MODE_MASK_NBITS);
531}
532
533static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port,
534 unsigned int mode,
535 const struct phylink_link_state *state)
536{
537 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
538 u32 id_mode_dis = 0, port_mode;
539 u32 reg, offset;
540
541 if (port == core_readl(priv, CORE_IMP0_PRT_ID))
542 return;
543
544 if (priv->type == BCM7445_DEVICE_ID)
545 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
546 else
547 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
548
549 switch (state->interface) {
550 case PHY_INTERFACE_MODE_RGMII:
551 id_mode_dis = 1;
552 /* fallthrough */
553 case PHY_INTERFACE_MODE_RGMII_TXID:
554 port_mode = EXT_GPHY;
555 break;
556 case PHY_INTERFACE_MODE_MII:
557 port_mode = EXT_EPHY;
558 break;
559 case PHY_INTERFACE_MODE_REVMII:
560 port_mode = EXT_REVMII;
561 break;
562 default:
563 /* all other PHYs: internal and MoCA */
564 goto force_link;
565 }
566
567 /* Clear id_mode_dis bit, and the existing port mode, let
568 * RGMII_MODE_EN bet set by mac_link_{up,down}
569 */
570 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
571 reg &= ~ID_MODE_DIS;
572 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
573 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
574
575 reg |= port_mode;
576 if (id_mode_dis)
577 reg |= ID_MODE_DIS;
578
579 if (state->pause & MLO_PAUSE_TXRX_MASK) {
580 if (state->pause & MLO_PAUSE_TX)
581 reg |= TX_PAUSE_EN;
582 reg |= RX_PAUSE_EN;
583 }
584
585 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
586
587force_link:
588 /* Force link settings detected from the PHY */
589 reg = SW_OVERRIDE;
590 switch (state->speed) {
591 case SPEED_1000:
592 reg |= SPDSTS_1000 << SPEED_SHIFT;
593 break;
594 case SPEED_100:
595 reg |= SPDSTS_100 << SPEED_SHIFT;
596 break;
597 }
598
599 if (state->link)
600 reg |= LINK_STS;
601 if (state->duplex == DUPLEX_FULL)
602 reg |= DUPLX_MODE;
603
604 core_writel(priv, reg, offset);
605}
606
607static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port,
608 phy_interface_t interface, bool link)
609{
610 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
611 u32 reg;
612
613 if (!phy_interface_mode_is_rgmii(interface) &&
614 interface != PHY_INTERFACE_MODE_MII &&
615 interface != PHY_INTERFACE_MODE_REVMII)
616 return;
617
618 /* If the link is down, just disable the interface to conserve power */
619 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
620 if (link)
621 reg |= RGMII_MODE_EN;
622 else
623 reg &= ~RGMII_MODE_EN;
624 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
625}
626
627static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port,
628 unsigned int mode,
629 phy_interface_t interface)
630{
631 bcm_sf2_sw_mac_link_set(ds, port, interface, false);
632}
633
634static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port,
635 unsigned int mode,
636 phy_interface_t interface,
637 struct phy_device *phydev)
638{
639 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
640 struct ethtool_eee *p = &priv->dev->ports[port].eee;
641
642 bcm_sf2_sw_mac_link_set(ds, port, interface, true);
643
644 if (mode == MLO_AN_PHY && phydev)
645 p->eee_enabled = b53_eee_init(ds, port, phydev);
646}
647
648static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port,
649 struct phylink_link_state *status)
650{
651 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
652
653 status->link = false;
654
655 /* MoCA port is special as we do not get link status from CORE_LNKSTS,
656 * which means that we need to force the link at the port override
657 * level to get the data to flow. We do use what the interrupt handler
658 * did determine before.
659 *
660 * For the other ports, we just force the link status, since this is
661 * a fixed PHY device.
662 */
663 if (port == priv->moca_port) {
664 status->link = priv->port_sts[port].link;
665 /* For MoCA interfaces, also force a link down notification
666 * since some version of the user-space daemon (mocad) use
667 * cmd->autoneg to force the link, which messes up the PHY
668 * state machine and make it go in PHY_FORCING state instead.
669 */
670 if (!status->link)
671 netif_carrier_off(ds->ports[port].slave);
672 status->duplex = DUPLEX_FULL;
673 } else {
674 status->link = true;
675 }
676}
677
678static void bcm_sf2_enable_acb(struct dsa_switch *ds)
679{
680 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
681 u32 reg;
682
683 /* Enable ACB globally */
684 reg = acb_readl(priv, ACB_CONTROL);
685 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
686 acb_writel(priv, reg, ACB_CONTROL);
687 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
688 reg |= ACB_EN | ACB_ALGORITHM;
689 acb_writel(priv, reg, ACB_CONTROL);
690}
691
692static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
693{
694 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
695 unsigned int port;
696
697 bcm_sf2_intr_disable(priv);
698
699 /* Disable all ports physically present including the IMP
700 * port, the other ones have already been disabled during
701 * bcm_sf2_sw_setup
702 */
703 for (port = 0; port < ds->num_ports; port++) {
704 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port))
705 bcm_sf2_port_disable(ds, port);
706 }
707
708 return 0;
709}
710
711static int bcm_sf2_sw_resume(struct dsa_switch *ds)
712{
713 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
714 int ret;
715
716 ret = bcm_sf2_sw_rst(priv);
717 if (ret) {
718 pr_err("%s: failed to software reset switch\n", __func__);
719 return ret;
720 }
721
722 ret = bcm_sf2_cfp_resume(ds);
723 if (ret)
724 return ret;
725
726 if (priv->hw_params.num_gphy == 1)
727 bcm_sf2_gphy_enable_set(ds, true);
728
729 ds->ops->setup(ds);
730
731 return 0;
732}
733
734static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
735 struct ethtool_wolinfo *wol)
736{
737 struct net_device *p = ds->ports[port].cpu_dp->master;
738 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
739 struct ethtool_wolinfo pwol = { };
740
741 /* Get the parent device WoL settings */
742 if (p->ethtool_ops->get_wol)
743 p->ethtool_ops->get_wol(p, &pwol);
744
745 /* Advertise the parent device supported settings */
746 wol->supported = pwol.supported;
747 memset(&wol->sopass, 0, sizeof(wol->sopass));
748
749 if (pwol.wolopts & WAKE_MAGICSECURE)
750 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
751
752 if (priv->wol_ports_mask & (1 << port))
753 wol->wolopts = pwol.wolopts;
754 else
755 wol->wolopts = 0;
756}
757
758static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
759 struct ethtool_wolinfo *wol)
760{
761 struct net_device *p = ds->ports[port].cpu_dp->master;
762 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
763 s8 cpu_port = ds->ports[port].cpu_dp->index;
764 struct ethtool_wolinfo pwol = { };
765
766 if (p->ethtool_ops->get_wol)
767 p->ethtool_ops->get_wol(p, &pwol);
768 if (wol->wolopts & ~pwol.supported)
769 return -EINVAL;
770
771 if (wol->wolopts)
772 priv->wol_ports_mask |= (1 << port);
773 else
774 priv->wol_ports_mask &= ~(1 << port);
775
776 /* If we have at least one port enabled, make sure the CPU port
777 * is also enabled. If the CPU port is the last one enabled, we disable
778 * it since this configuration does not make sense.
779 */
780 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
781 priv->wol_ports_mask |= (1 << cpu_port);
782 else
783 priv->wol_ports_mask &= ~(1 << cpu_port);
784
785 return p->ethtool_ops->set_wol(p, wol);
786}
787
788static int bcm_sf2_sw_setup(struct dsa_switch *ds)
789{
790 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
791 unsigned int port;
792
793 /* Enable all valid ports and disable those unused */
794 for (port = 0; port < priv->hw_params.num_ports; port++) {
795 /* IMP port receives special treatment */
796 if (dsa_is_user_port(ds, port))
797 bcm_sf2_port_setup(ds, port, NULL);
798 else if (dsa_is_cpu_port(ds, port))
799 bcm_sf2_imp_setup(ds, port);
800 else
801 bcm_sf2_port_disable(ds, port);
802 }
803
804 b53_configure_vlan(ds);
805 bcm_sf2_enable_acb(ds);
806
807 return 0;
808}
809
810/* The SWITCH_CORE register space is managed by b53 but operates on a page +
811 * register basis so we need to translate that into an address that the
812 * bus-glue understands.
813 */
814#define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2)
815
816static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
817 u8 *val)
818{
819 struct bcm_sf2_priv *priv = dev->priv;
820
821 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
822
823 return 0;
824}
825
826static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
827 u16 *val)
828{
829 struct bcm_sf2_priv *priv = dev->priv;
830
831 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
832
833 return 0;
834}
835
836static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
837 u32 *val)
838{
839 struct bcm_sf2_priv *priv = dev->priv;
840
841 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
842
843 return 0;
844}
845
846static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
847 u64 *val)
848{
849 struct bcm_sf2_priv *priv = dev->priv;
850
851 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
852
853 return 0;
854}
855
856static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
857 u8 value)
858{
859 struct bcm_sf2_priv *priv = dev->priv;
860
861 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
862
863 return 0;
864}
865
866static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
867 u16 value)
868{
869 struct bcm_sf2_priv *priv = dev->priv;
870
871 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
872
873 return 0;
874}
875
876static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
877 u32 value)
878{
879 struct bcm_sf2_priv *priv = dev->priv;
880
881 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
882
883 return 0;
884}
885
886static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
887 u64 value)
888{
889 struct bcm_sf2_priv *priv = dev->priv;
890
891 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
892
893 return 0;
894}
895
896static const struct b53_io_ops bcm_sf2_io_ops = {
897 .read8 = bcm_sf2_core_read8,
898 .read16 = bcm_sf2_core_read16,
899 .read32 = bcm_sf2_core_read32,
900 .read48 = bcm_sf2_core_read64,
901 .read64 = bcm_sf2_core_read64,
902 .write8 = bcm_sf2_core_write8,
903 .write16 = bcm_sf2_core_write16,
904 .write32 = bcm_sf2_core_write32,
905 .write48 = bcm_sf2_core_write64,
906 .write64 = bcm_sf2_core_write64,
907};
908
909static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port,
910 u32 stringset, uint8_t *data)
911{
912 int cnt = b53_get_sset_count(ds, port, stringset);
913
914 b53_get_strings(ds, port, stringset, data);
915 bcm_sf2_cfp_get_strings(ds, port, stringset,
916 data + cnt * ETH_GSTRING_LEN);
917}
918
919static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port,
920 uint64_t *data)
921{
922 int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS);
923
924 b53_get_ethtool_stats(ds, port, data);
925 bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt);
926}
927
928static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port,
929 int sset)
930{
931 int cnt = b53_get_sset_count(ds, port, sset);
932
933 if (cnt < 0)
934 return cnt;
935
936 cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset);
937
938 return cnt;
939}
940
941static const struct dsa_switch_ops bcm_sf2_ops = {
942 .get_tag_protocol = b53_get_tag_protocol,
943 .setup = bcm_sf2_sw_setup,
944 .get_strings = bcm_sf2_sw_get_strings,
945 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats,
946 .get_sset_count = bcm_sf2_sw_get_sset_count,
947 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
948 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
949 .phylink_validate = bcm_sf2_sw_validate,
950 .phylink_mac_config = bcm_sf2_sw_mac_config,
951 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down,
952 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up,
953 .phylink_fixed_state = bcm_sf2_sw_fixed_state,
954 .suspend = bcm_sf2_sw_suspend,
955 .resume = bcm_sf2_sw_resume,
956 .get_wol = bcm_sf2_sw_get_wol,
957 .set_wol = bcm_sf2_sw_set_wol,
958 .port_enable = bcm_sf2_port_setup,
959 .port_disable = bcm_sf2_port_disable,
960 .get_mac_eee = b53_get_mac_eee,
961 .set_mac_eee = b53_set_mac_eee,
962 .port_bridge_join = b53_br_join,
963 .port_bridge_leave = b53_br_leave,
964 .port_stp_state_set = b53_br_set_stp_state,
965 .port_fast_age = b53_br_fast_age,
966 .port_vlan_filtering = b53_vlan_filtering,
967 .port_vlan_prepare = b53_vlan_prepare,
968 .port_vlan_add = b53_vlan_add,
969 .port_vlan_del = b53_vlan_del,
970 .port_fdb_dump = b53_fdb_dump,
971 .port_fdb_add = b53_fdb_add,
972 .port_fdb_del = b53_fdb_del,
973 .get_rxnfc = bcm_sf2_get_rxnfc,
974 .set_rxnfc = bcm_sf2_set_rxnfc,
975 .port_mirror_add = b53_mirror_add,
976 .port_mirror_del = b53_mirror_del,
977};
978
979struct bcm_sf2_of_data {
980 u32 type;
981 const u16 *reg_offsets;
982 unsigned int core_reg_align;
983 unsigned int num_cfp_rules;
984};
985
986/* Register offsets for the SWITCH_REG_* block */
987static const u16 bcm_sf2_7445_reg_offsets[] = {
988 [REG_SWITCH_CNTRL] = 0x00,
989 [REG_SWITCH_STATUS] = 0x04,
990 [REG_DIR_DATA_WRITE] = 0x08,
991 [REG_DIR_DATA_READ] = 0x0C,
992 [REG_SWITCH_REVISION] = 0x18,
993 [REG_PHY_REVISION] = 0x1C,
994 [REG_SPHY_CNTRL] = 0x2C,
995 [REG_RGMII_0_CNTRL] = 0x34,
996 [REG_RGMII_1_CNTRL] = 0x40,
997 [REG_RGMII_2_CNTRL] = 0x4c,
998 [REG_LED_0_CNTRL] = 0x90,
999 [REG_LED_1_CNTRL] = 0x94,
1000 [REG_LED_2_CNTRL] = 0x98,
1001};
1002
1003static const struct bcm_sf2_of_data bcm_sf2_7445_data = {
1004 .type = BCM7445_DEVICE_ID,
1005 .core_reg_align = 0,
1006 .reg_offsets = bcm_sf2_7445_reg_offsets,
1007 .num_cfp_rules = 256,
1008};
1009
1010static const u16 bcm_sf2_7278_reg_offsets[] = {
1011 [REG_SWITCH_CNTRL] = 0x00,
1012 [REG_SWITCH_STATUS] = 0x04,
1013 [REG_DIR_DATA_WRITE] = 0x08,
1014 [REG_DIR_DATA_READ] = 0x0c,
1015 [REG_SWITCH_REVISION] = 0x10,
1016 [REG_PHY_REVISION] = 0x14,
1017 [REG_SPHY_CNTRL] = 0x24,
1018 [REG_RGMII_0_CNTRL] = 0xe0,
1019 [REG_RGMII_1_CNTRL] = 0xec,
1020 [REG_RGMII_2_CNTRL] = 0xf8,
1021 [REG_LED_0_CNTRL] = 0x40,
1022 [REG_LED_1_CNTRL] = 0x4c,
1023 [REG_LED_2_CNTRL] = 0x58,
1024};
1025
1026static const struct bcm_sf2_of_data bcm_sf2_7278_data = {
1027 .type = BCM7278_DEVICE_ID,
1028 .core_reg_align = 1,
1029 .reg_offsets = bcm_sf2_7278_reg_offsets,
1030 .num_cfp_rules = 128,
1031};
1032
1033static const struct of_device_id bcm_sf2_of_match[] = {
1034 { .compatible = "brcm,bcm7445-switch-v4.0",
1035 .data = &bcm_sf2_7445_data
1036 },
1037 { .compatible = "brcm,bcm7278-switch-v4.0",
1038 .data = &bcm_sf2_7278_data
1039 },
1040 { .compatible = "brcm,bcm7278-switch-v4.8",
1041 .data = &bcm_sf2_7278_data
1042 },
1043 { /* sentinel */ },
1044};
1045MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
1046
1047static int bcm_sf2_sw_probe(struct platform_device *pdev)
1048{
1049 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
1050 struct device_node *dn = pdev->dev.of_node;
1051 const struct of_device_id *of_id = NULL;
1052 const struct bcm_sf2_of_data *data;
1053 struct b53_platform_data *pdata;
1054 struct dsa_switch_ops *ops;
1055 struct bcm_sf2_priv *priv;
1056 struct b53_device *dev;
1057 struct dsa_switch *ds;
1058 void __iomem **base;
1059 unsigned int i;
1060 u32 reg, rev;
1061 int ret;
1062
1063 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1064 if (!priv)
1065 return -ENOMEM;
1066
1067 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL);
1068 if (!ops)
1069 return -ENOMEM;
1070
1071 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv);
1072 if (!dev)
1073 return -ENOMEM;
1074
1075 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1076 if (!pdata)
1077 return -ENOMEM;
1078
1079 of_id = of_match_node(bcm_sf2_of_match, dn);
1080 if (!of_id || !of_id->data)
1081 return -EINVAL;
1082
1083 data = of_id->data;
1084
1085 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */
1086 priv->type = data->type;
1087 priv->reg_offsets = data->reg_offsets;
1088 priv->core_reg_align = data->core_reg_align;
1089 priv->num_cfp_rules = data->num_cfp_rules;
1090
1091 /* Auto-detection using standard registers will not work, so
1092 * provide an indication of what kind of device we are for
1093 * b53_common to work with
1094 */
1095 pdata->chip_id = priv->type;
1096 dev->pdata = pdata;
1097
1098 priv->dev = dev;
1099 ds = dev->ds;
1100 ds->ops = &bcm_sf2_ops;
1101
1102 /* Advertise the 8 egress queues */
1103 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES;
1104
1105 dev_set_drvdata(&pdev->dev, priv);
1106
1107 spin_lock_init(&priv->indir_lock);
1108 mutex_init(&priv->cfp.lock);
1109 INIT_LIST_HEAD(&priv->cfp.rules_list);
1110
1111 /* CFP rule #0 cannot be used for specific classifications, flag it as
1112 * permanently used
1113 */
1114 set_bit(0, priv->cfp.used);
1115 set_bit(0, priv->cfp.unique);
1116
1117 bcm_sf2_identify_ports(priv, dn->child);
1118
1119 priv->irq0 = irq_of_parse_and_map(dn, 0);
1120 priv->irq1 = irq_of_parse_and_map(dn, 1);
1121
1122 base = &priv->core;
1123 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
1124 *base = devm_platform_ioremap_resource(pdev, i);
1125 if (IS_ERR(*base)) {
1126 pr_err("unable to find register: %s\n", reg_names[i]);
1127 return PTR_ERR(*base);
1128 }
1129 base++;
1130 }
1131
1132 ret = bcm_sf2_sw_rst(priv);
1133 if (ret) {
1134 pr_err("unable to software reset switch: %d\n", ret);
1135 return ret;
1136 }
1137
1138 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1139
1140 ret = bcm_sf2_mdio_register(ds);
1141 if (ret) {
1142 pr_err("failed to register MDIO bus\n");
1143 return ret;
1144 }
1145
1146 bcm_sf2_gphy_enable_set(priv->dev->ds, false);
1147
1148 ret = bcm_sf2_cfp_rst(priv);
1149 if (ret) {
1150 pr_err("failed to reset CFP\n");
1151 goto out_mdio;
1152 }
1153
1154 /* Disable all interrupts and request them */
1155 bcm_sf2_intr_disable(priv);
1156
1157 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0,
1158 "switch_0", ds);
1159 if (ret < 0) {
1160 pr_err("failed to request switch_0 IRQ\n");
1161 goto out_mdio;
1162 }
1163
1164 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0,
1165 "switch_1", ds);
1166 if (ret < 0) {
1167 pr_err("failed to request switch_1 IRQ\n");
1168 goto out_mdio;
1169 }
1170
1171 /* Reset the MIB counters */
1172 reg = core_readl(priv, CORE_GMNCFGCFG);
1173 reg |= RST_MIB_CNT;
1174 core_writel(priv, reg, CORE_GMNCFGCFG);
1175 reg &= ~RST_MIB_CNT;
1176 core_writel(priv, reg, CORE_GMNCFGCFG);
1177
1178 /* Get the maximum number of ports for this switch */
1179 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
1180 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
1181 priv->hw_params.num_ports = DSA_MAX_PORTS;
1182
1183 /* Assume a single GPHY setup if we can't read that property */
1184 if (of_property_read_u32(dn, "brcm,num-gphy",
1185 &priv->hw_params.num_gphy))
1186 priv->hw_params.num_gphy = 1;
1187
1188 rev = reg_readl(priv, REG_SWITCH_REVISION);
1189 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1190 SWITCH_TOP_REV_MASK;
1191 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1192
1193 rev = reg_readl(priv, REG_PHY_REVISION);
1194 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1195
1196 ret = b53_switch_register(dev);
1197 if (ret)
1198 goto out_mdio;
1199
1200 dev_info(&pdev->dev,
1201 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n",
1202 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1203 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1204 priv->irq0, priv->irq1);
1205
1206 return 0;
1207
1208out_mdio:
1209 bcm_sf2_mdio_unregister(priv);
1210 return ret;
1211}
1212
1213static int bcm_sf2_sw_remove(struct platform_device *pdev)
1214{
1215 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1216
1217 priv->wol_ports_mask = 0;
1218 /* Disable interrupts */
1219 bcm_sf2_intr_disable(priv);
1220 dsa_unregister_switch(priv->dev->ds);
1221 bcm_sf2_cfp_exit(priv->dev->ds);
1222 bcm_sf2_mdio_unregister(priv);
1223
1224 return 0;
1225}
1226
1227static void bcm_sf2_sw_shutdown(struct platform_device *pdev)
1228{
1229 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1230
1231 /* For a kernel about to be kexec'd we want to keep the GPHY on for a
1232 * successful MDIO bus scan to occur. If we did turn off the GPHY
1233 * before (e.g: port_disable), this will also power it back on.
1234 *
1235 * Do not rely on kexec_in_progress, just power the PHY on.
1236 */
1237 if (priv->hw_params.num_gphy == 1)
1238 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1239}
1240
1241#ifdef CONFIG_PM_SLEEP
1242static int bcm_sf2_suspend(struct device *dev)
1243{
1244 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1245
1246 return dsa_switch_suspend(priv->dev->ds);
1247}
1248
1249static int bcm_sf2_resume(struct device *dev)
1250{
1251 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1252
1253 return dsa_switch_resume(priv->dev->ds);
1254}
1255#endif /* CONFIG_PM_SLEEP */
1256
1257static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
1258 bcm_sf2_suspend, bcm_sf2_resume);
1259
1260
1261static struct platform_driver bcm_sf2_driver = {
1262 .probe = bcm_sf2_sw_probe,
1263 .remove = bcm_sf2_sw_remove,
1264 .shutdown = bcm_sf2_sw_shutdown,
1265 .driver = {
1266 .name = "brcm-sf2",
1267 .of_match_table = bcm_sf2_of_match,
1268 .pm = &bcm_sf2_pm_ops,
1269 },
1270};
1271module_platform_driver(bcm_sf2_driver);
1272
1273MODULE_AUTHOR("Broadcom Corporation");
1274MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1275MODULE_LICENSE("GPL");
1276MODULE_ALIAS("platform:brcm-sf2");
1/*
2 * Broadcom Starfighter 2 DSA switch driver
3 *
4 * Copyright (C) 2014, Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/list.h>
13#include <linux/module.h>
14#include <linux/netdevice.h>
15#include <linux/interrupt.h>
16#include <linux/platform_device.h>
17#include <linux/of.h>
18#include <linux/phy.h>
19#include <linux/phy_fixed.h>
20#include <linux/mii.h>
21#include <linux/of.h>
22#include <linux/of_irq.h>
23#include <linux/of_address.h>
24#include <linux/of_net.h>
25#include <net/dsa.h>
26#include <linux/ethtool.h>
27#include <linux/if_bridge.h>
28#include <linux/brcmphy.h>
29#include <linux/etherdevice.h>
30#include <net/switchdev.h>
31
32#include "bcm_sf2.h"
33#include "bcm_sf2_regs.h"
34
35/* String, offset, and register size in bytes if different from 4 bytes */
36static const struct bcm_sf2_hw_stats bcm_sf2_mib[] = {
37 { "TxOctets", 0x000, 8 },
38 { "TxDropPkts", 0x020 },
39 { "TxQPKTQ0", 0x030 },
40 { "TxBroadcastPkts", 0x040 },
41 { "TxMulticastPkts", 0x050 },
42 { "TxUnicastPKts", 0x060 },
43 { "TxCollisions", 0x070 },
44 { "TxSingleCollision", 0x080 },
45 { "TxMultipleCollision", 0x090 },
46 { "TxDeferredCollision", 0x0a0 },
47 { "TxLateCollision", 0x0b0 },
48 { "TxExcessiveCollision", 0x0c0 },
49 { "TxFrameInDisc", 0x0d0 },
50 { "TxPausePkts", 0x0e0 },
51 { "TxQPKTQ1", 0x0f0 },
52 { "TxQPKTQ2", 0x100 },
53 { "TxQPKTQ3", 0x110 },
54 { "TxQPKTQ4", 0x120 },
55 { "TxQPKTQ5", 0x130 },
56 { "RxOctets", 0x140, 8 },
57 { "RxUndersizePkts", 0x160 },
58 { "RxPausePkts", 0x170 },
59 { "RxPkts64Octets", 0x180 },
60 { "RxPkts65to127Octets", 0x190 },
61 { "RxPkts128to255Octets", 0x1a0 },
62 { "RxPkts256to511Octets", 0x1b0 },
63 { "RxPkts512to1023Octets", 0x1c0 },
64 { "RxPkts1024toMaxPktsOctets", 0x1d0 },
65 { "RxOversizePkts", 0x1e0 },
66 { "RxJabbers", 0x1f0 },
67 { "RxAlignmentErrors", 0x200 },
68 { "RxFCSErrors", 0x210 },
69 { "RxGoodOctets", 0x220, 8 },
70 { "RxDropPkts", 0x240 },
71 { "RxUnicastPkts", 0x250 },
72 { "RxMulticastPkts", 0x260 },
73 { "RxBroadcastPkts", 0x270 },
74 { "RxSAChanges", 0x280 },
75 { "RxFragments", 0x290 },
76 { "RxJumboPkt", 0x2a0 },
77 { "RxSymblErr", 0x2b0 },
78 { "InRangeErrCount", 0x2c0 },
79 { "OutRangeErrCount", 0x2d0 },
80 { "EEELpiEvent", 0x2e0 },
81 { "EEELpiDuration", 0x2f0 },
82 { "RxDiscard", 0x300, 8 },
83 { "TxQPKTQ6", 0x320 },
84 { "TxQPKTQ7", 0x330 },
85 { "TxPkts64Octets", 0x340 },
86 { "TxPkts65to127Octets", 0x350 },
87 { "TxPkts128to255Octets", 0x360 },
88 { "TxPkts256to511Ocets", 0x370 },
89 { "TxPkts512to1023Ocets", 0x380 },
90 { "TxPkts1024toMaxPktOcets", 0x390 },
91};
92
93#define BCM_SF2_STATS_SIZE ARRAY_SIZE(bcm_sf2_mib)
94
95static void bcm_sf2_sw_get_strings(struct dsa_switch *ds,
96 int port, uint8_t *data)
97{
98 unsigned int i;
99
100 for (i = 0; i < BCM_SF2_STATS_SIZE; i++)
101 memcpy(data + i * ETH_GSTRING_LEN,
102 bcm_sf2_mib[i].string, ETH_GSTRING_LEN);
103}
104
105static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds,
106 int port, uint64_t *data)
107{
108 struct bcm_sf2_priv *priv = ds_to_priv(ds);
109 const struct bcm_sf2_hw_stats *s;
110 unsigned int i;
111 u64 val = 0;
112 u32 offset;
113
114 mutex_lock(&priv->stats_mutex);
115
116 /* Now fetch the per-port counters */
117 for (i = 0; i < BCM_SF2_STATS_SIZE; i++) {
118 s = &bcm_sf2_mib[i];
119
120 /* Do a latched 64-bit read if needed */
121 offset = s->reg + CORE_P_MIB_OFFSET(port);
122 if (s->sizeof_stat == 8)
123 val = core_readq(priv, offset);
124 else
125 val = core_readl(priv, offset);
126
127 data[i] = (u64)val;
128 }
129
130 mutex_unlock(&priv->stats_mutex);
131}
132
133static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds)
134{
135 return BCM_SF2_STATS_SIZE;
136}
137
138static char *bcm_sf2_sw_probe(struct device *host_dev, int sw_addr)
139{
140 return "Broadcom Starfighter 2";
141}
142
143static void bcm_sf2_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
144{
145 struct bcm_sf2_priv *priv = ds_to_priv(ds);
146 unsigned int i;
147 u32 reg;
148
149 /* Enable the IMP Port to be in the same VLAN as the other ports
150 * on a per-port basis such that we only have Port i and IMP in
151 * the same VLAN.
152 */
153 for (i = 0; i < priv->hw_params.num_ports; i++) {
154 if (!((1 << i) & ds->phys_port_mask))
155 continue;
156
157 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
158 reg |= (1 << cpu_port);
159 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
160 }
161}
162
163static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
164{
165 struct bcm_sf2_priv *priv = ds_to_priv(ds);
166 u32 reg, val;
167
168 /* Enable the port memories */
169 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
170 reg &= ~P_TXQ_PSM_VDD(port);
171 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
172
173 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
174 reg = core_readl(priv, CORE_IMP_CTL);
175 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
176 reg &= ~(RX_DIS | TX_DIS);
177 core_writel(priv, reg, CORE_IMP_CTL);
178
179 /* Enable forwarding */
180 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
181
182 /* Enable IMP port in dumb mode */
183 reg = core_readl(priv, CORE_SWITCH_CTRL);
184 reg |= MII_DUMB_FWDG_EN;
185 core_writel(priv, reg, CORE_SWITCH_CTRL);
186
187 /* Resolve which bit controls the Broadcom tag */
188 switch (port) {
189 case 8:
190 val = BRCM_HDR_EN_P8;
191 break;
192 case 7:
193 val = BRCM_HDR_EN_P7;
194 break;
195 case 5:
196 val = BRCM_HDR_EN_P5;
197 break;
198 default:
199 val = 0;
200 break;
201 }
202
203 /* Enable Broadcom tags for IMP port */
204 reg = core_readl(priv, CORE_BRCM_HDR_CTRL);
205 reg |= val;
206 core_writel(priv, reg, CORE_BRCM_HDR_CTRL);
207
208 /* Enable reception Broadcom tag for CPU TX (switch RX) to
209 * allow us to tag outgoing frames
210 */
211 reg = core_readl(priv, CORE_BRCM_HDR_RX_DIS);
212 reg &= ~(1 << port);
213 core_writel(priv, reg, CORE_BRCM_HDR_RX_DIS);
214
215 /* Enable transmission of Broadcom tags from the switch (CPU RX) to
216 * allow delivering frames to the per-port net_devices
217 */
218 reg = core_readl(priv, CORE_BRCM_HDR_TX_DIS);
219 reg &= ~(1 << port);
220 core_writel(priv, reg, CORE_BRCM_HDR_TX_DIS);
221
222 /* Force link status for IMP port */
223 reg = core_readl(priv, CORE_STS_OVERRIDE_IMP);
224 reg |= (MII_SW_OR | LINK_STS);
225 core_writel(priv, reg, CORE_STS_OVERRIDE_IMP);
226}
227
228static void bcm_sf2_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
229{
230 struct bcm_sf2_priv *priv = ds_to_priv(ds);
231 u32 reg;
232
233 reg = core_readl(priv, CORE_EEE_EN_CTRL);
234 if (enable)
235 reg |= 1 << port;
236 else
237 reg &= ~(1 << port);
238 core_writel(priv, reg, CORE_EEE_EN_CTRL);
239}
240
241static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
242{
243 struct bcm_sf2_priv *priv = ds_to_priv(ds);
244 u32 reg;
245
246 reg = reg_readl(priv, REG_SPHY_CNTRL);
247 if (enable) {
248 reg |= PHY_RESET;
249 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | CK25_DIS);
250 reg_writel(priv, reg, REG_SPHY_CNTRL);
251 udelay(21);
252 reg = reg_readl(priv, REG_SPHY_CNTRL);
253 reg &= ~PHY_RESET;
254 } else {
255 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
256 reg_writel(priv, reg, REG_SPHY_CNTRL);
257 mdelay(1);
258 reg |= CK25_DIS;
259 }
260 reg_writel(priv, reg, REG_SPHY_CNTRL);
261
262 /* Use PHY-driven LED signaling */
263 if (!enable) {
264 reg = reg_readl(priv, REG_LED_CNTRL(0));
265 reg |= SPDLNK_SRC_SEL;
266 reg_writel(priv, reg, REG_LED_CNTRL(0));
267 }
268}
269
270static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
271 int port)
272{
273 unsigned int off;
274
275 switch (port) {
276 case 7:
277 off = P7_IRQ_OFF;
278 break;
279 case 0:
280 /* Port 0 interrupts are located on the first bank */
281 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
282 return;
283 default:
284 off = P_IRQ_OFF(port);
285 break;
286 }
287
288 intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
289}
290
291static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
292 int port)
293{
294 unsigned int off;
295
296 switch (port) {
297 case 7:
298 off = P7_IRQ_OFF;
299 break;
300 case 0:
301 /* Port 0 interrupts are located on the first bank */
302 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
303 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
304 return;
305 default:
306 off = P_IRQ_OFF(port);
307 break;
308 }
309
310 intrl2_1_mask_set(priv, P_IRQ_MASK(off));
311 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
312}
313
314static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
315 struct phy_device *phy)
316{
317 struct bcm_sf2_priv *priv = ds_to_priv(ds);
318 s8 cpu_port = ds->dst[ds->index].cpu_port;
319 u32 reg;
320
321 /* Clear the memory power down */
322 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
323 reg &= ~P_TXQ_PSM_VDD(port);
324 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
325
326 /* Clear the Rx and Tx disable bits and set to no spanning tree */
327 core_writel(priv, 0, CORE_G_PCTL_PORT(port));
328
329 /* Re-enable the GPHY and re-apply workarounds */
330 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
331 bcm_sf2_gphy_enable_set(ds, true);
332 if (phy) {
333 /* if phy_stop() has been called before, phy
334 * will be in halted state, and phy_start()
335 * will call resume.
336 *
337 * the resume path does not configure back
338 * autoneg settings, and since we hard reset
339 * the phy manually here, we need to reset the
340 * state machine also.
341 */
342 phy->state = PHY_READY;
343 phy_init_hw(phy);
344 }
345 }
346
347 /* Enable MoCA port interrupts to get notified */
348 if (port == priv->moca_port)
349 bcm_sf2_port_intr_enable(priv, port);
350
351 /* Set this port, and only this one to be in the default VLAN,
352 * if member of a bridge, restore its membership prior to
353 * bringing down this port.
354 */
355 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
356 reg &= ~PORT_VLAN_CTRL_MASK;
357 reg |= (1 << port);
358 reg |= priv->port_sts[port].vlan_ctl_mask;
359 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(port));
360
361 bcm_sf2_imp_vlan_setup(ds, cpu_port);
362
363 /* If EEE was enabled, restore it */
364 if (priv->port_sts[port].eee.eee_enabled)
365 bcm_sf2_eee_enable_set(ds, port, true);
366
367 return 0;
368}
369
370static void bcm_sf2_port_disable(struct dsa_switch *ds, int port,
371 struct phy_device *phy)
372{
373 struct bcm_sf2_priv *priv = ds_to_priv(ds);
374 u32 off, reg;
375
376 if (priv->wol_ports_mask & (1 << port))
377 return;
378
379 if (port == priv->moca_port)
380 bcm_sf2_port_intr_disable(priv, port);
381
382 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
383 bcm_sf2_gphy_enable_set(ds, false);
384
385 if (dsa_is_cpu_port(ds, port))
386 off = CORE_IMP_CTL;
387 else
388 off = CORE_G_PCTL_PORT(port);
389
390 reg = core_readl(priv, off);
391 reg |= RX_DIS | TX_DIS;
392 core_writel(priv, reg, off);
393
394 /* Power down the port memory */
395 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
396 reg |= P_TXQ_PSM_VDD(port);
397 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
398}
399
400/* Returns 0 if EEE was not enabled, or 1 otherwise
401 */
402static int bcm_sf2_eee_init(struct dsa_switch *ds, int port,
403 struct phy_device *phy)
404{
405 struct bcm_sf2_priv *priv = ds_to_priv(ds);
406 struct ethtool_eee *p = &priv->port_sts[port].eee;
407 int ret;
408
409 p->supported = (SUPPORTED_1000baseT_Full | SUPPORTED_100baseT_Full);
410
411 ret = phy_init_eee(phy, 0);
412 if (ret)
413 return 0;
414
415 bcm_sf2_eee_enable_set(ds, port, true);
416
417 return 1;
418}
419
420static int bcm_sf2_sw_get_eee(struct dsa_switch *ds, int port,
421 struct ethtool_eee *e)
422{
423 struct bcm_sf2_priv *priv = ds_to_priv(ds);
424 struct ethtool_eee *p = &priv->port_sts[port].eee;
425 u32 reg;
426
427 reg = core_readl(priv, CORE_EEE_LPI_INDICATE);
428 e->eee_enabled = p->eee_enabled;
429 e->eee_active = !!(reg & (1 << port));
430
431 return 0;
432}
433
434static int bcm_sf2_sw_set_eee(struct dsa_switch *ds, int port,
435 struct phy_device *phydev,
436 struct ethtool_eee *e)
437{
438 struct bcm_sf2_priv *priv = ds_to_priv(ds);
439 struct ethtool_eee *p = &priv->port_sts[port].eee;
440
441 p->eee_enabled = e->eee_enabled;
442
443 if (!p->eee_enabled) {
444 bcm_sf2_eee_enable_set(ds, port, false);
445 } else {
446 p->eee_enabled = bcm_sf2_eee_init(ds, port, phydev);
447 if (!p->eee_enabled)
448 return -EOPNOTSUPP;
449 }
450
451 return 0;
452}
453
454/* Fast-ageing of ARL entries for a given port, equivalent to an ARL
455 * flush for that port.
456 */
457static int bcm_sf2_sw_fast_age_port(struct dsa_switch *ds, int port)
458{
459 struct bcm_sf2_priv *priv = ds_to_priv(ds);
460 unsigned int timeout = 1000;
461 u32 reg;
462
463 core_writel(priv, port, CORE_FAST_AGE_PORT);
464
465 reg = core_readl(priv, CORE_FAST_AGE_CTRL);
466 reg |= EN_AGE_PORT | EN_AGE_DYNAMIC | FAST_AGE_STR_DONE;
467 core_writel(priv, reg, CORE_FAST_AGE_CTRL);
468
469 do {
470 reg = core_readl(priv, CORE_FAST_AGE_CTRL);
471 if (!(reg & FAST_AGE_STR_DONE))
472 break;
473
474 cpu_relax();
475 } while (timeout--);
476
477 if (!timeout)
478 return -ETIMEDOUT;
479
480 core_writel(priv, 0, CORE_FAST_AGE_CTRL);
481
482 return 0;
483}
484
485static int bcm_sf2_sw_br_join(struct dsa_switch *ds, int port,
486 struct net_device *bridge)
487{
488 struct bcm_sf2_priv *priv = ds_to_priv(ds);
489 unsigned int i;
490 u32 reg, p_ctl;
491
492 priv->port_sts[port].bridge_dev = bridge;
493 p_ctl = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
494
495 for (i = 0; i < priv->hw_params.num_ports; i++) {
496 if (priv->port_sts[i].bridge_dev != bridge)
497 continue;
498
499 /* Add this local port to the remote port VLAN control
500 * membership and update the remote port bitmask
501 */
502 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
503 reg |= 1 << port;
504 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
505 priv->port_sts[i].vlan_ctl_mask = reg;
506
507 p_ctl |= 1 << i;
508 }
509
510 /* Configure the local port VLAN control membership to include
511 * remote ports and update the local port bitmask
512 */
513 core_writel(priv, p_ctl, CORE_PORT_VLAN_CTL_PORT(port));
514 priv->port_sts[port].vlan_ctl_mask = p_ctl;
515
516 return 0;
517}
518
519static void bcm_sf2_sw_br_leave(struct dsa_switch *ds, int port)
520{
521 struct bcm_sf2_priv *priv = ds_to_priv(ds);
522 struct net_device *bridge = priv->port_sts[port].bridge_dev;
523 unsigned int i;
524 u32 reg, p_ctl;
525
526 p_ctl = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
527
528 for (i = 0; i < priv->hw_params.num_ports; i++) {
529 /* Don't touch the remaining ports */
530 if (priv->port_sts[i].bridge_dev != bridge)
531 continue;
532
533 reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
534 reg &= ~(1 << port);
535 core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
536 priv->port_sts[port].vlan_ctl_mask = reg;
537
538 /* Prevent self removal to preserve isolation */
539 if (port != i)
540 p_ctl &= ~(1 << i);
541 }
542
543 core_writel(priv, p_ctl, CORE_PORT_VLAN_CTL_PORT(port));
544 priv->port_sts[port].vlan_ctl_mask = p_ctl;
545 priv->port_sts[port].bridge_dev = NULL;
546}
547
548static int bcm_sf2_sw_br_set_stp_state(struct dsa_switch *ds, int port,
549 u8 state)
550{
551 struct bcm_sf2_priv *priv = ds_to_priv(ds);
552 u8 hw_state, cur_hw_state;
553 int ret = 0;
554 u32 reg;
555
556 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
557 cur_hw_state = reg & (G_MISTP_STATE_MASK << G_MISTP_STATE_SHIFT);
558
559 switch (state) {
560 case BR_STATE_DISABLED:
561 hw_state = G_MISTP_DIS_STATE;
562 break;
563 case BR_STATE_LISTENING:
564 hw_state = G_MISTP_LISTEN_STATE;
565 break;
566 case BR_STATE_LEARNING:
567 hw_state = G_MISTP_LEARN_STATE;
568 break;
569 case BR_STATE_FORWARDING:
570 hw_state = G_MISTP_FWD_STATE;
571 break;
572 case BR_STATE_BLOCKING:
573 hw_state = G_MISTP_BLOCK_STATE;
574 break;
575 default:
576 pr_err("%s: invalid STP state: %d\n", __func__, state);
577 return -EINVAL;
578 }
579
580 /* Fast-age ARL entries if we are moving a port from Learning or
581 * Forwarding (cur_hw_state) state to Disabled, Blocking or Listening
582 * state (hw_state)
583 */
584 if (cur_hw_state != hw_state) {
585 if (cur_hw_state >= G_MISTP_LEARN_STATE &&
586 hw_state <= G_MISTP_LISTEN_STATE) {
587 ret = bcm_sf2_sw_fast_age_port(ds, port);
588 if (ret) {
589 pr_err("%s: fast-ageing failed\n", __func__);
590 return ret;
591 }
592 }
593 }
594
595 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
596 reg &= ~(G_MISTP_STATE_MASK << G_MISTP_STATE_SHIFT);
597 reg |= hw_state;
598 core_writel(priv, reg, CORE_G_PCTL_PORT(port));
599
600 return 0;
601}
602
603/* Address Resolution Logic routines */
604static int bcm_sf2_arl_op_wait(struct bcm_sf2_priv *priv)
605{
606 unsigned int timeout = 10;
607 u32 reg;
608
609 do {
610 reg = core_readl(priv, CORE_ARLA_RWCTL);
611 if (!(reg & ARL_STRTDN))
612 return 0;
613
614 usleep_range(1000, 2000);
615 } while (timeout--);
616
617 return -ETIMEDOUT;
618}
619
620static int bcm_sf2_arl_rw_op(struct bcm_sf2_priv *priv, unsigned int op)
621{
622 u32 cmd;
623
624 if (op > ARL_RW)
625 return -EINVAL;
626
627 cmd = core_readl(priv, CORE_ARLA_RWCTL);
628 cmd &= ~IVL_SVL_SELECT;
629 cmd |= ARL_STRTDN;
630 if (op)
631 cmd |= ARL_RW;
632 else
633 cmd &= ~ARL_RW;
634 core_writel(priv, cmd, CORE_ARLA_RWCTL);
635
636 return bcm_sf2_arl_op_wait(priv);
637}
638
639static int bcm_sf2_arl_read(struct bcm_sf2_priv *priv, u64 mac,
640 u16 vid, struct bcm_sf2_arl_entry *ent, u8 *idx,
641 bool is_valid)
642{
643 unsigned int i;
644 int ret;
645
646 ret = bcm_sf2_arl_op_wait(priv);
647 if (ret)
648 return ret;
649
650 /* Read the 4 bins */
651 for (i = 0; i < 4; i++) {
652 u64 mac_vid;
653 u32 fwd_entry;
654
655 mac_vid = core_readq(priv, CORE_ARLA_MACVID_ENTRY(i));
656 fwd_entry = core_readl(priv, CORE_ARLA_FWD_ENTRY(i));
657 bcm_sf2_arl_to_entry(ent, mac_vid, fwd_entry);
658
659 if (ent->is_valid && is_valid) {
660 *idx = i;
661 return 0;
662 }
663
664 /* This is the MAC we just deleted */
665 if (!is_valid && (mac_vid & mac))
666 return 0;
667 }
668
669 return -ENOENT;
670}
671
672static int bcm_sf2_arl_op(struct bcm_sf2_priv *priv, int op, int port,
673 const unsigned char *addr, u16 vid, bool is_valid)
674{
675 struct bcm_sf2_arl_entry ent;
676 u32 fwd_entry;
677 u64 mac, mac_vid = 0;
678 u8 idx = 0;
679 int ret;
680
681 /* Convert the array into a 64-bit MAC */
682 mac = bcm_sf2_mac_to_u64(addr);
683
684 /* Perform a read for the given MAC and VID */
685 core_writeq(priv, mac, CORE_ARLA_MAC);
686 core_writel(priv, vid, CORE_ARLA_VID);
687
688 /* Issue a read operation for this MAC */
689 ret = bcm_sf2_arl_rw_op(priv, 1);
690 if (ret)
691 return ret;
692
693 ret = bcm_sf2_arl_read(priv, mac, vid, &ent, &idx, is_valid);
694 /* If this is a read, just finish now */
695 if (op)
696 return ret;
697
698 /* We could not find a matching MAC, so reset to a new entry */
699 if (ret) {
700 fwd_entry = 0;
701 idx = 0;
702 }
703
704 memset(&ent, 0, sizeof(ent));
705 ent.port = port;
706 ent.is_valid = is_valid;
707 ent.vid = vid;
708 ent.is_static = true;
709 memcpy(ent.mac, addr, ETH_ALEN);
710 bcm_sf2_arl_from_entry(&mac_vid, &fwd_entry, &ent);
711
712 core_writeq(priv, mac_vid, CORE_ARLA_MACVID_ENTRY(idx));
713 core_writel(priv, fwd_entry, CORE_ARLA_FWD_ENTRY(idx));
714
715 ret = bcm_sf2_arl_rw_op(priv, 0);
716 if (ret)
717 return ret;
718
719 /* Re-read the entry to check */
720 return bcm_sf2_arl_read(priv, mac, vid, &ent, &idx, is_valid);
721}
722
723static int bcm_sf2_sw_fdb_prepare(struct dsa_switch *ds, int port,
724 const struct switchdev_obj_port_fdb *fdb,
725 struct switchdev_trans *trans)
726{
727 /* We do not need to do anything specific here yet */
728 return 0;
729}
730
731static int bcm_sf2_sw_fdb_add(struct dsa_switch *ds, int port,
732 const struct switchdev_obj_port_fdb *fdb,
733 struct switchdev_trans *trans)
734{
735 struct bcm_sf2_priv *priv = ds_to_priv(ds);
736
737 return bcm_sf2_arl_op(priv, 0, port, fdb->addr, fdb->vid, true);
738}
739
740static int bcm_sf2_sw_fdb_del(struct dsa_switch *ds, int port,
741 const struct switchdev_obj_port_fdb *fdb)
742{
743 struct bcm_sf2_priv *priv = ds_to_priv(ds);
744
745 return bcm_sf2_arl_op(priv, 0, port, fdb->addr, fdb->vid, false);
746}
747
748static int bcm_sf2_arl_search_wait(struct bcm_sf2_priv *priv)
749{
750 unsigned timeout = 1000;
751 u32 reg;
752
753 do {
754 reg = core_readl(priv, CORE_ARLA_SRCH_CTL);
755 if (!(reg & ARLA_SRCH_STDN))
756 return 0;
757
758 if (reg & ARLA_SRCH_VLID)
759 return 0;
760
761 usleep_range(1000, 2000);
762 } while (timeout--);
763
764 return -ETIMEDOUT;
765}
766
767static void bcm_sf2_arl_search_rd(struct bcm_sf2_priv *priv, u8 idx,
768 struct bcm_sf2_arl_entry *ent)
769{
770 u64 mac_vid;
771 u32 fwd_entry;
772
773 mac_vid = core_readq(priv, CORE_ARLA_SRCH_RSLT_MACVID(idx));
774 fwd_entry = core_readl(priv, CORE_ARLA_SRCH_RSLT(idx));
775 bcm_sf2_arl_to_entry(ent, mac_vid, fwd_entry);
776}
777
778static int bcm_sf2_sw_fdb_copy(struct net_device *dev, int port,
779 const struct bcm_sf2_arl_entry *ent,
780 struct switchdev_obj_port_fdb *fdb,
781 int (*cb)(struct switchdev_obj *obj))
782{
783 if (!ent->is_valid)
784 return 0;
785
786 if (port != ent->port)
787 return 0;
788
789 ether_addr_copy(fdb->addr, ent->mac);
790 fdb->vid = ent->vid;
791 fdb->ndm_state = ent->is_static ? NUD_NOARP : NUD_REACHABLE;
792
793 return cb(&fdb->obj);
794}
795
796static int bcm_sf2_sw_fdb_dump(struct dsa_switch *ds, int port,
797 struct switchdev_obj_port_fdb *fdb,
798 int (*cb)(struct switchdev_obj *obj))
799{
800 struct bcm_sf2_priv *priv = ds_to_priv(ds);
801 struct net_device *dev = ds->ports[port];
802 struct bcm_sf2_arl_entry results[2];
803 unsigned int count = 0;
804 int ret;
805
806 /* Start search operation */
807 core_writel(priv, ARLA_SRCH_STDN, CORE_ARLA_SRCH_CTL);
808
809 do {
810 ret = bcm_sf2_arl_search_wait(priv);
811 if (ret)
812 return ret;
813
814 /* Read both entries, then return their values back */
815 bcm_sf2_arl_search_rd(priv, 0, &results[0]);
816 ret = bcm_sf2_sw_fdb_copy(dev, port, &results[0], fdb, cb);
817 if (ret)
818 return ret;
819
820 bcm_sf2_arl_search_rd(priv, 1, &results[1]);
821 ret = bcm_sf2_sw_fdb_copy(dev, port, &results[1], fdb, cb);
822 if (ret)
823 return ret;
824
825 if (!results[0].is_valid && !results[1].is_valid)
826 break;
827
828 } while (count++ < CORE_ARLA_NUM_ENTRIES);
829
830 return 0;
831}
832
833static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
834{
835 struct bcm_sf2_priv *priv = dev_id;
836
837 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
838 ~priv->irq0_mask;
839 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
840
841 return IRQ_HANDLED;
842}
843
844static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
845{
846 struct bcm_sf2_priv *priv = dev_id;
847
848 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
849 ~priv->irq1_mask;
850 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
851
852 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF))
853 priv->port_sts[7].link = 1;
854 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF))
855 priv->port_sts[7].link = 0;
856
857 return IRQ_HANDLED;
858}
859
860static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
861{
862 unsigned int timeout = 1000;
863 u32 reg;
864
865 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
866 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
867 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
868
869 do {
870 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
871 if (!(reg & SOFTWARE_RESET))
872 break;
873
874 usleep_range(1000, 2000);
875 } while (timeout-- > 0);
876
877 if (timeout == 0)
878 return -ETIMEDOUT;
879
880 return 0;
881}
882
883static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
884{
885 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
886 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
887 intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
888 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
889 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
890 intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
891}
892
893static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
894 struct device_node *dn)
895{
896 struct device_node *port;
897 const char *phy_mode_str;
898 int mode;
899 unsigned int port_num;
900 int ret;
901
902 priv->moca_port = -1;
903
904 for_each_available_child_of_node(dn, port) {
905 if (of_property_read_u32(port, "reg", &port_num))
906 continue;
907
908 /* Internal PHYs get assigned a specific 'phy-mode' property
909 * value: "internal" to help flag them before MDIO probing
910 * has completed, since they might be turned off at that
911 * time
912 */
913 mode = of_get_phy_mode(port);
914 if (mode < 0) {
915 ret = of_property_read_string(port, "phy-mode",
916 &phy_mode_str);
917 if (ret < 0)
918 continue;
919
920 if (!strcasecmp(phy_mode_str, "internal"))
921 priv->int_phy_mask |= 1 << port_num;
922 }
923
924 if (mode == PHY_INTERFACE_MODE_MOCA)
925 priv->moca_port = port_num;
926 }
927}
928
929static int bcm_sf2_sw_setup(struct dsa_switch *ds)
930{
931 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
932 struct bcm_sf2_priv *priv = ds_to_priv(ds);
933 struct device_node *dn;
934 void __iomem **base;
935 unsigned int port;
936 unsigned int i;
937 u32 reg, rev;
938 int ret;
939
940 spin_lock_init(&priv->indir_lock);
941 mutex_init(&priv->stats_mutex);
942
943 /* All the interesting properties are at the parent device_node
944 * level
945 */
946 dn = ds->pd->of_node->parent;
947 bcm_sf2_identify_ports(priv, ds->pd->of_node);
948
949 priv->irq0 = irq_of_parse_and_map(dn, 0);
950 priv->irq1 = irq_of_parse_and_map(dn, 1);
951
952 base = &priv->core;
953 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
954 *base = of_iomap(dn, i);
955 if (*base == NULL) {
956 pr_err("unable to find register: %s\n", reg_names[i]);
957 ret = -ENOMEM;
958 goto out_unmap;
959 }
960 base++;
961 }
962
963 ret = bcm_sf2_sw_rst(priv);
964 if (ret) {
965 pr_err("unable to software reset switch: %d\n", ret);
966 goto out_unmap;
967 }
968
969 /* Disable all interrupts and request them */
970 bcm_sf2_intr_disable(priv);
971
972 ret = request_irq(priv->irq0, bcm_sf2_switch_0_isr, 0,
973 "switch_0", priv);
974 if (ret < 0) {
975 pr_err("failed to request switch_0 IRQ\n");
976 goto out_unmap;
977 }
978
979 ret = request_irq(priv->irq1, bcm_sf2_switch_1_isr, 0,
980 "switch_1", priv);
981 if (ret < 0) {
982 pr_err("failed to request switch_1 IRQ\n");
983 goto out_free_irq0;
984 }
985
986 /* Reset the MIB counters */
987 reg = core_readl(priv, CORE_GMNCFGCFG);
988 reg |= RST_MIB_CNT;
989 core_writel(priv, reg, CORE_GMNCFGCFG);
990 reg &= ~RST_MIB_CNT;
991 core_writel(priv, reg, CORE_GMNCFGCFG);
992
993 /* Get the maximum number of ports for this switch */
994 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
995 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
996 priv->hw_params.num_ports = DSA_MAX_PORTS;
997
998 /* Assume a single GPHY setup if we can't read that property */
999 if (of_property_read_u32(dn, "brcm,num-gphy",
1000 &priv->hw_params.num_gphy))
1001 priv->hw_params.num_gphy = 1;
1002
1003 /* Enable all valid ports and disable those unused */
1004 for (port = 0; port < priv->hw_params.num_ports; port++) {
1005 /* IMP port receives special treatment */
1006 if ((1 << port) & ds->phys_port_mask)
1007 bcm_sf2_port_setup(ds, port, NULL);
1008 else if (dsa_is_cpu_port(ds, port))
1009 bcm_sf2_imp_setup(ds, port);
1010 else
1011 bcm_sf2_port_disable(ds, port, NULL);
1012 }
1013
1014 /* Include the pseudo-PHY address and the broadcast PHY address to
1015 * divert reads towards our workaround. This is only required for
1016 * 7445D0, since 7445E0 disconnects the internal switch pseudo-PHY such
1017 * that we can use the regular SWITCH_MDIO master controller instead.
1018 *
1019 * By default, DSA initializes ds->phys_mii_mask to ds->phys_port_mask
1020 * to have a 1:1 mapping between Port address and PHY address in order
1021 * to utilize the slave_mii_bus instance to read from Port PHYs. This is
1022 * not what we want here, so we initialize phys_mii_mask 0 to always
1023 * utilize the "master" MDIO bus backed by the "mdio-unimac" driver.
1024 */
1025 if (of_machine_is_compatible("brcm,bcm7445d0"))
1026 ds->phys_mii_mask |= ((1 << BRCM_PSEUDO_PHY_ADDR) | (1 << 0));
1027 else
1028 ds->phys_mii_mask = 0;
1029
1030 rev = reg_readl(priv, REG_SWITCH_REVISION);
1031 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1032 SWITCH_TOP_REV_MASK;
1033 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1034
1035 rev = reg_readl(priv, REG_PHY_REVISION);
1036 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1037
1038 pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n",
1039 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1040 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1041 priv->core, priv->irq0, priv->irq1);
1042
1043 return 0;
1044
1045out_free_irq0:
1046 free_irq(priv->irq0, priv);
1047out_unmap:
1048 base = &priv->core;
1049 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
1050 if (*base)
1051 iounmap(*base);
1052 base++;
1053 }
1054 return ret;
1055}
1056
1057static int bcm_sf2_sw_set_addr(struct dsa_switch *ds, u8 *addr)
1058{
1059 return 0;
1060}
1061
1062static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
1063{
1064 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1065
1066 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
1067 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
1068 * the REG_PHY_REVISION register layout is.
1069 */
1070
1071 return priv->hw_params.gphy_rev;
1072}
1073
1074static int bcm_sf2_sw_indir_rw(struct dsa_switch *ds, int op, int addr,
1075 int regnum, u16 val)
1076{
1077 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1078 int ret = 0;
1079 u32 reg;
1080
1081 reg = reg_readl(priv, REG_SWITCH_CNTRL);
1082 reg |= MDIO_MASTER_SEL;
1083 reg_writel(priv, reg, REG_SWITCH_CNTRL);
1084
1085 /* Page << 8 | offset */
1086 reg = 0x70;
1087 reg <<= 2;
1088 core_writel(priv, addr, reg);
1089
1090 /* Page << 8 | offset */
1091 reg = 0x80 << 8 | regnum << 1;
1092 reg <<= 2;
1093
1094 if (op)
1095 ret = core_readl(priv, reg);
1096 else
1097 core_writel(priv, val, reg);
1098
1099 reg = reg_readl(priv, REG_SWITCH_CNTRL);
1100 reg &= ~MDIO_MASTER_SEL;
1101 reg_writel(priv, reg, REG_SWITCH_CNTRL);
1102
1103 return ret & 0xffff;
1104}
1105
1106static int bcm_sf2_sw_phy_read(struct dsa_switch *ds, int addr, int regnum)
1107{
1108 /* Intercept reads from the MDIO broadcast address or Broadcom
1109 * pseudo-PHY address
1110 */
1111 switch (addr) {
1112 case 0:
1113 case BRCM_PSEUDO_PHY_ADDR:
1114 return bcm_sf2_sw_indir_rw(ds, 1, addr, regnum, 0);
1115 default:
1116 return 0xffff;
1117 }
1118}
1119
1120static int bcm_sf2_sw_phy_write(struct dsa_switch *ds, int addr, int regnum,
1121 u16 val)
1122{
1123 /* Intercept writes to the MDIO broadcast address or Broadcom
1124 * pseudo-PHY address
1125 */
1126 switch (addr) {
1127 case 0:
1128 case BRCM_PSEUDO_PHY_ADDR:
1129 bcm_sf2_sw_indir_rw(ds, 0, addr, regnum, val);
1130 break;
1131 }
1132
1133 return 0;
1134}
1135
1136static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port,
1137 struct phy_device *phydev)
1138{
1139 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1140 u32 id_mode_dis = 0, port_mode;
1141 const char *str = NULL;
1142 u32 reg;
1143
1144 switch (phydev->interface) {
1145 case PHY_INTERFACE_MODE_RGMII:
1146 str = "RGMII (no delay)";
1147 id_mode_dis = 1;
1148 case PHY_INTERFACE_MODE_RGMII_TXID:
1149 if (!str)
1150 str = "RGMII (TX delay)";
1151 port_mode = EXT_GPHY;
1152 break;
1153 case PHY_INTERFACE_MODE_MII:
1154 str = "MII";
1155 port_mode = EXT_EPHY;
1156 break;
1157 case PHY_INTERFACE_MODE_REVMII:
1158 str = "Reverse MII";
1159 port_mode = EXT_REVMII;
1160 break;
1161 default:
1162 /* All other PHYs: internal and MoCA */
1163 goto force_link;
1164 }
1165
1166 /* If the link is down, just disable the interface to conserve power */
1167 if (!phydev->link) {
1168 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
1169 reg &= ~RGMII_MODE_EN;
1170 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
1171 goto force_link;
1172 }
1173
1174 /* Clear id_mode_dis bit, and the existing port mode, but
1175 * make sure we enable the RGMII block for data to pass
1176 */
1177 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
1178 reg &= ~ID_MODE_DIS;
1179 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
1180 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
1181
1182 reg |= port_mode | RGMII_MODE_EN;
1183 if (id_mode_dis)
1184 reg |= ID_MODE_DIS;
1185
1186 if (phydev->pause) {
1187 if (phydev->asym_pause)
1188 reg |= TX_PAUSE_EN;
1189 reg |= RX_PAUSE_EN;
1190 }
1191
1192 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
1193
1194 pr_info("Port %d configured for %s\n", port, str);
1195
1196force_link:
1197 /* Force link settings detected from the PHY */
1198 reg = SW_OVERRIDE;
1199 switch (phydev->speed) {
1200 case SPEED_1000:
1201 reg |= SPDSTS_1000 << SPEED_SHIFT;
1202 break;
1203 case SPEED_100:
1204 reg |= SPDSTS_100 << SPEED_SHIFT;
1205 break;
1206 }
1207
1208 if (phydev->link)
1209 reg |= LINK_STS;
1210 if (phydev->duplex == DUPLEX_FULL)
1211 reg |= DUPLX_MODE;
1212
1213 core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));
1214}
1215
1216static void bcm_sf2_sw_fixed_link_update(struct dsa_switch *ds, int port,
1217 struct fixed_phy_status *status)
1218{
1219 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1220 u32 duplex, pause;
1221 u32 reg;
1222
1223 duplex = core_readl(priv, CORE_DUPSTS);
1224 pause = core_readl(priv, CORE_PAUSESTS);
1225
1226 status->link = 0;
1227
1228 /* MoCA port is special as we do not get link status from CORE_LNKSTS,
1229 * which means that we need to force the link at the port override
1230 * level to get the data to flow. We do use what the interrupt handler
1231 * did determine before.
1232 *
1233 * For the other ports, we just force the link status, since this is
1234 * a fixed PHY device.
1235 */
1236 if (port == priv->moca_port) {
1237 status->link = priv->port_sts[port].link;
1238 /* For MoCA interfaces, also force a link down notification
1239 * since some version of the user-space daemon (mocad) use
1240 * cmd->autoneg to force the link, which messes up the PHY
1241 * state machine and make it go in PHY_FORCING state instead.
1242 */
1243 if (!status->link)
1244 netif_carrier_off(ds->ports[port]);
1245 status->duplex = 1;
1246 } else {
1247 status->link = 1;
1248 status->duplex = !!(duplex & (1 << port));
1249 }
1250
1251 reg = core_readl(priv, CORE_STS_OVERRIDE_GMIIP_PORT(port));
1252 reg |= SW_OVERRIDE;
1253 if (status->link)
1254 reg |= LINK_STS;
1255 else
1256 reg &= ~LINK_STS;
1257 core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));
1258
1259 if ((pause & (1 << port)) &&
1260 (pause & (1 << (port + PAUSESTS_TX_PAUSE_SHIFT)))) {
1261 status->asym_pause = 1;
1262 status->pause = 1;
1263 }
1264
1265 if (pause & (1 << port))
1266 status->pause = 1;
1267}
1268
1269static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
1270{
1271 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1272 unsigned int port;
1273
1274 bcm_sf2_intr_disable(priv);
1275
1276 /* Disable all ports physically present including the IMP
1277 * port, the other ones have already been disabled during
1278 * bcm_sf2_sw_setup
1279 */
1280 for (port = 0; port < DSA_MAX_PORTS; port++) {
1281 if ((1 << port) & ds->phys_port_mask ||
1282 dsa_is_cpu_port(ds, port))
1283 bcm_sf2_port_disable(ds, port, NULL);
1284 }
1285
1286 return 0;
1287}
1288
1289static int bcm_sf2_sw_resume(struct dsa_switch *ds)
1290{
1291 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1292 unsigned int port;
1293 int ret;
1294
1295 ret = bcm_sf2_sw_rst(priv);
1296 if (ret) {
1297 pr_err("%s: failed to software reset switch\n", __func__);
1298 return ret;
1299 }
1300
1301 if (priv->hw_params.num_gphy == 1)
1302 bcm_sf2_gphy_enable_set(ds, true);
1303
1304 for (port = 0; port < DSA_MAX_PORTS; port++) {
1305 if ((1 << port) & ds->phys_port_mask)
1306 bcm_sf2_port_setup(ds, port, NULL);
1307 else if (dsa_is_cpu_port(ds, port))
1308 bcm_sf2_imp_setup(ds, port);
1309 }
1310
1311 return 0;
1312}
1313
1314static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
1315 struct ethtool_wolinfo *wol)
1316{
1317 struct net_device *p = ds->dst[ds->index].master_netdev;
1318 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1319 struct ethtool_wolinfo pwol;
1320
1321 /* Get the parent device WoL settings */
1322 p->ethtool_ops->get_wol(p, &pwol);
1323
1324 /* Advertise the parent device supported settings */
1325 wol->supported = pwol.supported;
1326 memset(&wol->sopass, 0, sizeof(wol->sopass));
1327
1328 if (pwol.wolopts & WAKE_MAGICSECURE)
1329 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
1330
1331 if (priv->wol_ports_mask & (1 << port))
1332 wol->wolopts = pwol.wolopts;
1333 else
1334 wol->wolopts = 0;
1335}
1336
1337static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
1338 struct ethtool_wolinfo *wol)
1339{
1340 struct net_device *p = ds->dst[ds->index].master_netdev;
1341 struct bcm_sf2_priv *priv = ds_to_priv(ds);
1342 s8 cpu_port = ds->dst[ds->index].cpu_port;
1343 struct ethtool_wolinfo pwol;
1344
1345 p->ethtool_ops->get_wol(p, &pwol);
1346 if (wol->wolopts & ~pwol.supported)
1347 return -EINVAL;
1348
1349 if (wol->wolopts)
1350 priv->wol_ports_mask |= (1 << port);
1351 else
1352 priv->wol_ports_mask &= ~(1 << port);
1353
1354 /* If we have at least one port enabled, make sure the CPU port
1355 * is also enabled. If the CPU port is the last one enabled, we disable
1356 * it since this configuration does not make sense.
1357 */
1358 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
1359 priv->wol_ports_mask |= (1 << cpu_port);
1360 else
1361 priv->wol_ports_mask &= ~(1 << cpu_port);
1362
1363 return p->ethtool_ops->set_wol(p, wol);
1364}
1365
1366static struct dsa_switch_driver bcm_sf2_switch_driver = {
1367 .tag_protocol = DSA_TAG_PROTO_BRCM,
1368 .priv_size = sizeof(struct bcm_sf2_priv),
1369 .probe = bcm_sf2_sw_probe,
1370 .setup = bcm_sf2_sw_setup,
1371 .set_addr = bcm_sf2_sw_set_addr,
1372 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
1373 .phy_read = bcm_sf2_sw_phy_read,
1374 .phy_write = bcm_sf2_sw_phy_write,
1375 .get_strings = bcm_sf2_sw_get_strings,
1376 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats,
1377 .get_sset_count = bcm_sf2_sw_get_sset_count,
1378 .adjust_link = bcm_sf2_sw_adjust_link,
1379 .fixed_link_update = bcm_sf2_sw_fixed_link_update,
1380 .suspend = bcm_sf2_sw_suspend,
1381 .resume = bcm_sf2_sw_resume,
1382 .get_wol = bcm_sf2_sw_get_wol,
1383 .set_wol = bcm_sf2_sw_set_wol,
1384 .port_enable = bcm_sf2_port_setup,
1385 .port_disable = bcm_sf2_port_disable,
1386 .get_eee = bcm_sf2_sw_get_eee,
1387 .set_eee = bcm_sf2_sw_set_eee,
1388 .port_bridge_join = bcm_sf2_sw_br_join,
1389 .port_bridge_leave = bcm_sf2_sw_br_leave,
1390 .port_stp_update = bcm_sf2_sw_br_set_stp_state,
1391 .port_fdb_prepare = bcm_sf2_sw_fdb_prepare,
1392 .port_fdb_add = bcm_sf2_sw_fdb_add,
1393 .port_fdb_del = bcm_sf2_sw_fdb_del,
1394 .port_fdb_dump = bcm_sf2_sw_fdb_dump,
1395};
1396
1397static int __init bcm_sf2_init(void)
1398{
1399 register_switch_driver(&bcm_sf2_switch_driver);
1400
1401 return 0;
1402}
1403module_init(bcm_sf2_init);
1404
1405static void __exit bcm_sf2_exit(void)
1406{
1407 unregister_switch_driver(&bcm_sf2_switch_driver);
1408}
1409module_exit(bcm_sf2_exit);
1410
1411MODULE_AUTHOR("Broadcom Corporation");
1412MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1413MODULE_LICENSE("GPL");
1414MODULE_ALIAS("platform:brcm-sf2");