1/*
  2 * Copyright (c) 2012-2016 VMware, Inc.  All rights reserved.
  3 *
  4 * This program is free software; you can redistribute it and/or
  5 * modify it under the terms of EITHER the GNU General Public License
  6 * version 2 as published by the Free Software Foundation or the BSD
  7 * 2-Clause License. This program is distributed in the hope that it
  8 * will be useful, but WITHOUT ANY WARRANTY; WITHOUT EVEN THE IMPLIED
  9 * WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE.
 10 * See the GNU General Public License version 2 for more details at
 11 * http://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html.
 12 *
 13 * You should have received a copy of the GNU General Public License
 14 * along with this program available in the file COPYING in the main
 15 * directory of this source tree.
 16 *
 17 * The BSD 2-Clause License
 18 *
 19 *     Redistribution and use in source and binary forms, with or
 20 *     without modification, are permitted provided that the following
 21 *     conditions are met:
 22 *
 23 *      - Redistributions of source code must retain the above
 24 *        copyright notice, this list of conditions and the following
 25 *        disclaimer.
 26 *
 27 *      - Redistributions in binary form must reproduce the above
 28 *        copyright notice, this list of conditions and the following
 29 *        disclaimer in the documentation and/or other materials
 30 *        provided with the distribution.
 31 *
 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
 35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
 36 * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
 37 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 39 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
 41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
 43 * OF THE POSSIBILITY OF SUCH DAMAGE.
 44 */
 45
 46#ifndef __PVRDMA_DEV_API_H__
 47#define __PVRDMA_DEV_API_H__
 48
 49#include <linux/types.h>
 50
 51#include "pvrdma_verbs.h"
 52
 53/*
 54 * PVRDMA version macros. Some new features require updates to PVRDMA_VERSION.
 55 * These macros allow us to check for different features if necessary.
 56 */
 57
 58#define PVRDMA_ROCEV1_VERSION		17
 59#define PVRDMA_ROCEV2_VERSION		18
 60#define PVRDMA_PPN64_VERSION		19
 61#define PVRDMA_VERSION			PVRDMA_PPN64_VERSION
 62
 63#define PVRDMA_BOARD_ID			1
 64#define PVRDMA_REV_ID			1
 65
 66/*
 67 * Masks and accessors for page directory, which is a two-level lookup:
 68 * page directory -> page table -> page. Only one directory for now, but we
 69 * could expand that easily. 9 bits for tables, 9 bits for pages, gives one
 70 * gigabyte for memory regions and so forth.
 71 */
 72
 73#define PVRDMA_PDIR_SHIFT		18
 74#define PVRDMA_PTABLE_SHIFT		9
 75#define PVRDMA_PAGE_DIR_DIR(x)		(((x) >> PVRDMA_PDIR_SHIFT) & 0x1)
 76#define PVRDMA_PAGE_DIR_TABLE(x)	(((x) >> PVRDMA_PTABLE_SHIFT) & 0x1ff)
 77#define PVRDMA_PAGE_DIR_PAGE(x)		((x) & 0x1ff)
 78#define PVRDMA_PAGE_DIR_MAX_PAGES	(1 * 512 * 512)
 79#define PVRDMA_MAX_FAST_REG_PAGES	128
 80
 81/*
 82 * Max MSI-X vectors.
 83 */
 84
 85#define PVRDMA_MAX_INTERRUPTS	3
 86
 87/* Register offsets within PCI resource on BAR1. */
 88#define PVRDMA_REG_VERSION	0x00	/* R: Version of device. */
 89#define PVRDMA_REG_DSRLOW	0x04	/* W: Device shared region low PA. */
 90#define PVRDMA_REG_DSRHIGH	0x08	/* W: Device shared region high PA. */
 91#define PVRDMA_REG_CTL		0x0c	/* W: PVRDMA_DEVICE_CTL */
 92#define PVRDMA_REG_REQUEST	0x10	/* W: Indicate device request. */
 93#define PVRDMA_REG_ERR		0x14	/* R: Device error. */
 94#define PVRDMA_REG_ICR		0x18	/* R: Interrupt cause. */
 95#define PVRDMA_REG_IMR		0x1c	/* R/W: Interrupt mask. */
 96#define PVRDMA_REG_MACL		0x20	/* R/W: MAC address low. */
 97#define PVRDMA_REG_MACH		0x24	/* R/W: MAC address high. */
 98
 99/* Object flags. */
100#define PVRDMA_CQ_FLAG_ARMED_SOL	BIT(0)	/* Armed for solicited-only. */
101#define PVRDMA_CQ_FLAG_ARMED		BIT(1)	/* Armed. */
102#define PVRDMA_MR_FLAG_DMA		BIT(0)	/* DMA region. */
103#define PVRDMA_MR_FLAG_FRMR		BIT(1)	/* Fast reg memory region. */
104
105/*
106 * Atomic operation capability (masked versions are extended atomic
107 * operations.
108 */
109
110#define PVRDMA_ATOMIC_OP_COMP_SWAP	BIT(0)	/* Compare and swap. */
111#define PVRDMA_ATOMIC_OP_FETCH_ADD	BIT(1)	/* Fetch and add. */
112#define PVRDMA_ATOMIC_OP_MASK_COMP_SWAP	BIT(2)	/* Masked compare and swap. */
113#define PVRDMA_ATOMIC_OP_MASK_FETCH_ADD	BIT(3)	/* Masked fetch and add. */
114
115/*
116 * Base Memory Management Extension flags to support Fast Reg Memory Regions
117 * and Fast Reg Work Requests. Each flag represents a verb operation and we
118 * must support all of them to qualify for the BMME device cap.
119 */
120
121#define PVRDMA_BMME_FLAG_LOCAL_INV	BIT(0)	/* Local Invalidate. */
122#define PVRDMA_BMME_FLAG_REMOTE_INV	BIT(1)	/* Remote Invalidate. */
123#define PVRDMA_BMME_FLAG_FAST_REG_WR	BIT(2)	/* Fast Reg Work Request. */
124
125/*
126 * GID types. The interpretation of the gid_types bit field in the device
127 * capabilities will depend on the device mode. For now, the device only
128 * supports RoCE as mode, so only the different GID types for RoCE are
129 * defined.
130 */
131
132#define PVRDMA_GID_TYPE_FLAG_ROCE_V1	BIT(0)
133#define PVRDMA_GID_TYPE_FLAG_ROCE_V2	BIT(1)
134
135/*
136 * Version checks. This checks whether each version supports specific
137 * capabilities from the device.
138 */
139
140#define PVRDMA_IS_VERSION17(_dev)					\
141	(_dev->dsr_version == PVRDMA_ROCEV1_VERSION &&			\
142	 _dev->dsr->caps.gid_types == PVRDMA_GID_TYPE_FLAG_ROCE_V1)
143
144#define PVRDMA_IS_VERSION18(_dev)					\
145	(_dev->dsr_version >= PVRDMA_ROCEV2_VERSION &&			\
146	 (_dev->dsr->caps.gid_types == PVRDMA_GID_TYPE_FLAG_ROCE_V1 ||  \
147	  _dev->dsr->caps.gid_types == PVRDMA_GID_TYPE_FLAG_ROCE_V2))	\
148
149#define PVRDMA_SUPPORTED(_dev)						\
150	((_dev->dsr->caps.mode == PVRDMA_DEVICE_MODE_ROCE) &&		\
151	 (PVRDMA_IS_VERSION17(_dev) || PVRDMA_IS_VERSION18(_dev)))
152
153/*
154 * Get capability values based on device version.
155 */
156
157#define PVRDMA_GET_CAP(_dev, _old_val, _val) \
158	((PVRDMA_IS_VERSION18(_dev)) ? _val : _old_val)
159
160enum pvrdma_pci_resource {
161	PVRDMA_PCI_RESOURCE_MSIX,	/* BAR0: MSI-X, MMIO. */
162	PVRDMA_PCI_RESOURCE_REG,	/* BAR1: Registers, MMIO. */
163	PVRDMA_PCI_RESOURCE_UAR,	/* BAR2: UAR pages, MMIO, 64-bit. */
164	PVRDMA_PCI_RESOURCE_LAST,	/* Last. */
165};
166
167enum pvrdma_device_ctl {
168	PVRDMA_DEVICE_CTL_ACTIVATE,	/* Activate device. */
169	PVRDMA_DEVICE_CTL_UNQUIESCE,	/* Unquiesce device. */
170	PVRDMA_DEVICE_CTL_RESET,	/* Reset device. */
171};
172
173enum pvrdma_intr_vector {
174	PVRDMA_INTR_VECTOR_RESPONSE,	/* Command response. */
175	PVRDMA_INTR_VECTOR_ASYNC,	/* Async events. */
176	PVRDMA_INTR_VECTOR_CQ,		/* CQ notification. */
177	/* Additional CQ notification vectors. */
178};
179
180enum pvrdma_intr_cause {
181	PVRDMA_INTR_CAUSE_RESPONSE	= (1 << PVRDMA_INTR_VECTOR_RESPONSE),
182	PVRDMA_INTR_CAUSE_ASYNC		= (1 << PVRDMA_INTR_VECTOR_ASYNC),
183	PVRDMA_INTR_CAUSE_CQ		= (1 << PVRDMA_INTR_VECTOR_CQ),
184};
185
186enum pvrdma_gos_bits {
187	PVRDMA_GOS_BITS_UNK,		/* Unknown. */
188	PVRDMA_GOS_BITS_32,		/* 32-bit. */
189	PVRDMA_GOS_BITS_64,		/* 64-bit. */
190};
191
192enum pvrdma_gos_type {
193	PVRDMA_GOS_TYPE_UNK,		/* Unknown. */
194	PVRDMA_GOS_TYPE_LINUX,		/* Linux. */
195};
196
197enum pvrdma_device_mode {
198	PVRDMA_DEVICE_MODE_ROCE,	/* RoCE. */
199	PVRDMA_DEVICE_MODE_IWARP,	/* iWarp. */
200	PVRDMA_DEVICE_MODE_IB,		/* InfiniBand. */
201};
202
203struct pvrdma_gos_info {
204	u32 gos_bits:2;			/* W: PVRDMA_GOS_BITS_ */
205	u32 gos_type:4;			/* W: PVRDMA_GOS_TYPE_ */
206	u32 gos_ver:16;			/* W: Guest OS version. */
207	u32 gos_misc:10;		/* W: Other. */
208	u32 pad;			/* Pad to 8-byte alignment. */
209};
210
211struct pvrdma_device_caps {
212	u64 fw_ver;				/* R: Query device. */
213	__be64 node_guid;
214	__be64 sys_image_guid;
215	u64 max_mr_size;
216	u64 page_size_cap;
217	u64 atomic_arg_sizes;			/* EX verbs. */
218	u32 ex_comp_mask;			/* EX verbs. */
219	u32 device_cap_flags2;			/* EX verbs. */
220	u32 max_fa_bit_boundary;		/* EX verbs. */
221	u32 log_max_atomic_inline_arg;		/* EX verbs. */
222	u32 vendor_id;
223	u32 vendor_part_id;
224	u32 hw_ver;
225	u32 max_qp;
226	u32 max_qp_wr;
227	u32 device_cap_flags;
228	u32 max_sge;
229	u32 max_sge_rd;
230	u32 max_cq;
231	u32 max_cqe;
232	u32 max_mr;
233	u32 max_pd;
234	u32 max_qp_rd_atom;
235	u32 max_ee_rd_atom;
236	u32 max_res_rd_atom;
237	u32 max_qp_init_rd_atom;
238	u32 max_ee_init_rd_atom;
239	u32 max_ee;
240	u32 max_rdd;
241	u32 max_mw;
242	u32 max_raw_ipv6_qp;
243	u32 max_raw_ethy_qp;
244	u32 max_mcast_grp;
245	u32 max_mcast_qp_attach;
246	u32 max_total_mcast_qp_attach;
247	u32 max_ah;
248	u32 max_fmr;
249	u32 max_map_per_fmr;
250	u32 max_srq;
251	u32 max_srq_wr;
252	u32 max_srq_sge;
253	u32 max_uar;
254	u32 gid_tbl_len;
255	u16 max_pkeys;
256	u8  local_ca_ack_delay;
257	u8  phys_port_cnt;
258	u8  mode;				/* PVRDMA_DEVICE_MODE_ */
259	u8  atomic_ops;				/* PVRDMA_ATOMIC_OP_* bits */
260	u8  bmme_flags;				/* FRWR Mem Mgmt Extensions */
261	u8  gid_types;				/* PVRDMA_GID_TYPE_FLAG_ */
262	u32 max_fast_reg_page_list_len;
263};
264
265struct pvrdma_ring_page_info {
266	u32 num_pages;				/* Num pages incl. header. */
267	u32 reserved;				/* Reserved. */
268	u64 pdir_dma;				/* Page directory PA. */
269};
270
271#pragma pack(push, 1)
272
273struct pvrdma_device_shared_region {
274	u32 driver_version;			/* W: Driver version. */
275	u32 pad;				/* Pad to 8-byte align. */
276	struct pvrdma_gos_info gos_info;	/* W: Guest OS information. */
277	u64 cmd_slot_dma;			/* W: Command slot address. */
278	u64 resp_slot_dma;			/* W: Response slot address. */
279	struct pvrdma_ring_page_info async_ring_pages;
280						/* W: Async ring page info. */
281	struct pvrdma_ring_page_info cq_ring_pages;
282						/* W: CQ ring page info. */
283	union {
284		u32 uar_pfn;			/* W: UAR pageframe. */
285		u64 uar_pfn64;			/* W: 64-bit UAR page frame. */
286	};
287	struct pvrdma_device_caps caps;		/* R: Device capabilities. */
288};
289
290#pragma pack(pop)
291
292/* Event types. Currently a 1:1 mapping with enum ib_event. */
293enum pvrdma_eqe_type {
294	PVRDMA_EVENT_CQ_ERR,
295	PVRDMA_EVENT_QP_FATAL,
296	PVRDMA_EVENT_QP_REQ_ERR,
297	PVRDMA_EVENT_QP_ACCESS_ERR,
298	PVRDMA_EVENT_COMM_EST,
299	PVRDMA_EVENT_SQ_DRAINED,
300	PVRDMA_EVENT_PATH_MIG,
301	PVRDMA_EVENT_PATH_MIG_ERR,
302	PVRDMA_EVENT_DEVICE_FATAL,
303	PVRDMA_EVENT_PORT_ACTIVE,
304	PVRDMA_EVENT_PORT_ERR,
305	PVRDMA_EVENT_LID_CHANGE,
306	PVRDMA_EVENT_PKEY_CHANGE,
307	PVRDMA_EVENT_SM_CHANGE,
308	PVRDMA_EVENT_SRQ_ERR,
309	PVRDMA_EVENT_SRQ_LIMIT_REACHED,
310	PVRDMA_EVENT_QP_LAST_WQE_REACHED,
311	PVRDMA_EVENT_CLIENT_REREGISTER,
312	PVRDMA_EVENT_GID_CHANGE,
313};
314
315/* Event queue element. */
316struct pvrdma_eqe {
317	u32 type;	/* Event type. */
318	u32 info;	/* Handle, other. */
319};
320
321/* CQ notification queue element. */
322struct pvrdma_cqne {
323	u32 info;	/* Handle */
324};
325
326enum {
327	PVRDMA_CMD_FIRST,
328	PVRDMA_CMD_QUERY_PORT = PVRDMA_CMD_FIRST,
329	PVRDMA_CMD_QUERY_PKEY,
330	PVRDMA_CMD_CREATE_PD,
331	PVRDMA_CMD_DESTROY_PD,
332	PVRDMA_CMD_CREATE_MR,
333	PVRDMA_CMD_DESTROY_MR,
334	PVRDMA_CMD_CREATE_CQ,
335	PVRDMA_CMD_RESIZE_CQ,
336	PVRDMA_CMD_DESTROY_CQ,
337	PVRDMA_CMD_CREATE_QP,
338	PVRDMA_CMD_MODIFY_QP,
339	PVRDMA_CMD_QUERY_QP,
340	PVRDMA_CMD_DESTROY_QP,
341	PVRDMA_CMD_CREATE_UC,
342	PVRDMA_CMD_DESTROY_UC,
343	PVRDMA_CMD_CREATE_BIND,
344	PVRDMA_CMD_DESTROY_BIND,
345	PVRDMA_CMD_CREATE_SRQ,
346	PVRDMA_CMD_MODIFY_SRQ,
347	PVRDMA_CMD_QUERY_SRQ,
348	PVRDMA_CMD_DESTROY_SRQ,
349	PVRDMA_CMD_MAX,
350};
351
352enum {
353	PVRDMA_CMD_FIRST_RESP = (1 << 31),
354	PVRDMA_CMD_QUERY_PORT_RESP = PVRDMA_CMD_FIRST_RESP,
355	PVRDMA_CMD_QUERY_PKEY_RESP,
356	PVRDMA_CMD_CREATE_PD_RESP,
357	PVRDMA_CMD_DESTROY_PD_RESP_NOOP,
358	PVRDMA_CMD_CREATE_MR_RESP,
359	PVRDMA_CMD_DESTROY_MR_RESP_NOOP,
360	PVRDMA_CMD_CREATE_CQ_RESP,
361	PVRDMA_CMD_RESIZE_CQ_RESP,
362	PVRDMA_CMD_DESTROY_CQ_RESP_NOOP,
363	PVRDMA_CMD_CREATE_QP_RESP,
364	PVRDMA_CMD_MODIFY_QP_RESP,
365	PVRDMA_CMD_QUERY_QP_RESP,
366	PVRDMA_CMD_DESTROY_QP_RESP,
367	PVRDMA_CMD_CREATE_UC_RESP,
368	PVRDMA_CMD_DESTROY_UC_RESP_NOOP,
369	PVRDMA_CMD_CREATE_BIND_RESP_NOOP,
370	PVRDMA_CMD_DESTROY_BIND_RESP_NOOP,
371	PVRDMA_CMD_CREATE_SRQ_RESP,
372	PVRDMA_CMD_MODIFY_SRQ_RESP,
373	PVRDMA_CMD_QUERY_SRQ_RESP,
374	PVRDMA_CMD_DESTROY_SRQ_RESP,
375	PVRDMA_CMD_MAX_RESP,
376};
377
378struct pvrdma_cmd_hdr {
379	u64 response;		/* Key for response lookup. */
380	u32 cmd;		/* PVRDMA_CMD_ */
381	u32 reserved;		/* Reserved. */
382};
383
384struct pvrdma_cmd_resp_hdr {
385	u64 response;		/* From cmd hdr. */
386	u32 ack;		/* PVRDMA_CMD_XXX_RESP */
387	u8 err;			/* Error. */
388	u8 reserved[3];		/* Reserved. */
389};
390
391struct pvrdma_cmd_query_port {
392	struct pvrdma_cmd_hdr hdr;
393	u8 port_num;
394	u8 reserved[7];
395};
396
397struct pvrdma_cmd_query_port_resp {
398	struct pvrdma_cmd_resp_hdr hdr;
399	struct pvrdma_port_attr attrs;
400};
401
402struct pvrdma_cmd_query_pkey {
403	struct pvrdma_cmd_hdr hdr;
404	u8 port_num;
405	u8 index;
406	u8 reserved[6];
407};
408
409struct pvrdma_cmd_query_pkey_resp {
410	struct pvrdma_cmd_resp_hdr hdr;
411	u16 pkey;
412	u8 reserved[6];
413};
414
415struct pvrdma_cmd_create_uc {
416	struct pvrdma_cmd_hdr hdr;
417	union {
418		u32 pfn; /* UAR page frame number */
419		u64 pfn64; /* 64-bit UAR page frame number */
420	};
421};
422
423struct pvrdma_cmd_create_uc_resp {
424	struct pvrdma_cmd_resp_hdr hdr;
425	u32 ctx_handle;
426	u8 reserved[4];
427};
428
429struct pvrdma_cmd_destroy_uc {
430	struct pvrdma_cmd_hdr hdr;
431	u32 ctx_handle;
432	u8 reserved[4];
433};
434
435struct pvrdma_cmd_create_pd {
436	struct pvrdma_cmd_hdr hdr;
437	u32 ctx_handle;
438	u8 reserved[4];
439};
440
441struct pvrdma_cmd_create_pd_resp {
442	struct pvrdma_cmd_resp_hdr hdr;
443	u32 pd_handle;
444	u8 reserved[4];
445};
446
447struct pvrdma_cmd_destroy_pd {
448	struct pvrdma_cmd_hdr hdr;
449	u32 pd_handle;
450	u8 reserved[4];
451};
452
453struct pvrdma_cmd_create_mr {
454	struct pvrdma_cmd_hdr hdr;
455	u64 start;
456	u64 length;
457	u64 pdir_dma;
458	u32 pd_handle;
459	u32 access_flags;
460	u32 flags;
461	u32 nchunks;
462};
463
464struct pvrdma_cmd_create_mr_resp {
465	struct pvrdma_cmd_resp_hdr hdr;
466	u32 mr_handle;
467	u32 lkey;
468	u32 rkey;
469	u8 reserved[4];
470};
471
472struct pvrdma_cmd_destroy_mr {
473	struct pvrdma_cmd_hdr hdr;
474	u32 mr_handle;
475	u8 reserved[4];
476};
477
478struct pvrdma_cmd_create_cq {
479	struct pvrdma_cmd_hdr hdr;
480	u64 pdir_dma;
481	u32 ctx_handle;
482	u32 cqe;
483	u32 nchunks;
484	u8 reserved[4];
485};
486
487struct pvrdma_cmd_create_cq_resp {
488	struct pvrdma_cmd_resp_hdr hdr;
489	u32 cq_handle;
490	u32 cqe;
491};
492
493struct pvrdma_cmd_resize_cq {
494	struct pvrdma_cmd_hdr hdr;
495	u32 cq_handle;
496	u32 cqe;
497};
498
499struct pvrdma_cmd_resize_cq_resp {
500	struct pvrdma_cmd_resp_hdr hdr;
501	u32 cqe;
502	u8 reserved[4];
503};
504
505struct pvrdma_cmd_destroy_cq {
506	struct pvrdma_cmd_hdr hdr;
507	u32 cq_handle;
508	u8 reserved[4];
509};
510
511struct pvrdma_cmd_create_srq {
512	struct pvrdma_cmd_hdr hdr;
513	u64 pdir_dma;
514	u32 pd_handle;
515	u32 nchunks;
516	struct pvrdma_srq_attr attrs;
517	u8 srq_type;
518	u8 reserved[7];
519};
520
521struct pvrdma_cmd_create_srq_resp {
522	struct pvrdma_cmd_resp_hdr hdr;
523	u32 srqn;
524	u8 reserved[4];
525};
526
527struct pvrdma_cmd_modify_srq {
528	struct pvrdma_cmd_hdr hdr;
529	u32 srq_handle;
530	u32 attr_mask;
531	struct pvrdma_srq_attr attrs;
532};
533
534struct pvrdma_cmd_query_srq {
535	struct pvrdma_cmd_hdr hdr;
536	u32 srq_handle;
537	u8 reserved[4];
538};
539
540struct pvrdma_cmd_query_srq_resp {
541	struct pvrdma_cmd_resp_hdr hdr;
542	struct pvrdma_srq_attr attrs;
543};
544
545struct pvrdma_cmd_destroy_srq {
546	struct pvrdma_cmd_hdr hdr;
547	u32 srq_handle;
548	u8 reserved[4];
549};
550
551struct pvrdma_cmd_create_qp {
552	struct pvrdma_cmd_hdr hdr;
553	u64 pdir_dma;
554	u32 pd_handle;
555	u32 send_cq_handle;
556	u32 recv_cq_handle;
557	u32 srq_handle;
558	u32 max_send_wr;
559	u32 max_recv_wr;
560	u32 max_send_sge;
561	u32 max_recv_sge;
562	u32 max_inline_data;
563	u32 lkey;
564	u32 access_flags;
565	u16 total_chunks;
566	u16 send_chunks;
567	u16 max_atomic_arg;
568	u8 sq_sig_all;
569	u8 qp_type;
570	u8 is_srq;
571	u8 reserved[3];
572};
573
574struct pvrdma_cmd_create_qp_resp {
575	struct pvrdma_cmd_resp_hdr hdr;
576	u32 qpn;
577	u32 max_send_wr;
578	u32 max_recv_wr;
579	u32 max_send_sge;
580	u32 max_recv_sge;
581	u32 max_inline_data;
582};
583
584struct pvrdma_cmd_modify_qp {
585	struct pvrdma_cmd_hdr hdr;
586	u32 qp_handle;
587	u32 attr_mask;
588	struct pvrdma_qp_attr attrs;
589};
590
591struct pvrdma_cmd_query_qp {
592	struct pvrdma_cmd_hdr hdr;
593	u32 qp_handle;
594	u32 attr_mask;
595};
596
597struct pvrdma_cmd_query_qp_resp {
598	struct pvrdma_cmd_resp_hdr hdr;
599	struct pvrdma_qp_attr attrs;
600};
601
602struct pvrdma_cmd_destroy_qp {
603	struct pvrdma_cmd_hdr hdr;
604	u32 qp_handle;
605	u8 reserved[4];
606};
607
608struct pvrdma_cmd_destroy_qp_resp {
609	struct pvrdma_cmd_resp_hdr hdr;
610	u32 events_reported;
611	u8 reserved[4];
612};
613
614struct pvrdma_cmd_create_bind {
615	struct pvrdma_cmd_hdr hdr;
616	u32 mtu;
617	u32 vlan;
618	u32 index;
619	u8 new_gid[16];
620	u8 gid_type;
621	u8 reserved[3];
622};
623
624struct pvrdma_cmd_destroy_bind {
625	struct pvrdma_cmd_hdr hdr;
626	u32 index;
627	u8 dest_gid[16];
628	u8 reserved[4];
629};
630
631union pvrdma_cmd_req {
632	struct pvrdma_cmd_hdr hdr;
633	struct pvrdma_cmd_query_port query_port;
634	struct pvrdma_cmd_query_pkey query_pkey;
635	struct pvrdma_cmd_create_uc create_uc;
636	struct pvrdma_cmd_destroy_uc destroy_uc;
637	struct pvrdma_cmd_create_pd create_pd;
638	struct pvrdma_cmd_destroy_pd destroy_pd;
639	struct pvrdma_cmd_create_mr create_mr;
640	struct pvrdma_cmd_destroy_mr destroy_mr;
641	struct pvrdma_cmd_create_cq create_cq;
642	struct pvrdma_cmd_resize_cq resize_cq;
643	struct pvrdma_cmd_destroy_cq destroy_cq;
644	struct pvrdma_cmd_create_qp create_qp;
645	struct pvrdma_cmd_modify_qp modify_qp;
646	struct pvrdma_cmd_query_qp query_qp;
647	struct pvrdma_cmd_destroy_qp destroy_qp;
648	struct pvrdma_cmd_create_bind create_bind;
649	struct pvrdma_cmd_destroy_bind destroy_bind;
650	struct pvrdma_cmd_create_srq create_srq;
651	struct pvrdma_cmd_modify_srq modify_srq;
652	struct pvrdma_cmd_query_srq query_srq;
653	struct pvrdma_cmd_destroy_srq destroy_srq;
654};
655
656union pvrdma_cmd_resp {
657	struct pvrdma_cmd_resp_hdr hdr;
658	struct pvrdma_cmd_query_port_resp query_port_resp;
659	struct pvrdma_cmd_query_pkey_resp query_pkey_resp;
660	struct pvrdma_cmd_create_uc_resp create_uc_resp;
661	struct pvrdma_cmd_create_pd_resp create_pd_resp;
662	struct pvrdma_cmd_create_mr_resp create_mr_resp;
663	struct pvrdma_cmd_create_cq_resp create_cq_resp;
664	struct pvrdma_cmd_resize_cq_resp resize_cq_resp;
665	struct pvrdma_cmd_create_qp_resp create_qp_resp;
666	struct pvrdma_cmd_query_qp_resp query_qp_resp;
667	struct pvrdma_cmd_destroy_qp_resp destroy_qp_resp;
668	struct pvrdma_cmd_create_srq_resp create_srq_resp;
669	struct pvrdma_cmd_query_srq_resp query_srq_resp;
670};
671
672#endif /* __PVRDMA_DEV_API_H__ */