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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * pata-legacy.c - Legacy port PATA/SATA controller driver.
4 * Copyright 2005/2006 Red Hat, all rights reserved.
5 *
6 * An ATA driver for the legacy ATA ports.
7 *
8 * Data Sources:
9 * Opti 82C465/82C611 support: Data sheets at opti-inc.com
10 * HT6560 series:
11 * Promise 20230/20620:
12 * http://www.ryston.cz/petr/vlb/pdc20230b.html
13 * http://www.ryston.cz/petr/vlb/pdc20230c.html
14 * http://www.ryston.cz/petr/vlb/pdc20630.html
15 * QDI65x0:
16 * http://www.ryston.cz/petr/vlb/qd6500.html
17 * http://www.ryston.cz/petr/vlb/qd6580.html
18 *
19 * QDI65x0 probe code based on drivers/ide/legacy/qd65xx.c
20 * Rewritten from the work of Colten Edwards <pje120@cs.usask.ca> by
21 * Samuel Thibault <samuel.thibault@ens-lyon.org>
22 *
23 * Unsupported but docs exist:
24 * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220
25 *
26 * This driver handles legacy (that is "ISA/VLB side") IDE ports found
27 * on PC class systems. There are three hybrid devices that are exceptions
28 * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and
29 * the MPIIX where the tuning is PCI side but the IDE is "ISA side".
30 *
31 * Specific support is included for the ht6560a/ht6560b/opti82c611a/
32 * opti82c465mv/promise 20230c/20630/qdi65x0/winbond83759A
33 *
34 * Support for the Winbond 83759A when operating in advanced mode.
35 * Multichip mode is not currently supported.
36 *
37 * Use the autospeed and pio_mask options with:
38 * Appian ADI/2 aka CLPD7220 or AIC25VL01.
39 * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with
40 * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759,
41 * Winbond W83759A, Promise PDC20230-B
42 *
43 * For now use autospeed and pio_mask as above with the W83759A. This may
44 * change.
45 */
46
47#include <linux/async.h>
48#include <linux/kernel.h>
49#include <linux/module.h>
50#include <linux/pci.h>
51#include <linux/init.h>
52#include <linux/blkdev.h>
53#include <linux/delay.h>
54#include <scsi/scsi_host.h>
55#include <linux/ata.h>
56#include <linux/libata.h>
57#include <linux/platform_device.h>
58
59#define DRV_NAME "pata_legacy"
60#define DRV_VERSION "0.6.5"
61
62#define NR_HOST 6
63
64static int all;
65module_param(all, int, 0444);
66MODULE_PARM_DESC(all, "Grab all legacy port devices, even if PCI(0=off, 1=on)");
67
68enum controller {
69 BIOS = 0,
70 SNOOP = 1,
71 PDC20230 = 2,
72 HT6560A = 3,
73 HT6560B = 4,
74 OPTI611A = 5,
75 OPTI46X = 6,
76 QDI6500 = 7,
77 QDI6580 = 8,
78 QDI6580DP = 9, /* Dual channel mode is different */
79 W83759A = 10,
80
81 UNKNOWN = -1
82};
83
84struct legacy_data {
85 unsigned long timing;
86 u8 clock[2];
87 u8 last;
88 int fast;
89 enum controller type;
90 struct platform_device *platform_dev;
91};
92
93struct legacy_probe {
94 unsigned char *name;
95 unsigned long port;
96 unsigned int irq;
97 unsigned int slot;
98 enum controller type;
99 unsigned long private;
100};
101
102struct legacy_controller {
103 const char *name;
104 struct ata_port_operations *ops;
105 unsigned int pio_mask;
106 unsigned int flags;
107 unsigned int pflags;
108 int (*setup)(struct platform_device *, struct legacy_probe *probe,
109 struct legacy_data *data);
110};
111
112static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 };
113
114static struct legacy_probe probe_list[NR_HOST];
115static struct legacy_data legacy_data[NR_HOST];
116static struct ata_host *legacy_host[NR_HOST];
117static int nr_legacy_host;
118
119
120static int probe_all; /* Set to check all ISA port ranges */
121static int ht6560a; /* HT 6560A on primary 1, second 2, both 3 */
122static int ht6560b; /* HT 6560A on primary 1, second 2, both 3 */
123static int opti82c611a; /* Opti82c611A on primary 1, sec 2, both 3 */
124static int opti82c46x; /* Opti 82c465MV present(pri/sec autodetect) */
125static int autospeed; /* Chip present which snoops speed changes */
126static int pio_mask = ATA_PIO4; /* PIO range for autospeed devices */
127static int iordy_mask = 0xFFFFFFFF; /* Use iordy if available */
128
129/* Set to probe QDI controllers */
130#ifdef CONFIG_PATA_QDI_MODULE
131static int qdi = 1;
132#else
133static int qdi;
134#endif
135
136#ifdef CONFIG_PATA_WINBOND_VLB_MODULE
137static int winbond = 1; /* Set to probe Winbond controllers,
138 give I/O port if non standard */
139#else
140static int winbond; /* Set to probe Winbond controllers,
141 give I/O port if non standard */
142#endif
143
144/**
145 * legacy_probe_add - Add interface to probe list
146 * @port: Controller port
147 * @irq: IRQ number
148 * @type: Controller type
149 * @private: Controller specific info
150 *
151 * Add an entry into the probe list for ATA controllers. This is used
152 * to add the default ISA slots and then to build up the table
153 * further according to other ISA/VLB/Weird device scans
154 *
155 * An I/O port list is used to keep ordering stable and sane, as we
156 * don't have any good way to talk about ordering otherwise
157 */
158
159static int legacy_probe_add(unsigned long port, unsigned int irq,
160 enum controller type, unsigned long private)
161{
162 struct legacy_probe *lp = &probe_list[0];
163 int i;
164 struct legacy_probe *free = NULL;
165
166 for (i = 0; i < NR_HOST; i++) {
167 if (lp->port == 0 && free == NULL)
168 free = lp;
169 /* Matching port, or the correct slot for ordering */
170 if (lp->port == port || legacy_port[i] == port) {
171 free = lp;
172 break;
173 }
174 lp++;
175 }
176 if (free == NULL) {
177 printk(KERN_ERR "pata_legacy: Too many interfaces.\n");
178 return -1;
179 }
180 /* Fill in the entry for later probing */
181 free->port = port;
182 free->irq = irq;
183 free->type = type;
184 free->private = private;
185 return 0;
186}
187
188
189/**
190 * legacy_set_mode - mode setting
191 * @link: IDE link
192 * @unused: Device that failed when error is returned
193 *
194 * Use a non standard set_mode function. We don't want to be tuned.
195 *
196 * The BIOS configured everything. Our job is not to fiddle. Just use
197 * whatever PIO the hardware is using and leave it at that. When we
198 * get some kind of nice user driven API for control then we can
199 * expand on this as per hdparm in the base kernel.
200 */
201
202static int legacy_set_mode(struct ata_link *link, struct ata_device **unused)
203{
204 struct ata_device *dev;
205
206 ata_for_each_dev(dev, link, ENABLED) {
207 ata_dev_info(dev, "configured for PIO\n");
208 dev->pio_mode = XFER_PIO_0;
209 dev->xfer_mode = XFER_PIO_0;
210 dev->xfer_shift = ATA_SHIFT_PIO;
211 dev->flags |= ATA_DFLAG_PIO;
212 }
213 return 0;
214}
215
216static struct scsi_host_template legacy_sht = {
217 ATA_PIO_SHT(DRV_NAME),
218};
219
220static const struct ata_port_operations legacy_base_port_ops = {
221 .inherits = &ata_sff_port_ops,
222 .cable_detect = ata_cable_40wire,
223};
224
225/*
226 * These ops are used if the user indicates the hardware
227 * snoops the commands to decide on the mode and handles the
228 * mode selection "magically" itself. Several legacy controllers
229 * do this. The mode range can be set if it is not 0x1F by setting
230 * pio_mask as well.
231 */
232
233static struct ata_port_operations simple_port_ops = {
234 .inherits = &legacy_base_port_ops,
235 .sff_data_xfer = ata_sff_data_xfer32,
236};
237
238static struct ata_port_operations legacy_port_ops = {
239 .inherits = &legacy_base_port_ops,
240 .sff_data_xfer = ata_sff_data_xfer32,
241 .set_mode = legacy_set_mode,
242};
243
244/*
245 * Promise 20230C and 20620 support
246 *
247 * This controller supports PIO0 to PIO2. We set PIO timings
248 * conservatively to allow for 50MHz Vesa Local Bus. The 20620 DMA
249 * support is weird being DMA to controller and PIO'd to the host
250 * and not supported.
251 */
252
253static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev)
254{
255 int tries = 5;
256 int pio = adev->pio_mode - XFER_PIO_0;
257 u8 rt;
258 unsigned long flags;
259
260 /* Safe as UP only. Force I/Os to occur together */
261
262 local_irq_save(flags);
263
264 /* Unlock the control interface */
265 do {
266 inb(0x1F5);
267 outb(inb(0x1F2) | 0x80, 0x1F2);
268 inb(0x1F2);
269 inb(0x3F6);
270 inb(0x3F6);
271 inb(0x1F2);
272 inb(0x1F2);
273 }
274 while ((inb(0x1F2) & 0x80) && --tries);
275
276 local_irq_restore(flags);
277
278 outb(inb(0x1F4) & 0x07, 0x1F4);
279
280 rt = inb(0x1F3);
281 rt &= 0x07 << (3 * adev->devno);
282 if (pio)
283 rt |= (1 + 3 * pio) << (3 * adev->devno);
284
285 udelay(100);
286 outb(inb(0x1F2) | 0x01, 0x1F2);
287 udelay(100);
288 inb(0x1F5);
289
290}
291
292static unsigned int pdc_data_xfer_vlb(struct ata_queued_cmd *qc,
293 unsigned char *buf, unsigned int buflen, int rw)
294{
295 struct ata_device *dev = qc->dev;
296 struct ata_port *ap = dev->link->ap;
297 int slop = buflen & 3;
298
299 /* 32bit I/O capable *and* we need to write a whole number of dwords */
300 if (ata_id_has_dword_io(dev->id) && (slop == 0 || slop == 3)
301 && (ap->pflags & ATA_PFLAG_PIO32)) {
302 unsigned long flags;
303
304 local_irq_save(flags);
305
306 /* Perform the 32bit I/O synchronization sequence */
307 ioread8(ap->ioaddr.nsect_addr);
308 ioread8(ap->ioaddr.nsect_addr);
309 ioread8(ap->ioaddr.nsect_addr);
310
311 /* Now the data */
312 if (rw == READ)
313 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
314 else
315 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
316
317 if (unlikely(slop)) {
318 __le32 pad;
319 if (rw == READ) {
320 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
321 memcpy(buf + buflen - slop, &pad, slop);
322 } else {
323 memcpy(&pad, buf + buflen - slop, slop);
324 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
325 }
326 buflen += 4 - slop;
327 }
328 local_irq_restore(flags);
329 } else
330 buflen = ata_sff_data_xfer32(qc, buf, buflen, rw);
331
332 return buflen;
333}
334
335static struct ata_port_operations pdc20230_port_ops = {
336 .inherits = &legacy_base_port_ops,
337 .set_piomode = pdc20230_set_piomode,
338 .sff_data_xfer = pdc_data_xfer_vlb,
339};
340
341/*
342 * Holtek 6560A support
343 *
344 * This controller supports PIO0 to PIO2 (no IORDY even though higher
345 * timings can be loaded).
346 */
347
348static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev)
349{
350 u8 active, recover;
351 struct ata_timing t;
352
353 /* Get the timing data in cycles. For now play safe at 50Mhz */
354 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
355
356 active = clamp_val(t.active, 2, 15);
357 recover = clamp_val(t.recover, 4, 15);
358
359 inb(0x3E6);
360 inb(0x3E6);
361 inb(0x3E6);
362 inb(0x3E6);
363
364 iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
365 ioread8(ap->ioaddr.status_addr);
366}
367
368static struct ata_port_operations ht6560a_port_ops = {
369 .inherits = &legacy_base_port_ops,
370 .set_piomode = ht6560a_set_piomode,
371};
372
373/*
374 * Holtek 6560B support
375 *
376 * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO
377 * setting unless we see an ATAPI device in which case we force it off.
378 *
379 * FIXME: need to implement 2nd channel support.
380 */
381
382static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev)
383{
384 u8 active, recover;
385 struct ata_timing t;
386
387 /* Get the timing data in cycles. For now play safe at 50Mhz */
388 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
389
390 active = clamp_val(t.active, 2, 15);
391 recover = clamp_val(t.recover, 2, 16) & 0x0F;
392
393 inb(0x3E6);
394 inb(0x3E6);
395 inb(0x3E6);
396 inb(0x3E6);
397
398 iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
399
400 if (adev->class != ATA_DEV_ATA) {
401 u8 rconf = inb(0x3E6);
402 if (rconf & 0x24) {
403 rconf &= ~0x24;
404 outb(rconf, 0x3E6);
405 }
406 }
407 ioread8(ap->ioaddr.status_addr);
408}
409
410static struct ata_port_operations ht6560b_port_ops = {
411 .inherits = &legacy_base_port_ops,
412 .set_piomode = ht6560b_set_piomode,
413};
414
415/*
416 * Opti core chipset helpers
417 */
418
419/**
420 * opti_syscfg - read OPTI chipset configuration
421 * @reg: Configuration register to read
422 *
423 * Returns the value of an OPTI system board configuration register.
424 */
425
426static u8 opti_syscfg(u8 reg)
427{
428 unsigned long flags;
429 u8 r;
430
431 /* Uniprocessor chipset and must force cycles adjancent */
432 local_irq_save(flags);
433 outb(reg, 0x22);
434 r = inb(0x24);
435 local_irq_restore(flags);
436 return r;
437}
438
439/*
440 * Opti 82C611A
441 *
442 * This controller supports PIO0 to PIO3.
443 */
444
445static void opti82c611a_set_piomode(struct ata_port *ap,
446 struct ata_device *adev)
447{
448 u8 active, recover, setup;
449 struct ata_timing t;
450 struct ata_device *pair = ata_dev_pair(adev);
451 int clock;
452 int khz[4] = { 50000, 40000, 33000, 25000 };
453 u8 rc;
454
455 /* Enter configuration mode */
456 ioread16(ap->ioaddr.error_addr);
457 ioread16(ap->ioaddr.error_addr);
458 iowrite8(3, ap->ioaddr.nsect_addr);
459
460 /* Read VLB clock strapping */
461 clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03];
462
463 /* Get the timing data in cycles */
464 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
465
466 /* Setup timing is shared */
467 if (pair) {
468 struct ata_timing tp;
469 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
470
471 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
472 }
473
474 active = clamp_val(t.active, 2, 17) - 2;
475 recover = clamp_val(t.recover, 1, 16) - 1;
476 setup = clamp_val(t.setup, 1, 4) - 1;
477
478 /* Select the right timing bank for write timing */
479 rc = ioread8(ap->ioaddr.lbal_addr);
480 rc &= 0x7F;
481 rc |= (adev->devno << 7);
482 iowrite8(rc, ap->ioaddr.lbal_addr);
483
484 /* Write the timings */
485 iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
486
487 /* Select the right bank for read timings, also
488 load the shared timings for address */
489 rc = ioread8(ap->ioaddr.device_addr);
490 rc &= 0xC0;
491 rc |= adev->devno; /* Index select */
492 rc |= (setup << 4) | 0x04;
493 iowrite8(rc, ap->ioaddr.device_addr);
494
495 /* Load the read timings */
496 iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
497
498 /* Ensure the timing register mode is right */
499 rc = ioread8(ap->ioaddr.lbal_addr);
500 rc &= 0x73;
501 rc |= 0x84;
502 iowrite8(rc, ap->ioaddr.lbal_addr);
503
504 /* Exit command mode */
505 iowrite8(0x83, ap->ioaddr.nsect_addr);
506}
507
508
509static struct ata_port_operations opti82c611a_port_ops = {
510 .inherits = &legacy_base_port_ops,
511 .set_piomode = opti82c611a_set_piomode,
512};
513
514/*
515 * Opti 82C465MV
516 *
517 * This controller supports PIO0 to PIO3. Unlike the 611A the MVB
518 * version is dual channel but doesn't have a lot of unique registers.
519 */
520
521static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev)
522{
523 u8 active, recover, setup;
524 struct ata_timing t;
525 struct ata_device *pair = ata_dev_pair(adev);
526 int clock;
527 int khz[4] = { 50000, 40000, 33000, 25000 };
528 u8 rc;
529 u8 sysclk;
530
531 /* Get the clock */
532 sysclk = (opti_syscfg(0xAC) & 0xC0) >> 6; /* BIOS set */
533
534 /* Enter configuration mode */
535 ioread16(ap->ioaddr.error_addr);
536 ioread16(ap->ioaddr.error_addr);
537 iowrite8(3, ap->ioaddr.nsect_addr);
538
539 /* Read VLB clock strapping */
540 clock = 1000000000 / khz[sysclk];
541
542 /* Get the timing data in cycles */
543 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
544
545 /* Setup timing is shared */
546 if (pair) {
547 struct ata_timing tp;
548 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
549
550 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
551 }
552
553 active = clamp_val(t.active, 2, 17) - 2;
554 recover = clamp_val(t.recover, 1, 16) - 1;
555 setup = clamp_val(t.setup, 1, 4) - 1;
556
557 /* Select the right timing bank for write timing */
558 rc = ioread8(ap->ioaddr.lbal_addr);
559 rc &= 0x7F;
560 rc |= (adev->devno << 7);
561 iowrite8(rc, ap->ioaddr.lbal_addr);
562
563 /* Write the timings */
564 iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
565
566 /* Select the right bank for read timings, also
567 load the shared timings for address */
568 rc = ioread8(ap->ioaddr.device_addr);
569 rc &= 0xC0;
570 rc |= adev->devno; /* Index select */
571 rc |= (setup << 4) | 0x04;
572 iowrite8(rc, ap->ioaddr.device_addr);
573
574 /* Load the read timings */
575 iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
576
577 /* Ensure the timing register mode is right */
578 rc = ioread8(ap->ioaddr.lbal_addr);
579 rc &= 0x73;
580 rc |= 0x84;
581 iowrite8(rc, ap->ioaddr.lbal_addr);
582
583 /* Exit command mode */
584 iowrite8(0x83, ap->ioaddr.nsect_addr);
585
586 /* We need to know this for quad device on the MVB */
587 ap->host->private_data = ap;
588}
589
590/**
591 * opt82c465mv_qc_issue - command issue
592 * @qc: command pending
593 *
594 * Called when the libata layer is about to issue a command. We wrap
595 * this interface so that we can load the correct ATA timings. The
596 * MVB has a single set of timing registers and these are shared
597 * across channels. As there are two registers we really ought to
598 * track the last two used values as a sort of register window. For
599 * now we just reload on a channel switch. On the single channel
600 * setup this condition never fires so we do nothing extra.
601 *
602 * FIXME: dual channel needs ->serialize support
603 */
604
605static unsigned int opti82c46x_qc_issue(struct ata_queued_cmd *qc)
606{
607 struct ata_port *ap = qc->ap;
608 struct ata_device *adev = qc->dev;
609
610 /* If timings are set and for the wrong channel (2nd test is
611 due to a libata shortcoming and will eventually go I hope) */
612 if (ap->host->private_data != ap->host
613 && ap->host->private_data != NULL)
614 opti82c46x_set_piomode(ap, adev);
615
616 return ata_sff_qc_issue(qc);
617}
618
619static struct ata_port_operations opti82c46x_port_ops = {
620 .inherits = &legacy_base_port_ops,
621 .set_piomode = opti82c46x_set_piomode,
622 .qc_issue = opti82c46x_qc_issue,
623};
624
625/**
626 * qdi65x0_set_piomode - PIO setup for QDI65x0
627 * @ap: Port
628 * @adev: Device
629 *
630 * In single channel mode the 6580 has one clock per device and we can
631 * avoid the requirement to clock switch. We also have to load the timing
632 * into the right clock according to whether we are master or slave.
633 *
634 * In dual channel mode the 6580 has one clock per channel and we have
635 * to software clockswitch in qc_issue.
636 */
637
638static void qdi65x0_set_piomode(struct ata_port *ap, struct ata_device *adev)
639{
640 struct ata_timing t;
641 struct legacy_data *ld_qdi = ap->host->private_data;
642 int active, recovery;
643 u8 timing;
644
645 /* Get the timing data in cycles */
646 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
647
648 if (ld_qdi->fast) {
649 active = 8 - clamp_val(t.active, 1, 8);
650 recovery = 18 - clamp_val(t.recover, 3, 18);
651 } else {
652 active = 9 - clamp_val(t.active, 2, 9);
653 recovery = 15 - clamp_val(t.recover, 0, 15);
654 }
655 timing = (recovery << 4) | active | 0x08;
656 ld_qdi->clock[adev->devno] = timing;
657
658 if (ld_qdi->type == QDI6580)
659 outb(timing, ld_qdi->timing + 2 * adev->devno);
660 else
661 outb(timing, ld_qdi->timing + 2 * ap->port_no);
662
663 /* Clear the FIFO */
664 if (ld_qdi->type != QDI6500 && adev->class != ATA_DEV_ATA)
665 outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3);
666}
667
668/**
669 * qdi_qc_issue - command issue
670 * @qc: command pending
671 *
672 * Called when the libata layer is about to issue a command. We wrap
673 * this interface so that we can load the correct ATA timings.
674 */
675
676static unsigned int qdi_qc_issue(struct ata_queued_cmd *qc)
677{
678 struct ata_port *ap = qc->ap;
679 struct ata_device *adev = qc->dev;
680 struct legacy_data *ld_qdi = ap->host->private_data;
681
682 if (ld_qdi->clock[adev->devno] != ld_qdi->last) {
683 if (adev->pio_mode) {
684 ld_qdi->last = ld_qdi->clock[adev->devno];
685 outb(ld_qdi->clock[adev->devno], ld_qdi->timing +
686 2 * ap->port_no);
687 }
688 }
689 return ata_sff_qc_issue(qc);
690}
691
692static unsigned int vlb32_data_xfer(struct ata_queued_cmd *qc,
693 unsigned char *buf,
694 unsigned int buflen, int rw)
695{
696 struct ata_device *adev = qc->dev;
697 struct ata_port *ap = adev->link->ap;
698 int slop = buflen & 3;
699
700 if (ata_id_has_dword_io(adev->id) && (slop == 0 || slop == 3)
701 && (ap->pflags & ATA_PFLAG_PIO32)) {
702 if (rw == WRITE)
703 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
704 else
705 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
706
707 if (unlikely(slop)) {
708 __le32 pad;
709 if (rw == WRITE) {
710 memcpy(&pad, buf + buflen - slop, slop);
711 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
712 } else {
713 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
714 memcpy(buf + buflen - slop, &pad, slop);
715 }
716 }
717 return (buflen + 3) & ~3;
718 } else
719 return ata_sff_data_xfer(qc, buf, buflen, rw);
720}
721
722static int qdi_port(struct platform_device *dev,
723 struct legacy_probe *lp, struct legacy_data *ld)
724{
725 if (devm_request_region(&dev->dev, lp->private, 4, "qdi") == NULL)
726 return -EBUSY;
727 ld->timing = lp->private;
728 return 0;
729}
730
731static struct ata_port_operations qdi6500_port_ops = {
732 .inherits = &legacy_base_port_ops,
733 .set_piomode = qdi65x0_set_piomode,
734 .qc_issue = qdi_qc_issue,
735 .sff_data_xfer = vlb32_data_xfer,
736};
737
738static struct ata_port_operations qdi6580_port_ops = {
739 .inherits = &legacy_base_port_ops,
740 .set_piomode = qdi65x0_set_piomode,
741 .sff_data_xfer = vlb32_data_xfer,
742};
743
744static struct ata_port_operations qdi6580dp_port_ops = {
745 .inherits = &legacy_base_port_ops,
746 .set_piomode = qdi65x0_set_piomode,
747 .qc_issue = qdi_qc_issue,
748 .sff_data_xfer = vlb32_data_xfer,
749};
750
751static DEFINE_SPINLOCK(winbond_lock);
752
753static void winbond_writecfg(unsigned long port, u8 reg, u8 val)
754{
755 unsigned long flags;
756 spin_lock_irqsave(&winbond_lock, flags);
757 outb(reg, port + 0x01);
758 outb(val, port + 0x02);
759 spin_unlock_irqrestore(&winbond_lock, flags);
760}
761
762static u8 winbond_readcfg(unsigned long port, u8 reg)
763{
764 u8 val;
765
766 unsigned long flags;
767 spin_lock_irqsave(&winbond_lock, flags);
768 outb(reg, port + 0x01);
769 val = inb(port + 0x02);
770 spin_unlock_irqrestore(&winbond_lock, flags);
771
772 return val;
773}
774
775static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev)
776{
777 struct ata_timing t;
778 struct legacy_data *ld_winbond = ap->host->private_data;
779 int active, recovery;
780 u8 reg;
781 int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2);
782
783 reg = winbond_readcfg(ld_winbond->timing, 0x81);
784
785 /* Get the timing data in cycles */
786 if (reg & 0x40) /* Fast VLB bus, assume 50MHz */
787 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
788 else
789 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
790
791 active = (clamp_val(t.active, 3, 17) - 1) & 0x0F;
792 recovery = (clamp_val(t.recover, 1, 15) + 1) & 0x0F;
793 timing = (active << 4) | recovery;
794 winbond_writecfg(ld_winbond->timing, timing, reg);
795
796 /* Load the setup timing */
797
798 reg = 0x35;
799 if (adev->class != ATA_DEV_ATA)
800 reg |= 0x08; /* FIFO off */
801 if (!ata_pio_need_iordy(adev))
802 reg |= 0x02; /* IORDY off */
803 reg |= (clamp_val(t.setup, 0, 3) << 6);
804 winbond_writecfg(ld_winbond->timing, timing + 1, reg);
805}
806
807static int winbond_port(struct platform_device *dev,
808 struct legacy_probe *lp, struct legacy_data *ld)
809{
810 if (devm_request_region(&dev->dev, lp->private, 4, "winbond") == NULL)
811 return -EBUSY;
812 ld->timing = lp->private;
813 return 0;
814}
815
816static struct ata_port_operations winbond_port_ops = {
817 .inherits = &legacy_base_port_ops,
818 .set_piomode = winbond_set_piomode,
819 .sff_data_xfer = vlb32_data_xfer,
820};
821
822static struct legacy_controller controllers[] = {
823 {"BIOS", &legacy_port_ops, ATA_PIO4,
824 ATA_FLAG_NO_IORDY, 0, NULL },
825 {"Snooping", &simple_port_ops, ATA_PIO4,
826 0, 0, NULL },
827 {"PDC20230", &pdc20230_port_ops, ATA_PIO2,
828 ATA_FLAG_NO_IORDY,
829 ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, NULL },
830 {"HT6560A", &ht6560a_port_ops, ATA_PIO2,
831 ATA_FLAG_NO_IORDY, 0, NULL },
832 {"HT6560B", &ht6560b_port_ops, ATA_PIO4,
833 ATA_FLAG_NO_IORDY, 0, NULL },
834 {"OPTI82C611A", &opti82c611a_port_ops, ATA_PIO3,
835 0, 0, NULL },
836 {"OPTI82C46X", &opti82c46x_port_ops, ATA_PIO3,
837 0, 0, NULL },
838 {"QDI6500", &qdi6500_port_ops, ATA_PIO2,
839 ATA_FLAG_NO_IORDY,
840 ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
841 {"QDI6580", &qdi6580_port_ops, ATA_PIO4,
842 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
843 {"QDI6580DP", &qdi6580dp_port_ops, ATA_PIO4,
844 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
845 {"W83759A", &winbond_port_ops, ATA_PIO4,
846 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE,
847 winbond_port }
848};
849
850/**
851 * probe_chip_type - Discover controller
852 * @probe: Probe entry to check
853 *
854 * Probe an ATA port and identify the type of controller. We don't
855 * check if the controller appears to be driveless at this point.
856 */
857
858static __init int probe_chip_type(struct legacy_probe *probe)
859{
860 int mask = 1 << probe->slot;
861
862 if (winbond && (probe->port == 0x1F0 || probe->port == 0x170)) {
863 u8 reg = winbond_readcfg(winbond, 0x81);
864 reg |= 0x80; /* jumpered mode off */
865 winbond_writecfg(winbond, 0x81, reg);
866 reg = winbond_readcfg(winbond, 0x83);
867 reg |= 0xF0; /* local control */
868 winbond_writecfg(winbond, 0x83, reg);
869 reg = winbond_readcfg(winbond, 0x85);
870 reg |= 0xF0; /* programmable timing */
871 winbond_writecfg(winbond, 0x85, reg);
872
873 reg = winbond_readcfg(winbond, 0x81);
874
875 if (reg & mask)
876 return W83759A;
877 }
878 if (probe->port == 0x1F0) {
879 unsigned long flags;
880 local_irq_save(flags);
881 /* Probes */
882 outb(inb(0x1F2) | 0x80, 0x1F2);
883 inb(0x1F5);
884 inb(0x1F2);
885 inb(0x3F6);
886 inb(0x3F6);
887 inb(0x1F2);
888 inb(0x1F2);
889
890 if ((inb(0x1F2) & 0x80) == 0) {
891 /* PDC20230c or 20630 ? */
892 printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller"
893 " detected.\n");
894 udelay(100);
895 inb(0x1F5);
896 local_irq_restore(flags);
897 return PDC20230;
898 } else {
899 outb(0x55, 0x1F2);
900 inb(0x1F2);
901 inb(0x1F2);
902 if (inb(0x1F2) == 0x00)
903 printk(KERN_INFO "PDC20230-B VLB ATA "
904 "controller detected.\n");
905 local_irq_restore(flags);
906 return BIOS;
907 }
908 }
909
910 if (ht6560a & mask)
911 return HT6560A;
912 if (ht6560b & mask)
913 return HT6560B;
914 if (opti82c611a & mask)
915 return OPTI611A;
916 if (opti82c46x & mask)
917 return OPTI46X;
918 if (autospeed & mask)
919 return SNOOP;
920 return BIOS;
921}
922
923
924/**
925 * legacy_init_one - attach a legacy interface
926 * @pl: probe record
927 *
928 * Register an ISA bus IDE interface. Such interfaces are PIO and we
929 * assume do not support IRQ sharing.
930 */
931
932static __init int legacy_init_one(struct legacy_probe *probe)
933{
934 struct legacy_controller *controller = &controllers[probe->type];
935 int pio_modes = controller->pio_mask;
936 unsigned long io = probe->port;
937 u32 mask = (1 << probe->slot);
938 struct ata_port_operations *ops = controller->ops;
939 struct legacy_data *ld = &legacy_data[probe->slot];
940 struct ata_host *host = NULL;
941 struct ata_port *ap;
942 struct platform_device *pdev;
943 struct ata_device *dev;
944 void __iomem *io_addr, *ctrl_addr;
945 u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY;
946 int ret;
947
948 iordy |= controller->flags;
949
950 pdev = platform_device_register_simple(DRV_NAME, probe->slot, NULL, 0);
951 if (IS_ERR(pdev))
952 return PTR_ERR(pdev);
953
954 ret = -EBUSY;
955 if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL ||
956 devm_request_region(&pdev->dev, io + 0x0206, 1,
957 "pata_legacy") == NULL)
958 goto fail;
959
960 ret = -ENOMEM;
961 io_addr = devm_ioport_map(&pdev->dev, io, 8);
962 ctrl_addr = devm_ioport_map(&pdev->dev, io + 0x0206, 1);
963 if (!io_addr || !ctrl_addr)
964 goto fail;
965 ld->type = probe->type;
966 if (controller->setup)
967 if (controller->setup(pdev, probe, ld) < 0)
968 goto fail;
969 host = ata_host_alloc(&pdev->dev, 1);
970 if (!host)
971 goto fail;
972 ap = host->ports[0];
973
974 ap->ops = ops;
975 ap->pio_mask = pio_modes;
976 ap->flags |= ATA_FLAG_SLAVE_POSS | iordy;
977 ap->pflags |= controller->pflags;
978 ap->ioaddr.cmd_addr = io_addr;
979 ap->ioaddr.altstatus_addr = ctrl_addr;
980 ap->ioaddr.ctl_addr = ctrl_addr;
981 ata_sff_std_ports(&ap->ioaddr);
982 ap->host->private_data = ld;
983
984 ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io, io + 0x0206);
985
986 ret = ata_host_activate(host, probe->irq, ata_sff_interrupt, 0,
987 &legacy_sht);
988 if (ret)
989 goto fail;
990 async_synchronize_full();
991 ld->platform_dev = pdev;
992
993 /* Nothing found means we drop the port as its probably not there */
994
995 ret = -ENODEV;
996 ata_for_each_dev(dev, &ap->link, ALL) {
997 if (!ata_dev_absent(dev)) {
998 legacy_host[probe->slot] = host;
999 ld->platform_dev = pdev;
1000 return 0;
1001 }
1002 }
1003 ata_host_detach(host);
1004fail:
1005 platform_device_unregister(pdev);
1006 return ret;
1007}
1008
1009/**
1010 * legacy_check_special_cases - ATA special cases
1011 * @p: PCI device to check
1012 * @master: set this if we find an ATA master
1013 * @master: set this if we find an ATA secondary
1014 *
1015 * A small number of vendors implemented early PCI ATA interfaces
1016 * on bridge logic without the ATA interface being PCI visible.
1017 * Where we have a matching PCI driver we must skip the relevant
1018 * device here. If we don't know about it then the legacy driver
1019 * is the right driver anyway.
1020 */
1021
1022static void __init legacy_check_special_cases(struct pci_dev *p, int *primary,
1023 int *secondary)
1024{
1025 /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */
1026 if (p->vendor == 0x1078 && p->device == 0x0000) {
1027 *primary = *secondary = 1;
1028 return;
1029 }
1030 /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */
1031 if (p->vendor == 0x1078 && p->device == 0x0002) {
1032 *primary = *secondary = 1;
1033 return;
1034 }
1035 /* Intel MPIIX - PIO ATA on non PCI side of bridge */
1036 if (p->vendor == 0x8086 && p->device == 0x1234) {
1037 u16 r;
1038 pci_read_config_word(p, 0x6C, &r);
1039 if (r & 0x8000) {
1040 /* ATA port enabled */
1041 if (r & 0x4000)
1042 *secondary = 1;
1043 else
1044 *primary = 1;
1045 }
1046 return;
1047 }
1048}
1049
1050static __init void probe_opti_vlb(void)
1051{
1052 /* If an OPTI 82C46X is present find out where the channels are */
1053 static const char *optis[4] = {
1054 "3/463MV", "5MV",
1055 "5MVA", "5MVB"
1056 };
1057 u8 chans = 1;
1058 u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6;
1059
1060 opti82c46x = 3; /* Assume master and slave first */
1061 printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n",
1062 optis[ctrl]);
1063 if (ctrl == 3)
1064 chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1;
1065 ctrl = opti_syscfg(0xAC);
1066 /* Check enabled and this port is the 465MV port. On the
1067 MVB we may have two channels */
1068 if (ctrl & 8) {
1069 if (chans == 2) {
1070 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1071 legacy_probe_add(0x170, 15, OPTI46X, 0);
1072 }
1073 if (ctrl & 4)
1074 legacy_probe_add(0x170, 15, OPTI46X, 0);
1075 else
1076 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1077 } else
1078 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1079}
1080
1081static __init void qdi65_identify_port(u8 r, u8 res, unsigned long port)
1082{
1083 static const unsigned long ide_port[2] = { 0x170, 0x1F0 };
1084 /* Check card type */
1085 if ((r & 0xF0) == 0xC0) {
1086 /* QD6500: single channel */
1087 if (r & 8)
1088 /* Disabled ? */
1089 return;
1090 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),
1091 QDI6500, port);
1092 }
1093 if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) {
1094 /* QD6580: dual channel */
1095 if (!request_region(port + 2 , 2, "pata_qdi")) {
1096 release_region(port, 2);
1097 return;
1098 }
1099 res = inb(port + 3);
1100 /* Single channel mode ? */
1101 if (res & 1)
1102 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),
1103 QDI6580, port);
1104 else { /* Dual channel mode */
1105 legacy_probe_add(0x1F0, 14, QDI6580DP, port);
1106 /* port + 0x02, r & 0x04 */
1107 legacy_probe_add(0x170, 15, QDI6580DP, port + 2);
1108 }
1109 release_region(port + 2, 2);
1110 }
1111}
1112
1113static __init void probe_qdi_vlb(void)
1114{
1115 unsigned long flags;
1116 static const unsigned long qd_port[2] = { 0x30, 0xB0 };
1117 int i;
1118
1119 /*
1120 * Check each possible QD65xx base address
1121 */
1122
1123 for (i = 0; i < 2; i++) {
1124 unsigned long port = qd_port[i];
1125 u8 r, res;
1126
1127
1128 if (request_region(port, 2, "pata_qdi")) {
1129 /* Check for a card */
1130 local_irq_save(flags);
1131 /* I have no h/w that needs this delay but it
1132 is present in the historic code */
1133 r = inb(port);
1134 udelay(1);
1135 outb(0x19, port);
1136 udelay(1);
1137 res = inb(port);
1138 udelay(1);
1139 outb(r, port);
1140 udelay(1);
1141 local_irq_restore(flags);
1142
1143 /* Fail */
1144 if (res == 0x19) {
1145 release_region(port, 2);
1146 continue;
1147 }
1148 /* Passes the presence test */
1149 r = inb(port + 1);
1150 udelay(1);
1151 /* Check port agrees with port set */
1152 if ((r & 2) >> 1 == i)
1153 qdi65_identify_port(r, res, port);
1154 release_region(port, 2);
1155 }
1156 }
1157}
1158
1159/**
1160 * legacy_init - attach legacy interfaces
1161 *
1162 * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects.
1163 * Right now we do not scan the ide0 and ide1 address but should do so
1164 * for non PCI systems or systems with no PCI IDE legacy mode devices.
1165 * If you fix that note there are special cases to consider like VLB
1166 * drivers and CS5510/20.
1167 */
1168
1169static __init int legacy_init(void)
1170{
1171 int i;
1172 int ct = 0;
1173 int primary = 0;
1174 int secondary = 0;
1175 int pci_present = 0;
1176 struct legacy_probe *pl = &probe_list[0];
1177 int slot = 0;
1178
1179 struct pci_dev *p = NULL;
1180
1181 for_each_pci_dev(p) {
1182 int r;
1183 /* Check for any overlap of the system ATA mappings. Native
1184 mode controllers stuck on these addresses or some devices
1185 in 'raid' mode won't be found by the storage class test */
1186 for (r = 0; r < 6; r++) {
1187 if (pci_resource_start(p, r) == 0x1f0)
1188 primary = 1;
1189 if (pci_resource_start(p, r) == 0x170)
1190 secondary = 1;
1191 }
1192 /* Check for special cases */
1193 legacy_check_special_cases(p, &primary, &secondary);
1194
1195 /* If PCI bus is present then don't probe for tertiary
1196 legacy ports */
1197 pci_present = 1;
1198 }
1199
1200 if (winbond == 1)
1201 winbond = 0x130; /* Default port, alt is 1B0 */
1202
1203 if (primary == 0 || all)
1204 legacy_probe_add(0x1F0, 14, UNKNOWN, 0);
1205 if (secondary == 0 || all)
1206 legacy_probe_add(0x170, 15, UNKNOWN, 0);
1207
1208 if (probe_all || !pci_present) {
1209 /* ISA/VLB extra ports */
1210 legacy_probe_add(0x1E8, 11, UNKNOWN, 0);
1211 legacy_probe_add(0x168, 10, UNKNOWN, 0);
1212 legacy_probe_add(0x1E0, 8, UNKNOWN, 0);
1213 legacy_probe_add(0x160, 12, UNKNOWN, 0);
1214 }
1215
1216 if (opti82c46x)
1217 probe_opti_vlb();
1218 if (qdi)
1219 probe_qdi_vlb();
1220
1221 for (i = 0; i < NR_HOST; i++, pl++) {
1222 if (pl->port == 0)
1223 continue;
1224 if (pl->type == UNKNOWN)
1225 pl->type = probe_chip_type(pl);
1226 pl->slot = slot++;
1227 if (legacy_init_one(pl) == 0)
1228 ct++;
1229 }
1230 if (ct != 0)
1231 return 0;
1232 return -ENODEV;
1233}
1234
1235static __exit void legacy_exit(void)
1236{
1237 int i;
1238
1239 for (i = 0; i < nr_legacy_host; i++) {
1240 struct legacy_data *ld = &legacy_data[i];
1241 ata_host_detach(legacy_host[i]);
1242 platform_device_unregister(ld->platform_dev);
1243 }
1244}
1245
1246MODULE_AUTHOR("Alan Cox");
1247MODULE_DESCRIPTION("low-level driver for legacy ATA");
1248MODULE_LICENSE("GPL");
1249MODULE_VERSION(DRV_VERSION);
1250MODULE_ALIAS("pata_qdi");
1251MODULE_ALIAS("pata_winbond");
1252
1253module_param(probe_all, int, 0);
1254module_param(autospeed, int, 0);
1255module_param(ht6560a, int, 0);
1256module_param(ht6560b, int, 0);
1257module_param(opti82c611a, int, 0);
1258module_param(opti82c46x, int, 0);
1259module_param(qdi, int, 0);
1260module_param(winbond, int, 0);
1261module_param(pio_mask, int, 0);
1262module_param(iordy_mask, int, 0);
1263
1264module_init(legacy_init);
1265module_exit(legacy_exit);
1/*
2 * pata-legacy.c - Legacy port PATA/SATA controller driver.
3 * Copyright 2005/2006 Red Hat, all rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2, or (at your option)
8 * any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; see the file COPYING. If not, write to
17 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
18 *
19 * An ATA driver for the legacy ATA ports.
20 *
21 * Data Sources:
22 * Opti 82C465/82C611 support: Data sheets at opti-inc.com
23 * HT6560 series:
24 * Promise 20230/20620:
25 * http://www.ryston.cz/petr/vlb/pdc20230b.html
26 * http://www.ryston.cz/petr/vlb/pdc20230c.html
27 * http://www.ryston.cz/petr/vlb/pdc20630.html
28 * QDI65x0:
29 * http://www.ryston.cz/petr/vlb/qd6500.html
30 * http://www.ryston.cz/petr/vlb/qd6580.html
31 *
32 * QDI65x0 probe code based on drivers/ide/legacy/qd65xx.c
33 * Rewritten from the work of Colten Edwards <pje120@cs.usask.ca> by
34 * Samuel Thibault <samuel.thibault@ens-lyon.org>
35 *
36 * Unsupported but docs exist:
37 * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220
38 *
39 * This driver handles legacy (that is "ISA/VLB side") IDE ports found
40 * on PC class systems. There are three hybrid devices that are exceptions
41 * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and
42 * the MPIIX where the tuning is PCI side but the IDE is "ISA side".
43 *
44 * Specific support is included for the ht6560a/ht6560b/opti82c611a/
45 * opti82c465mv/promise 20230c/20630/qdi65x0/winbond83759A
46 *
47 * Support for the Winbond 83759A when operating in advanced mode.
48 * Multichip mode is not currently supported.
49 *
50 * Use the autospeed and pio_mask options with:
51 * Appian ADI/2 aka CLPD7220 or AIC25VL01.
52 * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with
53 * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759,
54 * Winbond W83759A, Promise PDC20230-B
55 *
56 * For now use autospeed and pio_mask as above with the W83759A. This may
57 * change.
58 *
59 */
60
61#include <linux/async.h>
62#include <linux/kernel.h>
63#include <linux/module.h>
64#include <linux/pci.h>
65#include <linux/init.h>
66#include <linux/blkdev.h>
67#include <linux/delay.h>
68#include <scsi/scsi_host.h>
69#include <linux/ata.h>
70#include <linux/libata.h>
71#include <linux/platform_device.h>
72
73#define DRV_NAME "pata_legacy"
74#define DRV_VERSION "0.6.5"
75
76#define NR_HOST 6
77
78static int all;
79module_param(all, int, 0444);
80MODULE_PARM_DESC(all, "Grab all legacy port devices, even if PCI(0=off, 1=on)");
81
82enum controller {
83 BIOS = 0,
84 SNOOP = 1,
85 PDC20230 = 2,
86 HT6560A = 3,
87 HT6560B = 4,
88 OPTI611A = 5,
89 OPTI46X = 6,
90 QDI6500 = 7,
91 QDI6580 = 8,
92 QDI6580DP = 9, /* Dual channel mode is different */
93 W83759A = 10,
94
95 UNKNOWN = -1
96};
97
98struct legacy_data {
99 unsigned long timing;
100 u8 clock[2];
101 u8 last;
102 int fast;
103 enum controller type;
104 struct platform_device *platform_dev;
105};
106
107struct legacy_probe {
108 unsigned char *name;
109 unsigned long port;
110 unsigned int irq;
111 unsigned int slot;
112 enum controller type;
113 unsigned long private;
114};
115
116struct legacy_controller {
117 const char *name;
118 struct ata_port_operations *ops;
119 unsigned int pio_mask;
120 unsigned int flags;
121 unsigned int pflags;
122 int (*setup)(struct platform_device *, struct legacy_probe *probe,
123 struct legacy_data *data);
124};
125
126static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 };
127
128static struct legacy_probe probe_list[NR_HOST];
129static struct legacy_data legacy_data[NR_HOST];
130static struct ata_host *legacy_host[NR_HOST];
131static int nr_legacy_host;
132
133
134static int probe_all; /* Set to check all ISA port ranges */
135static int ht6560a; /* HT 6560A on primary 1, second 2, both 3 */
136static int ht6560b; /* HT 6560A on primary 1, second 2, both 3 */
137static int opti82c611a; /* Opti82c611A on primary 1, sec 2, both 3 */
138static int opti82c46x; /* Opti 82c465MV present(pri/sec autodetect) */
139static int autospeed; /* Chip present which snoops speed changes */
140static int pio_mask = ATA_PIO4; /* PIO range for autospeed devices */
141static int iordy_mask = 0xFFFFFFFF; /* Use iordy if available */
142
143/* Set to probe QDI controllers */
144#ifdef CONFIG_PATA_QDI_MODULE
145static int qdi = 1;
146#else
147static int qdi;
148#endif
149
150#ifdef CONFIG_PATA_WINBOND_VLB_MODULE
151static int winbond = 1; /* Set to probe Winbond controllers,
152 give I/O port if non standard */
153#else
154static int winbond; /* Set to probe Winbond controllers,
155 give I/O port if non standard */
156#endif
157
158/**
159 * legacy_probe_add - Add interface to probe list
160 * @port: Controller port
161 * @irq: IRQ number
162 * @type: Controller type
163 * @private: Controller specific info
164 *
165 * Add an entry into the probe list for ATA controllers. This is used
166 * to add the default ISA slots and then to build up the table
167 * further according to other ISA/VLB/Weird device scans
168 *
169 * An I/O port list is used to keep ordering stable and sane, as we
170 * don't have any good way to talk about ordering otherwise
171 */
172
173static int legacy_probe_add(unsigned long port, unsigned int irq,
174 enum controller type, unsigned long private)
175{
176 struct legacy_probe *lp = &probe_list[0];
177 int i;
178 struct legacy_probe *free = NULL;
179
180 for (i = 0; i < NR_HOST; i++) {
181 if (lp->port == 0 && free == NULL)
182 free = lp;
183 /* Matching port, or the correct slot for ordering */
184 if (lp->port == port || legacy_port[i] == port) {
185 free = lp;
186 break;
187 }
188 lp++;
189 }
190 if (free == NULL) {
191 printk(KERN_ERR "pata_legacy: Too many interfaces.\n");
192 return -1;
193 }
194 /* Fill in the entry for later probing */
195 free->port = port;
196 free->irq = irq;
197 free->type = type;
198 free->private = private;
199 return 0;
200}
201
202
203/**
204 * legacy_set_mode - mode setting
205 * @link: IDE link
206 * @unused: Device that failed when error is returned
207 *
208 * Use a non standard set_mode function. We don't want to be tuned.
209 *
210 * The BIOS configured everything. Our job is not to fiddle. Just use
211 * whatever PIO the hardware is using and leave it at that. When we
212 * get some kind of nice user driven API for control then we can
213 * expand on this as per hdparm in the base kernel.
214 */
215
216static int legacy_set_mode(struct ata_link *link, struct ata_device **unused)
217{
218 struct ata_device *dev;
219
220 ata_for_each_dev(dev, link, ENABLED) {
221 ata_dev_info(dev, "configured for PIO\n");
222 dev->pio_mode = XFER_PIO_0;
223 dev->xfer_mode = XFER_PIO_0;
224 dev->xfer_shift = ATA_SHIFT_PIO;
225 dev->flags |= ATA_DFLAG_PIO;
226 }
227 return 0;
228}
229
230static struct scsi_host_template legacy_sht = {
231 ATA_PIO_SHT(DRV_NAME),
232};
233
234static const struct ata_port_operations legacy_base_port_ops = {
235 .inherits = &ata_sff_port_ops,
236 .cable_detect = ata_cable_40wire,
237};
238
239/*
240 * These ops are used if the user indicates the hardware
241 * snoops the commands to decide on the mode and handles the
242 * mode selection "magically" itself. Several legacy controllers
243 * do this. The mode range can be set if it is not 0x1F by setting
244 * pio_mask as well.
245 */
246
247static struct ata_port_operations simple_port_ops = {
248 .inherits = &legacy_base_port_ops,
249 .sff_data_xfer = ata_sff_data_xfer_noirq,
250};
251
252static struct ata_port_operations legacy_port_ops = {
253 .inherits = &legacy_base_port_ops,
254 .sff_data_xfer = ata_sff_data_xfer_noirq,
255 .set_mode = legacy_set_mode,
256};
257
258/*
259 * Promise 20230C and 20620 support
260 *
261 * This controller supports PIO0 to PIO2. We set PIO timings
262 * conservatively to allow for 50MHz Vesa Local Bus. The 20620 DMA
263 * support is weird being DMA to controller and PIO'd to the host
264 * and not supported.
265 */
266
267static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev)
268{
269 int tries = 5;
270 int pio = adev->pio_mode - XFER_PIO_0;
271 u8 rt;
272 unsigned long flags;
273
274 /* Safe as UP only. Force I/Os to occur together */
275
276 local_irq_save(flags);
277
278 /* Unlock the control interface */
279 do {
280 inb(0x1F5);
281 outb(inb(0x1F2) | 0x80, 0x1F2);
282 inb(0x1F2);
283 inb(0x3F6);
284 inb(0x3F6);
285 inb(0x1F2);
286 inb(0x1F2);
287 }
288 while ((inb(0x1F2) & 0x80) && --tries);
289
290 local_irq_restore(flags);
291
292 outb(inb(0x1F4) & 0x07, 0x1F4);
293
294 rt = inb(0x1F3);
295 rt &= 0x07 << (3 * adev->devno);
296 if (pio)
297 rt |= (1 + 3 * pio) << (3 * adev->devno);
298
299 udelay(100);
300 outb(inb(0x1F2) | 0x01, 0x1F2);
301 udelay(100);
302 inb(0x1F5);
303
304}
305
306static unsigned int pdc_data_xfer_vlb(struct ata_device *dev,
307 unsigned char *buf, unsigned int buflen, int rw)
308{
309 int slop = buflen & 3;
310 struct ata_port *ap = dev->link->ap;
311
312 /* 32bit I/O capable *and* we need to write a whole number of dwords */
313 if (ata_id_has_dword_io(dev->id) && (slop == 0 || slop == 3)
314 && (ap->pflags & ATA_PFLAG_PIO32)) {
315 unsigned long flags;
316
317 local_irq_save(flags);
318
319 /* Perform the 32bit I/O synchronization sequence */
320 ioread8(ap->ioaddr.nsect_addr);
321 ioread8(ap->ioaddr.nsect_addr);
322 ioread8(ap->ioaddr.nsect_addr);
323
324 /* Now the data */
325 if (rw == READ)
326 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
327 else
328 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
329
330 if (unlikely(slop)) {
331 __le32 pad;
332 if (rw == READ) {
333 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
334 memcpy(buf + buflen - slop, &pad, slop);
335 } else {
336 memcpy(&pad, buf + buflen - slop, slop);
337 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
338 }
339 buflen += 4 - slop;
340 }
341 local_irq_restore(flags);
342 } else
343 buflen = ata_sff_data_xfer_noirq(dev, buf, buflen, rw);
344
345 return buflen;
346}
347
348static struct ata_port_operations pdc20230_port_ops = {
349 .inherits = &legacy_base_port_ops,
350 .set_piomode = pdc20230_set_piomode,
351 .sff_data_xfer = pdc_data_xfer_vlb,
352};
353
354/*
355 * Holtek 6560A support
356 *
357 * This controller supports PIO0 to PIO2 (no IORDY even though higher
358 * timings can be loaded).
359 */
360
361static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev)
362{
363 u8 active, recover;
364 struct ata_timing t;
365
366 /* Get the timing data in cycles. For now play safe at 50Mhz */
367 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
368
369 active = clamp_val(t.active, 2, 15);
370 recover = clamp_val(t.recover, 4, 15);
371
372 inb(0x3E6);
373 inb(0x3E6);
374 inb(0x3E6);
375 inb(0x3E6);
376
377 iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
378 ioread8(ap->ioaddr.status_addr);
379}
380
381static struct ata_port_operations ht6560a_port_ops = {
382 .inherits = &legacy_base_port_ops,
383 .set_piomode = ht6560a_set_piomode,
384};
385
386/*
387 * Holtek 6560B support
388 *
389 * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO
390 * setting unless we see an ATAPI device in which case we force it off.
391 *
392 * FIXME: need to implement 2nd channel support.
393 */
394
395static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev)
396{
397 u8 active, recover;
398 struct ata_timing t;
399
400 /* Get the timing data in cycles. For now play safe at 50Mhz */
401 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
402
403 active = clamp_val(t.active, 2, 15);
404 recover = clamp_val(t.recover, 2, 16) & 0x0F;
405
406 inb(0x3E6);
407 inb(0x3E6);
408 inb(0x3E6);
409 inb(0x3E6);
410
411 iowrite8(recover << 4 | active, ap->ioaddr.device_addr);
412
413 if (adev->class != ATA_DEV_ATA) {
414 u8 rconf = inb(0x3E6);
415 if (rconf & 0x24) {
416 rconf &= ~0x24;
417 outb(rconf, 0x3E6);
418 }
419 }
420 ioread8(ap->ioaddr.status_addr);
421}
422
423static struct ata_port_operations ht6560b_port_ops = {
424 .inherits = &legacy_base_port_ops,
425 .set_piomode = ht6560b_set_piomode,
426};
427
428/*
429 * Opti core chipset helpers
430 */
431
432/**
433 * opti_syscfg - read OPTI chipset configuration
434 * @reg: Configuration register to read
435 *
436 * Returns the value of an OPTI system board configuration register.
437 */
438
439static u8 opti_syscfg(u8 reg)
440{
441 unsigned long flags;
442 u8 r;
443
444 /* Uniprocessor chipset and must force cycles adjancent */
445 local_irq_save(flags);
446 outb(reg, 0x22);
447 r = inb(0x24);
448 local_irq_restore(flags);
449 return r;
450}
451
452/*
453 * Opti 82C611A
454 *
455 * This controller supports PIO0 to PIO3.
456 */
457
458static void opti82c611a_set_piomode(struct ata_port *ap,
459 struct ata_device *adev)
460{
461 u8 active, recover, setup;
462 struct ata_timing t;
463 struct ata_device *pair = ata_dev_pair(adev);
464 int clock;
465 int khz[4] = { 50000, 40000, 33000, 25000 };
466 u8 rc;
467
468 /* Enter configuration mode */
469 ioread16(ap->ioaddr.error_addr);
470 ioread16(ap->ioaddr.error_addr);
471 iowrite8(3, ap->ioaddr.nsect_addr);
472
473 /* Read VLB clock strapping */
474 clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03];
475
476 /* Get the timing data in cycles */
477 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
478
479 /* Setup timing is shared */
480 if (pair) {
481 struct ata_timing tp;
482 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
483
484 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
485 }
486
487 active = clamp_val(t.active, 2, 17) - 2;
488 recover = clamp_val(t.recover, 1, 16) - 1;
489 setup = clamp_val(t.setup, 1, 4) - 1;
490
491 /* Select the right timing bank for write timing */
492 rc = ioread8(ap->ioaddr.lbal_addr);
493 rc &= 0x7F;
494 rc |= (adev->devno << 7);
495 iowrite8(rc, ap->ioaddr.lbal_addr);
496
497 /* Write the timings */
498 iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
499
500 /* Select the right bank for read timings, also
501 load the shared timings for address */
502 rc = ioread8(ap->ioaddr.device_addr);
503 rc &= 0xC0;
504 rc |= adev->devno; /* Index select */
505 rc |= (setup << 4) | 0x04;
506 iowrite8(rc, ap->ioaddr.device_addr);
507
508 /* Load the read timings */
509 iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
510
511 /* Ensure the timing register mode is right */
512 rc = ioread8(ap->ioaddr.lbal_addr);
513 rc &= 0x73;
514 rc |= 0x84;
515 iowrite8(rc, ap->ioaddr.lbal_addr);
516
517 /* Exit command mode */
518 iowrite8(0x83, ap->ioaddr.nsect_addr);
519}
520
521
522static struct ata_port_operations opti82c611a_port_ops = {
523 .inherits = &legacy_base_port_ops,
524 .set_piomode = opti82c611a_set_piomode,
525};
526
527/*
528 * Opti 82C465MV
529 *
530 * This controller supports PIO0 to PIO3. Unlike the 611A the MVB
531 * version is dual channel but doesn't have a lot of unique registers.
532 */
533
534static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev)
535{
536 u8 active, recover, setup;
537 struct ata_timing t;
538 struct ata_device *pair = ata_dev_pair(adev);
539 int clock;
540 int khz[4] = { 50000, 40000, 33000, 25000 };
541 u8 rc;
542 u8 sysclk;
543
544 /* Get the clock */
545 sysclk = (opti_syscfg(0xAC) & 0xC0) >> 6; /* BIOS set */
546
547 /* Enter configuration mode */
548 ioread16(ap->ioaddr.error_addr);
549 ioread16(ap->ioaddr.error_addr);
550 iowrite8(3, ap->ioaddr.nsect_addr);
551
552 /* Read VLB clock strapping */
553 clock = 1000000000 / khz[sysclk];
554
555 /* Get the timing data in cycles */
556 ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000);
557
558 /* Setup timing is shared */
559 if (pair) {
560 struct ata_timing tp;
561 ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000);
562
563 ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP);
564 }
565
566 active = clamp_val(t.active, 2, 17) - 2;
567 recover = clamp_val(t.recover, 1, 16) - 1;
568 setup = clamp_val(t.setup, 1, 4) - 1;
569
570 /* Select the right timing bank for write timing */
571 rc = ioread8(ap->ioaddr.lbal_addr);
572 rc &= 0x7F;
573 rc |= (adev->devno << 7);
574 iowrite8(rc, ap->ioaddr.lbal_addr);
575
576 /* Write the timings */
577 iowrite8(active << 4 | recover, ap->ioaddr.error_addr);
578
579 /* Select the right bank for read timings, also
580 load the shared timings for address */
581 rc = ioread8(ap->ioaddr.device_addr);
582 rc &= 0xC0;
583 rc |= adev->devno; /* Index select */
584 rc |= (setup << 4) | 0x04;
585 iowrite8(rc, ap->ioaddr.device_addr);
586
587 /* Load the read timings */
588 iowrite8(active << 4 | recover, ap->ioaddr.data_addr);
589
590 /* Ensure the timing register mode is right */
591 rc = ioread8(ap->ioaddr.lbal_addr);
592 rc &= 0x73;
593 rc |= 0x84;
594 iowrite8(rc, ap->ioaddr.lbal_addr);
595
596 /* Exit command mode */
597 iowrite8(0x83, ap->ioaddr.nsect_addr);
598
599 /* We need to know this for quad device on the MVB */
600 ap->host->private_data = ap;
601}
602
603/**
604 * opt82c465mv_qc_issue - command issue
605 * @qc: command pending
606 *
607 * Called when the libata layer is about to issue a command. We wrap
608 * this interface so that we can load the correct ATA timings. The
609 * MVB has a single set of timing registers and these are shared
610 * across channels. As there are two registers we really ought to
611 * track the last two used values as a sort of register window. For
612 * now we just reload on a channel switch. On the single channel
613 * setup this condition never fires so we do nothing extra.
614 *
615 * FIXME: dual channel needs ->serialize support
616 */
617
618static unsigned int opti82c46x_qc_issue(struct ata_queued_cmd *qc)
619{
620 struct ata_port *ap = qc->ap;
621 struct ata_device *adev = qc->dev;
622
623 /* If timings are set and for the wrong channel (2nd test is
624 due to a libata shortcoming and will eventually go I hope) */
625 if (ap->host->private_data != ap->host
626 && ap->host->private_data != NULL)
627 opti82c46x_set_piomode(ap, adev);
628
629 return ata_sff_qc_issue(qc);
630}
631
632static struct ata_port_operations opti82c46x_port_ops = {
633 .inherits = &legacy_base_port_ops,
634 .set_piomode = opti82c46x_set_piomode,
635 .qc_issue = opti82c46x_qc_issue,
636};
637
638/**
639 * qdi65x0_set_piomode - PIO setup for QDI65x0
640 * @ap: Port
641 * @adev: Device
642 *
643 * In single channel mode the 6580 has one clock per device and we can
644 * avoid the requirement to clock switch. We also have to load the timing
645 * into the right clock according to whether we are master or slave.
646 *
647 * In dual channel mode the 6580 has one clock per channel and we have
648 * to software clockswitch in qc_issue.
649 */
650
651static void qdi65x0_set_piomode(struct ata_port *ap, struct ata_device *adev)
652{
653 struct ata_timing t;
654 struct legacy_data *ld_qdi = ap->host->private_data;
655 int active, recovery;
656 u8 timing;
657
658 /* Get the timing data in cycles */
659 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
660
661 if (ld_qdi->fast) {
662 active = 8 - clamp_val(t.active, 1, 8);
663 recovery = 18 - clamp_val(t.recover, 3, 18);
664 } else {
665 active = 9 - clamp_val(t.active, 2, 9);
666 recovery = 15 - clamp_val(t.recover, 0, 15);
667 }
668 timing = (recovery << 4) | active | 0x08;
669 ld_qdi->clock[adev->devno] = timing;
670
671 if (ld_qdi->type == QDI6580)
672 outb(timing, ld_qdi->timing + 2 * adev->devno);
673 else
674 outb(timing, ld_qdi->timing + 2 * ap->port_no);
675
676 /* Clear the FIFO */
677 if (ld_qdi->type != QDI6500 && adev->class != ATA_DEV_ATA)
678 outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3);
679}
680
681/**
682 * qdi_qc_issue - command issue
683 * @qc: command pending
684 *
685 * Called when the libata layer is about to issue a command. We wrap
686 * this interface so that we can load the correct ATA timings.
687 */
688
689static unsigned int qdi_qc_issue(struct ata_queued_cmd *qc)
690{
691 struct ata_port *ap = qc->ap;
692 struct ata_device *adev = qc->dev;
693 struct legacy_data *ld_qdi = ap->host->private_data;
694
695 if (ld_qdi->clock[adev->devno] != ld_qdi->last) {
696 if (adev->pio_mode) {
697 ld_qdi->last = ld_qdi->clock[adev->devno];
698 outb(ld_qdi->clock[adev->devno], ld_qdi->timing +
699 2 * ap->port_no);
700 }
701 }
702 return ata_sff_qc_issue(qc);
703}
704
705static unsigned int vlb32_data_xfer(struct ata_device *adev, unsigned char *buf,
706 unsigned int buflen, int rw)
707{
708 struct ata_port *ap = adev->link->ap;
709 int slop = buflen & 3;
710
711 if (ata_id_has_dword_io(adev->id) && (slop == 0 || slop == 3)
712 && (ap->pflags & ATA_PFLAG_PIO32)) {
713 if (rw == WRITE)
714 iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
715 else
716 ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2);
717
718 if (unlikely(slop)) {
719 __le32 pad;
720 if (rw == WRITE) {
721 memcpy(&pad, buf + buflen - slop, slop);
722 iowrite32(le32_to_cpu(pad), ap->ioaddr.data_addr);
723 } else {
724 pad = cpu_to_le32(ioread32(ap->ioaddr.data_addr));
725 memcpy(buf + buflen - slop, &pad, slop);
726 }
727 }
728 return (buflen + 3) & ~3;
729 } else
730 return ata_sff_data_xfer(adev, buf, buflen, rw);
731}
732
733static int qdi_port(struct platform_device *dev,
734 struct legacy_probe *lp, struct legacy_data *ld)
735{
736 if (devm_request_region(&dev->dev, lp->private, 4, "qdi") == NULL)
737 return -EBUSY;
738 ld->timing = lp->private;
739 return 0;
740}
741
742static struct ata_port_operations qdi6500_port_ops = {
743 .inherits = &legacy_base_port_ops,
744 .set_piomode = qdi65x0_set_piomode,
745 .qc_issue = qdi_qc_issue,
746 .sff_data_xfer = vlb32_data_xfer,
747};
748
749static struct ata_port_operations qdi6580_port_ops = {
750 .inherits = &legacy_base_port_ops,
751 .set_piomode = qdi65x0_set_piomode,
752 .sff_data_xfer = vlb32_data_xfer,
753};
754
755static struct ata_port_operations qdi6580dp_port_ops = {
756 .inherits = &legacy_base_port_ops,
757 .set_piomode = qdi65x0_set_piomode,
758 .qc_issue = qdi_qc_issue,
759 .sff_data_xfer = vlb32_data_xfer,
760};
761
762static DEFINE_SPINLOCK(winbond_lock);
763
764static void winbond_writecfg(unsigned long port, u8 reg, u8 val)
765{
766 unsigned long flags;
767 spin_lock_irqsave(&winbond_lock, flags);
768 outb(reg, port + 0x01);
769 outb(val, port + 0x02);
770 spin_unlock_irqrestore(&winbond_lock, flags);
771}
772
773static u8 winbond_readcfg(unsigned long port, u8 reg)
774{
775 u8 val;
776
777 unsigned long flags;
778 spin_lock_irqsave(&winbond_lock, flags);
779 outb(reg, port + 0x01);
780 val = inb(port + 0x02);
781 spin_unlock_irqrestore(&winbond_lock, flags);
782
783 return val;
784}
785
786static void winbond_set_piomode(struct ata_port *ap, struct ata_device *adev)
787{
788 struct ata_timing t;
789 struct legacy_data *ld_winbond = ap->host->private_data;
790 int active, recovery;
791 u8 reg;
792 int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2);
793
794 reg = winbond_readcfg(ld_winbond->timing, 0x81);
795
796 /* Get the timing data in cycles */
797 if (reg & 0x40) /* Fast VLB bus, assume 50MHz */
798 ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000);
799 else
800 ata_timing_compute(adev, adev->pio_mode, &t, 30303, 1000);
801
802 active = (clamp_val(t.active, 3, 17) - 1) & 0x0F;
803 recovery = (clamp_val(t.recover, 1, 15) + 1) & 0x0F;
804 timing = (active << 4) | recovery;
805 winbond_writecfg(ld_winbond->timing, timing, reg);
806
807 /* Load the setup timing */
808
809 reg = 0x35;
810 if (adev->class != ATA_DEV_ATA)
811 reg |= 0x08; /* FIFO off */
812 if (!ata_pio_need_iordy(adev))
813 reg |= 0x02; /* IORDY off */
814 reg |= (clamp_val(t.setup, 0, 3) << 6);
815 winbond_writecfg(ld_winbond->timing, timing + 1, reg);
816}
817
818static int winbond_port(struct platform_device *dev,
819 struct legacy_probe *lp, struct legacy_data *ld)
820{
821 if (devm_request_region(&dev->dev, lp->private, 4, "winbond") == NULL)
822 return -EBUSY;
823 ld->timing = lp->private;
824 return 0;
825}
826
827static struct ata_port_operations winbond_port_ops = {
828 .inherits = &legacy_base_port_ops,
829 .set_piomode = winbond_set_piomode,
830 .sff_data_xfer = vlb32_data_xfer,
831};
832
833static struct legacy_controller controllers[] = {
834 {"BIOS", &legacy_port_ops, ATA_PIO4,
835 ATA_FLAG_NO_IORDY, 0, NULL },
836 {"Snooping", &simple_port_ops, ATA_PIO4,
837 0, 0, NULL },
838 {"PDC20230", &pdc20230_port_ops, ATA_PIO2,
839 ATA_FLAG_NO_IORDY,
840 ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, NULL },
841 {"HT6560A", &ht6560a_port_ops, ATA_PIO2,
842 ATA_FLAG_NO_IORDY, 0, NULL },
843 {"HT6560B", &ht6560b_port_ops, ATA_PIO4,
844 ATA_FLAG_NO_IORDY, 0, NULL },
845 {"OPTI82C611A", &opti82c611a_port_ops, ATA_PIO3,
846 0, 0, NULL },
847 {"OPTI82C46X", &opti82c46x_port_ops, ATA_PIO3,
848 0, 0, NULL },
849 {"QDI6500", &qdi6500_port_ops, ATA_PIO2,
850 ATA_FLAG_NO_IORDY,
851 ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
852 {"QDI6580", &qdi6580_port_ops, ATA_PIO4,
853 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
854 {"QDI6580DP", &qdi6580dp_port_ops, ATA_PIO4,
855 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE, qdi_port },
856 {"W83759A", &winbond_port_ops, ATA_PIO4,
857 0, ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE,
858 winbond_port }
859};
860
861/**
862 * probe_chip_type - Discover controller
863 * @probe: Probe entry to check
864 *
865 * Probe an ATA port and identify the type of controller. We don't
866 * check if the controller appears to be driveless at this point.
867 */
868
869static __init int probe_chip_type(struct legacy_probe *probe)
870{
871 int mask = 1 << probe->slot;
872
873 if (winbond && (probe->port == 0x1F0 || probe->port == 0x170)) {
874 u8 reg = winbond_readcfg(winbond, 0x81);
875 reg |= 0x80; /* jumpered mode off */
876 winbond_writecfg(winbond, 0x81, reg);
877 reg = winbond_readcfg(winbond, 0x83);
878 reg |= 0xF0; /* local control */
879 winbond_writecfg(winbond, 0x83, reg);
880 reg = winbond_readcfg(winbond, 0x85);
881 reg |= 0xF0; /* programmable timing */
882 winbond_writecfg(winbond, 0x85, reg);
883
884 reg = winbond_readcfg(winbond, 0x81);
885
886 if (reg & mask)
887 return W83759A;
888 }
889 if (probe->port == 0x1F0) {
890 unsigned long flags;
891 local_irq_save(flags);
892 /* Probes */
893 outb(inb(0x1F2) | 0x80, 0x1F2);
894 inb(0x1F5);
895 inb(0x1F2);
896 inb(0x3F6);
897 inb(0x3F6);
898 inb(0x1F2);
899 inb(0x1F2);
900
901 if ((inb(0x1F2) & 0x80) == 0) {
902 /* PDC20230c or 20630 ? */
903 printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller"
904 " detected.\n");
905 udelay(100);
906 inb(0x1F5);
907 local_irq_restore(flags);
908 return PDC20230;
909 } else {
910 outb(0x55, 0x1F2);
911 inb(0x1F2);
912 inb(0x1F2);
913 if (inb(0x1F2) == 0x00)
914 printk(KERN_INFO "PDC20230-B VLB ATA "
915 "controller detected.\n");
916 local_irq_restore(flags);
917 return BIOS;
918 }
919 }
920
921 if (ht6560a & mask)
922 return HT6560A;
923 if (ht6560b & mask)
924 return HT6560B;
925 if (opti82c611a & mask)
926 return OPTI611A;
927 if (opti82c46x & mask)
928 return OPTI46X;
929 if (autospeed & mask)
930 return SNOOP;
931 return BIOS;
932}
933
934
935/**
936 * legacy_init_one - attach a legacy interface
937 * @pl: probe record
938 *
939 * Register an ISA bus IDE interface. Such interfaces are PIO and we
940 * assume do not support IRQ sharing.
941 */
942
943static __init int legacy_init_one(struct legacy_probe *probe)
944{
945 struct legacy_controller *controller = &controllers[probe->type];
946 int pio_modes = controller->pio_mask;
947 unsigned long io = probe->port;
948 u32 mask = (1 << probe->slot);
949 struct ata_port_operations *ops = controller->ops;
950 struct legacy_data *ld = &legacy_data[probe->slot];
951 struct ata_host *host = NULL;
952 struct ata_port *ap;
953 struct platform_device *pdev;
954 struct ata_device *dev;
955 void __iomem *io_addr, *ctrl_addr;
956 u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY;
957 int ret;
958
959 iordy |= controller->flags;
960
961 pdev = platform_device_register_simple(DRV_NAME, probe->slot, NULL, 0);
962 if (IS_ERR(pdev))
963 return PTR_ERR(pdev);
964
965 ret = -EBUSY;
966 if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL ||
967 devm_request_region(&pdev->dev, io + 0x0206, 1,
968 "pata_legacy") == NULL)
969 goto fail;
970
971 ret = -ENOMEM;
972 io_addr = devm_ioport_map(&pdev->dev, io, 8);
973 ctrl_addr = devm_ioport_map(&pdev->dev, io + 0x0206, 1);
974 if (!io_addr || !ctrl_addr)
975 goto fail;
976 ld->type = probe->type;
977 if (controller->setup)
978 if (controller->setup(pdev, probe, ld) < 0)
979 goto fail;
980 host = ata_host_alloc(&pdev->dev, 1);
981 if (!host)
982 goto fail;
983 ap = host->ports[0];
984
985 ap->ops = ops;
986 ap->pio_mask = pio_modes;
987 ap->flags |= ATA_FLAG_SLAVE_POSS | iordy;
988 ap->pflags |= controller->pflags;
989 ap->ioaddr.cmd_addr = io_addr;
990 ap->ioaddr.altstatus_addr = ctrl_addr;
991 ap->ioaddr.ctl_addr = ctrl_addr;
992 ata_sff_std_ports(&ap->ioaddr);
993 ap->host->private_data = ld;
994
995 ata_port_desc(ap, "cmd 0x%lx ctl 0x%lx", io, io + 0x0206);
996
997 ret = ata_host_activate(host, probe->irq, ata_sff_interrupt, 0,
998 &legacy_sht);
999 if (ret)
1000 goto fail;
1001 async_synchronize_full();
1002 ld->platform_dev = pdev;
1003
1004 /* Nothing found means we drop the port as its probably not there */
1005
1006 ret = -ENODEV;
1007 ata_for_each_dev(dev, &ap->link, ALL) {
1008 if (!ata_dev_absent(dev)) {
1009 legacy_host[probe->slot] = host;
1010 ld->platform_dev = pdev;
1011 return 0;
1012 }
1013 }
1014 ata_host_detach(host);
1015fail:
1016 platform_device_unregister(pdev);
1017 return ret;
1018}
1019
1020/**
1021 * legacy_check_special_cases - ATA special cases
1022 * @p: PCI device to check
1023 * @master: set this if we find an ATA master
1024 * @master: set this if we find an ATA secondary
1025 *
1026 * A small number of vendors implemented early PCI ATA interfaces
1027 * on bridge logic without the ATA interface being PCI visible.
1028 * Where we have a matching PCI driver we must skip the relevant
1029 * device here. If we don't know about it then the legacy driver
1030 * is the right driver anyway.
1031 */
1032
1033static void __init legacy_check_special_cases(struct pci_dev *p, int *primary,
1034 int *secondary)
1035{
1036 /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */
1037 if (p->vendor == 0x1078 && p->device == 0x0000) {
1038 *primary = *secondary = 1;
1039 return;
1040 }
1041 /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */
1042 if (p->vendor == 0x1078 && p->device == 0x0002) {
1043 *primary = *secondary = 1;
1044 return;
1045 }
1046 /* Intel MPIIX - PIO ATA on non PCI side of bridge */
1047 if (p->vendor == 0x8086 && p->device == 0x1234) {
1048 u16 r;
1049 pci_read_config_word(p, 0x6C, &r);
1050 if (r & 0x8000) {
1051 /* ATA port enabled */
1052 if (r & 0x4000)
1053 *secondary = 1;
1054 else
1055 *primary = 1;
1056 }
1057 return;
1058 }
1059}
1060
1061static __init void probe_opti_vlb(void)
1062{
1063 /* If an OPTI 82C46X is present find out where the channels are */
1064 static const char *optis[4] = {
1065 "3/463MV", "5MV",
1066 "5MVA", "5MVB"
1067 };
1068 u8 chans = 1;
1069 u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6;
1070
1071 opti82c46x = 3; /* Assume master and slave first */
1072 printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n",
1073 optis[ctrl]);
1074 if (ctrl == 3)
1075 chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1;
1076 ctrl = opti_syscfg(0xAC);
1077 /* Check enabled and this port is the 465MV port. On the
1078 MVB we may have two channels */
1079 if (ctrl & 8) {
1080 if (chans == 2) {
1081 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1082 legacy_probe_add(0x170, 15, OPTI46X, 0);
1083 }
1084 if (ctrl & 4)
1085 legacy_probe_add(0x170, 15, OPTI46X, 0);
1086 else
1087 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1088 } else
1089 legacy_probe_add(0x1F0, 14, OPTI46X, 0);
1090}
1091
1092static __init void qdi65_identify_port(u8 r, u8 res, unsigned long port)
1093{
1094 static const unsigned long ide_port[2] = { 0x170, 0x1F0 };
1095 /* Check card type */
1096 if ((r & 0xF0) == 0xC0) {
1097 /* QD6500: single channel */
1098 if (r & 8)
1099 /* Disabled ? */
1100 return;
1101 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),
1102 QDI6500, port);
1103 }
1104 if (((r & 0xF0) == 0xA0) || (r & 0xF0) == 0x50) {
1105 /* QD6580: dual channel */
1106 if (!request_region(port + 2 , 2, "pata_qdi")) {
1107 release_region(port, 2);
1108 return;
1109 }
1110 res = inb(port + 3);
1111 /* Single channel mode ? */
1112 if (res & 1)
1113 legacy_probe_add(ide_port[r & 0x01], 14 + (r & 0x01),
1114 QDI6580, port);
1115 else { /* Dual channel mode */
1116 legacy_probe_add(0x1F0, 14, QDI6580DP, port);
1117 /* port + 0x02, r & 0x04 */
1118 legacy_probe_add(0x170, 15, QDI6580DP, port + 2);
1119 }
1120 release_region(port + 2, 2);
1121 }
1122}
1123
1124static __init void probe_qdi_vlb(void)
1125{
1126 unsigned long flags;
1127 static const unsigned long qd_port[2] = { 0x30, 0xB0 };
1128 int i;
1129
1130 /*
1131 * Check each possible QD65xx base address
1132 */
1133
1134 for (i = 0; i < 2; i++) {
1135 unsigned long port = qd_port[i];
1136 u8 r, res;
1137
1138
1139 if (request_region(port, 2, "pata_qdi")) {
1140 /* Check for a card */
1141 local_irq_save(flags);
1142 /* I have no h/w that needs this delay but it
1143 is present in the historic code */
1144 r = inb(port);
1145 udelay(1);
1146 outb(0x19, port);
1147 udelay(1);
1148 res = inb(port);
1149 udelay(1);
1150 outb(r, port);
1151 udelay(1);
1152 local_irq_restore(flags);
1153
1154 /* Fail */
1155 if (res == 0x19) {
1156 release_region(port, 2);
1157 continue;
1158 }
1159 /* Passes the presence test */
1160 r = inb(port + 1);
1161 udelay(1);
1162 /* Check port agrees with port set */
1163 if ((r & 2) >> 1 == i)
1164 qdi65_identify_port(r, res, port);
1165 release_region(port, 2);
1166 }
1167 }
1168}
1169
1170/**
1171 * legacy_init - attach legacy interfaces
1172 *
1173 * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects.
1174 * Right now we do not scan the ide0 and ide1 address but should do so
1175 * for non PCI systems or systems with no PCI IDE legacy mode devices.
1176 * If you fix that note there are special cases to consider like VLB
1177 * drivers and CS5510/20.
1178 */
1179
1180static __init int legacy_init(void)
1181{
1182 int i;
1183 int ct = 0;
1184 int primary = 0;
1185 int secondary = 0;
1186 int pci_present = 0;
1187 struct legacy_probe *pl = &probe_list[0];
1188 int slot = 0;
1189
1190 struct pci_dev *p = NULL;
1191
1192 for_each_pci_dev(p) {
1193 int r;
1194 /* Check for any overlap of the system ATA mappings. Native
1195 mode controllers stuck on these addresses or some devices
1196 in 'raid' mode won't be found by the storage class test */
1197 for (r = 0; r < 6; r++) {
1198 if (pci_resource_start(p, r) == 0x1f0)
1199 primary = 1;
1200 if (pci_resource_start(p, r) == 0x170)
1201 secondary = 1;
1202 }
1203 /* Check for special cases */
1204 legacy_check_special_cases(p, &primary, &secondary);
1205
1206 /* If PCI bus is present then don't probe for tertiary
1207 legacy ports */
1208 pci_present = 1;
1209 }
1210
1211 if (winbond == 1)
1212 winbond = 0x130; /* Default port, alt is 1B0 */
1213
1214 if (primary == 0 || all)
1215 legacy_probe_add(0x1F0, 14, UNKNOWN, 0);
1216 if (secondary == 0 || all)
1217 legacy_probe_add(0x170, 15, UNKNOWN, 0);
1218
1219 if (probe_all || !pci_present) {
1220 /* ISA/VLB extra ports */
1221 legacy_probe_add(0x1E8, 11, UNKNOWN, 0);
1222 legacy_probe_add(0x168, 10, UNKNOWN, 0);
1223 legacy_probe_add(0x1E0, 8, UNKNOWN, 0);
1224 legacy_probe_add(0x160, 12, UNKNOWN, 0);
1225 }
1226
1227 if (opti82c46x)
1228 probe_opti_vlb();
1229 if (qdi)
1230 probe_qdi_vlb();
1231
1232 for (i = 0; i < NR_HOST; i++, pl++) {
1233 if (pl->port == 0)
1234 continue;
1235 if (pl->type == UNKNOWN)
1236 pl->type = probe_chip_type(pl);
1237 pl->slot = slot++;
1238 if (legacy_init_one(pl) == 0)
1239 ct++;
1240 }
1241 if (ct != 0)
1242 return 0;
1243 return -ENODEV;
1244}
1245
1246static __exit void legacy_exit(void)
1247{
1248 int i;
1249
1250 for (i = 0; i < nr_legacy_host; i++) {
1251 struct legacy_data *ld = &legacy_data[i];
1252 ata_host_detach(legacy_host[i]);
1253 platform_device_unregister(ld->platform_dev);
1254 }
1255}
1256
1257MODULE_AUTHOR("Alan Cox");
1258MODULE_DESCRIPTION("low-level driver for legacy ATA");
1259MODULE_LICENSE("GPL");
1260MODULE_VERSION(DRV_VERSION);
1261MODULE_ALIAS("pata_qdi");
1262MODULE_ALIAS("pata_winbond");
1263
1264module_param(probe_all, int, 0);
1265module_param(autospeed, int, 0);
1266module_param(ht6560a, int, 0);
1267module_param(ht6560b, int, 0);
1268module_param(opti82c611a, int, 0);
1269module_param(opti82c46x, int, 0);
1270module_param(qdi, int, 0);
1271module_param(winbond, int, 0);
1272module_param(pio_mask, int, 0);
1273module_param(iordy_mask, int, 0);
1274
1275module_init(legacy_init);
1276module_exit(legacy_exit);