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1// SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * x86 SMP booting functions
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7 * Copyright 2001 Andi Kleen, SuSE Labs.
8 *
9 * Much of the core SMP work is based on previous work by Thomas Radke, to
10 * whom a great many thanks are extended.
11 *
12 * Thanks to Intel for making available several different Pentium,
13 * Pentium Pro and Pentium-II/Xeon MP machines.
14 * Original development of Linux SMP code supported by Caldera.
15 *
16 * Fixes
17 * Felix Koop : NR_CPUS used properly
18 * Jose Renau : Handle single CPU case.
19 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
20 * Greg Wright : Fix for kernel stacks panic.
21 * Erich Boleyn : MP v1.4 and additional changes.
22 * Matthias Sattler : Changes for 2.1 kernel map.
23 * Michel Lespinasse : Changes for 2.1 kernel map.
24 * Michael Chastain : Change trampoline.S to gnu as.
25 * Alan Cox : Dumb bug: 'B' step PPro's are fine
26 * Ingo Molnar : Added APIC timers, based on code
27 * from Jose Renau
28 * Ingo Molnar : various cleanups and rewrites
29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
31 * Andi Kleen : Changed for SMP boot into long mode.
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
35 * Andi Kleen : Converted to new state machine.
36 * Ashok Raj : CPU hotplug support
37 * Glauber Costa : i386 and x86_64 integration
38 */
39
40#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
41
42#include <linux/init.h>
43#include <linux/smp.h>
44#include <linux/export.h>
45#include <linux/sched.h>
46#include <linux/sched/topology.h>
47#include <linux/sched/hotplug.h>
48#include <linux/sched/task_stack.h>
49#include <linux/percpu.h>
50#include <linux/memblock.h>
51#include <linux/err.h>
52#include <linux/nmi.h>
53#include <linux/tboot.h>
54#include <linux/stackprotector.h>
55#include <linux/gfp.h>
56#include <linux/cpuidle.h>
57#include <linux/numa.h>
58
59#include <asm/acpi.h>
60#include <asm/desc.h>
61#include <asm/nmi.h>
62#include <asm/irq.h>
63#include <asm/realmode.h>
64#include <asm/cpu.h>
65#include <asm/numa.h>
66#include <asm/pgtable.h>
67#include <asm/tlbflush.h>
68#include <asm/mtrr.h>
69#include <asm/mwait.h>
70#include <asm/apic.h>
71#include <asm/io_apic.h>
72#include <asm/fpu/internal.h>
73#include <asm/setup.h>
74#include <asm/uv/uv.h>
75#include <linux/mc146818rtc.h>
76#include <asm/i8259.h>
77#include <asm/misc.h>
78#include <asm/qspinlock.h>
79#include <asm/intel-family.h>
80#include <asm/cpu_device_id.h>
81#include <asm/spec-ctrl.h>
82#include <asm/hw_irq.h>
83
84/* representing HT siblings of each logical CPU */
85DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
86EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
87
88/* representing HT and core siblings of each logical CPU */
89DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
90EXPORT_PER_CPU_SYMBOL(cpu_core_map);
91
92/* representing HT, core, and die siblings of each logical CPU */
93DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map);
94EXPORT_PER_CPU_SYMBOL(cpu_die_map);
95
96DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
97
98/* Per CPU bogomips and other parameters */
99DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
100EXPORT_PER_CPU_SYMBOL(cpu_info);
101
102/* Logical package management. We might want to allocate that dynamically */
103unsigned int __max_logical_packages __read_mostly;
104EXPORT_SYMBOL(__max_logical_packages);
105static unsigned int logical_packages __read_mostly;
106static unsigned int logical_die __read_mostly;
107
108/* Maximum number of SMT threads on any online core */
109int __read_mostly __max_smt_threads = 1;
110
111/* Flag to indicate if a complete sched domain rebuild is required */
112bool x86_topology_update;
113
114int arch_update_cpu_topology(void)
115{
116 int retval = x86_topology_update;
117
118 x86_topology_update = false;
119 return retval;
120}
121
122static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
123{
124 unsigned long flags;
125
126 spin_lock_irqsave(&rtc_lock, flags);
127 CMOS_WRITE(0xa, 0xf);
128 spin_unlock_irqrestore(&rtc_lock, flags);
129 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
130 start_eip >> 4;
131 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
132 start_eip & 0xf;
133}
134
135static inline void smpboot_restore_warm_reset_vector(void)
136{
137 unsigned long flags;
138
139 /*
140 * Paranoid: Set warm reset code and vector here back
141 * to default values.
142 */
143 spin_lock_irqsave(&rtc_lock, flags);
144 CMOS_WRITE(0, 0xf);
145 spin_unlock_irqrestore(&rtc_lock, flags);
146
147 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
148}
149
150/*
151 * Report back to the Boot Processor during boot time or to the caller processor
152 * during CPU online.
153 */
154static void smp_callin(void)
155{
156 int cpuid;
157
158 /*
159 * If waken up by an INIT in an 82489DX configuration
160 * cpu_callout_mask guarantees we don't get here before
161 * an INIT_deassert IPI reaches our local APIC, so it is
162 * now safe to touch our local APIC.
163 */
164 cpuid = smp_processor_id();
165
166 /*
167 * the boot CPU has finished the init stage and is spinning
168 * on callin_map until we finish. We are free to set up this
169 * CPU, first the APIC. (this is probably redundant on most
170 * boards)
171 */
172 apic_ap_setup();
173
174 /*
175 * Save our processor parameters. Note: this information
176 * is needed for clock calibration.
177 */
178 smp_store_cpu_info(cpuid);
179
180 /*
181 * The topology information must be up to date before
182 * calibrate_delay() and notify_cpu_starting().
183 */
184 set_cpu_sibling_map(raw_smp_processor_id());
185
186 /*
187 * Get our bogomips.
188 * Update loops_per_jiffy in cpu_data. Previous call to
189 * smp_store_cpu_info() stored a value that is close but not as
190 * accurate as the value just calculated.
191 */
192 calibrate_delay();
193 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
194 pr_debug("Stack at about %p\n", &cpuid);
195
196 wmb();
197
198 notify_cpu_starting(cpuid);
199
200 /*
201 * Allow the master to continue.
202 */
203 cpumask_set_cpu(cpuid, cpu_callin_mask);
204}
205
206static int cpu0_logical_apicid;
207static int enable_start_cpu0;
208/*
209 * Activate a secondary processor.
210 */
211static void notrace start_secondary(void *unused)
212{
213 /*
214 * Don't put *anything* except direct CPU state initialization
215 * before cpu_init(), SMP booting is too fragile that we want to
216 * limit the things done here to the most necessary things.
217 */
218 cr4_init();
219
220#ifdef CONFIG_X86_32
221 /* switch away from the initial page table */
222 load_cr3(swapper_pg_dir);
223 __flush_tlb_all();
224#endif
225 load_current_idt();
226 cpu_init();
227 x86_cpuinit.early_percpu_clock_init();
228 preempt_disable();
229 smp_callin();
230
231 enable_start_cpu0 = 0;
232
233 /* otherwise gcc will move up smp_processor_id before the cpu_init */
234 barrier();
235 /*
236 * Check TSC synchronization with the boot CPU:
237 */
238 check_tsc_sync_target();
239
240 speculative_store_bypass_ht_init();
241
242 /*
243 * Lock vector_lock, set CPU online and bring the vector
244 * allocator online. Online must be set with vector_lock held
245 * to prevent a concurrent irq setup/teardown from seeing a
246 * half valid vector space.
247 */
248 lock_vector_lock();
249 set_cpu_online(smp_processor_id(), true);
250 lapic_online();
251 unlock_vector_lock();
252 cpu_set_state_online(smp_processor_id());
253 x86_platform.nmi_init();
254
255 /* enable local interrupts */
256 local_irq_enable();
257
258 /* to prevent fake stack check failure in clock setup */
259 boot_init_stack_canary();
260
261 x86_cpuinit.setup_percpu_clockev();
262
263 wmb();
264 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
265}
266
267/**
268 * topology_is_primary_thread - Check whether CPU is the primary SMT thread
269 * @cpu: CPU to check
270 */
271bool topology_is_primary_thread(unsigned int cpu)
272{
273 return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu));
274}
275
276/**
277 * topology_smt_supported - Check whether SMT is supported by the CPUs
278 */
279bool topology_smt_supported(void)
280{
281 return smp_num_siblings > 1;
282}
283
284/**
285 * topology_phys_to_logical_pkg - Map a physical package id to a logical
286 *
287 * Returns logical package id or -1 if not found
288 */
289int topology_phys_to_logical_pkg(unsigned int phys_pkg)
290{
291 int cpu;
292
293 for_each_possible_cpu(cpu) {
294 struct cpuinfo_x86 *c = &cpu_data(cpu);
295
296 if (c->initialized && c->phys_proc_id == phys_pkg)
297 return c->logical_proc_id;
298 }
299 return -1;
300}
301EXPORT_SYMBOL(topology_phys_to_logical_pkg);
302/**
303 * topology_phys_to_logical_die - Map a physical die id to logical
304 *
305 * Returns logical die id or -1 if not found
306 */
307int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu)
308{
309 int cpu;
310 int proc_id = cpu_data(cur_cpu).phys_proc_id;
311
312 for_each_possible_cpu(cpu) {
313 struct cpuinfo_x86 *c = &cpu_data(cpu);
314
315 if (c->initialized && c->cpu_die_id == die_id &&
316 c->phys_proc_id == proc_id)
317 return c->logical_die_id;
318 }
319 return -1;
320}
321EXPORT_SYMBOL(topology_phys_to_logical_die);
322
323/**
324 * topology_update_package_map - Update the physical to logical package map
325 * @pkg: The physical package id as retrieved via CPUID
326 * @cpu: The cpu for which this is updated
327 */
328int topology_update_package_map(unsigned int pkg, unsigned int cpu)
329{
330 int new;
331
332 /* Already available somewhere? */
333 new = topology_phys_to_logical_pkg(pkg);
334 if (new >= 0)
335 goto found;
336
337 new = logical_packages++;
338 if (new != pkg) {
339 pr_info("CPU %u Converting physical %u to logical package %u\n",
340 cpu, pkg, new);
341 }
342found:
343 cpu_data(cpu).logical_proc_id = new;
344 return 0;
345}
346/**
347 * topology_update_die_map - Update the physical to logical die map
348 * @die: The die id as retrieved via CPUID
349 * @cpu: The cpu for which this is updated
350 */
351int topology_update_die_map(unsigned int die, unsigned int cpu)
352{
353 int new;
354
355 /* Already available somewhere? */
356 new = topology_phys_to_logical_die(die, cpu);
357 if (new >= 0)
358 goto found;
359
360 new = logical_die++;
361 if (new != die) {
362 pr_info("CPU %u Converting physical %u to logical die %u\n",
363 cpu, die, new);
364 }
365found:
366 cpu_data(cpu).logical_die_id = new;
367 return 0;
368}
369
370void __init smp_store_boot_cpu_info(void)
371{
372 int id = 0; /* CPU 0 */
373 struct cpuinfo_x86 *c = &cpu_data(id);
374
375 *c = boot_cpu_data;
376 c->cpu_index = id;
377 topology_update_package_map(c->phys_proc_id, id);
378 topology_update_die_map(c->cpu_die_id, id);
379 c->initialized = true;
380}
381
382/*
383 * The bootstrap kernel entry code has set these up. Save them for
384 * a given CPU
385 */
386void smp_store_cpu_info(int id)
387{
388 struct cpuinfo_x86 *c = &cpu_data(id);
389
390 /* Copy boot_cpu_data only on the first bringup */
391 if (!c->initialized)
392 *c = boot_cpu_data;
393 c->cpu_index = id;
394 /*
395 * During boot time, CPU0 has this setup already. Save the info when
396 * bringing up AP or offlined CPU0.
397 */
398 identify_secondary_cpu(c);
399 c->initialized = true;
400}
401
402static bool
403topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
404{
405 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
406
407 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
408}
409
410static bool
411topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
412{
413 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
414
415 return !WARN_ONCE(!topology_same_node(c, o),
416 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
417 "[node: %d != %d]. Ignoring dependency.\n",
418 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
419}
420
421#define link_mask(mfunc, c1, c2) \
422do { \
423 cpumask_set_cpu((c1), mfunc(c2)); \
424 cpumask_set_cpu((c2), mfunc(c1)); \
425} while (0)
426
427static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
428{
429 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
430 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
431
432 if (c->phys_proc_id == o->phys_proc_id &&
433 c->cpu_die_id == o->cpu_die_id &&
434 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) {
435 if (c->cpu_core_id == o->cpu_core_id)
436 return topology_sane(c, o, "smt");
437
438 if ((c->cu_id != 0xff) &&
439 (o->cu_id != 0xff) &&
440 (c->cu_id == o->cu_id))
441 return topology_sane(c, o, "smt");
442 }
443
444 } else if (c->phys_proc_id == o->phys_proc_id &&
445 c->cpu_die_id == o->cpu_die_id &&
446 c->cpu_core_id == o->cpu_core_id) {
447 return topology_sane(c, o, "smt");
448 }
449
450 return false;
451}
452
453/*
454 * Define snc_cpu[] for SNC (Sub-NUMA Cluster) CPUs.
455 *
456 * These are Intel CPUs that enumerate an LLC that is shared by
457 * multiple NUMA nodes. The LLC on these systems is shared for
458 * off-package data access but private to the NUMA node (half
459 * of the package) for on-package access.
460 *
461 * CPUID (the source of the information about the LLC) can only
462 * enumerate the cache as being shared *or* unshared, but not
463 * this particular configuration. The CPU in this case enumerates
464 * the cache to be shared across the entire package (spanning both
465 * NUMA nodes).
466 */
467
468static const struct x86_cpu_id snc_cpu[] = {
469 { X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_X },
470 {}
471};
472
473static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
474{
475 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
476
477 /* Do not match if we do not have a valid APICID for cpu: */
478 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID)
479 return false;
480
481 /* Do not match if LLC id does not match: */
482 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2))
483 return false;
484
485 /*
486 * Allow the SNC topology without warning. Return of false
487 * means 'c' does not share the LLC of 'o'. This will be
488 * reflected to userspace.
489 */
490 if (!topology_same_node(c, o) && x86_match_cpu(snc_cpu))
491 return false;
492
493 return topology_sane(c, o, "llc");
494}
495
496/*
497 * Unlike the other levels, we do not enforce keeping a
498 * multicore group inside a NUMA node. If this happens, we will
499 * discard the MC level of the topology later.
500 */
501static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
502{
503 if (c->phys_proc_id == o->phys_proc_id)
504 return true;
505 return false;
506}
507
508static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
509{
510 if ((c->phys_proc_id == o->phys_proc_id) &&
511 (c->cpu_die_id == o->cpu_die_id))
512 return true;
513 return false;
514}
515
516
517#if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
518static inline int x86_sched_itmt_flags(void)
519{
520 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
521}
522
523#ifdef CONFIG_SCHED_MC
524static int x86_core_flags(void)
525{
526 return cpu_core_flags() | x86_sched_itmt_flags();
527}
528#endif
529#ifdef CONFIG_SCHED_SMT
530static int x86_smt_flags(void)
531{
532 return cpu_smt_flags() | x86_sched_itmt_flags();
533}
534#endif
535#endif
536
537static struct sched_domain_topology_level x86_numa_in_package_topology[] = {
538#ifdef CONFIG_SCHED_SMT
539 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
540#endif
541#ifdef CONFIG_SCHED_MC
542 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
543#endif
544 { NULL, },
545};
546
547static struct sched_domain_topology_level x86_topology[] = {
548#ifdef CONFIG_SCHED_SMT
549 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
550#endif
551#ifdef CONFIG_SCHED_MC
552 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
553#endif
554 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
555 { NULL, },
556};
557
558/*
559 * Set if a package/die has multiple NUMA nodes inside.
560 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel
561 * Sub-NUMA Clustering have this.
562 */
563static bool x86_has_numa_in_package;
564
565void set_cpu_sibling_map(int cpu)
566{
567 bool has_smt = smp_num_siblings > 1;
568 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
569 struct cpuinfo_x86 *c = &cpu_data(cpu);
570 struct cpuinfo_x86 *o;
571 int i, threads;
572
573 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
574
575 if (!has_mp) {
576 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
577 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
578 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
579 cpumask_set_cpu(cpu, topology_die_cpumask(cpu));
580 c->booted_cores = 1;
581 return;
582 }
583
584 for_each_cpu(i, cpu_sibling_setup_mask) {
585 o = &cpu_data(i);
586
587 if ((i == cpu) || (has_smt && match_smt(c, o)))
588 link_mask(topology_sibling_cpumask, cpu, i);
589
590 if ((i == cpu) || (has_mp && match_llc(c, o)))
591 link_mask(cpu_llc_shared_mask, cpu, i);
592
593 }
594
595 /*
596 * This needs a separate iteration over the cpus because we rely on all
597 * topology_sibling_cpumask links to be set-up.
598 */
599 for_each_cpu(i, cpu_sibling_setup_mask) {
600 o = &cpu_data(i);
601
602 if ((i == cpu) || (has_mp && match_pkg(c, o))) {
603 link_mask(topology_core_cpumask, cpu, i);
604
605 /*
606 * Does this new cpu bringup a new core?
607 */
608 if (cpumask_weight(
609 topology_sibling_cpumask(cpu)) == 1) {
610 /*
611 * for each core in package, increment
612 * the booted_cores for this new cpu
613 */
614 if (cpumask_first(
615 topology_sibling_cpumask(i)) == i)
616 c->booted_cores++;
617 /*
618 * increment the core count for all
619 * the other cpus in this package
620 */
621 if (i != cpu)
622 cpu_data(i).booted_cores++;
623 } else if (i != cpu && !c->booted_cores)
624 c->booted_cores = cpu_data(i).booted_cores;
625 }
626 if (match_pkg(c, o) && !topology_same_node(c, o))
627 x86_has_numa_in_package = true;
628
629 if ((i == cpu) || (has_mp && match_die(c, o)))
630 link_mask(topology_die_cpumask, cpu, i);
631 }
632
633 threads = cpumask_weight(topology_sibling_cpumask(cpu));
634 if (threads > __max_smt_threads)
635 __max_smt_threads = threads;
636}
637
638/* maps the cpu to the sched domain representing multi-core */
639const struct cpumask *cpu_coregroup_mask(int cpu)
640{
641 return cpu_llc_shared_mask(cpu);
642}
643
644static void impress_friends(void)
645{
646 int cpu;
647 unsigned long bogosum = 0;
648 /*
649 * Allow the user to impress friends.
650 */
651 pr_debug("Before bogomips\n");
652 for_each_possible_cpu(cpu)
653 if (cpumask_test_cpu(cpu, cpu_callout_mask))
654 bogosum += cpu_data(cpu).loops_per_jiffy;
655 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
656 num_online_cpus(),
657 bogosum/(500000/HZ),
658 (bogosum/(5000/HZ))%100);
659
660 pr_debug("Before bogocount - setting activated=1\n");
661}
662
663void __inquire_remote_apic(int apicid)
664{
665 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
666 const char * const names[] = { "ID", "VERSION", "SPIV" };
667 int timeout;
668 u32 status;
669
670 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
671
672 for (i = 0; i < ARRAY_SIZE(regs); i++) {
673 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
674
675 /*
676 * Wait for idle.
677 */
678 status = safe_apic_wait_icr_idle();
679 if (status)
680 pr_cont("a previous APIC delivery may have failed\n");
681
682 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
683
684 timeout = 0;
685 do {
686 udelay(100);
687 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
688 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
689
690 switch (status) {
691 case APIC_ICR_RR_VALID:
692 status = apic_read(APIC_RRR);
693 pr_cont("%08x\n", status);
694 break;
695 default:
696 pr_cont("failed\n");
697 }
698 }
699}
700
701/*
702 * The Multiprocessor Specification 1.4 (1997) example code suggests
703 * that there should be a 10ms delay between the BSP asserting INIT
704 * and de-asserting INIT, when starting a remote processor.
705 * But that slows boot and resume on modern processors, which include
706 * many cores and don't require that delay.
707 *
708 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
709 * Modern processor families are quirked to remove the delay entirely.
710 */
711#define UDELAY_10MS_DEFAULT 10000
712
713static unsigned int init_udelay = UINT_MAX;
714
715static int __init cpu_init_udelay(char *str)
716{
717 get_option(&str, &init_udelay);
718
719 return 0;
720}
721early_param("cpu_init_udelay", cpu_init_udelay);
722
723static void __init smp_quirk_init_udelay(void)
724{
725 /* if cmdline changed it from default, leave it alone */
726 if (init_udelay != UINT_MAX)
727 return;
728
729 /* if modern processor, use no delay */
730 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
731 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) ||
732 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
733 init_udelay = 0;
734 return;
735 }
736 /* else, use legacy delay */
737 init_udelay = UDELAY_10MS_DEFAULT;
738}
739
740/*
741 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
742 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
743 * won't ... remember to clear down the APIC, etc later.
744 */
745int
746wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
747{
748 unsigned long send_status, accept_status = 0;
749 int maxlvt;
750
751 /* Target chip */
752 /* Boot on the stack */
753 /* Kick the second */
754 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
755
756 pr_debug("Waiting for send to finish...\n");
757 send_status = safe_apic_wait_icr_idle();
758
759 /*
760 * Give the other CPU some time to accept the IPI.
761 */
762 udelay(200);
763 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
764 maxlvt = lapic_get_maxlvt();
765 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
766 apic_write(APIC_ESR, 0);
767 accept_status = (apic_read(APIC_ESR) & 0xEF);
768 }
769 pr_debug("NMI sent\n");
770
771 if (send_status)
772 pr_err("APIC never delivered???\n");
773 if (accept_status)
774 pr_err("APIC delivery error (%lx)\n", accept_status);
775
776 return (send_status | accept_status);
777}
778
779static int
780wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
781{
782 unsigned long send_status = 0, accept_status = 0;
783 int maxlvt, num_starts, j;
784
785 maxlvt = lapic_get_maxlvt();
786
787 /*
788 * Be paranoid about clearing APIC errors.
789 */
790 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
791 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
792 apic_write(APIC_ESR, 0);
793 apic_read(APIC_ESR);
794 }
795
796 pr_debug("Asserting INIT\n");
797
798 /*
799 * Turn INIT on target chip
800 */
801 /*
802 * Send IPI
803 */
804 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
805 phys_apicid);
806
807 pr_debug("Waiting for send to finish...\n");
808 send_status = safe_apic_wait_icr_idle();
809
810 udelay(init_udelay);
811
812 pr_debug("Deasserting INIT\n");
813
814 /* Target chip */
815 /* Send IPI */
816 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
817
818 pr_debug("Waiting for send to finish...\n");
819 send_status = safe_apic_wait_icr_idle();
820
821 mb();
822
823 /*
824 * Should we send STARTUP IPIs ?
825 *
826 * Determine this based on the APIC version.
827 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
828 */
829 if (APIC_INTEGRATED(boot_cpu_apic_version))
830 num_starts = 2;
831 else
832 num_starts = 0;
833
834 /*
835 * Run STARTUP IPI loop.
836 */
837 pr_debug("#startup loops: %d\n", num_starts);
838
839 for (j = 1; j <= num_starts; j++) {
840 pr_debug("Sending STARTUP #%d\n", j);
841 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
842 apic_write(APIC_ESR, 0);
843 apic_read(APIC_ESR);
844 pr_debug("After apic_write\n");
845
846 /*
847 * STARTUP IPI
848 */
849
850 /* Target chip */
851 /* Boot on the stack */
852 /* Kick the second */
853 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
854 phys_apicid);
855
856 /*
857 * Give the other CPU some time to accept the IPI.
858 */
859 if (init_udelay == 0)
860 udelay(10);
861 else
862 udelay(300);
863
864 pr_debug("Startup point 1\n");
865
866 pr_debug("Waiting for send to finish...\n");
867 send_status = safe_apic_wait_icr_idle();
868
869 /*
870 * Give the other CPU some time to accept the IPI.
871 */
872 if (init_udelay == 0)
873 udelay(10);
874 else
875 udelay(200);
876
877 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
878 apic_write(APIC_ESR, 0);
879 accept_status = (apic_read(APIC_ESR) & 0xEF);
880 if (send_status || accept_status)
881 break;
882 }
883 pr_debug("After Startup\n");
884
885 if (send_status)
886 pr_err("APIC never delivered???\n");
887 if (accept_status)
888 pr_err("APIC delivery error (%lx)\n", accept_status);
889
890 return (send_status | accept_status);
891}
892
893/* reduce the number of lines printed when booting a large cpu count system */
894static void announce_cpu(int cpu, int apicid)
895{
896 static int current_node = NUMA_NO_NODE;
897 int node = early_cpu_to_node(cpu);
898 static int width, node_width;
899
900 if (!width)
901 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
902
903 if (!node_width)
904 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
905
906 if (cpu == 1)
907 printk(KERN_INFO "x86: Booting SMP configuration:\n");
908
909 if (system_state < SYSTEM_RUNNING) {
910 if (node != current_node) {
911 if (current_node > (-1))
912 pr_cont("\n");
913 current_node = node;
914
915 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
916 node_width - num_digits(node), " ", node);
917 }
918
919 /* Add padding for the BSP */
920 if (cpu == 1)
921 pr_cont("%*s", width + 1, " ");
922
923 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
924
925 } else
926 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
927 node, cpu, apicid);
928}
929
930static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
931{
932 int cpu;
933
934 cpu = smp_processor_id();
935 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
936 return NMI_HANDLED;
937
938 return NMI_DONE;
939}
940
941/*
942 * Wake up AP by INIT, INIT, STARTUP sequence.
943 *
944 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
945 * boot-strap code which is not a desired behavior for waking up BSP. To
946 * void the boot-strap code, wake up CPU0 by NMI instead.
947 *
948 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
949 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
950 * We'll change this code in the future to wake up hard offlined CPU0 if
951 * real platform and request are available.
952 */
953static int
954wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
955 int *cpu0_nmi_registered)
956{
957 int id;
958 int boot_error;
959
960 preempt_disable();
961
962 /*
963 * Wake up AP by INIT, INIT, STARTUP sequence.
964 */
965 if (cpu) {
966 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
967 goto out;
968 }
969
970 /*
971 * Wake up BSP by nmi.
972 *
973 * Register a NMI handler to help wake up CPU0.
974 */
975 boot_error = register_nmi_handler(NMI_LOCAL,
976 wakeup_cpu0_nmi, 0, "wake_cpu0");
977
978 if (!boot_error) {
979 enable_start_cpu0 = 1;
980 *cpu0_nmi_registered = 1;
981 if (apic->dest_logical == APIC_DEST_LOGICAL)
982 id = cpu0_logical_apicid;
983 else
984 id = apicid;
985 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
986 }
987
988out:
989 preempt_enable();
990
991 return boot_error;
992}
993
994int common_cpu_up(unsigned int cpu, struct task_struct *idle)
995{
996 int ret;
997
998 /* Just in case we booted with a single CPU. */
999 alternatives_enable_smp();
1000
1001 per_cpu(current_task, cpu) = idle;
1002
1003 /* Initialize the interrupt stack(s) */
1004 ret = irq_init_percpu_irqstack(cpu);
1005 if (ret)
1006 return ret;
1007
1008#ifdef CONFIG_X86_32
1009 /* Stack for startup_32 can be just as for start_secondary onwards */
1010 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle);
1011#else
1012 initial_gs = per_cpu_offset(cpu);
1013#endif
1014 return 0;
1015}
1016
1017/*
1018 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
1019 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
1020 * Returns zero if CPU booted OK, else error code from
1021 * ->wakeup_secondary_cpu.
1022 */
1023static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle,
1024 int *cpu0_nmi_registered)
1025{
1026 /* start_ip had better be page-aligned! */
1027 unsigned long start_ip = real_mode_header->trampoline_start;
1028
1029 unsigned long boot_error = 0;
1030 unsigned long timeout;
1031
1032 idle->thread.sp = (unsigned long)task_pt_regs(idle);
1033 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
1034 initial_code = (unsigned long)start_secondary;
1035 initial_stack = idle->thread.sp;
1036
1037 /* Enable the espfix hack for this CPU */
1038 init_espfix_ap(cpu);
1039
1040 /* So we see what's up */
1041 announce_cpu(cpu, apicid);
1042
1043 /*
1044 * This grunge runs the startup process for
1045 * the targeted processor.
1046 */
1047
1048 if (x86_platform.legacy.warm_reset) {
1049
1050 pr_debug("Setting warm reset code and vector.\n");
1051
1052 smpboot_setup_warm_reset_vector(start_ip);
1053 /*
1054 * Be paranoid about clearing APIC errors.
1055 */
1056 if (APIC_INTEGRATED(boot_cpu_apic_version)) {
1057 apic_write(APIC_ESR, 0);
1058 apic_read(APIC_ESR);
1059 }
1060 }
1061
1062 /*
1063 * AP might wait on cpu_callout_mask in cpu_init() with
1064 * cpu_initialized_mask set if previous attempt to online
1065 * it timed-out. Clear cpu_initialized_mask so that after
1066 * INIT/SIPI it could start with a clean state.
1067 */
1068 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1069 smp_mb();
1070
1071 /*
1072 * Wake up a CPU in difference cases:
1073 * - Use the method in the APIC driver if it's defined
1074 * Otherwise,
1075 * - Use an INIT boot APIC message for APs or NMI for BSP.
1076 */
1077 if (apic->wakeup_secondary_cpu)
1078 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
1079 else
1080 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
1081 cpu0_nmi_registered);
1082
1083 if (!boot_error) {
1084 /*
1085 * Wait 10s total for first sign of life from AP
1086 */
1087 boot_error = -1;
1088 timeout = jiffies + 10*HZ;
1089 while (time_before(jiffies, timeout)) {
1090 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
1091 /*
1092 * Tell AP to proceed with initialization
1093 */
1094 cpumask_set_cpu(cpu, cpu_callout_mask);
1095 boot_error = 0;
1096 break;
1097 }
1098 schedule();
1099 }
1100 }
1101
1102 if (!boot_error) {
1103 /*
1104 * Wait till AP completes initial initialization
1105 */
1106 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
1107 /*
1108 * Allow other tasks to run while we wait for the
1109 * AP to come online. This also gives a chance
1110 * for the MTRR work(triggered by the AP coming online)
1111 * to be completed in the stop machine context.
1112 */
1113 schedule();
1114 }
1115 }
1116
1117 if (x86_platform.legacy.warm_reset) {
1118 /*
1119 * Cleanup possible dangling ends...
1120 */
1121 smpboot_restore_warm_reset_vector();
1122 }
1123
1124 return boot_error;
1125}
1126
1127int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
1128{
1129 int apicid = apic->cpu_present_to_apicid(cpu);
1130 int cpu0_nmi_registered = 0;
1131 unsigned long flags;
1132 int err, ret = 0;
1133
1134 lockdep_assert_irqs_enabled();
1135
1136 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1137
1138 if (apicid == BAD_APICID ||
1139 !physid_isset(apicid, phys_cpu_present_map) ||
1140 !apic->apic_id_valid(apicid)) {
1141 pr_err("%s: bad cpu %d\n", __func__, cpu);
1142 return -EINVAL;
1143 }
1144
1145 /*
1146 * Already booted CPU?
1147 */
1148 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
1149 pr_debug("do_boot_cpu %d Already started\n", cpu);
1150 return -ENOSYS;
1151 }
1152
1153 /*
1154 * Save current MTRR state in case it was changed since early boot
1155 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1156 */
1157 mtrr_save_state();
1158
1159 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1160 err = cpu_check_up_prepare(cpu);
1161 if (err && err != -EBUSY)
1162 return err;
1163
1164 /* the FPU context is blank, nobody can own it */
1165 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
1166
1167 err = common_cpu_up(cpu, tidle);
1168 if (err)
1169 return err;
1170
1171 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered);
1172 if (err) {
1173 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1174 ret = -EIO;
1175 goto unreg_nmi;
1176 }
1177
1178 /*
1179 * Check TSC synchronization with the AP (keep irqs disabled
1180 * while doing so):
1181 */
1182 local_irq_save(flags);
1183 check_tsc_sync_source(cpu);
1184 local_irq_restore(flags);
1185
1186 while (!cpu_online(cpu)) {
1187 cpu_relax();
1188 touch_nmi_watchdog();
1189 }
1190
1191unreg_nmi:
1192 /*
1193 * Clean up the nmi handler. Do this after the callin and callout sync
1194 * to avoid impact of possible long unregister time.
1195 */
1196 if (cpu0_nmi_registered)
1197 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1198
1199 return ret;
1200}
1201
1202/**
1203 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1204 */
1205void arch_disable_smp_support(void)
1206{
1207 disable_ioapic_support();
1208}
1209
1210/*
1211 * Fall back to non SMP mode after errors.
1212 *
1213 * RED-PEN audit/test this more. I bet there is more state messed up here.
1214 */
1215static __init void disable_smp(void)
1216{
1217 pr_info("SMP disabled\n");
1218
1219 disable_ioapic_support();
1220
1221 init_cpu_present(cpumask_of(0));
1222 init_cpu_possible(cpumask_of(0));
1223
1224 if (smp_found_config)
1225 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1226 else
1227 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1228 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1229 cpumask_set_cpu(0, topology_core_cpumask(0));
1230 cpumask_set_cpu(0, topology_die_cpumask(0));
1231}
1232
1233/*
1234 * Various sanity checks.
1235 */
1236static void __init smp_sanity_check(void)
1237{
1238 preempt_disable();
1239
1240#if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1241 if (def_to_bigsmp && nr_cpu_ids > 8) {
1242 unsigned int cpu;
1243 unsigned nr;
1244
1245 pr_warn("More than 8 CPUs detected - skipping them\n"
1246 "Use CONFIG_X86_BIGSMP\n");
1247
1248 nr = 0;
1249 for_each_present_cpu(cpu) {
1250 if (nr >= 8)
1251 set_cpu_present(cpu, false);
1252 nr++;
1253 }
1254
1255 nr = 0;
1256 for_each_possible_cpu(cpu) {
1257 if (nr >= 8)
1258 set_cpu_possible(cpu, false);
1259 nr++;
1260 }
1261
1262 nr_cpu_ids = 8;
1263 }
1264#endif
1265
1266 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1267 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1268 hard_smp_processor_id());
1269
1270 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1271 }
1272
1273 /*
1274 * Should not be necessary because the MP table should list the boot
1275 * CPU too, but we do it for the sake of robustness anyway.
1276 */
1277 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1278 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1279 boot_cpu_physical_apicid);
1280 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1281 }
1282 preempt_enable();
1283}
1284
1285static void __init smp_cpu_index_default(void)
1286{
1287 int i;
1288 struct cpuinfo_x86 *c;
1289
1290 for_each_possible_cpu(i) {
1291 c = &cpu_data(i);
1292 /* mark all to hotplug */
1293 c->cpu_index = nr_cpu_ids;
1294 }
1295}
1296
1297static void __init smp_get_logical_apicid(void)
1298{
1299 if (x2apic_mode)
1300 cpu0_logical_apicid = apic_read(APIC_LDR);
1301 else
1302 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1303}
1304
1305/*
1306 * Prepare for SMP bootup.
1307 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1308 * for common interface support.
1309 */
1310void __init native_smp_prepare_cpus(unsigned int max_cpus)
1311{
1312 unsigned int i;
1313
1314 smp_cpu_index_default();
1315
1316 /*
1317 * Setup boot CPU information
1318 */
1319 smp_store_boot_cpu_info(); /* Final full version of the data */
1320 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1321 mb();
1322
1323 for_each_possible_cpu(i) {
1324 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1325 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1326 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL);
1327 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1328 }
1329
1330 /*
1331 * Set 'default' x86 topology, this matches default_topology() in that
1332 * it has NUMA nodes as a topology level. See also
1333 * native_smp_cpus_done().
1334 *
1335 * Must be done before set_cpus_sibling_map() is ran.
1336 */
1337 set_sched_topology(x86_topology);
1338
1339 set_cpu_sibling_map(0);
1340
1341 smp_sanity_check();
1342
1343 switch (apic_intr_mode) {
1344 case APIC_PIC:
1345 case APIC_VIRTUAL_WIRE_NO_CONFIG:
1346 disable_smp();
1347 return;
1348 case APIC_SYMMETRIC_IO_NO_ROUTING:
1349 disable_smp();
1350 /* Setup local timer */
1351 x86_init.timers.setup_percpu_clockev();
1352 return;
1353 case APIC_VIRTUAL_WIRE:
1354 case APIC_SYMMETRIC_IO:
1355 break;
1356 }
1357
1358 /* Setup local timer */
1359 x86_init.timers.setup_percpu_clockev();
1360
1361 smp_get_logical_apicid();
1362
1363 pr_info("CPU0: ");
1364 print_cpu_info(&cpu_data(0));
1365
1366 uv_system_init();
1367
1368 set_mtrr_aps_delayed_init();
1369
1370 smp_quirk_init_udelay();
1371
1372 speculative_store_bypass_ht_init();
1373}
1374
1375void arch_enable_nonboot_cpus_begin(void)
1376{
1377 set_mtrr_aps_delayed_init();
1378}
1379
1380void arch_enable_nonboot_cpus_end(void)
1381{
1382 mtrr_aps_init();
1383}
1384
1385/*
1386 * Early setup to make printk work.
1387 */
1388void __init native_smp_prepare_boot_cpu(void)
1389{
1390 int me = smp_processor_id();
1391 switch_to_new_gdt(me);
1392 /* already set me in cpu_online_mask in boot_cpu_init() */
1393 cpumask_set_cpu(me, cpu_callout_mask);
1394 cpu_set_state_online(me);
1395 native_pv_lock_init();
1396}
1397
1398void __init calculate_max_logical_packages(void)
1399{
1400 int ncpus;
1401
1402 /*
1403 * Today neither Intel nor AMD support heterogenous systems so
1404 * extrapolate the boot cpu's data to all packages.
1405 */
1406 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads();
1407 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
1408 pr_info("Max logical packages: %u\n", __max_logical_packages);
1409}
1410
1411void __init native_smp_cpus_done(unsigned int max_cpus)
1412{
1413 pr_debug("Boot done\n");
1414
1415 calculate_max_logical_packages();
1416
1417 if (x86_has_numa_in_package)
1418 set_sched_topology(x86_numa_in_package_topology);
1419
1420 nmi_selftest();
1421 impress_friends();
1422 mtrr_aps_init();
1423}
1424
1425static int __initdata setup_possible_cpus = -1;
1426static int __init _setup_possible_cpus(char *str)
1427{
1428 get_option(&str, &setup_possible_cpus);
1429 return 0;
1430}
1431early_param("possible_cpus", _setup_possible_cpus);
1432
1433
1434/*
1435 * cpu_possible_mask should be static, it cannot change as cpu's
1436 * are onlined, or offlined. The reason is per-cpu data-structures
1437 * are allocated by some modules at init time, and dont expect to
1438 * do this dynamically on cpu arrival/departure.
1439 * cpu_present_mask on the other hand can change dynamically.
1440 * In case when cpu_hotplug is not compiled, then we resort to current
1441 * behaviour, which is cpu_possible == cpu_present.
1442 * - Ashok Raj
1443 *
1444 * Three ways to find out the number of additional hotplug CPUs:
1445 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1446 * - The user can overwrite it with possible_cpus=NUM
1447 * - Otherwise don't reserve additional CPUs.
1448 * We do this because additional CPUs waste a lot of memory.
1449 * -AK
1450 */
1451__init void prefill_possible_map(void)
1452{
1453 int i, possible;
1454
1455 /* No boot processor was found in mptable or ACPI MADT */
1456 if (!num_processors) {
1457 if (boot_cpu_has(X86_FEATURE_APIC)) {
1458 int apicid = boot_cpu_physical_apicid;
1459 int cpu = hard_smp_processor_id();
1460
1461 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
1462
1463 /* Make sure boot cpu is enumerated */
1464 if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
1465 apic->apic_id_valid(apicid))
1466 generic_processor_info(apicid, boot_cpu_apic_version);
1467 }
1468
1469 if (!num_processors)
1470 num_processors = 1;
1471 }
1472
1473 i = setup_max_cpus ?: 1;
1474 if (setup_possible_cpus == -1) {
1475 possible = num_processors;
1476#ifdef CONFIG_HOTPLUG_CPU
1477 if (setup_max_cpus)
1478 possible += disabled_cpus;
1479#else
1480 if (possible > i)
1481 possible = i;
1482#endif
1483 } else
1484 possible = setup_possible_cpus;
1485
1486 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1487
1488 /* nr_cpu_ids could be reduced via nr_cpus= */
1489 if (possible > nr_cpu_ids) {
1490 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
1491 possible, nr_cpu_ids);
1492 possible = nr_cpu_ids;
1493 }
1494
1495#ifdef CONFIG_HOTPLUG_CPU
1496 if (!setup_max_cpus)
1497#endif
1498 if (possible > i) {
1499 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1500 possible, setup_max_cpus);
1501 possible = i;
1502 }
1503
1504 nr_cpu_ids = possible;
1505
1506 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1507 possible, max_t(int, possible - num_processors, 0));
1508
1509 reset_cpu_possible_mask();
1510
1511 for (i = 0; i < possible; i++)
1512 set_cpu_possible(i, true);
1513}
1514
1515#ifdef CONFIG_HOTPLUG_CPU
1516
1517/* Recompute SMT state for all CPUs on offline */
1518static void recompute_smt_state(void)
1519{
1520 int max_threads, cpu;
1521
1522 max_threads = 0;
1523 for_each_online_cpu (cpu) {
1524 int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1525
1526 if (threads > max_threads)
1527 max_threads = threads;
1528 }
1529 __max_smt_threads = max_threads;
1530}
1531
1532static void remove_siblinginfo(int cpu)
1533{
1534 int sibling;
1535 struct cpuinfo_x86 *c = &cpu_data(cpu);
1536
1537 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1538 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1539 /*/
1540 * last thread sibling in this cpu core going down
1541 */
1542 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1543 cpu_data(sibling).booted_cores--;
1544 }
1545
1546 for_each_cpu(sibling, topology_die_cpumask(cpu))
1547 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling));
1548 for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1549 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1550 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1551 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1552 cpumask_clear(cpu_llc_shared_mask(cpu));
1553 cpumask_clear(topology_sibling_cpumask(cpu));
1554 cpumask_clear(topology_core_cpumask(cpu));
1555 cpumask_clear(topology_die_cpumask(cpu));
1556 c->cpu_core_id = 0;
1557 c->booted_cores = 0;
1558 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1559 recompute_smt_state();
1560}
1561
1562static void remove_cpu_from_maps(int cpu)
1563{
1564 set_cpu_online(cpu, false);
1565 cpumask_clear_cpu(cpu, cpu_callout_mask);
1566 cpumask_clear_cpu(cpu, cpu_callin_mask);
1567 /* was set by cpu_init() */
1568 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1569 numa_remove_cpu(cpu);
1570}
1571
1572void cpu_disable_common(void)
1573{
1574 int cpu = smp_processor_id();
1575
1576 remove_siblinginfo(cpu);
1577
1578 /* It's now safe to remove this processor from the online map */
1579 lock_vector_lock();
1580 remove_cpu_from_maps(cpu);
1581 unlock_vector_lock();
1582 fixup_irqs();
1583 lapic_offline();
1584}
1585
1586int native_cpu_disable(void)
1587{
1588 int ret;
1589
1590 ret = lapic_can_unplug_cpu();
1591 if (ret)
1592 return ret;
1593
1594 /*
1595 * Disable the local APIC. Otherwise IPI broadcasts will reach
1596 * it. It still responds normally to INIT, NMI, SMI, and SIPI
1597 * messages.
1598 */
1599 apic_soft_disable();
1600 cpu_disable_common();
1601
1602 return 0;
1603}
1604
1605int common_cpu_die(unsigned int cpu)
1606{
1607 int ret = 0;
1608
1609 /* We don't do anything here: idle task is faking death itself. */
1610
1611 /* They ack this in play_dead() by setting CPU_DEAD */
1612 if (cpu_wait_death(cpu, 5)) {
1613 if (system_state == SYSTEM_RUNNING)
1614 pr_info("CPU %u is now offline\n", cpu);
1615 } else {
1616 pr_err("CPU %u didn't die...\n", cpu);
1617 ret = -1;
1618 }
1619
1620 return ret;
1621}
1622
1623void native_cpu_die(unsigned int cpu)
1624{
1625 common_cpu_die(cpu);
1626}
1627
1628void play_dead_common(void)
1629{
1630 idle_task_exit();
1631
1632 /* Ack it */
1633 (void)cpu_report_death();
1634
1635 /*
1636 * With physical CPU hotplug, we should halt the cpu
1637 */
1638 local_irq_disable();
1639}
1640
1641static bool wakeup_cpu0(void)
1642{
1643 if (smp_processor_id() == 0 && enable_start_cpu0)
1644 return true;
1645
1646 return false;
1647}
1648
1649/*
1650 * We need to flush the caches before going to sleep, lest we have
1651 * dirty data in our caches when we come back up.
1652 */
1653static inline void mwait_play_dead(void)
1654{
1655 unsigned int eax, ebx, ecx, edx;
1656 unsigned int highest_cstate = 0;
1657 unsigned int highest_subcstate = 0;
1658 void *mwait_ptr;
1659 int i;
1660
1661 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
1662 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
1663 return;
1664 if (!this_cpu_has(X86_FEATURE_MWAIT))
1665 return;
1666 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1667 return;
1668 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1669 return;
1670
1671 eax = CPUID_MWAIT_LEAF;
1672 ecx = 0;
1673 native_cpuid(&eax, &ebx, &ecx, &edx);
1674
1675 /*
1676 * eax will be 0 if EDX enumeration is not valid.
1677 * Initialized below to cstate, sub_cstate value when EDX is valid.
1678 */
1679 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1680 eax = 0;
1681 } else {
1682 edx >>= MWAIT_SUBSTATE_SIZE;
1683 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1684 if (edx & MWAIT_SUBSTATE_MASK) {
1685 highest_cstate = i;
1686 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1687 }
1688 }
1689 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1690 (highest_subcstate - 1);
1691 }
1692
1693 /*
1694 * This should be a memory location in a cache line which is
1695 * unlikely to be touched by other processors. The actual
1696 * content is immaterial as it is not actually modified in any way.
1697 */
1698 mwait_ptr = ¤t_thread_info()->flags;
1699
1700 wbinvd();
1701
1702 while (1) {
1703 /*
1704 * The CLFLUSH is a workaround for erratum AAI65 for
1705 * the Xeon 7400 series. It's not clear it is actually
1706 * needed, but it should be harmless in either case.
1707 * The WBINVD is insufficient due to the spurious-wakeup
1708 * case where we return around the loop.
1709 */
1710 mb();
1711 clflush(mwait_ptr);
1712 mb();
1713 __monitor(mwait_ptr, 0, 0);
1714 mb();
1715 __mwait(eax, 0);
1716 /*
1717 * If NMI wants to wake up CPU0, start CPU0.
1718 */
1719 if (wakeup_cpu0())
1720 start_cpu0();
1721 }
1722}
1723
1724void hlt_play_dead(void)
1725{
1726 if (__this_cpu_read(cpu_info.x86) >= 4)
1727 wbinvd();
1728
1729 while (1) {
1730 native_halt();
1731 /*
1732 * If NMI wants to wake up CPU0, start CPU0.
1733 */
1734 if (wakeup_cpu0())
1735 start_cpu0();
1736 }
1737}
1738
1739void native_play_dead(void)
1740{
1741 play_dead_common();
1742 tboot_shutdown(TB_SHUTDOWN_WFS);
1743
1744 mwait_play_dead(); /* Only returns on failure */
1745 if (cpuidle_play_dead())
1746 hlt_play_dead();
1747}
1748
1749#else /* ... !CONFIG_HOTPLUG_CPU */
1750int native_cpu_disable(void)
1751{
1752 return -ENOSYS;
1753}
1754
1755void native_cpu_die(unsigned int cpu)
1756{
1757 /* We said "no" in __cpu_disable */
1758 BUG();
1759}
1760
1761void native_play_dead(void)
1762{
1763 BUG();
1764}
1765
1766#endif
1 /*
2 * x86 SMP booting functions
3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
7 *
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
10 *
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
14 *
15 * This code is released under the GNU General Public License version 2 or
16 * later.
17 *
18 * Fixes
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
29 * from Jose Renau
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
40 */
41
42#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
43
44#include <linux/init.h>
45#include <linux/smp.h>
46#include <linux/module.h>
47#include <linux/sched.h>
48#include <linux/percpu.h>
49#include <linux/bootmem.h>
50#include <linux/err.h>
51#include <linux/nmi.h>
52#include <linux/tboot.h>
53#include <linux/stackprotector.h>
54#include <linux/gfp.h>
55#include <linux/cpuidle.h>
56
57#include <asm/acpi.h>
58#include <asm/desc.h>
59#include <asm/nmi.h>
60#include <asm/irq.h>
61#include <asm/idle.h>
62#include <asm/realmode.h>
63#include <asm/cpu.h>
64#include <asm/numa.h>
65#include <asm/pgtable.h>
66#include <asm/tlbflush.h>
67#include <asm/mtrr.h>
68#include <asm/mwait.h>
69#include <asm/apic.h>
70#include <asm/io_apic.h>
71#include <asm/fpu/internal.h>
72#include <asm/setup.h>
73#include <asm/uv/uv.h>
74#include <linux/mc146818rtc.h>
75#include <asm/i8259.h>
76#include <asm/realmode.h>
77#include <asm/misc.h>
78
79/* Number of siblings per CPU package */
80int smp_num_siblings = 1;
81EXPORT_SYMBOL(smp_num_siblings);
82
83/* Last level cache ID of each logical CPU */
84DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
85
86/* representing HT siblings of each logical CPU */
87DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
88EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
89
90/* representing HT and core siblings of each logical CPU */
91DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
92EXPORT_PER_CPU_SYMBOL(cpu_core_map);
93
94DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
95
96/* Per CPU bogomips and other parameters */
97DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
98EXPORT_PER_CPU_SYMBOL(cpu_info);
99
100/* Logical package management. We might want to allocate that dynamically */
101static int *physical_to_logical_pkg __read_mostly;
102static unsigned long *physical_package_map __read_mostly;;
103static unsigned long *logical_package_map __read_mostly;
104static unsigned int max_physical_pkg_id __read_mostly;
105unsigned int __max_logical_packages __read_mostly;
106EXPORT_SYMBOL(__max_logical_packages);
107
108static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
109{
110 unsigned long flags;
111
112 spin_lock_irqsave(&rtc_lock, flags);
113 CMOS_WRITE(0xa, 0xf);
114 spin_unlock_irqrestore(&rtc_lock, flags);
115 local_flush_tlb();
116 pr_debug("1.\n");
117 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
118 start_eip >> 4;
119 pr_debug("2.\n");
120 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
121 start_eip & 0xf;
122 pr_debug("3.\n");
123}
124
125static inline void smpboot_restore_warm_reset_vector(void)
126{
127 unsigned long flags;
128
129 /*
130 * Install writable page 0 entry to set BIOS data area.
131 */
132 local_flush_tlb();
133
134 /*
135 * Paranoid: Set warm reset code and vector here back
136 * to default values.
137 */
138 spin_lock_irqsave(&rtc_lock, flags);
139 CMOS_WRITE(0, 0xf);
140 spin_unlock_irqrestore(&rtc_lock, flags);
141
142 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
143}
144
145/*
146 * Report back to the Boot Processor during boot time or to the caller processor
147 * during CPU online.
148 */
149static void smp_callin(void)
150{
151 int cpuid, phys_id;
152
153 /*
154 * If waken up by an INIT in an 82489DX configuration
155 * cpu_callout_mask guarantees we don't get here before
156 * an INIT_deassert IPI reaches our local APIC, so it is
157 * now safe to touch our local APIC.
158 */
159 cpuid = smp_processor_id();
160
161 /*
162 * (This works even if the APIC is not enabled.)
163 */
164 phys_id = read_apic_id();
165
166 /*
167 * the boot CPU has finished the init stage and is spinning
168 * on callin_map until we finish. We are free to set up this
169 * CPU, first the APIC. (this is probably redundant on most
170 * boards)
171 */
172 apic_ap_setup();
173
174 /*
175 * Save our processor parameters. Note: this information
176 * is needed for clock calibration.
177 */
178 smp_store_cpu_info(cpuid);
179
180 /*
181 * Get our bogomips.
182 * Update loops_per_jiffy in cpu_data. Previous call to
183 * smp_store_cpu_info() stored a value that is close but not as
184 * accurate as the value just calculated.
185 */
186 calibrate_delay();
187 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
188 pr_debug("Stack at about %p\n", &cpuid);
189
190 /*
191 * This must be done before setting cpu_online_mask
192 * or calling notify_cpu_starting.
193 */
194 set_cpu_sibling_map(raw_smp_processor_id());
195 wmb();
196
197 notify_cpu_starting(cpuid);
198
199 /*
200 * Allow the master to continue.
201 */
202 cpumask_set_cpu(cpuid, cpu_callin_mask);
203}
204
205static int cpu0_logical_apicid;
206static int enable_start_cpu0;
207/*
208 * Activate a secondary processor.
209 */
210static void notrace start_secondary(void *unused)
211{
212 /*
213 * Don't put *anything* before cpu_init(), SMP booting is too
214 * fragile that we want to limit the things done here to the
215 * most necessary things.
216 */
217 cpu_init();
218 x86_cpuinit.early_percpu_clock_init();
219 preempt_disable();
220 smp_callin();
221
222 enable_start_cpu0 = 0;
223
224#ifdef CONFIG_X86_32
225 /* switch away from the initial page table */
226 load_cr3(swapper_pg_dir);
227 __flush_tlb_all();
228#endif
229
230 /* otherwise gcc will move up smp_processor_id before the cpu_init */
231 barrier();
232 /*
233 * Check TSC synchronization with the BP:
234 */
235 check_tsc_sync_target();
236
237 /*
238 * Lock vector_lock and initialize the vectors on this cpu
239 * before setting the cpu online. We must set it online with
240 * vector_lock held to prevent a concurrent setup/teardown
241 * from seeing a half valid vector space.
242 */
243 lock_vector_lock();
244 setup_vector_irq(smp_processor_id());
245 set_cpu_online(smp_processor_id(), true);
246 unlock_vector_lock();
247 cpu_set_state_online(smp_processor_id());
248 x86_platform.nmi_init();
249
250 /* enable local interrupts */
251 local_irq_enable();
252
253 /* to prevent fake stack check failure in clock setup */
254 boot_init_stack_canary();
255
256 x86_cpuinit.setup_percpu_clockev();
257
258 wmb();
259 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
260}
261
262int topology_update_package_map(unsigned int apicid, unsigned int cpu)
263{
264 unsigned int new, pkg = apicid >> boot_cpu_data.x86_coreid_bits;
265
266 /* Called from early boot ? */
267 if (!physical_package_map)
268 return 0;
269
270 if (pkg >= max_physical_pkg_id)
271 return -EINVAL;
272
273 /* Set the logical package id */
274 if (test_and_set_bit(pkg, physical_package_map))
275 goto found;
276
277 new = find_first_zero_bit(logical_package_map, __max_logical_packages);
278 if (new >= __max_logical_packages) {
279 physical_to_logical_pkg[pkg] = -1;
280 pr_warn("APIC(%x) Package %u exceeds logical package map\n",
281 apicid, pkg);
282 return -ENOSPC;
283 }
284 set_bit(new, logical_package_map);
285 pr_info("APIC(%x) Converting physical %u to logical package %u\n",
286 apicid, pkg, new);
287 physical_to_logical_pkg[pkg] = new;
288
289found:
290 cpu_data(cpu).logical_proc_id = physical_to_logical_pkg[pkg];
291 return 0;
292}
293
294/**
295 * topology_phys_to_logical_pkg - Map a physical package id to a logical
296 *
297 * Returns logical package id or -1 if not found
298 */
299int topology_phys_to_logical_pkg(unsigned int phys_pkg)
300{
301 if (phys_pkg >= max_physical_pkg_id)
302 return -1;
303 return physical_to_logical_pkg[phys_pkg];
304}
305EXPORT_SYMBOL(topology_phys_to_logical_pkg);
306
307static void __init smp_init_package_map(void)
308{
309 unsigned int ncpus, cpu;
310 size_t size;
311
312 /*
313 * Today neither Intel nor AMD support heterogenous systems. That
314 * might change in the future....
315 *
316 * While ideally we'd want '* smp_num_siblings' in the below @ncpus
317 * computation, this won't actually work since some Intel BIOSes
318 * report inconsistent HT data when they disable HT.
319 *
320 * In particular, they reduce the APIC-IDs to only include the cores,
321 * but leave the CPUID topology to say there are (2) siblings.
322 * This means we don't know how many threads there will be until
323 * after the APIC enumeration.
324 *
325 * By not including this we'll sometimes over-estimate the number of
326 * logical packages by the amount of !present siblings, but this is
327 * still better than MAX_LOCAL_APIC.
328 *
329 * We use total_cpus not nr_cpu_ids because nr_cpu_ids can be limited
330 * on the command line leading to a similar issue as the HT disable
331 * problem because the hyperthreads are usually enumerated after the
332 * primary cores.
333 */
334 ncpus = boot_cpu_data.x86_max_cores;
335 if (!ncpus) {
336 pr_warn("x86_max_cores == zero !?!?");
337 ncpus = 1;
338 }
339
340 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
341
342 /*
343 * Possibly larger than what we need as the number of apic ids per
344 * package can be smaller than the actual used apic ids.
345 */
346 max_physical_pkg_id = DIV_ROUND_UP(MAX_LOCAL_APIC, ncpus);
347 size = max_physical_pkg_id * sizeof(unsigned int);
348 physical_to_logical_pkg = kmalloc(size, GFP_KERNEL);
349 memset(physical_to_logical_pkg, 0xff, size);
350 size = BITS_TO_LONGS(max_physical_pkg_id) * sizeof(unsigned long);
351 physical_package_map = kzalloc(size, GFP_KERNEL);
352 size = BITS_TO_LONGS(__max_logical_packages) * sizeof(unsigned long);
353 logical_package_map = kzalloc(size, GFP_KERNEL);
354
355 pr_info("Max logical packages: %u\n", __max_logical_packages);
356
357 for_each_present_cpu(cpu) {
358 unsigned int apicid = apic->cpu_present_to_apicid(cpu);
359
360 if (apicid == BAD_APICID || !apic->apic_id_valid(apicid))
361 continue;
362 if (!topology_update_package_map(apicid, cpu))
363 continue;
364 pr_warn("CPU %u APICId %x disabled\n", cpu, apicid);
365 per_cpu(x86_bios_cpu_apicid, cpu) = BAD_APICID;
366 set_cpu_possible(cpu, false);
367 set_cpu_present(cpu, false);
368 }
369}
370
371void __init smp_store_boot_cpu_info(void)
372{
373 int id = 0; /* CPU 0 */
374 struct cpuinfo_x86 *c = &cpu_data(id);
375
376 *c = boot_cpu_data;
377 c->cpu_index = id;
378 smp_init_package_map();
379}
380
381/*
382 * The bootstrap kernel entry code has set these up. Save them for
383 * a given CPU
384 */
385void smp_store_cpu_info(int id)
386{
387 struct cpuinfo_x86 *c = &cpu_data(id);
388
389 *c = boot_cpu_data;
390 c->cpu_index = id;
391 /*
392 * During boot time, CPU0 has this setup already. Save the info when
393 * bringing up AP or offlined CPU0.
394 */
395 identify_secondary_cpu(c);
396}
397
398static bool
399topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
400{
401 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
402
403 return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
404}
405
406static bool
407topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
408{
409 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
410
411 return !WARN_ONCE(!topology_same_node(c, o),
412 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
413 "[node: %d != %d]. Ignoring dependency.\n",
414 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
415}
416
417#define link_mask(mfunc, c1, c2) \
418do { \
419 cpumask_set_cpu((c1), mfunc(c2)); \
420 cpumask_set_cpu((c2), mfunc(c1)); \
421} while (0)
422
423static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
424{
425 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
426 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
427
428 if (c->phys_proc_id == o->phys_proc_id &&
429 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) &&
430 c->cpu_core_id == o->cpu_core_id)
431 return topology_sane(c, o, "smt");
432
433 } else if (c->phys_proc_id == o->phys_proc_id &&
434 c->cpu_core_id == o->cpu_core_id) {
435 return topology_sane(c, o, "smt");
436 }
437
438 return false;
439}
440
441static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
442{
443 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
444
445 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID &&
446 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2))
447 return topology_sane(c, o, "llc");
448
449 return false;
450}
451
452/*
453 * Unlike the other levels, we do not enforce keeping a
454 * multicore group inside a NUMA node. If this happens, we will
455 * discard the MC level of the topology later.
456 */
457static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
458{
459 if (c->phys_proc_id == o->phys_proc_id)
460 return true;
461 return false;
462}
463
464static struct sched_domain_topology_level numa_inside_package_topology[] = {
465#ifdef CONFIG_SCHED_SMT
466 { cpu_smt_mask, cpu_smt_flags, SD_INIT_NAME(SMT) },
467#endif
468#ifdef CONFIG_SCHED_MC
469 { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) },
470#endif
471 { NULL, },
472};
473/*
474 * set_sched_topology() sets the topology internal to a CPU. The
475 * NUMA topologies are layered on top of it to build the full
476 * system topology.
477 *
478 * If NUMA nodes are observed to occur within a CPU package, this
479 * function should be called. It forces the sched domain code to
480 * only use the SMT level for the CPU portion of the topology.
481 * This essentially falls back to relying on NUMA information
482 * from the SRAT table to describe the entire system topology
483 * (except for hyperthreads).
484 */
485static void primarily_use_numa_for_topology(void)
486{
487 set_sched_topology(numa_inside_package_topology);
488}
489
490void set_cpu_sibling_map(int cpu)
491{
492 bool has_smt = smp_num_siblings > 1;
493 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
494 struct cpuinfo_x86 *c = &cpu_data(cpu);
495 struct cpuinfo_x86 *o;
496 int i;
497
498 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
499
500 if (!has_mp) {
501 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
502 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
503 cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
504 c->booted_cores = 1;
505 return;
506 }
507
508 for_each_cpu(i, cpu_sibling_setup_mask) {
509 o = &cpu_data(i);
510
511 if ((i == cpu) || (has_smt && match_smt(c, o)))
512 link_mask(topology_sibling_cpumask, cpu, i);
513
514 if ((i == cpu) || (has_mp && match_llc(c, o)))
515 link_mask(cpu_llc_shared_mask, cpu, i);
516
517 }
518
519 /*
520 * This needs a separate iteration over the cpus because we rely on all
521 * topology_sibling_cpumask links to be set-up.
522 */
523 for_each_cpu(i, cpu_sibling_setup_mask) {
524 o = &cpu_data(i);
525
526 if ((i == cpu) || (has_mp && match_die(c, o))) {
527 link_mask(topology_core_cpumask, cpu, i);
528
529 /*
530 * Does this new cpu bringup a new core?
531 */
532 if (cpumask_weight(
533 topology_sibling_cpumask(cpu)) == 1) {
534 /*
535 * for each core in package, increment
536 * the booted_cores for this new cpu
537 */
538 if (cpumask_first(
539 topology_sibling_cpumask(i)) == i)
540 c->booted_cores++;
541 /*
542 * increment the core count for all
543 * the other cpus in this package
544 */
545 if (i != cpu)
546 cpu_data(i).booted_cores++;
547 } else if (i != cpu && !c->booted_cores)
548 c->booted_cores = cpu_data(i).booted_cores;
549 }
550 if (match_die(c, o) && !topology_same_node(c, o))
551 primarily_use_numa_for_topology();
552 }
553}
554
555/* maps the cpu to the sched domain representing multi-core */
556const struct cpumask *cpu_coregroup_mask(int cpu)
557{
558 return cpu_llc_shared_mask(cpu);
559}
560
561static void impress_friends(void)
562{
563 int cpu;
564 unsigned long bogosum = 0;
565 /*
566 * Allow the user to impress friends.
567 */
568 pr_debug("Before bogomips\n");
569 for_each_possible_cpu(cpu)
570 if (cpumask_test_cpu(cpu, cpu_callout_mask))
571 bogosum += cpu_data(cpu).loops_per_jiffy;
572 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
573 num_online_cpus(),
574 bogosum/(500000/HZ),
575 (bogosum/(5000/HZ))%100);
576
577 pr_debug("Before bogocount - setting activated=1\n");
578}
579
580void __inquire_remote_apic(int apicid)
581{
582 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
583 const char * const names[] = { "ID", "VERSION", "SPIV" };
584 int timeout;
585 u32 status;
586
587 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
588
589 for (i = 0; i < ARRAY_SIZE(regs); i++) {
590 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
591
592 /*
593 * Wait for idle.
594 */
595 status = safe_apic_wait_icr_idle();
596 if (status)
597 pr_cont("a previous APIC delivery may have failed\n");
598
599 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
600
601 timeout = 0;
602 do {
603 udelay(100);
604 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
605 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
606
607 switch (status) {
608 case APIC_ICR_RR_VALID:
609 status = apic_read(APIC_RRR);
610 pr_cont("%08x\n", status);
611 break;
612 default:
613 pr_cont("failed\n");
614 }
615 }
616}
617
618/*
619 * The Multiprocessor Specification 1.4 (1997) example code suggests
620 * that there should be a 10ms delay between the BSP asserting INIT
621 * and de-asserting INIT, when starting a remote processor.
622 * But that slows boot and resume on modern processors, which include
623 * many cores and don't require that delay.
624 *
625 * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
626 * Modern processor families are quirked to remove the delay entirely.
627 */
628#define UDELAY_10MS_DEFAULT 10000
629
630static unsigned int init_udelay = UINT_MAX;
631
632static int __init cpu_init_udelay(char *str)
633{
634 get_option(&str, &init_udelay);
635
636 return 0;
637}
638early_param("cpu_init_udelay", cpu_init_udelay);
639
640static void __init smp_quirk_init_udelay(void)
641{
642 /* if cmdline changed it from default, leave it alone */
643 if (init_udelay != UINT_MAX)
644 return;
645
646 /* if modern processor, use no delay */
647 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
648 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
649 init_udelay = 0;
650 return;
651 }
652 /* else, use legacy delay */
653 init_udelay = UDELAY_10MS_DEFAULT;
654}
655
656/*
657 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
658 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
659 * won't ... remember to clear down the APIC, etc later.
660 */
661int
662wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
663{
664 unsigned long send_status, accept_status = 0;
665 int maxlvt;
666
667 /* Target chip */
668 /* Boot on the stack */
669 /* Kick the second */
670 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
671
672 pr_debug("Waiting for send to finish...\n");
673 send_status = safe_apic_wait_icr_idle();
674
675 /*
676 * Give the other CPU some time to accept the IPI.
677 */
678 udelay(200);
679 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
680 maxlvt = lapic_get_maxlvt();
681 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
682 apic_write(APIC_ESR, 0);
683 accept_status = (apic_read(APIC_ESR) & 0xEF);
684 }
685 pr_debug("NMI sent\n");
686
687 if (send_status)
688 pr_err("APIC never delivered???\n");
689 if (accept_status)
690 pr_err("APIC delivery error (%lx)\n", accept_status);
691
692 return (send_status | accept_status);
693}
694
695static int
696wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
697{
698 unsigned long send_status = 0, accept_status = 0;
699 int maxlvt, num_starts, j;
700
701 maxlvt = lapic_get_maxlvt();
702
703 /*
704 * Be paranoid about clearing APIC errors.
705 */
706 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
707 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
708 apic_write(APIC_ESR, 0);
709 apic_read(APIC_ESR);
710 }
711
712 pr_debug("Asserting INIT\n");
713
714 /*
715 * Turn INIT on target chip
716 */
717 /*
718 * Send IPI
719 */
720 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
721 phys_apicid);
722
723 pr_debug("Waiting for send to finish...\n");
724 send_status = safe_apic_wait_icr_idle();
725
726 udelay(init_udelay);
727
728 pr_debug("Deasserting INIT\n");
729
730 /* Target chip */
731 /* Send IPI */
732 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
733
734 pr_debug("Waiting for send to finish...\n");
735 send_status = safe_apic_wait_icr_idle();
736
737 mb();
738
739 /*
740 * Should we send STARTUP IPIs ?
741 *
742 * Determine this based on the APIC version.
743 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
744 */
745 if (APIC_INTEGRATED(apic_version[phys_apicid]))
746 num_starts = 2;
747 else
748 num_starts = 0;
749
750 /*
751 * Run STARTUP IPI loop.
752 */
753 pr_debug("#startup loops: %d\n", num_starts);
754
755 for (j = 1; j <= num_starts; j++) {
756 pr_debug("Sending STARTUP #%d\n", j);
757 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
758 apic_write(APIC_ESR, 0);
759 apic_read(APIC_ESR);
760 pr_debug("After apic_write\n");
761
762 /*
763 * STARTUP IPI
764 */
765
766 /* Target chip */
767 /* Boot on the stack */
768 /* Kick the second */
769 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
770 phys_apicid);
771
772 /*
773 * Give the other CPU some time to accept the IPI.
774 */
775 if (init_udelay == 0)
776 udelay(10);
777 else
778 udelay(300);
779
780 pr_debug("Startup point 1\n");
781
782 pr_debug("Waiting for send to finish...\n");
783 send_status = safe_apic_wait_icr_idle();
784
785 /*
786 * Give the other CPU some time to accept the IPI.
787 */
788 if (init_udelay == 0)
789 udelay(10);
790 else
791 udelay(200);
792
793 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
794 apic_write(APIC_ESR, 0);
795 accept_status = (apic_read(APIC_ESR) & 0xEF);
796 if (send_status || accept_status)
797 break;
798 }
799 pr_debug("After Startup\n");
800
801 if (send_status)
802 pr_err("APIC never delivered???\n");
803 if (accept_status)
804 pr_err("APIC delivery error (%lx)\n", accept_status);
805
806 return (send_status | accept_status);
807}
808
809void smp_announce(void)
810{
811 int num_nodes = num_online_nodes();
812
813 printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n",
814 num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus());
815}
816
817/* reduce the number of lines printed when booting a large cpu count system */
818static void announce_cpu(int cpu, int apicid)
819{
820 static int current_node = -1;
821 int node = early_cpu_to_node(cpu);
822 static int width, node_width;
823
824 if (!width)
825 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
826
827 if (!node_width)
828 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
829
830 if (cpu == 1)
831 printk(KERN_INFO "x86: Booting SMP configuration:\n");
832
833 if (system_state == SYSTEM_BOOTING) {
834 if (node != current_node) {
835 if (current_node > (-1))
836 pr_cont("\n");
837 current_node = node;
838
839 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
840 node_width - num_digits(node), " ", node);
841 }
842
843 /* Add padding for the BSP */
844 if (cpu == 1)
845 pr_cont("%*s", width + 1, " ");
846
847 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
848
849 } else
850 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
851 node, cpu, apicid);
852}
853
854static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
855{
856 int cpu;
857
858 cpu = smp_processor_id();
859 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
860 return NMI_HANDLED;
861
862 return NMI_DONE;
863}
864
865/*
866 * Wake up AP by INIT, INIT, STARTUP sequence.
867 *
868 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
869 * boot-strap code which is not a desired behavior for waking up BSP. To
870 * void the boot-strap code, wake up CPU0 by NMI instead.
871 *
872 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
873 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
874 * We'll change this code in the future to wake up hard offlined CPU0 if
875 * real platform and request are available.
876 */
877static int
878wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
879 int *cpu0_nmi_registered)
880{
881 int id;
882 int boot_error;
883
884 preempt_disable();
885
886 /*
887 * Wake up AP by INIT, INIT, STARTUP sequence.
888 */
889 if (cpu) {
890 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
891 goto out;
892 }
893
894 /*
895 * Wake up BSP by nmi.
896 *
897 * Register a NMI handler to help wake up CPU0.
898 */
899 boot_error = register_nmi_handler(NMI_LOCAL,
900 wakeup_cpu0_nmi, 0, "wake_cpu0");
901
902 if (!boot_error) {
903 enable_start_cpu0 = 1;
904 *cpu0_nmi_registered = 1;
905 if (apic->dest_logical == APIC_DEST_LOGICAL)
906 id = cpu0_logical_apicid;
907 else
908 id = apicid;
909 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
910 }
911
912out:
913 preempt_enable();
914
915 return boot_error;
916}
917
918void common_cpu_up(unsigned int cpu, struct task_struct *idle)
919{
920 /* Just in case we booted with a single CPU. */
921 alternatives_enable_smp();
922
923 per_cpu(current_task, cpu) = idle;
924
925#ifdef CONFIG_X86_32
926 /* Stack for startup_32 can be just as for start_secondary onwards */
927 irq_ctx_init(cpu);
928 per_cpu(cpu_current_top_of_stack, cpu) =
929 (unsigned long)task_stack_page(idle) + THREAD_SIZE;
930#else
931 clear_tsk_thread_flag(idle, TIF_FORK);
932 initial_gs = per_cpu_offset(cpu);
933#endif
934}
935
936/*
937 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
938 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
939 * Returns zero if CPU booted OK, else error code from
940 * ->wakeup_secondary_cpu.
941 */
942static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle)
943{
944 volatile u32 *trampoline_status =
945 (volatile u32 *) __va(real_mode_header->trampoline_status);
946 /* start_ip had better be page-aligned! */
947 unsigned long start_ip = real_mode_header->trampoline_start;
948
949 unsigned long boot_error = 0;
950 int cpu0_nmi_registered = 0;
951 unsigned long timeout;
952
953 idle->thread.sp = (unsigned long) (((struct pt_regs *)
954 (THREAD_SIZE + task_stack_page(idle))) - 1);
955
956 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
957 initial_code = (unsigned long)start_secondary;
958 stack_start = idle->thread.sp;
959
960 /*
961 * Enable the espfix hack for this CPU
962 */
963#ifdef CONFIG_X86_ESPFIX64
964 init_espfix_ap(cpu);
965#endif
966
967 /* So we see what's up */
968 announce_cpu(cpu, apicid);
969
970 /*
971 * This grunge runs the startup process for
972 * the targeted processor.
973 */
974
975 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
976
977 pr_debug("Setting warm reset code and vector.\n");
978
979 smpboot_setup_warm_reset_vector(start_ip);
980 /*
981 * Be paranoid about clearing APIC errors.
982 */
983 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
984 apic_write(APIC_ESR, 0);
985 apic_read(APIC_ESR);
986 }
987 }
988
989 /*
990 * AP might wait on cpu_callout_mask in cpu_init() with
991 * cpu_initialized_mask set if previous attempt to online
992 * it timed-out. Clear cpu_initialized_mask so that after
993 * INIT/SIPI it could start with a clean state.
994 */
995 cpumask_clear_cpu(cpu, cpu_initialized_mask);
996 smp_mb();
997
998 /*
999 * Wake up a CPU in difference cases:
1000 * - Use the method in the APIC driver if it's defined
1001 * Otherwise,
1002 * - Use an INIT boot APIC message for APs or NMI for BSP.
1003 */
1004 if (apic->wakeup_secondary_cpu)
1005 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
1006 else
1007 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
1008 &cpu0_nmi_registered);
1009
1010 if (!boot_error) {
1011 /*
1012 * Wait 10s total for first sign of life from AP
1013 */
1014 boot_error = -1;
1015 timeout = jiffies + 10*HZ;
1016 while (time_before(jiffies, timeout)) {
1017 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
1018 /*
1019 * Tell AP to proceed with initialization
1020 */
1021 cpumask_set_cpu(cpu, cpu_callout_mask);
1022 boot_error = 0;
1023 break;
1024 }
1025 schedule();
1026 }
1027 }
1028
1029 if (!boot_error) {
1030 /*
1031 * Wait till AP completes initial initialization
1032 */
1033 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
1034 /*
1035 * Allow other tasks to run while we wait for the
1036 * AP to come online. This also gives a chance
1037 * for the MTRR work(triggered by the AP coming online)
1038 * to be completed in the stop machine context.
1039 */
1040 schedule();
1041 }
1042 }
1043
1044 /* mark "stuck" area as not stuck */
1045 *trampoline_status = 0;
1046
1047 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
1048 /*
1049 * Cleanup possible dangling ends...
1050 */
1051 smpboot_restore_warm_reset_vector();
1052 }
1053 /*
1054 * Clean up the nmi handler. Do this after the callin and callout sync
1055 * to avoid impact of possible long unregister time.
1056 */
1057 if (cpu0_nmi_registered)
1058 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1059
1060 return boot_error;
1061}
1062
1063int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
1064{
1065 int apicid = apic->cpu_present_to_apicid(cpu);
1066 unsigned long flags;
1067 int err;
1068
1069 WARN_ON(irqs_disabled());
1070
1071 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
1072
1073 if (apicid == BAD_APICID ||
1074 !physid_isset(apicid, phys_cpu_present_map) ||
1075 !apic->apic_id_valid(apicid)) {
1076 pr_err("%s: bad cpu %d\n", __func__, cpu);
1077 return -EINVAL;
1078 }
1079
1080 /*
1081 * Already booted CPU?
1082 */
1083 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
1084 pr_debug("do_boot_cpu %d Already started\n", cpu);
1085 return -ENOSYS;
1086 }
1087
1088 /*
1089 * Save current MTRR state in case it was changed since early boot
1090 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1091 */
1092 mtrr_save_state();
1093
1094 /* x86 CPUs take themselves offline, so delayed offline is OK. */
1095 err = cpu_check_up_prepare(cpu);
1096 if (err && err != -EBUSY)
1097 return err;
1098
1099 /* the FPU context is blank, nobody can own it */
1100 __cpu_disable_lazy_restore(cpu);
1101
1102 common_cpu_up(cpu, tidle);
1103
1104 /*
1105 * We have to walk the irq descriptors to setup the vector
1106 * space for the cpu which comes online. Prevent irq
1107 * alloc/free across the bringup.
1108 */
1109 irq_lock_sparse();
1110
1111 err = do_boot_cpu(apicid, cpu, tidle);
1112
1113 if (err) {
1114 irq_unlock_sparse();
1115 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1116 return -EIO;
1117 }
1118
1119 /*
1120 * Check TSC synchronization with the AP (keep irqs disabled
1121 * while doing so):
1122 */
1123 local_irq_save(flags);
1124 check_tsc_sync_source(cpu);
1125 local_irq_restore(flags);
1126
1127 while (!cpu_online(cpu)) {
1128 cpu_relax();
1129 touch_nmi_watchdog();
1130 }
1131
1132 irq_unlock_sparse();
1133
1134 return 0;
1135}
1136
1137/**
1138 * arch_disable_smp_support() - disables SMP support for x86 at runtime
1139 */
1140void arch_disable_smp_support(void)
1141{
1142 disable_ioapic_support();
1143}
1144
1145/*
1146 * Fall back to non SMP mode after errors.
1147 *
1148 * RED-PEN audit/test this more. I bet there is more state messed up here.
1149 */
1150static __init void disable_smp(void)
1151{
1152 pr_info("SMP disabled\n");
1153
1154 disable_ioapic_support();
1155
1156 init_cpu_present(cpumask_of(0));
1157 init_cpu_possible(cpumask_of(0));
1158
1159 if (smp_found_config)
1160 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1161 else
1162 physid_set_mask_of_physid(0, &phys_cpu_present_map);
1163 cpumask_set_cpu(0, topology_sibling_cpumask(0));
1164 cpumask_set_cpu(0, topology_core_cpumask(0));
1165}
1166
1167enum {
1168 SMP_OK,
1169 SMP_NO_CONFIG,
1170 SMP_NO_APIC,
1171 SMP_FORCE_UP,
1172};
1173
1174/*
1175 * Various sanity checks.
1176 */
1177static int __init smp_sanity_check(unsigned max_cpus)
1178{
1179 preempt_disable();
1180
1181#if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1182 if (def_to_bigsmp && nr_cpu_ids > 8) {
1183 unsigned int cpu;
1184 unsigned nr;
1185
1186 pr_warn("More than 8 CPUs detected - skipping them\n"
1187 "Use CONFIG_X86_BIGSMP\n");
1188
1189 nr = 0;
1190 for_each_present_cpu(cpu) {
1191 if (nr >= 8)
1192 set_cpu_present(cpu, false);
1193 nr++;
1194 }
1195
1196 nr = 0;
1197 for_each_possible_cpu(cpu) {
1198 if (nr >= 8)
1199 set_cpu_possible(cpu, false);
1200 nr++;
1201 }
1202
1203 nr_cpu_ids = 8;
1204 }
1205#endif
1206
1207 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1208 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1209 hard_smp_processor_id());
1210
1211 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1212 }
1213
1214 /*
1215 * If we couldn't find an SMP configuration at boot time,
1216 * get out of here now!
1217 */
1218 if (!smp_found_config && !acpi_lapic) {
1219 preempt_enable();
1220 pr_notice("SMP motherboard not detected\n");
1221 return SMP_NO_CONFIG;
1222 }
1223
1224 /*
1225 * Should not be necessary because the MP table should list the boot
1226 * CPU too, but we do it for the sake of robustness anyway.
1227 */
1228 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1229 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1230 boot_cpu_physical_apicid);
1231 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1232 }
1233 preempt_enable();
1234
1235 /*
1236 * If we couldn't find a local APIC, then get out of here now!
1237 */
1238 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
1239 !cpu_has_apic) {
1240 if (!disable_apic) {
1241 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1242 boot_cpu_physical_apicid);
1243 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1244 }
1245 return SMP_NO_APIC;
1246 }
1247
1248 /*
1249 * If SMP should be disabled, then really disable it!
1250 */
1251 if (!max_cpus) {
1252 pr_info("SMP mode deactivated\n");
1253 return SMP_FORCE_UP;
1254 }
1255
1256 return SMP_OK;
1257}
1258
1259static void __init smp_cpu_index_default(void)
1260{
1261 int i;
1262 struct cpuinfo_x86 *c;
1263
1264 for_each_possible_cpu(i) {
1265 c = &cpu_data(i);
1266 /* mark all to hotplug */
1267 c->cpu_index = nr_cpu_ids;
1268 }
1269}
1270
1271/*
1272 * Prepare for SMP bootup. The MP table or ACPI has been read
1273 * earlier. Just do some sanity checking here and enable APIC mode.
1274 */
1275void __init native_smp_prepare_cpus(unsigned int max_cpus)
1276{
1277 unsigned int i;
1278
1279 smp_cpu_index_default();
1280
1281 /*
1282 * Setup boot CPU information
1283 */
1284 smp_store_boot_cpu_info(); /* Final full version of the data */
1285 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1286 mb();
1287
1288 current_thread_info()->cpu = 0; /* needed? */
1289 for_each_possible_cpu(i) {
1290 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1291 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1292 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1293 }
1294 set_cpu_sibling_map(0);
1295
1296 switch (smp_sanity_check(max_cpus)) {
1297 case SMP_NO_CONFIG:
1298 disable_smp();
1299 if (APIC_init_uniprocessor())
1300 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1301 return;
1302 case SMP_NO_APIC:
1303 disable_smp();
1304 return;
1305 case SMP_FORCE_UP:
1306 disable_smp();
1307 apic_bsp_setup(false);
1308 return;
1309 case SMP_OK:
1310 break;
1311 }
1312
1313 default_setup_apic_routing();
1314
1315 if (read_apic_id() != boot_cpu_physical_apicid) {
1316 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1317 read_apic_id(), boot_cpu_physical_apicid);
1318 /* Or can we switch back to PIC here? */
1319 }
1320
1321 cpu0_logical_apicid = apic_bsp_setup(false);
1322
1323 pr_info("CPU%d: ", 0);
1324 print_cpu_info(&cpu_data(0));
1325
1326 if (is_uv_system())
1327 uv_system_init();
1328
1329 set_mtrr_aps_delayed_init();
1330
1331 smp_quirk_init_udelay();
1332}
1333
1334void arch_enable_nonboot_cpus_begin(void)
1335{
1336 set_mtrr_aps_delayed_init();
1337}
1338
1339void arch_enable_nonboot_cpus_end(void)
1340{
1341 mtrr_aps_init();
1342}
1343
1344/*
1345 * Early setup to make printk work.
1346 */
1347void __init native_smp_prepare_boot_cpu(void)
1348{
1349 int me = smp_processor_id();
1350 switch_to_new_gdt(me);
1351 /* already set me in cpu_online_mask in boot_cpu_init() */
1352 cpumask_set_cpu(me, cpu_callout_mask);
1353 cpu_set_state_online(me);
1354}
1355
1356void __init native_smp_cpus_done(unsigned int max_cpus)
1357{
1358 pr_debug("Boot done\n");
1359
1360 nmi_selftest();
1361 impress_friends();
1362 setup_ioapic_dest();
1363 mtrr_aps_init();
1364}
1365
1366static int __initdata setup_possible_cpus = -1;
1367static int __init _setup_possible_cpus(char *str)
1368{
1369 get_option(&str, &setup_possible_cpus);
1370 return 0;
1371}
1372early_param("possible_cpus", _setup_possible_cpus);
1373
1374
1375/*
1376 * cpu_possible_mask should be static, it cannot change as cpu's
1377 * are onlined, or offlined. The reason is per-cpu data-structures
1378 * are allocated by some modules at init time, and dont expect to
1379 * do this dynamically on cpu arrival/departure.
1380 * cpu_present_mask on the other hand can change dynamically.
1381 * In case when cpu_hotplug is not compiled, then we resort to current
1382 * behaviour, which is cpu_possible == cpu_present.
1383 * - Ashok Raj
1384 *
1385 * Three ways to find out the number of additional hotplug CPUs:
1386 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1387 * - The user can overwrite it with possible_cpus=NUM
1388 * - Otherwise don't reserve additional CPUs.
1389 * We do this because additional CPUs waste a lot of memory.
1390 * -AK
1391 */
1392__init void prefill_possible_map(void)
1393{
1394 int i, possible;
1395
1396 /* no processor from mptable or madt */
1397 if (!num_processors)
1398 num_processors = 1;
1399
1400 i = setup_max_cpus ?: 1;
1401 if (setup_possible_cpus == -1) {
1402 possible = num_processors;
1403#ifdef CONFIG_HOTPLUG_CPU
1404 if (setup_max_cpus)
1405 possible += disabled_cpus;
1406#else
1407 if (possible > i)
1408 possible = i;
1409#endif
1410 } else
1411 possible = setup_possible_cpus;
1412
1413 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1414
1415 /* nr_cpu_ids could be reduced via nr_cpus= */
1416 if (possible > nr_cpu_ids) {
1417 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1418 possible, nr_cpu_ids);
1419 possible = nr_cpu_ids;
1420 }
1421
1422#ifdef CONFIG_HOTPLUG_CPU
1423 if (!setup_max_cpus)
1424#endif
1425 if (possible > i) {
1426 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1427 possible, setup_max_cpus);
1428 possible = i;
1429 }
1430
1431 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1432 possible, max_t(int, possible - num_processors, 0));
1433
1434 for (i = 0; i < possible; i++)
1435 set_cpu_possible(i, true);
1436 for (; i < NR_CPUS; i++)
1437 set_cpu_possible(i, false);
1438
1439 nr_cpu_ids = possible;
1440}
1441
1442#ifdef CONFIG_HOTPLUG_CPU
1443
1444static void remove_siblinginfo(int cpu)
1445{
1446 int sibling;
1447 struct cpuinfo_x86 *c = &cpu_data(cpu);
1448
1449 for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1450 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1451 /*/
1452 * last thread sibling in this cpu core going down
1453 */
1454 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1455 cpu_data(sibling).booted_cores--;
1456 }
1457
1458 for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1459 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1460 for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1461 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1462 cpumask_clear(cpu_llc_shared_mask(cpu));
1463 cpumask_clear(topology_sibling_cpumask(cpu));
1464 cpumask_clear(topology_core_cpumask(cpu));
1465 c->phys_proc_id = 0;
1466 c->cpu_core_id = 0;
1467 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1468}
1469
1470static void remove_cpu_from_maps(int cpu)
1471{
1472 set_cpu_online(cpu, false);
1473 cpumask_clear_cpu(cpu, cpu_callout_mask);
1474 cpumask_clear_cpu(cpu, cpu_callin_mask);
1475 /* was set by cpu_init() */
1476 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1477 numa_remove_cpu(cpu);
1478}
1479
1480void cpu_disable_common(void)
1481{
1482 int cpu = smp_processor_id();
1483
1484 remove_siblinginfo(cpu);
1485
1486 /* It's now safe to remove this processor from the online map */
1487 lock_vector_lock();
1488 remove_cpu_from_maps(cpu);
1489 unlock_vector_lock();
1490 fixup_irqs();
1491}
1492
1493int native_cpu_disable(void)
1494{
1495 int ret;
1496
1497 ret = check_irq_vectors_for_cpu_disable();
1498 if (ret)
1499 return ret;
1500
1501 clear_local_APIC();
1502 cpu_disable_common();
1503
1504 return 0;
1505}
1506
1507int common_cpu_die(unsigned int cpu)
1508{
1509 int ret = 0;
1510
1511 /* We don't do anything here: idle task is faking death itself. */
1512
1513 /* They ack this in play_dead() by setting CPU_DEAD */
1514 if (cpu_wait_death(cpu, 5)) {
1515 if (system_state == SYSTEM_RUNNING)
1516 pr_info("CPU %u is now offline\n", cpu);
1517 } else {
1518 pr_err("CPU %u didn't die...\n", cpu);
1519 ret = -1;
1520 }
1521
1522 return ret;
1523}
1524
1525void native_cpu_die(unsigned int cpu)
1526{
1527 common_cpu_die(cpu);
1528}
1529
1530void play_dead_common(void)
1531{
1532 idle_task_exit();
1533 reset_lazy_tlbstate();
1534 amd_e400_remove_cpu(raw_smp_processor_id());
1535
1536 /* Ack it */
1537 (void)cpu_report_death();
1538
1539 /*
1540 * With physical CPU hotplug, we should halt the cpu
1541 */
1542 local_irq_disable();
1543}
1544
1545static bool wakeup_cpu0(void)
1546{
1547 if (smp_processor_id() == 0 && enable_start_cpu0)
1548 return true;
1549
1550 return false;
1551}
1552
1553/*
1554 * We need to flush the caches before going to sleep, lest we have
1555 * dirty data in our caches when we come back up.
1556 */
1557static inline void mwait_play_dead(void)
1558{
1559 unsigned int eax, ebx, ecx, edx;
1560 unsigned int highest_cstate = 0;
1561 unsigned int highest_subcstate = 0;
1562 void *mwait_ptr;
1563 int i;
1564
1565 if (!this_cpu_has(X86_FEATURE_MWAIT))
1566 return;
1567 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1568 return;
1569 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1570 return;
1571
1572 eax = CPUID_MWAIT_LEAF;
1573 ecx = 0;
1574 native_cpuid(&eax, &ebx, &ecx, &edx);
1575
1576 /*
1577 * eax will be 0 if EDX enumeration is not valid.
1578 * Initialized below to cstate, sub_cstate value when EDX is valid.
1579 */
1580 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1581 eax = 0;
1582 } else {
1583 edx >>= MWAIT_SUBSTATE_SIZE;
1584 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1585 if (edx & MWAIT_SUBSTATE_MASK) {
1586 highest_cstate = i;
1587 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1588 }
1589 }
1590 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1591 (highest_subcstate - 1);
1592 }
1593
1594 /*
1595 * This should be a memory location in a cache line which is
1596 * unlikely to be touched by other processors. The actual
1597 * content is immaterial as it is not actually modified in any way.
1598 */
1599 mwait_ptr = ¤t_thread_info()->flags;
1600
1601 wbinvd();
1602
1603 while (1) {
1604 /*
1605 * The CLFLUSH is a workaround for erratum AAI65 for
1606 * the Xeon 7400 series. It's not clear it is actually
1607 * needed, but it should be harmless in either case.
1608 * The WBINVD is insufficient due to the spurious-wakeup
1609 * case where we return around the loop.
1610 */
1611 mb();
1612 clflush(mwait_ptr);
1613 mb();
1614 __monitor(mwait_ptr, 0, 0);
1615 mb();
1616 __mwait(eax, 0);
1617 /*
1618 * If NMI wants to wake up CPU0, start CPU0.
1619 */
1620 if (wakeup_cpu0())
1621 start_cpu0();
1622 }
1623}
1624
1625static inline void hlt_play_dead(void)
1626{
1627 if (__this_cpu_read(cpu_info.x86) >= 4)
1628 wbinvd();
1629
1630 while (1) {
1631 native_halt();
1632 /*
1633 * If NMI wants to wake up CPU0, start CPU0.
1634 */
1635 if (wakeup_cpu0())
1636 start_cpu0();
1637 }
1638}
1639
1640void native_play_dead(void)
1641{
1642 play_dead_common();
1643 tboot_shutdown(TB_SHUTDOWN_WFS);
1644
1645 mwait_play_dead(); /* Only returns on failure */
1646 if (cpuidle_play_dead())
1647 hlt_play_dead();
1648}
1649
1650#else /* ... !CONFIG_HOTPLUG_CPU */
1651int native_cpu_disable(void)
1652{
1653 return -ENOSYS;
1654}
1655
1656void native_cpu_die(unsigned int cpu)
1657{
1658 /* We said "no" in __cpu_disable */
1659 BUG();
1660}
1661
1662void native_play_dead(void)
1663{
1664 BUG();
1665}
1666
1667#endif