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1// SPDX-License-Identifier: GPL-2.0
2#include <linux/linkage.h>
3#include <linux/errno.h>
4#include <linux/signal.h>
5#include <linux/sched.h>
6#include <linux/ioport.h>
7#include <linux/interrupt.h>
8#include <linux/irq.h>
9#include <linux/timex.h>
10#include <linux/random.h>
11#include <linux/init.h>
12#include <linux/kernel_stat.h>
13#include <linux/syscore_ops.h>
14#include <linux/bitops.h>
15#include <linux/acpi.h>
16#include <linux/io.h>
17#include <linux/delay.h>
18
19#include <linux/atomic.h>
20#include <asm/timer.h>
21#include <asm/hw_irq.h>
22#include <asm/pgtable.h>
23#include <asm/desc.h>
24#include <asm/apic.h>
25#include <asm/i8259.h>
26
27/*
28 * This is the 'legacy' 8259A Programmable Interrupt Controller,
29 * present in the majority of PC/AT boxes.
30 * plus some generic x86 specific things if generic specifics makes
31 * any sense at all.
32 */
33static void init_8259A(int auto_eoi);
34
35static int i8259A_auto_eoi;
36DEFINE_RAW_SPINLOCK(i8259A_lock);
37
38/*
39 * 8259A PIC functions to handle ISA devices:
40 */
41
42/*
43 * This contains the irq mask for both 8259A irq controllers,
44 */
45unsigned int cached_irq_mask = 0xffff;
46
47/*
48 * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
49 * boards the timer interrupt is not really connected to any IO-APIC pin,
50 * it's fed to the master 8259A's IR0 line only.
51 *
52 * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
53 * this 'mixed mode' IRQ handling costs nothing because it's only used
54 * at IRQ setup time.
55 */
56unsigned long io_apic_irqs;
57
58static void mask_8259A_irq(unsigned int irq)
59{
60 unsigned int mask = 1 << irq;
61 unsigned long flags;
62
63 raw_spin_lock_irqsave(&i8259A_lock, flags);
64 cached_irq_mask |= mask;
65 if (irq & 8)
66 outb(cached_slave_mask, PIC_SLAVE_IMR);
67 else
68 outb(cached_master_mask, PIC_MASTER_IMR);
69 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
70}
71
72static void disable_8259A_irq(struct irq_data *data)
73{
74 mask_8259A_irq(data->irq);
75}
76
77static void unmask_8259A_irq(unsigned int irq)
78{
79 unsigned int mask = ~(1 << irq);
80 unsigned long flags;
81
82 raw_spin_lock_irqsave(&i8259A_lock, flags);
83 cached_irq_mask &= mask;
84 if (irq & 8)
85 outb(cached_slave_mask, PIC_SLAVE_IMR);
86 else
87 outb(cached_master_mask, PIC_MASTER_IMR);
88 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
89}
90
91static void enable_8259A_irq(struct irq_data *data)
92{
93 unmask_8259A_irq(data->irq);
94}
95
96static int i8259A_irq_pending(unsigned int irq)
97{
98 unsigned int mask = 1<<irq;
99 unsigned long flags;
100 int ret;
101
102 raw_spin_lock_irqsave(&i8259A_lock, flags);
103 if (irq < 8)
104 ret = inb(PIC_MASTER_CMD) & mask;
105 else
106 ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
107 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
108
109 return ret;
110}
111
112static void make_8259A_irq(unsigned int irq)
113{
114 disable_irq_nosync(irq);
115 io_apic_irqs &= ~(1<<irq);
116 irq_set_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
117 enable_irq(irq);
118 lapic_assign_legacy_vector(irq, true);
119}
120
121/*
122 * This function assumes to be called rarely. Switching between
123 * 8259A registers is slow.
124 * This has to be protected by the irq controller spinlock
125 * before being called.
126 */
127static inline int i8259A_irq_real(unsigned int irq)
128{
129 int value;
130 int irqmask = 1<<irq;
131
132 if (irq < 8) {
133 outb(0x0B, PIC_MASTER_CMD); /* ISR register */
134 value = inb(PIC_MASTER_CMD) & irqmask;
135 outb(0x0A, PIC_MASTER_CMD); /* back to the IRR register */
136 return value;
137 }
138 outb(0x0B, PIC_SLAVE_CMD); /* ISR register */
139 value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
140 outb(0x0A, PIC_SLAVE_CMD); /* back to the IRR register */
141 return value;
142}
143
144/*
145 * Careful! The 8259A is a fragile beast, it pretty
146 * much _has_ to be done exactly like this (mask it
147 * first, _then_ send the EOI, and the order of EOI
148 * to the two 8259s is important!
149 */
150static void mask_and_ack_8259A(struct irq_data *data)
151{
152 unsigned int irq = data->irq;
153 unsigned int irqmask = 1 << irq;
154 unsigned long flags;
155
156 raw_spin_lock_irqsave(&i8259A_lock, flags);
157 /*
158 * Lightweight spurious IRQ detection. We do not want
159 * to overdo spurious IRQ handling - it's usually a sign
160 * of hardware problems, so we only do the checks we can
161 * do without slowing down good hardware unnecessarily.
162 *
163 * Note that IRQ7 and IRQ15 (the two spurious IRQs
164 * usually resulting from the 8259A-1|2 PICs) occur
165 * even if the IRQ is masked in the 8259A. Thus we
166 * can check spurious 8259A IRQs without doing the
167 * quite slow i8259A_irq_real() call for every IRQ.
168 * This does not cover 100% of spurious interrupts,
169 * but should be enough to warn the user that there
170 * is something bad going on ...
171 */
172 if (cached_irq_mask & irqmask)
173 goto spurious_8259A_irq;
174 cached_irq_mask |= irqmask;
175
176handle_real_irq:
177 if (irq & 8) {
178 inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
179 outb(cached_slave_mask, PIC_SLAVE_IMR);
180 /* 'Specific EOI' to slave */
181 outb(0x60+(irq&7), PIC_SLAVE_CMD);
182 /* 'Specific EOI' to master-IRQ2 */
183 outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD);
184 } else {
185 inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
186 outb(cached_master_mask, PIC_MASTER_IMR);
187 outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */
188 }
189 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
190 return;
191
192spurious_8259A_irq:
193 /*
194 * this is the slow path - should happen rarely.
195 */
196 if (i8259A_irq_real(irq))
197 /*
198 * oops, the IRQ _is_ in service according to the
199 * 8259A - not spurious, go handle it.
200 */
201 goto handle_real_irq;
202
203 {
204 static int spurious_irq_mask;
205 /*
206 * At this point we can be sure the IRQ is spurious,
207 * lets ACK and report it. [once per IRQ]
208 */
209 if (!(spurious_irq_mask & irqmask)) {
210 printk(KERN_DEBUG
211 "spurious 8259A interrupt: IRQ%d.\n", irq);
212 spurious_irq_mask |= irqmask;
213 }
214 atomic_inc(&irq_err_count);
215 /*
216 * Theoretically we do not have to handle this IRQ,
217 * but in Linux this does not cause problems and is
218 * simpler for us.
219 */
220 goto handle_real_irq;
221 }
222}
223
224struct irq_chip i8259A_chip = {
225 .name = "XT-PIC",
226 .irq_mask = disable_8259A_irq,
227 .irq_disable = disable_8259A_irq,
228 .irq_unmask = enable_8259A_irq,
229 .irq_mask_ack = mask_and_ack_8259A,
230};
231
232static char irq_trigger[2];
233/**
234 * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
235 */
236static void restore_ELCR(char *trigger)
237{
238 outb(trigger[0], 0x4d0);
239 outb(trigger[1], 0x4d1);
240}
241
242static void save_ELCR(char *trigger)
243{
244 /* IRQ 0,1,2,8,13 are marked as reserved */
245 trigger[0] = inb(0x4d0) & 0xF8;
246 trigger[1] = inb(0x4d1) & 0xDE;
247}
248
249static void i8259A_resume(void)
250{
251 init_8259A(i8259A_auto_eoi);
252 restore_ELCR(irq_trigger);
253}
254
255static int i8259A_suspend(void)
256{
257 save_ELCR(irq_trigger);
258 return 0;
259}
260
261static void i8259A_shutdown(void)
262{
263 /* Put the i8259A into a quiescent state that
264 * the kernel initialization code can get it
265 * out of.
266 */
267 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
268 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
269}
270
271static struct syscore_ops i8259_syscore_ops = {
272 .suspend = i8259A_suspend,
273 .resume = i8259A_resume,
274 .shutdown = i8259A_shutdown,
275};
276
277static void mask_8259A(void)
278{
279 unsigned long flags;
280
281 raw_spin_lock_irqsave(&i8259A_lock, flags);
282
283 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
284 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
285
286 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
287}
288
289static void unmask_8259A(void)
290{
291 unsigned long flags;
292
293 raw_spin_lock_irqsave(&i8259A_lock, flags);
294
295 outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
296 outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
297
298 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
299}
300
301static int probe_8259A(void)
302{
303 unsigned long flags;
304 unsigned char probe_val = ~(1 << PIC_CASCADE_IR);
305 unsigned char new_val;
306 /*
307 * Check to see if we have a PIC.
308 * Mask all except the cascade and read
309 * back the value we just wrote. If we don't
310 * have a PIC, we will read 0xff as opposed to the
311 * value we wrote.
312 */
313 raw_spin_lock_irqsave(&i8259A_lock, flags);
314
315 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
316 outb(probe_val, PIC_MASTER_IMR);
317 new_val = inb(PIC_MASTER_IMR);
318 if (new_val != probe_val) {
319 printk(KERN_INFO "Using NULL legacy PIC\n");
320 legacy_pic = &null_legacy_pic;
321 }
322
323 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
324 return nr_legacy_irqs();
325}
326
327static void init_8259A(int auto_eoi)
328{
329 unsigned long flags;
330
331 i8259A_auto_eoi = auto_eoi;
332
333 raw_spin_lock_irqsave(&i8259A_lock, flags);
334
335 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
336
337 /*
338 * outb_pic - this has to work on a wide range of PC hardware.
339 */
340 outb_pic(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
341
342 /* ICW2: 8259A-1 IR0-7 mapped to ISA_IRQ_VECTOR(0) */
343 outb_pic(ISA_IRQ_VECTOR(0), PIC_MASTER_IMR);
344
345 /* 8259A-1 (the master) has a slave on IR2 */
346 outb_pic(1U << PIC_CASCADE_IR, PIC_MASTER_IMR);
347
348 if (auto_eoi) /* master does Auto EOI */
349 outb_pic(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
350 else /* master expects normal EOI */
351 outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
352
353 outb_pic(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */
354
355 /* ICW2: 8259A-2 IR0-7 mapped to ISA_IRQ_VECTOR(8) */
356 outb_pic(ISA_IRQ_VECTOR(8), PIC_SLAVE_IMR);
357 /* 8259A-2 is a slave on master's IR2 */
358 outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR);
359 /* (slave's support for AEOI in flat mode is to be investigated) */
360 outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR);
361
362 if (auto_eoi)
363 /*
364 * In AEOI mode we just have to mask the interrupt
365 * when acking.
366 */
367 i8259A_chip.irq_mask_ack = disable_8259A_irq;
368 else
369 i8259A_chip.irq_mask_ack = mask_and_ack_8259A;
370
371 udelay(100); /* wait for 8259A to initialize */
372
373 outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
374 outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
375
376 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
377}
378
379/*
380 * make i8259 a driver so that we can select pic functions at run time. the goal
381 * is to make x86 binary compatible among pc compatible and non-pc compatible
382 * platforms, such as x86 MID.
383 */
384
385static void legacy_pic_noop(void) { };
386static void legacy_pic_uint_noop(unsigned int unused) { };
387static void legacy_pic_int_noop(int unused) { };
388static int legacy_pic_irq_pending_noop(unsigned int irq)
389{
390 return 0;
391}
392static int legacy_pic_probe(void)
393{
394 return 0;
395}
396
397struct legacy_pic null_legacy_pic = {
398 .nr_legacy_irqs = 0,
399 .chip = &dummy_irq_chip,
400 .mask = legacy_pic_uint_noop,
401 .unmask = legacy_pic_uint_noop,
402 .mask_all = legacy_pic_noop,
403 .restore_mask = legacy_pic_noop,
404 .init = legacy_pic_int_noop,
405 .probe = legacy_pic_probe,
406 .irq_pending = legacy_pic_irq_pending_noop,
407 .make_irq = legacy_pic_uint_noop,
408};
409
410struct legacy_pic default_legacy_pic = {
411 .nr_legacy_irqs = NR_IRQS_LEGACY,
412 .chip = &i8259A_chip,
413 .mask = mask_8259A_irq,
414 .unmask = unmask_8259A_irq,
415 .mask_all = mask_8259A,
416 .restore_mask = unmask_8259A,
417 .init = init_8259A,
418 .probe = probe_8259A,
419 .irq_pending = i8259A_irq_pending,
420 .make_irq = make_8259A_irq,
421};
422
423struct legacy_pic *legacy_pic = &default_legacy_pic;
424EXPORT_SYMBOL(legacy_pic);
425
426static int __init i8259A_init_ops(void)
427{
428 if (legacy_pic == &default_legacy_pic)
429 register_syscore_ops(&i8259_syscore_ops);
430
431 return 0;
432}
433
434device_initcall(i8259A_init_ops);
1#include <linux/linkage.h>
2#include <linux/errno.h>
3#include <linux/signal.h>
4#include <linux/sched.h>
5#include <linux/ioport.h>
6#include <linux/interrupt.h>
7#include <linux/timex.h>
8#include <linux/random.h>
9#include <linux/init.h>
10#include <linux/kernel_stat.h>
11#include <linux/syscore_ops.h>
12#include <linux/bitops.h>
13#include <linux/acpi.h>
14#include <linux/io.h>
15#include <linux/delay.h>
16
17#include <linux/atomic.h>
18#include <asm/timer.h>
19#include <asm/hw_irq.h>
20#include <asm/pgtable.h>
21#include <asm/desc.h>
22#include <asm/apic.h>
23#include <asm/i8259.h>
24
25/*
26 * This is the 'legacy' 8259A Programmable Interrupt Controller,
27 * present in the majority of PC/AT boxes.
28 * plus some generic x86 specific things if generic specifics makes
29 * any sense at all.
30 */
31static void init_8259A(int auto_eoi);
32
33static int i8259A_auto_eoi;
34DEFINE_RAW_SPINLOCK(i8259A_lock);
35
36/*
37 * 8259A PIC functions to handle ISA devices:
38 */
39
40/*
41 * This contains the irq mask for both 8259A irq controllers,
42 */
43unsigned int cached_irq_mask = 0xffff;
44
45/*
46 * Not all IRQs can be routed through the IO-APIC, eg. on certain (older)
47 * boards the timer interrupt is not really connected to any IO-APIC pin,
48 * it's fed to the master 8259A's IR0 line only.
49 *
50 * Any '1' bit in this mask means the IRQ is routed through the IO-APIC.
51 * this 'mixed mode' IRQ handling costs nothing because it's only used
52 * at IRQ setup time.
53 */
54unsigned long io_apic_irqs;
55
56static void mask_8259A_irq(unsigned int irq)
57{
58 unsigned int mask = 1 << irq;
59 unsigned long flags;
60
61 raw_spin_lock_irqsave(&i8259A_lock, flags);
62 cached_irq_mask |= mask;
63 if (irq & 8)
64 outb(cached_slave_mask, PIC_SLAVE_IMR);
65 else
66 outb(cached_master_mask, PIC_MASTER_IMR);
67 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
68}
69
70static void disable_8259A_irq(struct irq_data *data)
71{
72 mask_8259A_irq(data->irq);
73}
74
75static void unmask_8259A_irq(unsigned int irq)
76{
77 unsigned int mask = ~(1 << irq);
78 unsigned long flags;
79
80 raw_spin_lock_irqsave(&i8259A_lock, flags);
81 cached_irq_mask &= mask;
82 if (irq & 8)
83 outb(cached_slave_mask, PIC_SLAVE_IMR);
84 else
85 outb(cached_master_mask, PIC_MASTER_IMR);
86 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
87}
88
89static void enable_8259A_irq(struct irq_data *data)
90{
91 unmask_8259A_irq(data->irq);
92}
93
94static int i8259A_irq_pending(unsigned int irq)
95{
96 unsigned int mask = 1<<irq;
97 unsigned long flags;
98 int ret;
99
100 raw_spin_lock_irqsave(&i8259A_lock, flags);
101 if (irq < 8)
102 ret = inb(PIC_MASTER_CMD) & mask;
103 else
104 ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
105 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
106
107 return ret;
108}
109
110static void make_8259A_irq(unsigned int irq)
111{
112 disable_irq_nosync(irq);
113 io_apic_irqs &= ~(1<<irq);
114 irq_set_chip_and_handler(irq, &i8259A_chip, handle_level_irq);
115 enable_irq(irq);
116}
117
118/*
119 * This function assumes to be called rarely. Switching between
120 * 8259A registers is slow.
121 * This has to be protected by the irq controller spinlock
122 * before being called.
123 */
124static inline int i8259A_irq_real(unsigned int irq)
125{
126 int value;
127 int irqmask = 1<<irq;
128
129 if (irq < 8) {
130 outb(0x0B, PIC_MASTER_CMD); /* ISR register */
131 value = inb(PIC_MASTER_CMD) & irqmask;
132 outb(0x0A, PIC_MASTER_CMD); /* back to the IRR register */
133 return value;
134 }
135 outb(0x0B, PIC_SLAVE_CMD); /* ISR register */
136 value = inb(PIC_SLAVE_CMD) & (irqmask >> 8);
137 outb(0x0A, PIC_SLAVE_CMD); /* back to the IRR register */
138 return value;
139}
140
141/*
142 * Careful! The 8259A is a fragile beast, it pretty
143 * much _has_ to be done exactly like this (mask it
144 * first, _then_ send the EOI, and the order of EOI
145 * to the two 8259s is important!
146 */
147static void mask_and_ack_8259A(struct irq_data *data)
148{
149 unsigned int irq = data->irq;
150 unsigned int irqmask = 1 << irq;
151 unsigned long flags;
152
153 raw_spin_lock_irqsave(&i8259A_lock, flags);
154 /*
155 * Lightweight spurious IRQ detection. We do not want
156 * to overdo spurious IRQ handling - it's usually a sign
157 * of hardware problems, so we only do the checks we can
158 * do without slowing down good hardware unnecessarily.
159 *
160 * Note that IRQ7 and IRQ15 (the two spurious IRQs
161 * usually resulting from the 8259A-1|2 PICs) occur
162 * even if the IRQ is masked in the 8259A. Thus we
163 * can check spurious 8259A IRQs without doing the
164 * quite slow i8259A_irq_real() call for every IRQ.
165 * This does not cover 100% of spurious interrupts,
166 * but should be enough to warn the user that there
167 * is something bad going on ...
168 */
169 if (cached_irq_mask & irqmask)
170 goto spurious_8259A_irq;
171 cached_irq_mask |= irqmask;
172
173handle_real_irq:
174 if (irq & 8) {
175 inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
176 outb(cached_slave_mask, PIC_SLAVE_IMR);
177 /* 'Specific EOI' to slave */
178 outb(0x60+(irq&7), PIC_SLAVE_CMD);
179 /* 'Specific EOI' to master-IRQ2 */
180 outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD);
181 } else {
182 inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
183 outb(cached_master_mask, PIC_MASTER_IMR);
184 outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */
185 }
186 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
187 return;
188
189spurious_8259A_irq:
190 /*
191 * this is the slow path - should happen rarely.
192 */
193 if (i8259A_irq_real(irq))
194 /*
195 * oops, the IRQ _is_ in service according to the
196 * 8259A - not spurious, go handle it.
197 */
198 goto handle_real_irq;
199
200 {
201 static int spurious_irq_mask;
202 /*
203 * At this point we can be sure the IRQ is spurious,
204 * lets ACK and report it. [once per IRQ]
205 */
206 if (!(spurious_irq_mask & irqmask)) {
207 printk(KERN_DEBUG
208 "spurious 8259A interrupt: IRQ%d.\n", irq);
209 spurious_irq_mask |= irqmask;
210 }
211 atomic_inc(&irq_err_count);
212 /*
213 * Theoretically we do not have to handle this IRQ,
214 * but in Linux this does not cause problems and is
215 * simpler for us.
216 */
217 goto handle_real_irq;
218 }
219}
220
221struct irq_chip i8259A_chip = {
222 .name = "XT-PIC",
223 .irq_mask = disable_8259A_irq,
224 .irq_disable = disable_8259A_irq,
225 .irq_unmask = enable_8259A_irq,
226 .irq_mask_ack = mask_and_ack_8259A,
227};
228
229static char irq_trigger[2];
230/**
231 * ELCR registers (0x4d0, 0x4d1) control edge/level of IRQ
232 */
233static void restore_ELCR(char *trigger)
234{
235 outb(trigger[0], 0x4d0);
236 outb(trigger[1], 0x4d1);
237}
238
239static void save_ELCR(char *trigger)
240{
241 /* IRQ 0,1,2,8,13 are marked as reserved */
242 trigger[0] = inb(0x4d0) & 0xF8;
243 trigger[1] = inb(0x4d1) & 0xDE;
244}
245
246static void i8259A_resume(void)
247{
248 init_8259A(i8259A_auto_eoi);
249 restore_ELCR(irq_trigger);
250}
251
252static int i8259A_suspend(void)
253{
254 save_ELCR(irq_trigger);
255 return 0;
256}
257
258static void i8259A_shutdown(void)
259{
260 /* Put the i8259A into a quiescent state that
261 * the kernel initialization code can get it
262 * out of.
263 */
264 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
265 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
266}
267
268static struct syscore_ops i8259_syscore_ops = {
269 .suspend = i8259A_suspend,
270 .resume = i8259A_resume,
271 .shutdown = i8259A_shutdown,
272};
273
274static void mask_8259A(void)
275{
276 unsigned long flags;
277
278 raw_spin_lock_irqsave(&i8259A_lock, flags);
279
280 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
281 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
282
283 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
284}
285
286static void unmask_8259A(void)
287{
288 unsigned long flags;
289
290 raw_spin_lock_irqsave(&i8259A_lock, flags);
291
292 outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
293 outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
294
295 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
296}
297
298static int probe_8259A(void)
299{
300 unsigned long flags;
301 unsigned char probe_val = ~(1 << PIC_CASCADE_IR);
302 unsigned char new_val;
303 /*
304 * Check to see if we have a PIC.
305 * Mask all except the cascade and read
306 * back the value we just wrote. If we don't
307 * have a PIC, we will read 0xff as opposed to the
308 * value we wrote.
309 */
310 raw_spin_lock_irqsave(&i8259A_lock, flags);
311
312 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
313 outb(probe_val, PIC_MASTER_IMR);
314 new_val = inb(PIC_MASTER_IMR);
315 if (new_val != probe_val) {
316 printk(KERN_INFO "Using NULL legacy PIC\n");
317 legacy_pic = &null_legacy_pic;
318 }
319
320 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
321 return nr_legacy_irqs();
322}
323
324static void init_8259A(int auto_eoi)
325{
326 unsigned long flags;
327
328 i8259A_auto_eoi = auto_eoi;
329
330 raw_spin_lock_irqsave(&i8259A_lock, flags);
331
332 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
333
334 /*
335 * outb_pic - this has to work on a wide range of PC hardware.
336 */
337 outb_pic(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */
338
339 /* ICW2: 8259A-1 IR0-7 mapped to ISA_IRQ_VECTOR(0) */
340 outb_pic(ISA_IRQ_VECTOR(0), PIC_MASTER_IMR);
341
342 /* 8259A-1 (the master) has a slave on IR2 */
343 outb_pic(1U << PIC_CASCADE_IR, PIC_MASTER_IMR);
344
345 if (auto_eoi) /* master does Auto EOI */
346 outb_pic(MASTER_ICW4_DEFAULT | PIC_ICW4_AEOI, PIC_MASTER_IMR);
347 else /* master expects normal EOI */
348 outb_pic(MASTER_ICW4_DEFAULT, PIC_MASTER_IMR);
349
350 outb_pic(0x11, PIC_SLAVE_CMD); /* ICW1: select 8259A-2 init */
351
352 /* ICW2: 8259A-2 IR0-7 mapped to ISA_IRQ_VECTOR(8) */
353 outb_pic(ISA_IRQ_VECTOR(8), PIC_SLAVE_IMR);
354 /* 8259A-2 is a slave on master's IR2 */
355 outb_pic(PIC_CASCADE_IR, PIC_SLAVE_IMR);
356 /* (slave's support for AEOI in flat mode is to be investigated) */
357 outb_pic(SLAVE_ICW4_DEFAULT, PIC_SLAVE_IMR);
358
359 if (auto_eoi)
360 /*
361 * In AEOI mode we just have to mask the interrupt
362 * when acking.
363 */
364 i8259A_chip.irq_mask_ack = disable_8259A_irq;
365 else
366 i8259A_chip.irq_mask_ack = mask_and_ack_8259A;
367
368 udelay(100); /* wait for 8259A to initialize */
369
370 outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
371 outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
372
373 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
374}
375
376/*
377 * make i8259 a driver so that we can select pic functions at run time. the goal
378 * is to make x86 binary compatible among pc compatible and non-pc compatible
379 * platforms, such as x86 MID.
380 */
381
382static void legacy_pic_noop(void) { };
383static void legacy_pic_uint_noop(unsigned int unused) { };
384static void legacy_pic_int_noop(int unused) { };
385static int legacy_pic_irq_pending_noop(unsigned int irq)
386{
387 return 0;
388}
389static int legacy_pic_probe(void)
390{
391 return 0;
392}
393
394struct legacy_pic null_legacy_pic = {
395 .nr_legacy_irqs = 0,
396 .chip = &dummy_irq_chip,
397 .mask = legacy_pic_uint_noop,
398 .unmask = legacy_pic_uint_noop,
399 .mask_all = legacy_pic_noop,
400 .restore_mask = legacy_pic_noop,
401 .init = legacy_pic_int_noop,
402 .probe = legacy_pic_probe,
403 .irq_pending = legacy_pic_irq_pending_noop,
404 .make_irq = legacy_pic_uint_noop,
405};
406
407struct legacy_pic default_legacy_pic = {
408 .nr_legacy_irqs = NR_IRQS_LEGACY,
409 .chip = &i8259A_chip,
410 .mask = mask_8259A_irq,
411 .unmask = unmask_8259A_irq,
412 .mask_all = mask_8259A,
413 .restore_mask = unmask_8259A,
414 .init = init_8259A,
415 .probe = probe_8259A,
416 .irq_pending = i8259A_irq_pending,
417 .make_irq = make_8259A_irq,
418};
419
420struct legacy_pic *legacy_pic = &default_legacy_pic;
421
422static int __init i8259A_init_ops(void)
423{
424 if (legacy_pic == &default_legacy_pic)
425 register_syscore_ops(&i8259_syscore_ops);
426
427 return 0;
428}
429
430device_initcall(i8259A_init_ops);