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1// SPDX-License-Identifier: GPL-2.0
2/* Various workarounds for chipset bugs.
3 This code runs very early and can't use the regular PCI subsystem
4 The entries are keyed to PCI bridges which usually identify chipsets
5 uniquely.
6 This is only for whole classes of chipsets with specific problems which
7 need early invasive action (e.g. before the timers are initialized).
8 Most PCI device specific workarounds can be done later and should be
9 in standard PCI quirks
10 Mainboard specific bugs should be handled by DMI entries.
11 CPU specific bugs in setup.c */
12
13#include <linux/pci.h>
14#include <linux/acpi.h>
15#include <linux/delay.h>
16#include <linux/pci_ids.h>
17#include <linux/bcma/bcma.h>
18#include <linux/bcma/bcma_regs.h>
19#include <linux/platform_data/x86/apple.h>
20#include <drm/i915_drm.h>
21#include <asm/pci-direct.h>
22#include <asm/dma.h>
23#include <asm/io_apic.h>
24#include <asm/apic.h>
25#include <asm/hpet.h>
26#include <asm/iommu.h>
27#include <asm/gart.h>
28#include <asm/irq_remapping.h>
29#include <asm/early_ioremap.h>
30
31static void __init fix_hypertransport_config(int num, int slot, int func)
32{
33 u32 htcfg;
34 /*
35 * we found a hypertransport bus
36 * make sure that we are broadcasting
37 * interrupts to all cpus on the ht bus
38 * if we're using extended apic ids
39 */
40 htcfg = read_pci_config(num, slot, func, 0x68);
41 if (htcfg & (1 << 18)) {
42 printk(KERN_INFO "Detected use of extended apic ids "
43 "on hypertransport bus\n");
44 if ((htcfg & (1 << 17)) == 0) {
45 printk(KERN_INFO "Enabling hypertransport extended "
46 "apic interrupt broadcast\n");
47 printk(KERN_INFO "Note this is a bios bug, "
48 "please contact your hw vendor\n");
49 htcfg |= (1 << 17);
50 write_pci_config(num, slot, func, 0x68, htcfg);
51 }
52 }
53
54
55}
56
57static void __init via_bugs(int num, int slot, int func)
58{
59#ifdef CONFIG_GART_IOMMU
60 if ((max_pfn > MAX_DMA32_PFN || force_iommu) &&
61 !gart_iommu_aperture_allowed) {
62 printk(KERN_INFO
63 "Looks like a VIA chipset. Disabling IOMMU."
64 " Override with iommu=allowed\n");
65 gart_iommu_aperture_disabled = 1;
66 }
67#endif
68}
69
70#ifdef CONFIG_ACPI
71#ifdef CONFIG_X86_IO_APIC
72
73static int __init nvidia_hpet_check(struct acpi_table_header *header)
74{
75 return 0;
76}
77#endif /* CONFIG_X86_IO_APIC */
78#endif /* CONFIG_ACPI */
79
80static void __init nvidia_bugs(int num, int slot, int func)
81{
82#ifdef CONFIG_ACPI
83#ifdef CONFIG_X86_IO_APIC
84 /*
85 * Only applies to Nvidia root ports (bus 0) and not to
86 * Nvidia graphics cards with PCI ports on secondary buses.
87 */
88 if (num)
89 return;
90
91 /*
92 * All timer overrides on Nvidia are
93 * wrong unless HPET is enabled.
94 * Unfortunately that's not true on many Asus boards.
95 * We don't know yet how to detect this automatically, but
96 * at least allow a command line override.
97 */
98 if (acpi_use_timer_override)
99 return;
100
101 if (acpi_table_parse(ACPI_SIG_HPET, nvidia_hpet_check)) {
102 acpi_skip_timer_override = 1;
103 printk(KERN_INFO "Nvidia board "
104 "detected. Ignoring ACPI "
105 "timer override.\n");
106 printk(KERN_INFO "If you got timer trouble "
107 "try acpi_use_timer_override\n");
108 }
109#endif
110#endif
111 /* RED-PEN skip them on mptables too? */
112
113}
114
115#if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC)
116static u32 __init ati_ixp4x0_rev(int num, int slot, int func)
117{
118 u32 d;
119 u8 b;
120
121 b = read_pci_config_byte(num, slot, func, 0xac);
122 b &= ~(1<<5);
123 write_pci_config_byte(num, slot, func, 0xac, b);
124
125 d = read_pci_config(num, slot, func, 0x70);
126 d |= 1<<8;
127 write_pci_config(num, slot, func, 0x70, d);
128
129 d = read_pci_config(num, slot, func, 0x8);
130 d &= 0xff;
131 return d;
132}
133
134static void __init ati_bugs(int num, int slot, int func)
135{
136 u32 d;
137 u8 b;
138
139 if (acpi_use_timer_override)
140 return;
141
142 d = ati_ixp4x0_rev(num, slot, func);
143 if (d < 0x82)
144 acpi_skip_timer_override = 1;
145 else {
146 /* check for IRQ0 interrupt swap */
147 outb(0x72, 0xcd6); b = inb(0xcd7);
148 if (!(b & 0x2))
149 acpi_skip_timer_override = 1;
150 }
151
152 if (acpi_skip_timer_override) {
153 printk(KERN_INFO "SB4X0 revision 0x%x\n", d);
154 printk(KERN_INFO "Ignoring ACPI timer override.\n");
155 printk(KERN_INFO "If you got timer trouble "
156 "try acpi_use_timer_override\n");
157 }
158}
159
160static u32 __init ati_sbx00_rev(int num, int slot, int func)
161{
162 u32 d;
163
164 d = read_pci_config(num, slot, func, 0x8);
165 d &= 0xff;
166
167 return d;
168}
169
170static void __init ati_bugs_contd(int num, int slot, int func)
171{
172 u32 d, rev;
173
174 rev = ati_sbx00_rev(num, slot, func);
175 if (rev >= 0x40)
176 acpi_fix_pin2_polarity = 1;
177
178 /*
179 * SB600: revisions 0x11, 0x12, 0x13, 0x14, ...
180 * SB700: revisions 0x39, 0x3a, ...
181 * SB800: revisions 0x40, 0x41, ...
182 */
183 if (rev >= 0x39)
184 return;
185
186 if (acpi_use_timer_override)
187 return;
188
189 /* check for IRQ0 interrupt swap */
190 d = read_pci_config(num, slot, func, 0x64);
191 if (!(d & (1<<14)))
192 acpi_skip_timer_override = 1;
193
194 if (acpi_skip_timer_override) {
195 printk(KERN_INFO "SB600 revision 0x%x\n", rev);
196 printk(KERN_INFO "Ignoring ACPI timer override.\n");
197 printk(KERN_INFO "If you got timer trouble "
198 "try acpi_use_timer_override\n");
199 }
200}
201#else
202static void __init ati_bugs(int num, int slot, int func)
203{
204}
205
206static void __init ati_bugs_contd(int num, int slot, int func)
207{
208}
209#endif
210
211static void __init intel_remapping_check(int num, int slot, int func)
212{
213 u8 revision;
214 u16 device;
215
216 device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
217 revision = read_pci_config_byte(num, slot, func, PCI_REVISION_ID);
218
219 /*
220 * Revision <= 13 of all triggering devices id in this quirk
221 * have a problem draining interrupts when irq remapping is
222 * enabled, and should be flagged as broken. Additionally
223 * revision 0x22 of device id 0x3405 has this problem.
224 */
225 if (revision <= 0x13)
226 set_irq_remapping_broken();
227 else if (device == 0x3405 && revision == 0x22)
228 set_irq_remapping_broken();
229}
230
231/*
232 * Systems with Intel graphics controllers set aside memory exclusively
233 * for gfx driver use. This memory is not marked in the E820 as reserved
234 * or as RAM, and so is subject to overlap from E820 manipulation later
235 * in the boot process. On some systems, MMIO space is allocated on top,
236 * despite the efforts of the "RAM buffer" approach, which simply rounds
237 * memory boundaries up to 64M to try to catch space that may decode
238 * as RAM and so is not suitable for MMIO.
239 */
240
241#define KB(x) ((x) * 1024UL)
242#define MB(x) (KB (KB (x)))
243
244static resource_size_t __init i830_tseg_size(void)
245{
246 u8 esmramc = read_pci_config_byte(0, 0, 0, I830_ESMRAMC);
247
248 if (!(esmramc & TSEG_ENABLE))
249 return 0;
250
251 if (esmramc & I830_TSEG_SIZE_1M)
252 return MB(1);
253 else
254 return KB(512);
255}
256
257static resource_size_t __init i845_tseg_size(void)
258{
259 u8 esmramc = read_pci_config_byte(0, 0, 0, I845_ESMRAMC);
260 u8 tseg_size = esmramc & I845_TSEG_SIZE_MASK;
261
262 if (!(esmramc & TSEG_ENABLE))
263 return 0;
264
265 switch (tseg_size) {
266 case I845_TSEG_SIZE_512K: return KB(512);
267 case I845_TSEG_SIZE_1M: return MB(1);
268 default:
269 WARN(1, "Unknown ESMRAMC value: %x!\n", esmramc);
270 }
271 return 0;
272}
273
274static resource_size_t __init i85x_tseg_size(void)
275{
276 u8 esmramc = read_pci_config_byte(0, 0, 0, I85X_ESMRAMC);
277
278 if (!(esmramc & TSEG_ENABLE))
279 return 0;
280
281 return MB(1);
282}
283
284static resource_size_t __init i830_mem_size(void)
285{
286 return read_pci_config_byte(0, 0, 0, I830_DRB3) * MB(32);
287}
288
289static resource_size_t __init i85x_mem_size(void)
290{
291 return read_pci_config_byte(0, 0, 1, I85X_DRB3) * MB(32);
292}
293
294/*
295 * On 830/845/85x the stolen memory base isn't available in any
296 * register. We need to calculate it as TOM-TSEG_SIZE-stolen_size.
297 */
298static resource_size_t __init i830_stolen_base(int num, int slot, int func,
299 resource_size_t stolen_size)
300{
301 return i830_mem_size() - i830_tseg_size() - stolen_size;
302}
303
304static resource_size_t __init i845_stolen_base(int num, int slot, int func,
305 resource_size_t stolen_size)
306{
307 return i830_mem_size() - i845_tseg_size() - stolen_size;
308}
309
310static resource_size_t __init i85x_stolen_base(int num, int slot, int func,
311 resource_size_t stolen_size)
312{
313 return i85x_mem_size() - i85x_tseg_size() - stolen_size;
314}
315
316static resource_size_t __init i865_stolen_base(int num, int slot, int func,
317 resource_size_t stolen_size)
318{
319 u16 toud = 0;
320
321 toud = read_pci_config_16(0, 0, 0, I865_TOUD);
322
323 return toud * KB(64) + i845_tseg_size();
324}
325
326static resource_size_t __init gen3_stolen_base(int num, int slot, int func,
327 resource_size_t stolen_size)
328{
329 u32 bsm;
330
331 /* Almost universally we can find the Graphics Base of Stolen Memory
332 * at register BSM (0x5c) in the igfx configuration space. On a few
333 * (desktop) machines this is also mirrored in the bridge device at
334 * different locations, or in the MCHBAR.
335 */
336 bsm = read_pci_config(num, slot, func, INTEL_BSM);
337
338 return bsm & INTEL_BSM_MASK;
339}
340
341static resource_size_t __init gen11_stolen_base(int num, int slot, int func,
342 resource_size_t stolen_size)
343{
344 u64 bsm;
345
346 bsm = read_pci_config(num, slot, func, INTEL_GEN11_BSM_DW0);
347 bsm &= INTEL_BSM_MASK;
348 bsm |= (u64)read_pci_config(num, slot, func, INTEL_GEN11_BSM_DW1) << 32;
349
350 return bsm;
351}
352
353static resource_size_t __init i830_stolen_size(int num, int slot, int func)
354{
355 u16 gmch_ctrl;
356 u16 gms;
357
358 gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
359 gms = gmch_ctrl & I830_GMCH_GMS_MASK;
360
361 switch (gms) {
362 case I830_GMCH_GMS_STOLEN_512: return KB(512);
363 case I830_GMCH_GMS_STOLEN_1024: return MB(1);
364 case I830_GMCH_GMS_STOLEN_8192: return MB(8);
365 /* local memory isn't part of the normal address space */
366 case I830_GMCH_GMS_LOCAL: return 0;
367 default:
368 WARN(1, "Unknown GMCH_CTRL value: %x!\n", gmch_ctrl);
369 }
370
371 return 0;
372}
373
374static resource_size_t __init gen3_stolen_size(int num, int slot, int func)
375{
376 u16 gmch_ctrl;
377 u16 gms;
378
379 gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
380 gms = gmch_ctrl & I855_GMCH_GMS_MASK;
381
382 switch (gms) {
383 case I855_GMCH_GMS_STOLEN_1M: return MB(1);
384 case I855_GMCH_GMS_STOLEN_4M: return MB(4);
385 case I855_GMCH_GMS_STOLEN_8M: return MB(8);
386 case I855_GMCH_GMS_STOLEN_16M: return MB(16);
387 case I855_GMCH_GMS_STOLEN_32M: return MB(32);
388 case I915_GMCH_GMS_STOLEN_48M: return MB(48);
389 case I915_GMCH_GMS_STOLEN_64M: return MB(64);
390 case G33_GMCH_GMS_STOLEN_128M: return MB(128);
391 case G33_GMCH_GMS_STOLEN_256M: return MB(256);
392 case INTEL_GMCH_GMS_STOLEN_96M: return MB(96);
393 case INTEL_GMCH_GMS_STOLEN_160M:return MB(160);
394 case INTEL_GMCH_GMS_STOLEN_224M:return MB(224);
395 case INTEL_GMCH_GMS_STOLEN_352M:return MB(352);
396 default:
397 WARN(1, "Unknown GMCH_CTRL value: %x!\n", gmch_ctrl);
398 }
399
400 return 0;
401}
402
403static resource_size_t __init gen6_stolen_size(int num, int slot, int func)
404{
405 u16 gmch_ctrl;
406 u16 gms;
407
408 gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
409 gms = (gmch_ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK;
410
411 return gms * MB(32);
412}
413
414static resource_size_t __init gen8_stolen_size(int num, int slot, int func)
415{
416 u16 gmch_ctrl;
417 u16 gms;
418
419 gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
420 gms = (gmch_ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK;
421
422 return gms * MB(32);
423}
424
425static resource_size_t __init chv_stolen_size(int num, int slot, int func)
426{
427 u16 gmch_ctrl;
428 u16 gms;
429
430 gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
431 gms = (gmch_ctrl >> SNB_GMCH_GMS_SHIFT) & SNB_GMCH_GMS_MASK;
432
433 /*
434 * 0x0 to 0x10: 32MB increments starting at 0MB
435 * 0x11 to 0x16: 4MB increments starting at 8MB
436 * 0x17 to 0x1d: 4MB increments start at 36MB
437 */
438 if (gms < 0x11)
439 return gms * MB(32);
440 else if (gms < 0x17)
441 return (gms - 0x11) * MB(4) + MB(8);
442 else
443 return (gms - 0x17) * MB(4) + MB(36);
444}
445
446static resource_size_t __init gen9_stolen_size(int num, int slot, int func)
447{
448 u16 gmch_ctrl;
449 u16 gms;
450
451 gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
452 gms = (gmch_ctrl >> BDW_GMCH_GMS_SHIFT) & BDW_GMCH_GMS_MASK;
453
454 /* 0x0 to 0xef: 32MB increments starting at 0MB */
455 /* 0xf0 to 0xfe: 4MB increments starting at 4MB */
456 if (gms < 0xf0)
457 return gms * MB(32);
458 else
459 return (gms - 0xf0) * MB(4) + MB(4);
460}
461
462struct intel_early_ops {
463 resource_size_t (*stolen_size)(int num, int slot, int func);
464 resource_size_t (*stolen_base)(int num, int slot, int func,
465 resource_size_t size);
466};
467
468static const struct intel_early_ops i830_early_ops __initconst = {
469 .stolen_base = i830_stolen_base,
470 .stolen_size = i830_stolen_size,
471};
472
473static const struct intel_early_ops i845_early_ops __initconst = {
474 .stolen_base = i845_stolen_base,
475 .stolen_size = i830_stolen_size,
476};
477
478static const struct intel_early_ops i85x_early_ops __initconst = {
479 .stolen_base = i85x_stolen_base,
480 .stolen_size = gen3_stolen_size,
481};
482
483static const struct intel_early_ops i865_early_ops __initconst = {
484 .stolen_base = i865_stolen_base,
485 .stolen_size = gen3_stolen_size,
486};
487
488static const struct intel_early_ops gen3_early_ops __initconst = {
489 .stolen_base = gen3_stolen_base,
490 .stolen_size = gen3_stolen_size,
491};
492
493static const struct intel_early_ops gen6_early_ops __initconst = {
494 .stolen_base = gen3_stolen_base,
495 .stolen_size = gen6_stolen_size,
496};
497
498static const struct intel_early_ops gen8_early_ops __initconst = {
499 .stolen_base = gen3_stolen_base,
500 .stolen_size = gen8_stolen_size,
501};
502
503static const struct intel_early_ops gen9_early_ops __initconst = {
504 .stolen_base = gen3_stolen_base,
505 .stolen_size = gen9_stolen_size,
506};
507
508static const struct intel_early_ops chv_early_ops __initconst = {
509 .stolen_base = gen3_stolen_base,
510 .stolen_size = chv_stolen_size,
511};
512
513static const struct intel_early_ops gen11_early_ops __initconst = {
514 .stolen_base = gen11_stolen_base,
515 .stolen_size = gen9_stolen_size,
516};
517
518static const struct pci_device_id intel_early_ids[] __initconst = {
519 INTEL_I830_IDS(&i830_early_ops),
520 INTEL_I845G_IDS(&i845_early_ops),
521 INTEL_I85X_IDS(&i85x_early_ops),
522 INTEL_I865G_IDS(&i865_early_ops),
523 INTEL_I915G_IDS(&gen3_early_ops),
524 INTEL_I915GM_IDS(&gen3_early_ops),
525 INTEL_I945G_IDS(&gen3_early_ops),
526 INTEL_I945GM_IDS(&gen3_early_ops),
527 INTEL_VLV_IDS(&gen6_early_ops),
528 INTEL_PINEVIEW_G_IDS(&gen3_early_ops),
529 INTEL_PINEVIEW_M_IDS(&gen3_early_ops),
530 INTEL_I965G_IDS(&gen3_early_ops),
531 INTEL_G33_IDS(&gen3_early_ops),
532 INTEL_I965GM_IDS(&gen3_early_ops),
533 INTEL_GM45_IDS(&gen3_early_ops),
534 INTEL_G45_IDS(&gen3_early_ops),
535 INTEL_IRONLAKE_D_IDS(&gen3_early_ops),
536 INTEL_IRONLAKE_M_IDS(&gen3_early_ops),
537 INTEL_SNB_D_IDS(&gen6_early_ops),
538 INTEL_SNB_M_IDS(&gen6_early_ops),
539 INTEL_IVB_M_IDS(&gen6_early_ops),
540 INTEL_IVB_D_IDS(&gen6_early_ops),
541 INTEL_HSW_IDS(&gen6_early_ops),
542 INTEL_BDW_IDS(&gen8_early_ops),
543 INTEL_CHV_IDS(&chv_early_ops),
544 INTEL_SKL_IDS(&gen9_early_ops),
545 INTEL_BXT_IDS(&gen9_early_ops),
546 INTEL_KBL_IDS(&gen9_early_ops),
547 INTEL_CFL_IDS(&gen9_early_ops),
548 INTEL_GLK_IDS(&gen9_early_ops),
549 INTEL_CNL_IDS(&gen9_early_ops),
550 INTEL_ICL_11_IDS(&gen11_early_ops),
551 INTEL_EHL_IDS(&gen11_early_ops),
552 INTEL_TGL_12_IDS(&gen11_early_ops),
553};
554
555struct resource intel_graphics_stolen_res __ro_after_init = DEFINE_RES_MEM(0, 0);
556EXPORT_SYMBOL(intel_graphics_stolen_res);
557
558static void __init
559intel_graphics_stolen(int num, int slot, int func,
560 const struct intel_early_ops *early_ops)
561{
562 resource_size_t base, size;
563 resource_size_t end;
564
565 size = early_ops->stolen_size(num, slot, func);
566 base = early_ops->stolen_base(num, slot, func, size);
567
568 if (!size || !base)
569 return;
570
571 end = base + size - 1;
572
573 intel_graphics_stolen_res.start = base;
574 intel_graphics_stolen_res.end = end;
575
576 printk(KERN_INFO "Reserving Intel graphics memory at %pR\n",
577 &intel_graphics_stolen_res);
578
579 /* Mark this space as reserved */
580 e820__range_add(base, size, E820_TYPE_RESERVED);
581 e820__update_table(e820_table);
582}
583
584static void __init intel_graphics_quirks(int num, int slot, int func)
585{
586 const struct intel_early_ops *early_ops;
587 u16 device;
588 int i;
589
590 device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
591
592 for (i = 0; i < ARRAY_SIZE(intel_early_ids); i++) {
593 kernel_ulong_t driver_data = intel_early_ids[i].driver_data;
594
595 if (intel_early_ids[i].device != device)
596 continue;
597
598 early_ops = (typeof(early_ops))driver_data;
599
600 intel_graphics_stolen(num, slot, func, early_ops);
601
602 return;
603 }
604}
605
606static void __init force_disable_hpet(int num, int slot, int func)
607{
608#ifdef CONFIG_HPET_TIMER
609 boot_hpet_disable = true;
610 pr_info("x86/hpet: Will disable the HPET for this platform because it's not reliable\n");
611#endif
612}
613
614#define BCM4331_MMIO_SIZE 16384
615#define BCM4331_PM_CAP 0x40
616#define bcma_aread32(reg) ioread32(mmio + 1 * BCMA_CORE_SIZE + reg)
617#define bcma_awrite32(reg, val) iowrite32(val, mmio + 1 * BCMA_CORE_SIZE + reg)
618
619static void __init apple_airport_reset(int bus, int slot, int func)
620{
621 void __iomem *mmio;
622 u16 pmcsr;
623 u64 addr;
624 int i;
625
626 if (!x86_apple_machine)
627 return;
628
629 /* Card may have been put into PCI_D3hot by grub quirk */
630 pmcsr = read_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL);
631
632 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) {
633 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
634 write_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL, pmcsr);
635 mdelay(10);
636
637 pmcsr = read_pci_config_16(bus, slot, func, BCM4331_PM_CAP + PCI_PM_CTRL);
638 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) {
639 pr_err("pci 0000:%02x:%02x.%d: Cannot power up Apple AirPort card\n",
640 bus, slot, func);
641 return;
642 }
643 }
644
645 addr = read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_0);
646 addr |= (u64)read_pci_config(bus, slot, func, PCI_BASE_ADDRESS_1) << 32;
647 addr &= PCI_BASE_ADDRESS_MEM_MASK;
648
649 mmio = early_ioremap(addr, BCM4331_MMIO_SIZE);
650 if (!mmio) {
651 pr_err("pci 0000:%02x:%02x.%d: Cannot iomap Apple AirPort card\n",
652 bus, slot, func);
653 return;
654 }
655
656 pr_info("Resetting Apple AirPort card (left enabled by EFI)\n");
657
658 for (i = 0; bcma_aread32(BCMA_RESET_ST) && i < 30; i++)
659 udelay(10);
660
661 bcma_awrite32(BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
662 bcma_aread32(BCMA_RESET_CTL);
663 udelay(1);
664
665 bcma_awrite32(BCMA_RESET_CTL, 0);
666 bcma_aread32(BCMA_RESET_CTL);
667 udelay(10);
668
669 early_iounmap(mmio, BCM4331_MMIO_SIZE);
670}
671
672#define QFLAG_APPLY_ONCE 0x1
673#define QFLAG_APPLIED 0x2
674#define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
675struct chipset {
676 u32 vendor;
677 u32 device;
678 u32 class;
679 u32 class_mask;
680 u32 flags;
681 void (*f)(int num, int slot, int func);
682};
683
684static struct chipset early_qrk[] __initdata = {
685 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
686 PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs },
687 { PCI_VENDOR_ID_VIA, PCI_ANY_ID,
688 PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs },
689 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
690 PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config },
691 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
692 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
693 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
694 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
695 { PCI_VENDOR_ID_INTEL, 0x3403, PCI_CLASS_BRIDGE_HOST,
696 PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
697 { PCI_VENDOR_ID_INTEL, 0x3405, PCI_CLASS_BRIDGE_HOST,
698 PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
699 { PCI_VENDOR_ID_INTEL, 0x3406, PCI_CLASS_BRIDGE_HOST,
700 PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
701 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, PCI_ANY_ID,
702 QFLAG_APPLY_ONCE, intel_graphics_quirks },
703 /*
704 * HPET on the current version of the Baytrail platform has accuracy
705 * problems: it will halt in deep idle state - so we disable it.
706 *
707 * More details can be found in section 18.10.1.3 of the datasheet:
708 *
709 * http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-z8000-datasheet-vol-1.pdf
710 */
711 { PCI_VENDOR_ID_INTEL, 0x0f00,
712 PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet},
713 { PCI_VENDOR_ID_INTEL, 0x3ec4,
714 PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet},
715 { PCI_VENDOR_ID_BROADCOM, 0x4331,
716 PCI_CLASS_NETWORK_OTHER, PCI_ANY_ID, 0, apple_airport_reset},
717 {}
718};
719
720static void __init early_pci_scan_bus(int bus);
721
722/**
723 * check_dev_quirk - apply early quirks to a given PCI device
724 * @num: bus number
725 * @slot: slot number
726 * @func: PCI function
727 *
728 * Check the vendor & device ID against the early quirks table.
729 *
730 * If the device is single function, let early_pci_scan_bus() know so we don't
731 * poke at this device again.
732 */
733static int __init check_dev_quirk(int num, int slot, int func)
734{
735 u16 class;
736 u16 vendor;
737 u16 device;
738 u8 type;
739 u8 sec;
740 int i;
741
742 class = read_pci_config_16(num, slot, func, PCI_CLASS_DEVICE);
743
744 if (class == 0xffff)
745 return -1; /* no class, treat as single function */
746
747 vendor = read_pci_config_16(num, slot, func, PCI_VENDOR_ID);
748
749 device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
750
751 for (i = 0; early_qrk[i].f != NULL; i++) {
752 if (((early_qrk[i].vendor == PCI_ANY_ID) ||
753 (early_qrk[i].vendor == vendor)) &&
754 ((early_qrk[i].device == PCI_ANY_ID) ||
755 (early_qrk[i].device == device)) &&
756 (!((early_qrk[i].class ^ class) &
757 early_qrk[i].class_mask))) {
758 if ((early_qrk[i].flags &
759 QFLAG_DONE) != QFLAG_DONE)
760 early_qrk[i].f(num, slot, func);
761 early_qrk[i].flags |= QFLAG_APPLIED;
762 }
763 }
764
765 type = read_pci_config_byte(num, slot, func,
766 PCI_HEADER_TYPE);
767
768 if ((type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
769 sec = read_pci_config_byte(num, slot, func, PCI_SECONDARY_BUS);
770 if (sec > num)
771 early_pci_scan_bus(sec);
772 }
773
774 if (!(type & 0x80))
775 return -1;
776
777 return 0;
778}
779
780static void __init early_pci_scan_bus(int bus)
781{
782 int slot, func;
783
784 /* Poor man's PCI discovery */
785 for (slot = 0; slot < 32; slot++)
786 for (func = 0; func < 8; func++) {
787 /* Only probe function 0 on single fn devices */
788 if (check_dev_quirk(bus, slot, func))
789 break;
790 }
791}
792
793void __init early_quirks(void)
794{
795 if (!early_pci_allowed())
796 return;
797
798 early_pci_scan_bus(0);
799}
1/* Various workarounds for chipset bugs.
2 This code runs very early and can't use the regular PCI subsystem
3 The entries are keyed to PCI bridges which usually identify chipsets
4 uniquely.
5 This is only for whole classes of chipsets with specific problems which
6 need early invasive action (e.g. before the timers are initialized).
7 Most PCI device specific workarounds can be done later and should be
8 in standard PCI quirks
9 Mainboard specific bugs should be handled by DMI entries.
10 CPU specific bugs in setup.c */
11
12#include <linux/pci.h>
13#include <linux/acpi.h>
14#include <linux/pci_ids.h>
15#include <drm/i915_drm.h>
16#include <asm/pci-direct.h>
17#include <asm/dma.h>
18#include <asm/io_apic.h>
19#include <asm/apic.h>
20#include <asm/hpet.h>
21#include <asm/iommu.h>
22#include <asm/gart.h>
23#include <asm/irq_remapping.h>
24
25static void __init fix_hypertransport_config(int num, int slot, int func)
26{
27 u32 htcfg;
28 /*
29 * we found a hypertransport bus
30 * make sure that we are broadcasting
31 * interrupts to all cpus on the ht bus
32 * if we're using extended apic ids
33 */
34 htcfg = read_pci_config(num, slot, func, 0x68);
35 if (htcfg & (1 << 18)) {
36 printk(KERN_INFO "Detected use of extended apic ids "
37 "on hypertransport bus\n");
38 if ((htcfg & (1 << 17)) == 0) {
39 printk(KERN_INFO "Enabling hypertransport extended "
40 "apic interrupt broadcast\n");
41 printk(KERN_INFO "Note this is a bios bug, "
42 "please contact your hw vendor\n");
43 htcfg |= (1 << 17);
44 write_pci_config(num, slot, func, 0x68, htcfg);
45 }
46 }
47
48
49}
50
51static void __init via_bugs(int num, int slot, int func)
52{
53#ifdef CONFIG_GART_IOMMU
54 if ((max_pfn > MAX_DMA32_PFN || force_iommu) &&
55 !gart_iommu_aperture_allowed) {
56 printk(KERN_INFO
57 "Looks like a VIA chipset. Disabling IOMMU."
58 " Override with iommu=allowed\n");
59 gart_iommu_aperture_disabled = 1;
60 }
61#endif
62}
63
64#ifdef CONFIG_ACPI
65#ifdef CONFIG_X86_IO_APIC
66
67static int __init nvidia_hpet_check(struct acpi_table_header *header)
68{
69 return 0;
70}
71#endif /* CONFIG_X86_IO_APIC */
72#endif /* CONFIG_ACPI */
73
74static void __init nvidia_bugs(int num, int slot, int func)
75{
76#ifdef CONFIG_ACPI
77#ifdef CONFIG_X86_IO_APIC
78 /*
79 * All timer overrides on Nvidia are
80 * wrong unless HPET is enabled.
81 * Unfortunately that's not true on many Asus boards.
82 * We don't know yet how to detect this automatically, but
83 * at least allow a command line override.
84 */
85 if (acpi_use_timer_override)
86 return;
87
88 if (acpi_table_parse(ACPI_SIG_HPET, nvidia_hpet_check)) {
89 acpi_skip_timer_override = 1;
90 printk(KERN_INFO "Nvidia board "
91 "detected. Ignoring ACPI "
92 "timer override.\n");
93 printk(KERN_INFO "If you got timer trouble "
94 "try acpi_use_timer_override\n");
95 }
96#endif
97#endif
98 /* RED-PEN skip them on mptables too? */
99
100}
101
102#if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC)
103static u32 __init ati_ixp4x0_rev(int num, int slot, int func)
104{
105 u32 d;
106 u8 b;
107
108 b = read_pci_config_byte(num, slot, func, 0xac);
109 b &= ~(1<<5);
110 write_pci_config_byte(num, slot, func, 0xac, b);
111
112 d = read_pci_config(num, slot, func, 0x70);
113 d |= 1<<8;
114 write_pci_config(num, slot, func, 0x70, d);
115
116 d = read_pci_config(num, slot, func, 0x8);
117 d &= 0xff;
118 return d;
119}
120
121static void __init ati_bugs(int num, int slot, int func)
122{
123 u32 d;
124 u8 b;
125
126 if (acpi_use_timer_override)
127 return;
128
129 d = ati_ixp4x0_rev(num, slot, func);
130 if (d < 0x82)
131 acpi_skip_timer_override = 1;
132 else {
133 /* check for IRQ0 interrupt swap */
134 outb(0x72, 0xcd6); b = inb(0xcd7);
135 if (!(b & 0x2))
136 acpi_skip_timer_override = 1;
137 }
138
139 if (acpi_skip_timer_override) {
140 printk(KERN_INFO "SB4X0 revision 0x%x\n", d);
141 printk(KERN_INFO "Ignoring ACPI timer override.\n");
142 printk(KERN_INFO "If you got timer trouble "
143 "try acpi_use_timer_override\n");
144 }
145}
146
147static u32 __init ati_sbx00_rev(int num, int slot, int func)
148{
149 u32 d;
150
151 d = read_pci_config(num, slot, func, 0x8);
152 d &= 0xff;
153
154 return d;
155}
156
157static void __init ati_bugs_contd(int num, int slot, int func)
158{
159 u32 d, rev;
160
161 rev = ati_sbx00_rev(num, slot, func);
162 if (rev >= 0x40)
163 acpi_fix_pin2_polarity = 1;
164
165 /*
166 * SB600: revisions 0x11, 0x12, 0x13, 0x14, ...
167 * SB700: revisions 0x39, 0x3a, ...
168 * SB800: revisions 0x40, 0x41, ...
169 */
170 if (rev >= 0x39)
171 return;
172
173 if (acpi_use_timer_override)
174 return;
175
176 /* check for IRQ0 interrupt swap */
177 d = read_pci_config(num, slot, func, 0x64);
178 if (!(d & (1<<14)))
179 acpi_skip_timer_override = 1;
180
181 if (acpi_skip_timer_override) {
182 printk(KERN_INFO "SB600 revision 0x%x\n", rev);
183 printk(KERN_INFO "Ignoring ACPI timer override.\n");
184 printk(KERN_INFO "If you got timer trouble "
185 "try acpi_use_timer_override\n");
186 }
187}
188#else
189static void __init ati_bugs(int num, int slot, int func)
190{
191}
192
193static void __init ati_bugs_contd(int num, int slot, int func)
194{
195}
196#endif
197
198static void __init intel_remapping_check(int num, int slot, int func)
199{
200 u8 revision;
201 u16 device;
202
203 device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
204 revision = read_pci_config_byte(num, slot, func, PCI_REVISION_ID);
205
206 /*
207 * Revision <= 13 of all triggering devices id in this quirk
208 * have a problem draining interrupts when irq remapping is
209 * enabled, and should be flagged as broken. Additionally
210 * revision 0x22 of device id 0x3405 has this problem.
211 */
212 if (revision <= 0x13)
213 set_irq_remapping_broken();
214 else if (device == 0x3405 && revision == 0x22)
215 set_irq_remapping_broken();
216}
217
218/*
219 * Systems with Intel graphics controllers set aside memory exclusively
220 * for gfx driver use. This memory is not marked in the E820 as reserved
221 * or as RAM, and so is subject to overlap from E820 manipulation later
222 * in the boot process. On some systems, MMIO space is allocated on top,
223 * despite the efforts of the "RAM buffer" approach, which simply rounds
224 * memory boundaries up to 64M to try to catch space that may decode
225 * as RAM and so is not suitable for MMIO.
226 *
227 * And yes, so far on current devices the base addr is always under 4G.
228 */
229static u32 __init intel_stolen_base(int num, int slot, int func, size_t stolen_size)
230{
231 u32 base;
232
233 /*
234 * For the PCI IDs in this quirk, the stolen base is always
235 * in 0x5c, aka the BDSM register (yes that's really what
236 * it's called).
237 */
238 base = read_pci_config(num, slot, func, 0x5c);
239 base &= ~((1<<20) - 1);
240
241 return base;
242}
243
244#define KB(x) ((x) * 1024UL)
245#define MB(x) (KB (KB (x)))
246#define GB(x) (MB (KB (x)))
247
248static size_t __init i830_tseg_size(void)
249{
250 u8 tmp = read_pci_config_byte(0, 0, 0, I830_ESMRAMC);
251
252 if (!(tmp & TSEG_ENABLE))
253 return 0;
254
255 if (tmp & I830_TSEG_SIZE_1M)
256 return MB(1);
257 else
258 return KB(512);
259}
260
261static size_t __init i845_tseg_size(void)
262{
263 u8 tmp = read_pci_config_byte(0, 0, 0, I845_ESMRAMC);
264
265 if (!(tmp & TSEG_ENABLE))
266 return 0;
267
268 switch (tmp & I845_TSEG_SIZE_MASK) {
269 case I845_TSEG_SIZE_512K:
270 return KB(512);
271 case I845_TSEG_SIZE_1M:
272 return MB(1);
273 default:
274 WARN_ON(1);
275 return 0;
276 }
277}
278
279static size_t __init i85x_tseg_size(void)
280{
281 u8 tmp = read_pci_config_byte(0, 0, 0, I85X_ESMRAMC);
282
283 if (!(tmp & TSEG_ENABLE))
284 return 0;
285
286 return MB(1);
287}
288
289static size_t __init i830_mem_size(void)
290{
291 return read_pci_config_byte(0, 0, 0, I830_DRB3) * MB(32);
292}
293
294static size_t __init i85x_mem_size(void)
295{
296 return read_pci_config_byte(0, 0, 1, I85X_DRB3) * MB(32);
297}
298
299/*
300 * On 830/845/85x the stolen memory base isn't available in any
301 * register. We need to calculate it as TOM-TSEG_SIZE-stolen_size.
302 */
303static u32 __init i830_stolen_base(int num, int slot, int func, size_t stolen_size)
304{
305 return i830_mem_size() - i830_tseg_size() - stolen_size;
306}
307
308static u32 __init i845_stolen_base(int num, int slot, int func, size_t stolen_size)
309{
310 return i830_mem_size() - i845_tseg_size() - stolen_size;
311}
312
313static u32 __init i85x_stolen_base(int num, int slot, int func, size_t stolen_size)
314{
315 return i85x_mem_size() - i85x_tseg_size() - stolen_size;
316}
317
318static u32 __init i865_stolen_base(int num, int slot, int func, size_t stolen_size)
319{
320 /*
321 * FIXME is the graphics stolen memory region
322 * always at TOUD? Ie. is it always the last
323 * one to be allocated by the BIOS?
324 */
325 return read_pci_config_16(0, 0, 0, I865_TOUD) << 16;
326}
327
328static size_t __init i830_stolen_size(int num, int slot, int func)
329{
330 size_t stolen_size;
331 u16 gmch_ctrl;
332
333 gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
334
335 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
336 case I830_GMCH_GMS_STOLEN_512:
337 stolen_size = KB(512);
338 break;
339 case I830_GMCH_GMS_STOLEN_1024:
340 stolen_size = MB(1);
341 break;
342 case I830_GMCH_GMS_STOLEN_8192:
343 stolen_size = MB(8);
344 break;
345 case I830_GMCH_GMS_LOCAL:
346 /* local memory isn't part of the normal address space */
347 stolen_size = 0;
348 break;
349 default:
350 return 0;
351 }
352
353 return stolen_size;
354}
355
356static size_t __init gen3_stolen_size(int num, int slot, int func)
357{
358 size_t stolen_size;
359 u16 gmch_ctrl;
360
361 gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
362
363 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
364 case I855_GMCH_GMS_STOLEN_1M:
365 stolen_size = MB(1);
366 break;
367 case I855_GMCH_GMS_STOLEN_4M:
368 stolen_size = MB(4);
369 break;
370 case I855_GMCH_GMS_STOLEN_8M:
371 stolen_size = MB(8);
372 break;
373 case I855_GMCH_GMS_STOLEN_16M:
374 stolen_size = MB(16);
375 break;
376 case I855_GMCH_GMS_STOLEN_32M:
377 stolen_size = MB(32);
378 break;
379 case I915_GMCH_GMS_STOLEN_48M:
380 stolen_size = MB(48);
381 break;
382 case I915_GMCH_GMS_STOLEN_64M:
383 stolen_size = MB(64);
384 break;
385 case G33_GMCH_GMS_STOLEN_128M:
386 stolen_size = MB(128);
387 break;
388 case G33_GMCH_GMS_STOLEN_256M:
389 stolen_size = MB(256);
390 break;
391 case INTEL_GMCH_GMS_STOLEN_96M:
392 stolen_size = MB(96);
393 break;
394 case INTEL_GMCH_GMS_STOLEN_160M:
395 stolen_size = MB(160);
396 break;
397 case INTEL_GMCH_GMS_STOLEN_224M:
398 stolen_size = MB(224);
399 break;
400 case INTEL_GMCH_GMS_STOLEN_352M:
401 stolen_size = MB(352);
402 break;
403 default:
404 stolen_size = 0;
405 break;
406 }
407
408 return stolen_size;
409}
410
411static size_t __init gen6_stolen_size(int num, int slot, int func)
412{
413 u16 gmch_ctrl;
414
415 gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
416 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
417 gmch_ctrl &= SNB_GMCH_GMS_MASK;
418
419 return gmch_ctrl << 25; /* 32 MB units */
420}
421
422static size_t __init gen8_stolen_size(int num, int slot, int func)
423{
424 u16 gmch_ctrl;
425
426 gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
427 gmch_ctrl >>= BDW_GMCH_GMS_SHIFT;
428 gmch_ctrl &= BDW_GMCH_GMS_MASK;
429 return gmch_ctrl << 25; /* 32 MB units */
430}
431
432static size_t __init chv_stolen_size(int num, int slot, int func)
433{
434 u16 gmch_ctrl;
435
436 gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
437 gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
438 gmch_ctrl &= SNB_GMCH_GMS_MASK;
439
440 /*
441 * 0x0 to 0x10: 32MB increments starting at 0MB
442 * 0x11 to 0x16: 4MB increments starting at 8MB
443 * 0x17 to 0x1d: 4MB increments start at 36MB
444 */
445 if (gmch_ctrl < 0x11)
446 return gmch_ctrl << 25;
447 else if (gmch_ctrl < 0x17)
448 return (gmch_ctrl - 0x11 + 2) << 22;
449 else
450 return (gmch_ctrl - 0x17 + 9) << 22;
451}
452
453struct intel_stolen_funcs {
454 size_t (*size)(int num, int slot, int func);
455 u32 (*base)(int num, int slot, int func, size_t size);
456};
457
458static size_t __init gen9_stolen_size(int num, int slot, int func)
459{
460 u16 gmch_ctrl;
461
462 gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
463 gmch_ctrl >>= BDW_GMCH_GMS_SHIFT;
464 gmch_ctrl &= BDW_GMCH_GMS_MASK;
465
466 if (gmch_ctrl < 0xf0)
467 return gmch_ctrl << 25; /* 32 MB units */
468 else
469 /* 4MB increments starting at 0xf0 for 4MB */
470 return (gmch_ctrl - 0xf0 + 1) << 22;
471}
472
473typedef size_t (*stolen_size_fn)(int num, int slot, int func);
474
475static const struct intel_stolen_funcs i830_stolen_funcs __initconst = {
476 .base = i830_stolen_base,
477 .size = i830_stolen_size,
478};
479
480static const struct intel_stolen_funcs i845_stolen_funcs __initconst = {
481 .base = i845_stolen_base,
482 .size = i830_stolen_size,
483};
484
485static const struct intel_stolen_funcs i85x_stolen_funcs __initconst = {
486 .base = i85x_stolen_base,
487 .size = gen3_stolen_size,
488};
489
490static const struct intel_stolen_funcs i865_stolen_funcs __initconst = {
491 .base = i865_stolen_base,
492 .size = gen3_stolen_size,
493};
494
495static const struct intel_stolen_funcs gen3_stolen_funcs __initconst = {
496 .base = intel_stolen_base,
497 .size = gen3_stolen_size,
498};
499
500static const struct intel_stolen_funcs gen6_stolen_funcs __initconst = {
501 .base = intel_stolen_base,
502 .size = gen6_stolen_size,
503};
504
505static const struct intel_stolen_funcs gen8_stolen_funcs __initconst = {
506 .base = intel_stolen_base,
507 .size = gen8_stolen_size,
508};
509
510static const struct intel_stolen_funcs gen9_stolen_funcs __initconst = {
511 .base = intel_stolen_base,
512 .size = gen9_stolen_size,
513};
514
515static const struct intel_stolen_funcs chv_stolen_funcs __initconst = {
516 .base = intel_stolen_base,
517 .size = chv_stolen_size,
518};
519
520static const struct pci_device_id intel_stolen_ids[] __initconst = {
521 INTEL_I830_IDS(&i830_stolen_funcs),
522 INTEL_I845G_IDS(&i845_stolen_funcs),
523 INTEL_I85X_IDS(&i85x_stolen_funcs),
524 INTEL_I865G_IDS(&i865_stolen_funcs),
525 INTEL_I915G_IDS(&gen3_stolen_funcs),
526 INTEL_I915GM_IDS(&gen3_stolen_funcs),
527 INTEL_I945G_IDS(&gen3_stolen_funcs),
528 INTEL_I945GM_IDS(&gen3_stolen_funcs),
529 INTEL_VLV_M_IDS(&gen6_stolen_funcs),
530 INTEL_VLV_D_IDS(&gen6_stolen_funcs),
531 INTEL_PINEVIEW_IDS(&gen3_stolen_funcs),
532 INTEL_I965G_IDS(&gen3_stolen_funcs),
533 INTEL_G33_IDS(&gen3_stolen_funcs),
534 INTEL_I965GM_IDS(&gen3_stolen_funcs),
535 INTEL_GM45_IDS(&gen3_stolen_funcs),
536 INTEL_G45_IDS(&gen3_stolen_funcs),
537 INTEL_IRONLAKE_D_IDS(&gen3_stolen_funcs),
538 INTEL_IRONLAKE_M_IDS(&gen3_stolen_funcs),
539 INTEL_SNB_D_IDS(&gen6_stolen_funcs),
540 INTEL_SNB_M_IDS(&gen6_stolen_funcs),
541 INTEL_IVB_M_IDS(&gen6_stolen_funcs),
542 INTEL_IVB_D_IDS(&gen6_stolen_funcs),
543 INTEL_HSW_D_IDS(&gen6_stolen_funcs),
544 INTEL_HSW_M_IDS(&gen6_stolen_funcs),
545 INTEL_BDW_M_IDS(&gen8_stolen_funcs),
546 INTEL_BDW_D_IDS(&gen8_stolen_funcs),
547 INTEL_CHV_IDS(&chv_stolen_funcs),
548 INTEL_SKL_IDS(&gen9_stolen_funcs),
549 INTEL_BXT_IDS(&gen9_stolen_funcs),
550 INTEL_KBL_IDS(&gen9_stolen_funcs),
551};
552
553static void __init intel_graphics_stolen(int num, int slot, int func)
554{
555 size_t size;
556 int i;
557 u32 start;
558 u16 device, subvendor, subdevice;
559
560 device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
561 subvendor = read_pci_config_16(num, slot, func,
562 PCI_SUBSYSTEM_VENDOR_ID);
563 subdevice = read_pci_config_16(num, slot, func, PCI_SUBSYSTEM_ID);
564
565 for (i = 0; i < ARRAY_SIZE(intel_stolen_ids); i++) {
566 if (intel_stolen_ids[i].device == device) {
567 const struct intel_stolen_funcs *stolen_funcs =
568 (const struct intel_stolen_funcs *)intel_stolen_ids[i].driver_data;
569 size = stolen_funcs->size(num, slot, func);
570 start = stolen_funcs->base(num, slot, func, size);
571 if (size && start) {
572 printk(KERN_INFO "Reserving Intel graphics stolen memory at 0x%x-0x%x\n",
573 start, start + (u32)size - 1);
574 /* Mark this space as reserved */
575 e820_add_region(start, size, E820_RESERVED);
576 sanitize_e820_map(e820.map,
577 ARRAY_SIZE(e820.map),
578 &e820.nr_map);
579 }
580 return;
581 }
582 }
583}
584
585static void __init force_disable_hpet(int num, int slot, int func)
586{
587#ifdef CONFIG_HPET_TIMER
588 boot_hpet_disable = true;
589 pr_info("x86/hpet: Will disable the HPET for this platform because it's not reliable\n");
590#endif
591}
592
593
594#define QFLAG_APPLY_ONCE 0x1
595#define QFLAG_APPLIED 0x2
596#define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
597struct chipset {
598 u32 vendor;
599 u32 device;
600 u32 class;
601 u32 class_mask;
602 u32 flags;
603 void (*f)(int num, int slot, int func);
604};
605
606/*
607 * Only works for devices on the root bus. If you add any devices
608 * not on bus 0 readd another loop level in early_quirks(). But
609 * be careful because at least the Nvidia quirk here relies on
610 * only matching on bus 0.
611 */
612static struct chipset early_qrk[] __initdata = {
613 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
614 PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs },
615 { PCI_VENDOR_ID_VIA, PCI_ANY_ID,
616 PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs },
617 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
618 PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config },
619 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
620 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
621 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
622 PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
623 { PCI_VENDOR_ID_INTEL, 0x3403, PCI_CLASS_BRIDGE_HOST,
624 PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
625 { PCI_VENDOR_ID_INTEL, 0x3405, PCI_CLASS_BRIDGE_HOST,
626 PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
627 { PCI_VENDOR_ID_INTEL, 0x3406, PCI_CLASS_BRIDGE_HOST,
628 PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
629 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, PCI_ANY_ID,
630 QFLAG_APPLY_ONCE, intel_graphics_stolen },
631 /*
632 * HPET on the current version of the Baytrail platform has accuracy
633 * problems: it will halt in deep idle state - so we disable it.
634 *
635 * More details can be found in section 18.10.1.3 of the datasheet:
636 *
637 * http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/atom-z8000-datasheet-vol-1.pdf
638 */
639 { PCI_VENDOR_ID_INTEL, 0x0f00,
640 PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, force_disable_hpet},
641 {}
642};
643
644/**
645 * check_dev_quirk - apply early quirks to a given PCI device
646 * @num: bus number
647 * @slot: slot number
648 * @func: PCI function
649 *
650 * Check the vendor & device ID against the early quirks table.
651 *
652 * If the device is single function, let early_quirks() know so we don't
653 * poke at this device again.
654 */
655static int __init check_dev_quirk(int num, int slot, int func)
656{
657 u16 class;
658 u16 vendor;
659 u16 device;
660 u8 type;
661 int i;
662
663 class = read_pci_config_16(num, slot, func, PCI_CLASS_DEVICE);
664
665 if (class == 0xffff)
666 return -1; /* no class, treat as single function */
667
668 vendor = read_pci_config_16(num, slot, func, PCI_VENDOR_ID);
669
670 device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
671
672 for (i = 0; early_qrk[i].f != NULL; i++) {
673 if (((early_qrk[i].vendor == PCI_ANY_ID) ||
674 (early_qrk[i].vendor == vendor)) &&
675 ((early_qrk[i].device == PCI_ANY_ID) ||
676 (early_qrk[i].device == device)) &&
677 (!((early_qrk[i].class ^ class) &
678 early_qrk[i].class_mask))) {
679 if ((early_qrk[i].flags &
680 QFLAG_DONE) != QFLAG_DONE)
681 early_qrk[i].f(num, slot, func);
682 early_qrk[i].flags |= QFLAG_APPLIED;
683 }
684 }
685
686 type = read_pci_config_byte(num, slot, func,
687 PCI_HEADER_TYPE);
688 if (!(type & 0x80))
689 return -1;
690
691 return 0;
692}
693
694void __init early_quirks(void)
695{
696 int slot, func;
697
698 if (!early_pci_allowed())
699 return;
700
701 /* Poor man's PCI discovery */
702 /* Only scan the root bus */
703 for (slot = 0; slot < 32; slot++)
704 for (func = 0; func < 8; func++) {
705 /* Only probe function 0 on single fn devices */
706 if (check_dev_quirk(0, slot, func))
707 break;
708 }
709}