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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Numascale NumaConnect-Specific APIC Code
7 *
8 * Copyright (C) 2011 Numascale AS. All rights reserved.
9 *
10 * Send feedback to <support@numascale.com>
11 *
12 */
13#include <linux/types.h>
14#include <linux/init.h>
15
16#include <asm/numachip/numachip.h>
17#include <asm/numachip/numachip_csr.h>
18
19#include <asm/pgtable.h>
20
21#include "local.h"
22
23u8 numachip_system __read_mostly;
24static const struct apic apic_numachip1;
25static const struct apic apic_numachip2;
26static void (*numachip_apic_icr_write)(int apicid, unsigned int val) __read_mostly;
27
28static unsigned int numachip1_get_apic_id(unsigned long x)
29{
30 unsigned long value;
31 unsigned int id = (x >> 24) & 0xff;
32
33 if (static_cpu_has(X86_FEATURE_NODEID_MSR)) {
34 rdmsrl(MSR_FAM10H_NODE_ID, value);
35 id |= (value << 2) & 0xff00;
36 }
37
38 return id;
39}
40
41static u32 numachip1_set_apic_id(unsigned int id)
42{
43 return (id & 0xff) << 24;
44}
45
46static unsigned int numachip2_get_apic_id(unsigned long x)
47{
48 u64 mcfg;
49
50 rdmsrl(MSR_FAM10H_MMIO_CONF_BASE, mcfg);
51 return ((mcfg >> (28 - 8)) & 0xfff00) | (x >> 24);
52}
53
54static u32 numachip2_set_apic_id(unsigned int id)
55{
56 return id << 24;
57}
58
59static int numachip_apic_id_valid(u32 apicid)
60{
61 /* Trust what bootloader passes in MADT */
62 return 1;
63}
64
65static int numachip_apic_id_registered(void)
66{
67 return 1;
68}
69
70static int numachip_phys_pkg_id(int initial_apic_id, int index_msb)
71{
72 return initial_apic_id >> index_msb;
73}
74
75static void numachip1_apic_icr_write(int apicid, unsigned int val)
76{
77 write_lcsr(CSR_G3_EXT_IRQ_GEN, (apicid << 16) | val);
78}
79
80static void numachip2_apic_icr_write(int apicid, unsigned int val)
81{
82 numachip2_write32_lcsr(NUMACHIP2_APIC_ICR, (apicid << 12) | val);
83}
84
85static int numachip_wakeup_secondary(int phys_apicid, unsigned long start_rip)
86{
87 numachip_apic_icr_write(phys_apicid, APIC_DM_INIT);
88 numachip_apic_icr_write(phys_apicid, APIC_DM_STARTUP |
89 (start_rip >> 12));
90
91 return 0;
92}
93
94static void numachip_send_IPI_one(int cpu, int vector)
95{
96 int local_apicid, apicid = per_cpu(x86_cpu_to_apicid, cpu);
97 unsigned int dmode;
98
99 preempt_disable();
100 local_apicid = __this_cpu_read(x86_cpu_to_apicid);
101
102 /* Send via local APIC where non-local part matches */
103 if (!((apicid ^ local_apicid) >> NUMACHIP_LAPIC_BITS)) {
104 unsigned long flags;
105
106 local_irq_save(flags);
107 __default_send_IPI_dest_field(apicid, vector,
108 APIC_DEST_PHYSICAL);
109 local_irq_restore(flags);
110 preempt_enable();
111 return;
112 }
113 preempt_enable();
114
115 dmode = (vector == NMI_VECTOR) ? APIC_DM_NMI : APIC_DM_FIXED;
116 numachip_apic_icr_write(apicid, dmode | vector);
117}
118
119static void numachip_send_IPI_mask(const struct cpumask *mask, int vector)
120{
121 unsigned int cpu;
122
123 for_each_cpu(cpu, mask)
124 numachip_send_IPI_one(cpu, vector);
125}
126
127static void numachip_send_IPI_mask_allbutself(const struct cpumask *mask,
128 int vector)
129{
130 unsigned int this_cpu = smp_processor_id();
131 unsigned int cpu;
132
133 for_each_cpu(cpu, mask) {
134 if (cpu != this_cpu)
135 numachip_send_IPI_one(cpu, vector);
136 }
137}
138
139static void numachip_send_IPI_allbutself(int vector)
140{
141 unsigned int this_cpu = smp_processor_id();
142 unsigned int cpu;
143
144 for_each_online_cpu(cpu) {
145 if (cpu != this_cpu)
146 numachip_send_IPI_one(cpu, vector);
147 }
148}
149
150static void numachip_send_IPI_all(int vector)
151{
152 numachip_send_IPI_mask(cpu_online_mask, vector);
153}
154
155static void numachip_send_IPI_self(int vector)
156{
157 apic_write(APIC_SELF_IPI, vector);
158}
159
160static int __init numachip1_probe(void)
161{
162 return apic == &apic_numachip1;
163}
164
165static int __init numachip2_probe(void)
166{
167 return apic == &apic_numachip2;
168}
169
170static void fixup_cpu_id(struct cpuinfo_x86 *c, int node)
171{
172 u64 val;
173 u32 nodes = 1;
174
175 this_cpu_write(cpu_llc_id, node);
176
177 /* Account for nodes per socket in multi-core-module processors */
178 if (boot_cpu_has(X86_FEATURE_NODEID_MSR)) {
179 rdmsrl(MSR_FAM10H_NODE_ID, val);
180 nodes = ((val >> 3) & 7) + 1;
181 }
182
183 c->phys_proc_id = node / nodes;
184}
185
186static int __init numachip_system_init(void)
187{
188 /* Map the LCSR area and set up the apic_icr_write function */
189 switch (numachip_system) {
190 case 1:
191 init_extra_mapping_uc(NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_SIZE);
192 numachip_apic_icr_write = numachip1_apic_icr_write;
193 break;
194 case 2:
195 init_extra_mapping_uc(NUMACHIP2_LCSR_BASE, NUMACHIP2_LCSR_SIZE);
196 numachip_apic_icr_write = numachip2_apic_icr_write;
197 break;
198 default:
199 return 0;
200 }
201
202 x86_cpuinit.fixup_cpu_id = fixup_cpu_id;
203 x86_init.pci.arch_init = pci_numachip_init;
204
205 return 0;
206}
207early_initcall(numachip_system_init);
208
209static int numachip1_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
210{
211 if ((strncmp(oem_id, "NUMASC", 6) != 0) ||
212 (strncmp(oem_table_id, "NCONNECT", 8) != 0))
213 return 0;
214
215 numachip_system = 1;
216
217 return 1;
218}
219
220static int numachip2_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
221{
222 if ((strncmp(oem_id, "NUMASC", 6) != 0) ||
223 (strncmp(oem_table_id, "NCONECT2", 8) != 0))
224 return 0;
225
226 numachip_system = 2;
227
228 return 1;
229}
230
231/* APIC IPIs are queued */
232static void numachip_apic_wait_icr_idle(void)
233{
234}
235
236/* APIC NMI IPIs are queued */
237static u32 numachip_safe_apic_wait_icr_idle(void)
238{
239 return 0;
240}
241
242static const struct apic apic_numachip1 __refconst = {
243 .name = "NumaConnect system",
244 .probe = numachip1_probe,
245 .acpi_madt_oem_check = numachip1_acpi_madt_oem_check,
246 .apic_id_valid = numachip_apic_id_valid,
247 .apic_id_registered = numachip_apic_id_registered,
248
249 .irq_delivery_mode = dest_Fixed,
250 .irq_dest_mode = 0, /* physical */
251
252 .disable_esr = 0,
253 .dest_logical = 0,
254 .check_apicid_used = NULL,
255
256 .init_apic_ldr = flat_init_apic_ldr,
257
258 .ioapic_phys_id_map = NULL,
259 .setup_apic_routing = NULL,
260 .cpu_present_to_apicid = default_cpu_present_to_apicid,
261 .apicid_to_cpu_present = NULL,
262 .check_phys_apicid_present = default_check_phys_apicid_present,
263 .phys_pkg_id = numachip_phys_pkg_id,
264
265 .get_apic_id = numachip1_get_apic_id,
266 .set_apic_id = numachip1_set_apic_id,
267
268 .calc_dest_apicid = apic_default_calc_apicid,
269
270 .send_IPI = numachip_send_IPI_one,
271 .send_IPI_mask = numachip_send_IPI_mask,
272 .send_IPI_mask_allbutself = numachip_send_IPI_mask_allbutself,
273 .send_IPI_allbutself = numachip_send_IPI_allbutself,
274 .send_IPI_all = numachip_send_IPI_all,
275 .send_IPI_self = numachip_send_IPI_self,
276
277 .wakeup_secondary_cpu = numachip_wakeup_secondary,
278 .inquire_remote_apic = NULL, /* REMRD not supported */
279
280 .read = native_apic_mem_read,
281 .write = native_apic_mem_write,
282 .eoi_write = native_apic_mem_write,
283 .icr_read = native_apic_icr_read,
284 .icr_write = native_apic_icr_write,
285 .wait_icr_idle = numachip_apic_wait_icr_idle,
286 .safe_wait_icr_idle = numachip_safe_apic_wait_icr_idle,
287};
288
289apic_driver(apic_numachip1);
290
291static const struct apic apic_numachip2 __refconst = {
292 .name = "NumaConnect2 system",
293 .probe = numachip2_probe,
294 .acpi_madt_oem_check = numachip2_acpi_madt_oem_check,
295 .apic_id_valid = numachip_apic_id_valid,
296 .apic_id_registered = numachip_apic_id_registered,
297
298 .irq_delivery_mode = dest_Fixed,
299 .irq_dest_mode = 0, /* physical */
300
301 .disable_esr = 0,
302 .dest_logical = 0,
303 .check_apicid_used = NULL,
304
305 .init_apic_ldr = flat_init_apic_ldr,
306
307 .ioapic_phys_id_map = NULL,
308 .setup_apic_routing = NULL,
309 .cpu_present_to_apicid = default_cpu_present_to_apicid,
310 .apicid_to_cpu_present = NULL,
311 .check_phys_apicid_present = default_check_phys_apicid_present,
312 .phys_pkg_id = numachip_phys_pkg_id,
313
314 .get_apic_id = numachip2_get_apic_id,
315 .set_apic_id = numachip2_set_apic_id,
316
317 .calc_dest_apicid = apic_default_calc_apicid,
318
319 .send_IPI = numachip_send_IPI_one,
320 .send_IPI_mask = numachip_send_IPI_mask,
321 .send_IPI_mask_allbutself = numachip_send_IPI_mask_allbutself,
322 .send_IPI_allbutself = numachip_send_IPI_allbutself,
323 .send_IPI_all = numachip_send_IPI_all,
324 .send_IPI_self = numachip_send_IPI_self,
325
326 .wakeup_secondary_cpu = numachip_wakeup_secondary,
327 .inquire_remote_apic = NULL, /* REMRD not supported */
328
329 .read = native_apic_mem_read,
330 .write = native_apic_mem_write,
331 .eoi_write = native_apic_mem_write,
332 .icr_read = native_apic_icr_read,
333 .icr_write = native_apic_icr_write,
334 .wait_icr_idle = numachip_apic_wait_icr_idle,
335 .safe_wait_icr_idle = numachip_safe_apic_wait_icr_idle,
336};
337
338apic_driver(apic_numachip2);
1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Numascale NumaConnect-Specific APIC Code
7 *
8 * Copyright (C) 2011 Numascale AS. All rights reserved.
9 *
10 * Send feedback to <support@numascale.com>
11 *
12 */
13
14#include <linux/init.h>
15
16#include <asm/numachip/numachip.h>
17#include <asm/numachip/numachip_csr.h>
18#include <asm/ipi.h>
19#include <asm/apic_flat_64.h>
20#include <asm/pgtable.h>
21#include <asm/pci_x86.h>
22
23u8 numachip_system __read_mostly;
24static const struct apic apic_numachip1;
25static const struct apic apic_numachip2;
26static void (*numachip_apic_icr_write)(int apicid, unsigned int val) __read_mostly;
27
28static unsigned int numachip1_get_apic_id(unsigned long x)
29{
30 unsigned long value;
31 unsigned int id = (x >> 24) & 0xff;
32
33 if (static_cpu_has(X86_FEATURE_NODEID_MSR)) {
34 rdmsrl(MSR_FAM10H_NODE_ID, value);
35 id |= (value << 2) & 0xff00;
36 }
37
38 return id;
39}
40
41static unsigned long numachip1_set_apic_id(unsigned int id)
42{
43 unsigned long x;
44
45 x = ((id & 0xffU) << 24);
46 return x;
47}
48
49static unsigned int numachip2_get_apic_id(unsigned long x)
50{
51 u64 mcfg;
52
53 rdmsrl(MSR_FAM10H_MMIO_CONF_BASE, mcfg);
54 return ((mcfg >> (28 - 8)) & 0xfff00) | (x >> 24);
55}
56
57static unsigned long numachip2_set_apic_id(unsigned int id)
58{
59 return id << 24;
60}
61
62static int numachip_apic_id_valid(int apicid)
63{
64 /* Trust what bootloader passes in MADT */
65 return 1;
66}
67
68static int numachip_apic_id_registered(void)
69{
70 return 1;
71}
72
73static int numachip_phys_pkg_id(int initial_apic_id, int index_msb)
74{
75 return initial_apic_id >> index_msb;
76}
77
78static void numachip1_apic_icr_write(int apicid, unsigned int val)
79{
80 write_lcsr(CSR_G3_EXT_IRQ_GEN, (apicid << 16) | val);
81}
82
83static void numachip2_apic_icr_write(int apicid, unsigned int val)
84{
85 numachip2_write32_lcsr(NUMACHIP2_APIC_ICR, (apicid << 12) | val);
86}
87
88static int numachip_wakeup_secondary(int phys_apicid, unsigned long start_rip)
89{
90 numachip_apic_icr_write(phys_apicid, APIC_DM_INIT);
91 numachip_apic_icr_write(phys_apicid, APIC_DM_STARTUP |
92 (start_rip >> 12));
93
94 return 0;
95}
96
97static void numachip_send_IPI_one(int cpu, int vector)
98{
99 int local_apicid, apicid = per_cpu(x86_cpu_to_apicid, cpu);
100 unsigned int dmode;
101
102 preempt_disable();
103 local_apicid = __this_cpu_read(x86_cpu_to_apicid);
104
105 /* Send via local APIC where non-local part matches */
106 if (!((apicid ^ local_apicid) >> NUMACHIP_LAPIC_BITS)) {
107 unsigned long flags;
108
109 local_irq_save(flags);
110 __default_send_IPI_dest_field(apicid, vector,
111 APIC_DEST_PHYSICAL);
112 local_irq_restore(flags);
113 preempt_enable();
114 return;
115 }
116 preempt_enable();
117
118 dmode = (vector == NMI_VECTOR) ? APIC_DM_NMI : APIC_DM_FIXED;
119 numachip_apic_icr_write(apicid, dmode | vector);
120}
121
122static void numachip_send_IPI_mask(const struct cpumask *mask, int vector)
123{
124 unsigned int cpu;
125
126 for_each_cpu(cpu, mask)
127 numachip_send_IPI_one(cpu, vector);
128}
129
130static void numachip_send_IPI_mask_allbutself(const struct cpumask *mask,
131 int vector)
132{
133 unsigned int this_cpu = smp_processor_id();
134 unsigned int cpu;
135
136 for_each_cpu(cpu, mask) {
137 if (cpu != this_cpu)
138 numachip_send_IPI_one(cpu, vector);
139 }
140}
141
142static void numachip_send_IPI_allbutself(int vector)
143{
144 unsigned int this_cpu = smp_processor_id();
145 unsigned int cpu;
146
147 for_each_online_cpu(cpu) {
148 if (cpu != this_cpu)
149 numachip_send_IPI_one(cpu, vector);
150 }
151}
152
153static void numachip_send_IPI_all(int vector)
154{
155 numachip_send_IPI_mask(cpu_online_mask, vector);
156}
157
158static void numachip_send_IPI_self(int vector)
159{
160 apic_write(APIC_SELF_IPI, vector);
161}
162
163static int __init numachip1_probe(void)
164{
165 return apic == &apic_numachip1;
166}
167
168static int __init numachip2_probe(void)
169{
170 return apic == &apic_numachip2;
171}
172
173static void fixup_cpu_id(struct cpuinfo_x86 *c, int node)
174{
175 u64 val;
176 u32 nodes = 1;
177
178 this_cpu_write(cpu_llc_id, node);
179
180 /* Account for nodes per socket in multi-core-module processors */
181 if (static_cpu_has(X86_FEATURE_NODEID_MSR)) {
182 rdmsrl(MSR_FAM10H_NODE_ID, val);
183 nodes = ((val >> 3) & 7) + 1;
184 }
185
186 c->phys_proc_id = node / nodes;
187}
188
189static int __init numachip_system_init(void)
190{
191 /* Map the LCSR area and set up the apic_icr_write function */
192 switch (numachip_system) {
193 case 1:
194 init_extra_mapping_uc(NUMACHIP_LCSR_BASE, NUMACHIP_LCSR_SIZE);
195 numachip_apic_icr_write = numachip1_apic_icr_write;
196 break;
197 case 2:
198 init_extra_mapping_uc(NUMACHIP2_LCSR_BASE, NUMACHIP2_LCSR_SIZE);
199 numachip_apic_icr_write = numachip2_apic_icr_write;
200 break;
201 default:
202 return 0;
203 }
204
205 x86_cpuinit.fixup_cpu_id = fixup_cpu_id;
206 x86_init.pci.arch_init = pci_numachip_init;
207
208 return 0;
209}
210early_initcall(numachip_system_init);
211
212static int numachip1_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
213{
214 if ((strncmp(oem_id, "NUMASC", 6) != 0) ||
215 (strncmp(oem_table_id, "NCONNECT", 8) != 0))
216 return 0;
217
218 numachip_system = 1;
219
220 return 1;
221}
222
223static int numachip2_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
224{
225 if ((strncmp(oem_id, "NUMASC", 6) != 0) ||
226 (strncmp(oem_table_id, "NCONECT2", 8) != 0))
227 return 0;
228
229 numachip_system = 2;
230
231 return 1;
232}
233
234/* APIC IPIs are queued */
235static void numachip_apic_wait_icr_idle(void)
236{
237}
238
239/* APIC NMI IPIs are queued */
240static u32 numachip_safe_apic_wait_icr_idle(void)
241{
242 return 0;
243}
244
245static const struct apic apic_numachip1 __refconst = {
246 .name = "NumaConnect system",
247 .probe = numachip1_probe,
248 .acpi_madt_oem_check = numachip1_acpi_madt_oem_check,
249 .apic_id_valid = numachip_apic_id_valid,
250 .apic_id_registered = numachip_apic_id_registered,
251
252 .irq_delivery_mode = dest_Fixed,
253 .irq_dest_mode = 0, /* physical */
254
255 .target_cpus = online_target_cpus,
256 .disable_esr = 0,
257 .dest_logical = 0,
258 .check_apicid_used = NULL,
259
260 .vector_allocation_domain = default_vector_allocation_domain,
261 .init_apic_ldr = flat_init_apic_ldr,
262
263 .ioapic_phys_id_map = NULL,
264 .setup_apic_routing = NULL,
265 .cpu_present_to_apicid = default_cpu_present_to_apicid,
266 .apicid_to_cpu_present = NULL,
267 .check_phys_apicid_present = default_check_phys_apicid_present,
268 .phys_pkg_id = numachip_phys_pkg_id,
269
270 .get_apic_id = numachip1_get_apic_id,
271 .set_apic_id = numachip1_set_apic_id,
272 .apic_id_mask = 0xffU << 24,
273
274 .cpu_mask_to_apicid_and = default_cpu_mask_to_apicid_and,
275
276 .send_IPI = numachip_send_IPI_one,
277 .send_IPI_mask = numachip_send_IPI_mask,
278 .send_IPI_mask_allbutself = numachip_send_IPI_mask_allbutself,
279 .send_IPI_allbutself = numachip_send_IPI_allbutself,
280 .send_IPI_all = numachip_send_IPI_all,
281 .send_IPI_self = numachip_send_IPI_self,
282
283 .wakeup_secondary_cpu = numachip_wakeup_secondary,
284 .inquire_remote_apic = NULL, /* REMRD not supported */
285
286 .read = native_apic_mem_read,
287 .write = native_apic_mem_write,
288 .eoi_write = native_apic_mem_write,
289 .icr_read = native_apic_icr_read,
290 .icr_write = native_apic_icr_write,
291 .wait_icr_idle = numachip_apic_wait_icr_idle,
292 .safe_wait_icr_idle = numachip_safe_apic_wait_icr_idle,
293};
294
295apic_driver(apic_numachip1);
296
297static const struct apic apic_numachip2 __refconst = {
298 .name = "NumaConnect2 system",
299 .probe = numachip2_probe,
300 .acpi_madt_oem_check = numachip2_acpi_madt_oem_check,
301 .apic_id_valid = numachip_apic_id_valid,
302 .apic_id_registered = numachip_apic_id_registered,
303
304 .irq_delivery_mode = dest_Fixed,
305 .irq_dest_mode = 0, /* physical */
306
307 .target_cpus = online_target_cpus,
308 .disable_esr = 0,
309 .dest_logical = 0,
310 .check_apicid_used = NULL,
311
312 .vector_allocation_domain = default_vector_allocation_domain,
313 .init_apic_ldr = flat_init_apic_ldr,
314
315 .ioapic_phys_id_map = NULL,
316 .setup_apic_routing = NULL,
317 .cpu_present_to_apicid = default_cpu_present_to_apicid,
318 .apicid_to_cpu_present = NULL,
319 .check_phys_apicid_present = default_check_phys_apicid_present,
320 .phys_pkg_id = numachip_phys_pkg_id,
321
322 .get_apic_id = numachip2_get_apic_id,
323 .set_apic_id = numachip2_set_apic_id,
324 .apic_id_mask = 0xffU << 24,
325
326 .cpu_mask_to_apicid_and = default_cpu_mask_to_apicid_and,
327
328 .send_IPI = numachip_send_IPI_one,
329 .send_IPI_mask = numachip_send_IPI_mask,
330 .send_IPI_mask_allbutself = numachip_send_IPI_mask_allbutself,
331 .send_IPI_allbutself = numachip_send_IPI_allbutself,
332 .send_IPI_all = numachip_send_IPI_all,
333 .send_IPI_self = numachip_send_IPI_self,
334
335 .wakeup_secondary_cpu = numachip_wakeup_secondary,
336 .inquire_remote_apic = NULL, /* REMRD not supported */
337
338 .read = native_apic_mem_read,
339 .write = native_apic_mem_write,
340 .eoi_write = native_apic_mem_write,
341 .icr_read = native_apic_icr_read,
342 .icr_write = native_apic_icr_write,
343 .wait_icr_idle = numachip_apic_wait_icr_idle,
344 .safe_wait_icr_idle = numachip_safe_apic_wait_icr_idle,
345};
346
347apic_driver(apic_numachip2);