Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * arch/sh/mm/cache.c
4 *
5 * Copyright (C) 1999, 2000, 2002 Niibe Yutaka
6 * Copyright (C) 2002 - 2010 Paul Mundt
7 */
8#include <linux/mm.h>
9#include <linux/init.h>
10#include <linux/mutex.h>
11#include <linux/fs.h>
12#include <linux/smp.h>
13#include <linux/highmem.h>
14#include <linux/module.h>
15#include <asm/mmu_context.h>
16#include <asm/cacheflush.h>
17
18void (*local_flush_cache_all)(void *args) = cache_noop;
19void (*local_flush_cache_mm)(void *args) = cache_noop;
20void (*local_flush_cache_dup_mm)(void *args) = cache_noop;
21void (*local_flush_cache_page)(void *args) = cache_noop;
22void (*local_flush_cache_range)(void *args) = cache_noop;
23void (*local_flush_dcache_page)(void *args) = cache_noop;
24void (*local_flush_icache_range)(void *args) = cache_noop;
25void (*local_flush_icache_page)(void *args) = cache_noop;
26void (*local_flush_cache_sigtramp)(void *args) = cache_noop;
27
28void (*__flush_wback_region)(void *start, int size);
29EXPORT_SYMBOL(__flush_wback_region);
30void (*__flush_purge_region)(void *start, int size);
31EXPORT_SYMBOL(__flush_purge_region);
32void (*__flush_invalidate_region)(void *start, int size);
33EXPORT_SYMBOL(__flush_invalidate_region);
34
35static inline void noop__flush_region(void *start, int size)
36{
37}
38
39static inline void cacheop_on_each_cpu(void (*func) (void *info), void *info,
40 int wait)
41{
42 preempt_disable();
43
44 /* Needing IPI for cross-core flush is SHX3-specific. */
45#ifdef CONFIG_CPU_SHX3
46 /*
47 * It's possible that this gets called early on when IRQs are
48 * still disabled due to ioremapping by the boot CPU, so don't
49 * even attempt IPIs unless there are other CPUs online.
50 */
51 if (num_online_cpus() > 1)
52 smp_call_function(func, info, wait);
53#endif
54
55 func(info);
56
57 preempt_enable();
58}
59
60void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
61 unsigned long vaddr, void *dst, const void *src,
62 unsigned long len)
63{
64 if (boot_cpu_data.dcache.n_aliases && page_mapcount(page) &&
65 test_bit(PG_dcache_clean, &page->flags)) {
66 void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
67 memcpy(vto, src, len);
68 kunmap_coherent(vto);
69 } else {
70 memcpy(dst, src, len);
71 if (boot_cpu_data.dcache.n_aliases)
72 clear_bit(PG_dcache_clean, &page->flags);
73 }
74
75 if (vma->vm_flags & VM_EXEC)
76 flush_cache_page(vma, vaddr, page_to_pfn(page));
77}
78
79void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
80 unsigned long vaddr, void *dst, const void *src,
81 unsigned long len)
82{
83 if (boot_cpu_data.dcache.n_aliases && page_mapcount(page) &&
84 test_bit(PG_dcache_clean, &page->flags)) {
85 void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
86 memcpy(dst, vfrom, len);
87 kunmap_coherent(vfrom);
88 } else {
89 memcpy(dst, src, len);
90 if (boot_cpu_data.dcache.n_aliases)
91 clear_bit(PG_dcache_clean, &page->flags);
92 }
93}
94
95void copy_user_highpage(struct page *to, struct page *from,
96 unsigned long vaddr, struct vm_area_struct *vma)
97{
98 void *vfrom, *vto;
99
100 vto = kmap_atomic(to);
101
102 if (boot_cpu_data.dcache.n_aliases && page_mapcount(from) &&
103 test_bit(PG_dcache_clean, &from->flags)) {
104 vfrom = kmap_coherent(from, vaddr);
105 copy_page(vto, vfrom);
106 kunmap_coherent(vfrom);
107 } else {
108 vfrom = kmap_atomic(from);
109 copy_page(vto, vfrom);
110 kunmap_atomic(vfrom);
111 }
112
113 if (pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK) ||
114 (vma->vm_flags & VM_EXEC))
115 __flush_purge_region(vto, PAGE_SIZE);
116
117 kunmap_atomic(vto);
118 /* Make sure this page is cleared on other CPU's too before using it */
119 smp_wmb();
120}
121EXPORT_SYMBOL(copy_user_highpage);
122
123void clear_user_highpage(struct page *page, unsigned long vaddr)
124{
125 void *kaddr = kmap_atomic(page);
126
127 clear_page(kaddr);
128
129 if (pages_do_alias((unsigned long)kaddr, vaddr & PAGE_MASK))
130 __flush_purge_region(kaddr, PAGE_SIZE);
131
132 kunmap_atomic(kaddr);
133}
134EXPORT_SYMBOL(clear_user_highpage);
135
136void __update_cache(struct vm_area_struct *vma,
137 unsigned long address, pte_t pte)
138{
139 struct page *page;
140 unsigned long pfn = pte_pfn(pte);
141
142 if (!boot_cpu_data.dcache.n_aliases)
143 return;
144
145 page = pfn_to_page(pfn);
146 if (pfn_valid(pfn)) {
147 int dirty = !test_and_set_bit(PG_dcache_clean, &page->flags);
148 if (dirty)
149 __flush_purge_region(page_address(page), PAGE_SIZE);
150 }
151}
152
153void __flush_anon_page(struct page *page, unsigned long vmaddr)
154{
155 unsigned long addr = (unsigned long) page_address(page);
156
157 if (pages_do_alias(addr, vmaddr)) {
158 if (boot_cpu_data.dcache.n_aliases && page_mapcount(page) &&
159 test_bit(PG_dcache_clean, &page->flags)) {
160 void *kaddr;
161
162 kaddr = kmap_coherent(page, vmaddr);
163 /* XXX.. For now kunmap_coherent() does a purge */
164 /* __flush_purge_region((void *)kaddr, PAGE_SIZE); */
165 kunmap_coherent(kaddr);
166 } else
167 __flush_purge_region((void *)addr, PAGE_SIZE);
168 }
169}
170
171void flush_cache_all(void)
172{
173 cacheop_on_each_cpu(local_flush_cache_all, NULL, 1);
174}
175EXPORT_SYMBOL(flush_cache_all);
176
177void flush_cache_mm(struct mm_struct *mm)
178{
179 if (boot_cpu_data.dcache.n_aliases == 0)
180 return;
181
182 cacheop_on_each_cpu(local_flush_cache_mm, mm, 1);
183}
184
185void flush_cache_dup_mm(struct mm_struct *mm)
186{
187 if (boot_cpu_data.dcache.n_aliases == 0)
188 return;
189
190 cacheop_on_each_cpu(local_flush_cache_dup_mm, mm, 1);
191}
192
193void flush_cache_page(struct vm_area_struct *vma, unsigned long addr,
194 unsigned long pfn)
195{
196 struct flusher_data data;
197
198 data.vma = vma;
199 data.addr1 = addr;
200 data.addr2 = pfn;
201
202 cacheop_on_each_cpu(local_flush_cache_page, (void *)&data, 1);
203}
204
205void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
206 unsigned long end)
207{
208 struct flusher_data data;
209
210 data.vma = vma;
211 data.addr1 = start;
212 data.addr2 = end;
213
214 cacheop_on_each_cpu(local_flush_cache_range, (void *)&data, 1);
215}
216EXPORT_SYMBOL(flush_cache_range);
217
218void flush_dcache_page(struct page *page)
219{
220 cacheop_on_each_cpu(local_flush_dcache_page, page, 1);
221}
222EXPORT_SYMBOL(flush_dcache_page);
223
224void flush_icache_range(unsigned long start, unsigned long end)
225{
226 struct flusher_data data;
227
228 data.vma = NULL;
229 data.addr1 = start;
230 data.addr2 = end;
231
232 cacheop_on_each_cpu(local_flush_icache_range, (void *)&data, 1);
233}
234EXPORT_SYMBOL(flush_icache_range);
235
236void flush_icache_page(struct vm_area_struct *vma, struct page *page)
237{
238 /* Nothing uses the VMA, so just pass the struct page along */
239 cacheop_on_each_cpu(local_flush_icache_page, page, 1);
240}
241
242void flush_cache_sigtramp(unsigned long address)
243{
244 cacheop_on_each_cpu(local_flush_cache_sigtramp, (void *)address, 1);
245}
246
247static void compute_alias(struct cache_info *c)
248{
249#ifdef CONFIG_MMU
250 c->alias_mask = ((c->sets - 1) << c->entry_shift) & ~(PAGE_SIZE - 1);
251#else
252 c->alias_mask = 0;
253#endif
254 c->n_aliases = c->alias_mask ? (c->alias_mask >> PAGE_SHIFT) + 1 : 0;
255}
256
257static void __init emit_cache_params(void)
258{
259 printk(KERN_NOTICE "I-cache : n_ways=%d n_sets=%d way_incr=%d\n",
260 boot_cpu_data.icache.ways,
261 boot_cpu_data.icache.sets,
262 boot_cpu_data.icache.way_incr);
263 printk(KERN_NOTICE "I-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
264 boot_cpu_data.icache.entry_mask,
265 boot_cpu_data.icache.alias_mask,
266 boot_cpu_data.icache.n_aliases);
267 printk(KERN_NOTICE "D-cache : n_ways=%d n_sets=%d way_incr=%d\n",
268 boot_cpu_data.dcache.ways,
269 boot_cpu_data.dcache.sets,
270 boot_cpu_data.dcache.way_incr);
271 printk(KERN_NOTICE "D-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
272 boot_cpu_data.dcache.entry_mask,
273 boot_cpu_data.dcache.alias_mask,
274 boot_cpu_data.dcache.n_aliases);
275
276 /*
277 * Emit Secondary Cache parameters if the CPU has a probed L2.
278 */
279 if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
280 printk(KERN_NOTICE "S-cache : n_ways=%d n_sets=%d way_incr=%d\n",
281 boot_cpu_data.scache.ways,
282 boot_cpu_data.scache.sets,
283 boot_cpu_data.scache.way_incr);
284 printk(KERN_NOTICE "S-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
285 boot_cpu_data.scache.entry_mask,
286 boot_cpu_data.scache.alias_mask,
287 boot_cpu_data.scache.n_aliases);
288 }
289}
290
291void __init cpu_cache_init(void)
292{
293 unsigned int cache_disabled = 0;
294
295#ifdef SH_CCR
296 cache_disabled = !(__raw_readl(SH_CCR) & CCR_CACHE_ENABLE);
297#endif
298
299 compute_alias(&boot_cpu_data.icache);
300 compute_alias(&boot_cpu_data.dcache);
301 compute_alias(&boot_cpu_data.scache);
302
303 __flush_wback_region = noop__flush_region;
304 __flush_purge_region = noop__flush_region;
305 __flush_invalidate_region = noop__flush_region;
306
307 /*
308 * No flushing is necessary in the disabled cache case so we can
309 * just keep the noop functions in local_flush_..() and __flush_..()
310 */
311 if (unlikely(cache_disabled))
312 goto skip;
313
314 if (boot_cpu_data.type == CPU_J2) {
315 extern void __weak j2_cache_init(void);
316
317 j2_cache_init();
318 } else if (boot_cpu_data.family == CPU_FAMILY_SH2) {
319 extern void __weak sh2_cache_init(void);
320
321 sh2_cache_init();
322 }
323
324 if (boot_cpu_data.family == CPU_FAMILY_SH2A) {
325 extern void __weak sh2a_cache_init(void);
326
327 sh2a_cache_init();
328 }
329
330 if (boot_cpu_data.family == CPU_FAMILY_SH3) {
331 extern void __weak sh3_cache_init(void);
332
333 sh3_cache_init();
334
335 if ((boot_cpu_data.type == CPU_SH7705) &&
336 (boot_cpu_data.dcache.sets == 512)) {
337 extern void __weak sh7705_cache_init(void);
338
339 sh7705_cache_init();
340 }
341 }
342
343 if ((boot_cpu_data.family == CPU_FAMILY_SH4) ||
344 (boot_cpu_data.family == CPU_FAMILY_SH4A) ||
345 (boot_cpu_data.family == CPU_FAMILY_SH4AL_DSP)) {
346 extern void __weak sh4_cache_init(void);
347
348 sh4_cache_init();
349
350 if ((boot_cpu_data.type == CPU_SH7786) ||
351 (boot_cpu_data.type == CPU_SHX3)) {
352 extern void __weak shx3_cache_init(void);
353
354 shx3_cache_init();
355 }
356 }
357
358 if (boot_cpu_data.family == CPU_FAMILY_SH5) {
359 extern void __weak sh5_cache_init(void);
360
361 sh5_cache_init();
362 }
363
364skip:
365 emit_cache_params();
366}
1/*
2 * arch/sh/mm/cache.c
3 *
4 * Copyright (C) 1999, 2000, 2002 Niibe Yutaka
5 * Copyright (C) 2002 - 2010 Paul Mundt
6 *
7 * Released under the terms of the GNU GPL v2.0.
8 */
9#include <linux/mm.h>
10#include <linux/init.h>
11#include <linux/mutex.h>
12#include <linux/fs.h>
13#include <linux/smp.h>
14#include <linux/highmem.h>
15#include <linux/module.h>
16#include <asm/mmu_context.h>
17#include <asm/cacheflush.h>
18
19void (*local_flush_cache_all)(void *args) = cache_noop;
20void (*local_flush_cache_mm)(void *args) = cache_noop;
21void (*local_flush_cache_dup_mm)(void *args) = cache_noop;
22void (*local_flush_cache_page)(void *args) = cache_noop;
23void (*local_flush_cache_range)(void *args) = cache_noop;
24void (*local_flush_dcache_page)(void *args) = cache_noop;
25void (*local_flush_icache_range)(void *args) = cache_noop;
26void (*local_flush_icache_page)(void *args) = cache_noop;
27void (*local_flush_cache_sigtramp)(void *args) = cache_noop;
28
29void (*__flush_wback_region)(void *start, int size);
30EXPORT_SYMBOL(__flush_wback_region);
31void (*__flush_purge_region)(void *start, int size);
32EXPORT_SYMBOL(__flush_purge_region);
33void (*__flush_invalidate_region)(void *start, int size);
34EXPORT_SYMBOL(__flush_invalidate_region);
35
36static inline void noop__flush_region(void *start, int size)
37{
38}
39
40static inline void cacheop_on_each_cpu(void (*func) (void *info), void *info,
41 int wait)
42{
43 preempt_disable();
44
45 /*
46 * It's possible that this gets called early on when IRQs are
47 * still disabled due to ioremapping by the boot CPU, so don't
48 * even attempt IPIs unless there are other CPUs online.
49 */
50 if (num_online_cpus() > 1)
51 smp_call_function(func, info, wait);
52
53 func(info);
54
55 preempt_enable();
56}
57
58void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
59 unsigned long vaddr, void *dst, const void *src,
60 unsigned long len)
61{
62 if (boot_cpu_data.dcache.n_aliases && page_mapcount(page) &&
63 test_bit(PG_dcache_clean, &page->flags)) {
64 void *vto = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
65 memcpy(vto, src, len);
66 kunmap_coherent(vto);
67 } else {
68 memcpy(dst, src, len);
69 if (boot_cpu_data.dcache.n_aliases)
70 clear_bit(PG_dcache_clean, &page->flags);
71 }
72
73 if (vma->vm_flags & VM_EXEC)
74 flush_cache_page(vma, vaddr, page_to_pfn(page));
75}
76
77void copy_from_user_page(struct vm_area_struct *vma, struct page *page,
78 unsigned long vaddr, void *dst, const void *src,
79 unsigned long len)
80{
81 if (boot_cpu_data.dcache.n_aliases && page_mapcount(page) &&
82 test_bit(PG_dcache_clean, &page->flags)) {
83 void *vfrom = kmap_coherent(page, vaddr) + (vaddr & ~PAGE_MASK);
84 memcpy(dst, vfrom, len);
85 kunmap_coherent(vfrom);
86 } else {
87 memcpy(dst, src, len);
88 if (boot_cpu_data.dcache.n_aliases)
89 clear_bit(PG_dcache_clean, &page->flags);
90 }
91}
92
93void copy_user_highpage(struct page *to, struct page *from,
94 unsigned long vaddr, struct vm_area_struct *vma)
95{
96 void *vfrom, *vto;
97
98 vto = kmap_atomic(to);
99
100 if (boot_cpu_data.dcache.n_aliases && page_mapcount(from) &&
101 test_bit(PG_dcache_clean, &from->flags)) {
102 vfrom = kmap_coherent(from, vaddr);
103 copy_page(vto, vfrom);
104 kunmap_coherent(vfrom);
105 } else {
106 vfrom = kmap_atomic(from);
107 copy_page(vto, vfrom);
108 kunmap_atomic(vfrom);
109 }
110
111 if (pages_do_alias((unsigned long)vto, vaddr & PAGE_MASK) ||
112 (vma->vm_flags & VM_EXEC))
113 __flush_purge_region(vto, PAGE_SIZE);
114
115 kunmap_atomic(vto);
116 /* Make sure this page is cleared on other CPU's too before using it */
117 smp_wmb();
118}
119EXPORT_SYMBOL(copy_user_highpage);
120
121void clear_user_highpage(struct page *page, unsigned long vaddr)
122{
123 void *kaddr = kmap_atomic(page);
124
125 clear_page(kaddr);
126
127 if (pages_do_alias((unsigned long)kaddr, vaddr & PAGE_MASK))
128 __flush_purge_region(kaddr, PAGE_SIZE);
129
130 kunmap_atomic(kaddr);
131}
132EXPORT_SYMBOL(clear_user_highpage);
133
134void __update_cache(struct vm_area_struct *vma,
135 unsigned long address, pte_t pte)
136{
137 struct page *page;
138 unsigned long pfn = pte_pfn(pte);
139
140 if (!boot_cpu_data.dcache.n_aliases)
141 return;
142
143 page = pfn_to_page(pfn);
144 if (pfn_valid(pfn)) {
145 int dirty = !test_and_set_bit(PG_dcache_clean, &page->flags);
146 if (dirty)
147 __flush_purge_region(page_address(page), PAGE_SIZE);
148 }
149}
150
151void __flush_anon_page(struct page *page, unsigned long vmaddr)
152{
153 unsigned long addr = (unsigned long) page_address(page);
154
155 if (pages_do_alias(addr, vmaddr)) {
156 if (boot_cpu_data.dcache.n_aliases && page_mapcount(page) &&
157 test_bit(PG_dcache_clean, &page->flags)) {
158 void *kaddr;
159
160 kaddr = kmap_coherent(page, vmaddr);
161 /* XXX.. For now kunmap_coherent() does a purge */
162 /* __flush_purge_region((void *)kaddr, PAGE_SIZE); */
163 kunmap_coherent(kaddr);
164 } else
165 __flush_purge_region((void *)addr, PAGE_SIZE);
166 }
167}
168
169void flush_cache_all(void)
170{
171 cacheop_on_each_cpu(local_flush_cache_all, NULL, 1);
172}
173EXPORT_SYMBOL(flush_cache_all);
174
175void flush_cache_mm(struct mm_struct *mm)
176{
177 if (boot_cpu_data.dcache.n_aliases == 0)
178 return;
179
180 cacheop_on_each_cpu(local_flush_cache_mm, mm, 1);
181}
182
183void flush_cache_dup_mm(struct mm_struct *mm)
184{
185 if (boot_cpu_data.dcache.n_aliases == 0)
186 return;
187
188 cacheop_on_each_cpu(local_flush_cache_dup_mm, mm, 1);
189}
190
191void flush_cache_page(struct vm_area_struct *vma, unsigned long addr,
192 unsigned long pfn)
193{
194 struct flusher_data data;
195
196 data.vma = vma;
197 data.addr1 = addr;
198 data.addr2 = pfn;
199
200 cacheop_on_each_cpu(local_flush_cache_page, (void *)&data, 1);
201}
202
203void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
204 unsigned long end)
205{
206 struct flusher_data data;
207
208 data.vma = vma;
209 data.addr1 = start;
210 data.addr2 = end;
211
212 cacheop_on_each_cpu(local_flush_cache_range, (void *)&data, 1);
213}
214EXPORT_SYMBOL(flush_cache_range);
215
216void flush_dcache_page(struct page *page)
217{
218 cacheop_on_each_cpu(local_flush_dcache_page, page, 1);
219}
220EXPORT_SYMBOL(flush_dcache_page);
221
222void flush_icache_range(unsigned long start, unsigned long end)
223{
224 struct flusher_data data;
225
226 data.vma = NULL;
227 data.addr1 = start;
228 data.addr2 = end;
229
230 cacheop_on_each_cpu(local_flush_icache_range, (void *)&data, 1);
231}
232EXPORT_SYMBOL(flush_icache_range);
233
234void flush_icache_page(struct vm_area_struct *vma, struct page *page)
235{
236 /* Nothing uses the VMA, so just pass the struct page along */
237 cacheop_on_each_cpu(local_flush_icache_page, page, 1);
238}
239
240void flush_cache_sigtramp(unsigned long address)
241{
242 cacheop_on_each_cpu(local_flush_cache_sigtramp, (void *)address, 1);
243}
244
245static void compute_alias(struct cache_info *c)
246{
247 c->alias_mask = ((c->sets - 1) << c->entry_shift) & ~(PAGE_SIZE - 1);
248 c->n_aliases = c->alias_mask ? (c->alias_mask >> PAGE_SHIFT) + 1 : 0;
249}
250
251static void __init emit_cache_params(void)
252{
253 printk(KERN_NOTICE "I-cache : n_ways=%d n_sets=%d way_incr=%d\n",
254 boot_cpu_data.icache.ways,
255 boot_cpu_data.icache.sets,
256 boot_cpu_data.icache.way_incr);
257 printk(KERN_NOTICE "I-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
258 boot_cpu_data.icache.entry_mask,
259 boot_cpu_data.icache.alias_mask,
260 boot_cpu_data.icache.n_aliases);
261 printk(KERN_NOTICE "D-cache : n_ways=%d n_sets=%d way_incr=%d\n",
262 boot_cpu_data.dcache.ways,
263 boot_cpu_data.dcache.sets,
264 boot_cpu_data.dcache.way_incr);
265 printk(KERN_NOTICE "D-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
266 boot_cpu_data.dcache.entry_mask,
267 boot_cpu_data.dcache.alias_mask,
268 boot_cpu_data.dcache.n_aliases);
269
270 /*
271 * Emit Secondary Cache parameters if the CPU has a probed L2.
272 */
273 if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
274 printk(KERN_NOTICE "S-cache : n_ways=%d n_sets=%d way_incr=%d\n",
275 boot_cpu_data.scache.ways,
276 boot_cpu_data.scache.sets,
277 boot_cpu_data.scache.way_incr);
278 printk(KERN_NOTICE "S-cache : entry_mask=0x%08x alias_mask=0x%08x n_aliases=%d\n",
279 boot_cpu_data.scache.entry_mask,
280 boot_cpu_data.scache.alias_mask,
281 boot_cpu_data.scache.n_aliases);
282 }
283}
284
285void __init cpu_cache_init(void)
286{
287 unsigned int cache_disabled = 0;
288
289#ifdef SH_CCR
290 cache_disabled = !(__raw_readl(SH_CCR) & CCR_CACHE_ENABLE);
291#endif
292
293 compute_alias(&boot_cpu_data.icache);
294 compute_alias(&boot_cpu_data.dcache);
295 compute_alias(&boot_cpu_data.scache);
296
297 __flush_wback_region = noop__flush_region;
298 __flush_purge_region = noop__flush_region;
299 __flush_invalidate_region = noop__flush_region;
300
301 /*
302 * No flushing is necessary in the disabled cache case so we can
303 * just keep the noop functions in local_flush_..() and __flush_..()
304 */
305 if (unlikely(cache_disabled))
306 goto skip;
307
308 if (boot_cpu_data.family == CPU_FAMILY_SH2) {
309 extern void __weak sh2_cache_init(void);
310
311 sh2_cache_init();
312 }
313
314 if (boot_cpu_data.family == CPU_FAMILY_SH2A) {
315 extern void __weak sh2a_cache_init(void);
316
317 sh2a_cache_init();
318 }
319
320 if (boot_cpu_data.family == CPU_FAMILY_SH3) {
321 extern void __weak sh3_cache_init(void);
322
323 sh3_cache_init();
324
325 if ((boot_cpu_data.type == CPU_SH7705) &&
326 (boot_cpu_data.dcache.sets == 512)) {
327 extern void __weak sh7705_cache_init(void);
328
329 sh7705_cache_init();
330 }
331 }
332
333 if ((boot_cpu_data.family == CPU_FAMILY_SH4) ||
334 (boot_cpu_data.family == CPU_FAMILY_SH4A) ||
335 (boot_cpu_data.family == CPU_FAMILY_SH4AL_DSP)) {
336 extern void __weak sh4_cache_init(void);
337
338 sh4_cache_init();
339
340 if ((boot_cpu_data.type == CPU_SH7786) ||
341 (boot_cpu_data.type == CPU_SHX3)) {
342 extern void __weak shx3_cache_init(void);
343
344 shx3_cache_init();
345 }
346 }
347
348 if (boot_cpu_data.family == CPU_FAMILY_SH5) {
349 extern void __weak sh5_cache_init(void);
350
351 sh5_cache_init();
352 }
353
354skip:
355 emit_cache_params();
356}