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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Out of line spinlock code.
4 *
5 * Copyright IBM Corp. 2004, 2006
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
7 */
8
9#include <linux/types.h>
10#include <linux/export.h>
11#include <linux/spinlock.h>
12#include <linux/jiffies.h>
13#include <linux/init.h>
14#include <linux/smp.h>
15#include <linux/percpu.h>
16#include <asm/alternative.h>
17#include <asm/io.h>
18
19int spin_retry = -1;
20
21static int __init spin_retry_init(void)
22{
23 if (spin_retry < 0)
24 spin_retry = 1000;
25 return 0;
26}
27early_initcall(spin_retry_init);
28
29/**
30 * spin_retry= parameter
31 */
32static int __init spin_retry_setup(char *str)
33{
34 spin_retry = simple_strtoul(str, &str, 0);
35 return 1;
36}
37__setup("spin_retry=", spin_retry_setup);
38
39struct spin_wait {
40 struct spin_wait *next, *prev;
41 int node_id;
42} __aligned(32);
43
44static DEFINE_PER_CPU_ALIGNED(struct spin_wait, spin_wait[4]);
45
46#define _Q_LOCK_CPU_OFFSET 0
47#define _Q_LOCK_STEAL_OFFSET 16
48#define _Q_TAIL_IDX_OFFSET 18
49#define _Q_TAIL_CPU_OFFSET 20
50
51#define _Q_LOCK_CPU_MASK 0x0000ffff
52#define _Q_LOCK_STEAL_ADD 0x00010000
53#define _Q_LOCK_STEAL_MASK 0x00030000
54#define _Q_TAIL_IDX_MASK 0x000c0000
55#define _Q_TAIL_CPU_MASK 0xfff00000
56
57#define _Q_LOCK_MASK (_Q_LOCK_CPU_MASK | _Q_LOCK_STEAL_MASK)
58#define _Q_TAIL_MASK (_Q_TAIL_IDX_MASK | _Q_TAIL_CPU_MASK)
59
60void arch_spin_lock_setup(int cpu)
61{
62 struct spin_wait *node;
63 int ix;
64
65 node = per_cpu_ptr(&spin_wait[0], cpu);
66 for (ix = 0; ix < 4; ix++, node++) {
67 memset(node, 0, sizeof(*node));
68 node->node_id = ((cpu + 1) << _Q_TAIL_CPU_OFFSET) +
69 (ix << _Q_TAIL_IDX_OFFSET);
70 }
71}
72
73static inline int arch_load_niai4(int *lock)
74{
75 int owner;
76
77 asm volatile(
78 ALTERNATIVE("", ".long 0xb2fa0040", 49) /* NIAI 4 */
79 " l %0,%1\n"
80 : "=d" (owner) : "Q" (*lock) : "memory");
81 return owner;
82}
83
84static inline int arch_cmpxchg_niai8(int *lock, int old, int new)
85{
86 int expected = old;
87
88 asm volatile(
89 ALTERNATIVE("", ".long 0xb2fa0080", 49) /* NIAI 8 */
90 " cs %0,%3,%1\n"
91 : "=d" (old), "=Q" (*lock)
92 : "0" (old), "d" (new), "Q" (*lock)
93 : "cc", "memory");
94 return expected == old;
95}
96
97static inline struct spin_wait *arch_spin_decode_tail(int lock)
98{
99 int ix, cpu;
100
101 ix = (lock & _Q_TAIL_IDX_MASK) >> _Q_TAIL_IDX_OFFSET;
102 cpu = (lock & _Q_TAIL_CPU_MASK) >> _Q_TAIL_CPU_OFFSET;
103 return per_cpu_ptr(&spin_wait[ix], cpu - 1);
104}
105
106static inline int arch_spin_yield_target(int lock, struct spin_wait *node)
107{
108 if (lock & _Q_LOCK_CPU_MASK)
109 return lock & _Q_LOCK_CPU_MASK;
110 if (node == NULL || node->prev == NULL)
111 return 0; /* 0 -> no target cpu */
112 while (node->prev)
113 node = node->prev;
114 return node->node_id >> _Q_TAIL_CPU_OFFSET;
115}
116
117static inline void arch_spin_lock_queued(arch_spinlock_t *lp)
118{
119 struct spin_wait *node, *next;
120 int lockval, ix, node_id, tail_id, old, new, owner, count;
121
122 ix = S390_lowcore.spinlock_index++;
123 barrier();
124 lockval = SPINLOCK_LOCKVAL; /* cpu + 1 */
125 node = this_cpu_ptr(&spin_wait[ix]);
126 node->prev = node->next = NULL;
127 node_id = node->node_id;
128
129 /* Enqueue the node for this CPU in the spinlock wait queue */
130 while (1) {
131 old = READ_ONCE(lp->lock);
132 if ((old & _Q_LOCK_CPU_MASK) == 0 &&
133 (old & _Q_LOCK_STEAL_MASK) != _Q_LOCK_STEAL_MASK) {
134 /*
135 * The lock is free but there may be waiters.
136 * With no waiters simply take the lock, if there
137 * are waiters try to steal the lock. The lock may
138 * be stolen three times before the next queued
139 * waiter will get the lock.
140 */
141 new = (old ? (old + _Q_LOCK_STEAL_ADD) : 0) | lockval;
142 if (__atomic_cmpxchg_bool(&lp->lock, old, new))
143 /* Got the lock */
144 goto out;
145 /* lock passing in progress */
146 continue;
147 }
148 /* Make the node of this CPU the new tail. */
149 new = node_id | (old & _Q_LOCK_MASK);
150 if (__atomic_cmpxchg_bool(&lp->lock, old, new))
151 break;
152 }
153 /* Set the 'next' pointer of the tail node in the queue */
154 tail_id = old & _Q_TAIL_MASK;
155 if (tail_id != 0) {
156 node->prev = arch_spin_decode_tail(tail_id);
157 WRITE_ONCE(node->prev->next, node);
158 }
159
160 /* Pass the virtual CPU to the lock holder if it is not running */
161 owner = arch_spin_yield_target(old, node);
162 if (owner && arch_vcpu_is_preempted(owner - 1))
163 smp_yield_cpu(owner - 1);
164
165 /* Spin on the CPU local node->prev pointer */
166 if (tail_id != 0) {
167 count = spin_retry;
168 while (READ_ONCE(node->prev) != NULL) {
169 if (count-- >= 0)
170 continue;
171 count = spin_retry;
172 /* Query running state of lock holder again. */
173 owner = arch_spin_yield_target(old, node);
174 if (owner && arch_vcpu_is_preempted(owner - 1))
175 smp_yield_cpu(owner - 1);
176 }
177 }
178
179 /* Spin on the lock value in the spinlock_t */
180 count = spin_retry;
181 while (1) {
182 old = READ_ONCE(lp->lock);
183 owner = old & _Q_LOCK_CPU_MASK;
184 if (!owner) {
185 tail_id = old & _Q_TAIL_MASK;
186 new = ((tail_id != node_id) ? tail_id : 0) | lockval;
187 if (__atomic_cmpxchg_bool(&lp->lock, old, new))
188 /* Got the lock */
189 break;
190 continue;
191 }
192 if (count-- >= 0)
193 continue;
194 count = spin_retry;
195 if (!MACHINE_IS_LPAR || arch_vcpu_is_preempted(owner - 1))
196 smp_yield_cpu(owner - 1);
197 }
198
199 /* Pass lock_spin job to next CPU in the queue */
200 if (node_id && tail_id != node_id) {
201 /* Wait until the next CPU has set up the 'next' pointer */
202 while ((next = READ_ONCE(node->next)) == NULL)
203 ;
204 next->prev = NULL;
205 }
206
207 out:
208 S390_lowcore.spinlock_index--;
209}
210
211static inline void arch_spin_lock_classic(arch_spinlock_t *lp)
212{
213 int lockval, old, new, owner, count;
214
215 lockval = SPINLOCK_LOCKVAL; /* cpu + 1 */
216
217 /* Pass the virtual CPU to the lock holder if it is not running */
218 owner = arch_spin_yield_target(READ_ONCE(lp->lock), NULL);
219 if (owner && arch_vcpu_is_preempted(owner - 1))
220 smp_yield_cpu(owner - 1);
221
222 count = spin_retry;
223 while (1) {
224 old = arch_load_niai4(&lp->lock);
225 owner = old & _Q_LOCK_CPU_MASK;
226 /* Try to get the lock if it is free. */
227 if (!owner) {
228 new = (old & _Q_TAIL_MASK) | lockval;
229 if (arch_cmpxchg_niai8(&lp->lock, old, new)) {
230 /* Got the lock */
231 return;
232 }
233 continue;
234 }
235 if (count-- >= 0)
236 continue;
237 count = spin_retry;
238 if (!MACHINE_IS_LPAR || arch_vcpu_is_preempted(owner - 1))
239 smp_yield_cpu(owner - 1);
240 }
241}
242
243void arch_spin_lock_wait(arch_spinlock_t *lp)
244{
245 /* Use classic spinlocks + niai if the steal time is >= 10% */
246 if (test_cpu_flag(CIF_DEDICATED_CPU))
247 arch_spin_lock_queued(lp);
248 else
249 arch_spin_lock_classic(lp);
250}
251EXPORT_SYMBOL(arch_spin_lock_wait);
252
253int arch_spin_trylock_retry(arch_spinlock_t *lp)
254{
255 int cpu = SPINLOCK_LOCKVAL;
256 int owner, count;
257
258 for (count = spin_retry; count > 0; count--) {
259 owner = READ_ONCE(lp->lock);
260 /* Try to get the lock if it is free. */
261 if (!owner) {
262 if (__atomic_cmpxchg_bool(&lp->lock, 0, cpu))
263 return 1;
264 }
265 }
266 return 0;
267}
268EXPORT_SYMBOL(arch_spin_trylock_retry);
269
270void arch_read_lock_wait(arch_rwlock_t *rw)
271{
272 if (unlikely(in_interrupt())) {
273 while (READ_ONCE(rw->cnts) & 0x10000)
274 barrier();
275 return;
276 }
277
278 /* Remove this reader again to allow recursive read locking */
279 __atomic_add_const(-1, &rw->cnts);
280 /* Put the reader into the wait queue */
281 arch_spin_lock(&rw->wait);
282 /* Now add this reader to the count value again */
283 __atomic_add_const(1, &rw->cnts);
284 /* Loop until the writer is done */
285 while (READ_ONCE(rw->cnts) & 0x10000)
286 barrier();
287 arch_spin_unlock(&rw->wait);
288}
289EXPORT_SYMBOL(arch_read_lock_wait);
290
291void arch_write_lock_wait(arch_rwlock_t *rw)
292{
293 int old;
294
295 /* Add this CPU to the write waiters */
296 __atomic_add(0x20000, &rw->cnts);
297
298 /* Put the writer into the wait queue */
299 arch_spin_lock(&rw->wait);
300
301 while (1) {
302 old = READ_ONCE(rw->cnts);
303 if ((old & 0x1ffff) == 0 &&
304 __atomic_cmpxchg_bool(&rw->cnts, old, old | 0x10000))
305 /* Got the lock */
306 break;
307 barrier();
308 }
309
310 arch_spin_unlock(&rw->wait);
311}
312EXPORT_SYMBOL(arch_write_lock_wait);
313
314void arch_spin_relax(arch_spinlock_t *lp)
315{
316 int cpu;
317
318 cpu = READ_ONCE(lp->lock) & _Q_LOCK_CPU_MASK;
319 if (!cpu)
320 return;
321 if (MACHINE_IS_LPAR && !arch_vcpu_is_preempted(cpu - 1))
322 return;
323 smp_yield_cpu(cpu - 1);
324}
325EXPORT_SYMBOL(arch_spin_relax);
1/*
2 * Out of line spinlock code.
3 *
4 * Copyright IBM Corp. 2004, 2006
5 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
6 */
7
8#include <linux/types.h>
9#include <linux/module.h>
10#include <linux/spinlock.h>
11#include <linux/init.h>
12#include <linux/smp.h>
13#include <asm/io.h>
14
15int spin_retry = -1;
16
17static int __init spin_retry_init(void)
18{
19 if (spin_retry < 0)
20 spin_retry = MACHINE_HAS_CAD ? 10 : 1000;
21 return 0;
22}
23early_initcall(spin_retry_init);
24
25/**
26 * spin_retry= parameter
27 */
28static int __init spin_retry_setup(char *str)
29{
30 spin_retry = simple_strtoul(str, &str, 0);
31 return 1;
32}
33__setup("spin_retry=", spin_retry_setup);
34
35static inline void _raw_compare_and_delay(unsigned int *lock, unsigned int old)
36{
37 asm(".insn rsy,0xeb0000000022,%0,0,%1" : : "d" (old), "Q" (*lock));
38}
39
40static inline int cpu_is_preempted(int cpu)
41{
42 if (test_cpu_flag_of(CIF_ENABLED_WAIT, cpu))
43 return 0;
44 if (smp_vcpu_scheduled(cpu))
45 return 0;
46 return 1;
47}
48
49void arch_spin_lock_wait(arch_spinlock_t *lp)
50{
51 unsigned int cpu = SPINLOCK_LOCKVAL;
52 unsigned int owner;
53 int count, first_diag;
54
55 first_diag = 1;
56 while (1) {
57 owner = ACCESS_ONCE(lp->lock);
58 /* Try to get the lock if it is free. */
59 if (!owner) {
60 if (_raw_compare_and_swap(&lp->lock, 0, cpu))
61 return;
62 continue;
63 }
64 /* First iteration: check if the lock owner is running. */
65 if (first_diag && cpu_is_preempted(~owner)) {
66 smp_yield_cpu(~owner);
67 first_diag = 0;
68 continue;
69 }
70 /* Loop for a while on the lock value. */
71 count = spin_retry;
72 do {
73 if (MACHINE_HAS_CAD)
74 _raw_compare_and_delay(&lp->lock, owner);
75 owner = ACCESS_ONCE(lp->lock);
76 } while (owner && count-- > 0);
77 if (!owner)
78 continue;
79 /*
80 * For multiple layers of hypervisors, e.g. z/VM + LPAR
81 * yield the CPU unconditionally. For LPAR rely on the
82 * sense running status.
83 */
84 if (!MACHINE_IS_LPAR || cpu_is_preempted(~owner)) {
85 smp_yield_cpu(~owner);
86 first_diag = 0;
87 }
88 }
89}
90EXPORT_SYMBOL(arch_spin_lock_wait);
91
92void arch_spin_lock_wait_flags(arch_spinlock_t *lp, unsigned long flags)
93{
94 unsigned int cpu = SPINLOCK_LOCKVAL;
95 unsigned int owner;
96 int count, first_diag;
97
98 local_irq_restore(flags);
99 first_diag = 1;
100 while (1) {
101 owner = ACCESS_ONCE(lp->lock);
102 /* Try to get the lock if it is free. */
103 if (!owner) {
104 local_irq_disable();
105 if (_raw_compare_and_swap(&lp->lock, 0, cpu))
106 return;
107 local_irq_restore(flags);
108 continue;
109 }
110 /* Check if the lock owner is running. */
111 if (first_diag && cpu_is_preempted(~owner)) {
112 smp_yield_cpu(~owner);
113 first_diag = 0;
114 continue;
115 }
116 /* Loop for a while on the lock value. */
117 count = spin_retry;
118 do {
119 if (MACHINE_HAS_CAD)
120 _raw_compare_and_delay(&lp->lock, owner);
121 owner = ACCESS_ONCE(lp->lock);
122 } while (owner && count-- > 0);
123 if (!owner)
124 continue;
125 /*
126 * For multiple layers of hypervisors, e.g. z/VM + LPAR
127 * yield the CPU unconditionally. For LPAR rely on the
128 * sense running status.
129 */
130 if (!MACHINE_IS_LPAR || cpu_is_preempted(~owner)) {
131 smp_yield_cpu(~owner);
132 first_diag = 0;
133 }
134 }
135}
136EXPORT_SYMBOL(arch_spin_lock_wait_flags);
137
138int arch_spin_trylock_retry(arch_spinlock_t *lp)
139{
140 unsigned int cpu = SPINLOCK_LOCKVAL;
141 unsigned int owner;
142 int count;
143
144 for (count = spin_retry; count > 0; count--) {
145 owner = ACCESS_ONCE(lp->lock);
146 /* Try to get the lock if it is free. */
147 if (!owner) {
148 if (_raw_compare_and_swap(&lp->lock, 0, cpu))
149 return 1;
150 } else if (MACHINE_HAS_CAD)
151 _raw_compare_and_delay(&lp->lock, owner);
152 }
153 return 0;
154}
155EXPORT_SYMBOL(arch_spin_trylock_retry);
156
157void _raw_read_lock_wait(arch_rwlock_t *rw)
158{
159 unsigned int owner, old;
160 int count = spin_retry;
161
162#ifdef CONFIG_HAVE_MARCH_Z196_FEATURES
163 __RAW_LOCK(&rw->lock, -1, __RAW_OP_ADD);
164#endif
165 owner = 0;
166 while (1) {
167 if (count-- <= 0) {
168 if (owner && cpu_is_preempted(~owner))
169 smp_yield_cpu(~owner);
170 count = spin_retry;
171 }
172 old = ACCESS_ONCE(rw->lock);
173 owner = ACCESS_ONCE(rw->owner);
174 if ((int) old < 0) {
175 if (MACHINE_HAS_CAD)
176 _raw_compare_and_delay(&rw->lock, old);
177 continue;
178 }
179 if (_raw_compare_and_swap(&rw->lock, old, old + 1))
180 return;
181 }
182}
183EXPORT_SYMBOL(_raw_read_lock_wait);
184
185int _raw_read_trylock_retry(arch_rwlock_t *rw)
186{
187 unsigned int old;
188 int count = spin_retry;
189
190 while (count-- > 0) {
191 old = ACCESS_ONCE(rw->lock);
192 if ((int) old < 0) {
193 if (MACHINE_HAS_CAD)
194 _raw_compare_and_delay(&rw->lock, old);
195 continue;
196 }
197 if (_raw_compare_and_swap(&rw->lock, old, old + 1))
198 return 1;
199 }
200 return 0;
201}
202EXPORT_SYMBOL(_raw_read_trylock_retry);
203
204#ifdef CONFIG_HAVE_MARCH_Z196_FEATURES
205
206void _raw_write_lock_wait(arch_rwlock_t *rw, unsigned int prev)
207{
208 unsigned int owner, old;
209 int count = spin_retry;
210
211 owner = 0;
212 while (1) {
213 if (count-- <= 0) {
214 if (owner && cpu_is_preempted(~owner))
215 smp_yield_cpu(~owner);
216 count = spin_retry;
217 }
218 old = ACCESS_ONCE(rw->lock);
219 owner = ACCESS_ONCE(rw->owner);
220 smp_mb();
221 if ((int) old >= 0) {
222 prev = __RAW_LOCK(&rw->lock, 0x80000000, __RAW_OP_OR);
223 old = prev;
224 }
225 if ((old & 0x7fffffff) == 0 && (int) prev >= 0)
226 break;
227 if (MACHINE_HAS_CAD)
228 _raw_compare_and_delay(&rw->lock, old);
229 }
230}
231EXPORT_SYMBOL(_raw_write_lock_wait);
232
233#else /* CONFIG_HAVE_MARCH_Z196_FEATURES */
234
235void _raw_write_lock_wait(arch_rwlock_t *rw)
236{
237 unsigned int owner, old, prev;
238 int count = spin_retry;
239
240 prev = 0x80000000;
241 owner = 0;
242 while (1) {
243 if (count-- <= 0) {
244 if (owner && cpu_is_preempted(~owner))
245 smp_yield_cpu(~owner);
246 count = spin_retry;
247 }
248 old = ACCESS_ONCE(rw->lock);
249 owner = ACCESS_ONCE(rw->owner);
250 if ((int) old >= 0 &&
251 _raw_compare_and_swap(&rw->lock, old, old | 0x80000000))
252 prev = old;
253 else
254 smp_mb();
255 if ((old & 0x7fffffff) == 0 && (int) prev >= 0)
256 break;
257 if (MACHINE_HAS_CAD)
258 _raw_compare_and_delay(&rw->lock, old);
259 }
260}
261EXPORT_SYMBOL(_raw_write_lock_wait);
262
263#endif /* CONFIG_HAVE_MARCH_Z196_FEATURES */
264
265int _raw_write_trylock_retry(arch_rwlock_t *rw)
266{
267 unsigned int old;
268 int count = spin_retry;
269
270 while (count-- > 0) {
271 old = ACCESS_ONCE(rw->lock);
272 if (old) {
273 if (MACHINE_HAS_CAD)
274 _raw_compare_and_delay(&rw->lock, old);
275 continue;
276 }
277 if (_raw_compare_and_swap(&rw->lock, 0, 0x80000000))
278 return 1;
279 }
280 return 0;
281}
282EXPORT_SYMBOL(_raw_write_trylock_retry);
283
284void arch_lock_relax(unsigned int cpu)
285{
286 if (!cpu)
287 return;
288 if (MACHINE_IS_LPAR && !cpu_is_preempted(~cpu))
289 return;
290 smp_yield_cpu(~cpu);
291}
292EXPORT_SYMBOL(arch_lock_relax);