1/* SPDX-License-Identifier: GPL-2.0 */
 2/*
 3 * arch/arm/include/asm/vfpmacros.h
 4 *
 5 * Assembler-only file containing VFP macros and register definitions.
 6 */
 7#include <asm/hwcap.h>
 8
 9#include <asm/vfp.h>
10
11@ Macros to allow building with old toolkits (with no VFP support)
12	.macro	VFPFMRX, rd, sysreg, cond
13	MRC\cond	p10, 7, \rd, \sysreg, cr0, 0	@ FMRX	\rd, \sysreg
14	.endm
15
16	.macro	VFPFMXR, sysreg, rd, cond
17	MCR\cond	p10, 7, \rd, \sysreg, cr0, 0	@ FMXR	\sysreg, \rd
18	.endm
19
20	@ read all the working registers back into the VFP
21	.macro	VFPFLDMIA, base, tmp
22#if __LINUX_ARM_ARCH__ < 6
23	LDC	p11, cr0, [\base],#33*4		    @ FLDMIAX \base!, {d0-d15}
24#else
25	LDC	p11, cr0, [\base],#32*4		    @ FLDMIAD \base!, {d0-d15}
26#endif
27#ifdef CONFIG_VFPv3
28#if __LINUX_ARM_ARCH__ <= 6
29	ldr	\tmp, =elf_hwcap		    @ may not have MVFR regs
30	ldr	\tmp, [\tmp, #0]
31	tst	\tmp, #HWCAP_VFPD32
32	ldclne	p11, cr0, [\base],#32*4		    @ FLDMIAD \base!, {d16-d31}
33	addeq	\base, \base, #32*4		    @ step over unused register space
34#else
35	VFPFMRX	\tmp, MVFR0			    @ Media and VFP Feature Register 0
36	and	\tmp, \tmp, #MVFR0_A_SIMD_MASK	    @ A_SIMD field
37	cmp	\tmp, #2			    @ 32 x 64bit registers?
38	ldcleq	p11, cr0, [\base],#32*4		    @ FLDMIAD \base!, {d16-d31}
39	addne	\base, \base, #32*4		    @ step over unused register space
40#endif
41#endif
42	.endm
43
44	@ write all the working registers out of the VFP
45	.macro	VFPFSTMIA, base, tmp
46#if __LINUX_ARM_ARCH__ < 6
47	STC	p11, cr0, [\base],#33*4		    @ FSTMIAX \base!, {d0-d15}
48#else
49	STC	p11, cr0, [\base],#32*4		    @ FSTMIAD \base!, {d0-d15}
50#endif
51#ifdef CONFIG_VFPv3
52#if __LINUX_ARM_ARCH__ <= 6
53	ldr	\tmp, =elf_hwcap		    @ may not have MVFR regs
54	ldr	\tmp, [\tmp, #0]
55	tst	\tmp, #HWCAP_VFPD32
56	stclne	p11, cr0, [\base],#32*4		    @ FSTMIAD \base!, {d16-d31}
57	addeq	\base, \base, #32*4		    @ step over unused register space
58#else
59	VFPFMRX	\tmp, MVFR0			    @ Media and VFP Feature Register 0
60	and	\tmp, \tmp, #MVFR0_A_SIMD_MASK	    @ A_SIMD field
61	cmp	\tmp, #2			    @ 32 x 64bit registers?
62	stcleq	p11, cr0, [\base],#32*4		    @ FSTMIAD \base!, {d16-d31}
63	addne	\base, \base, #32*4		    @ step over unused register space
64#endif
65#endif
66	.endm

 
 1/*
 2 * arch/arm/include/asm/vfpmacros.h
 3 *
 4 * Assembler-only file containing VFP macros and register definitions.
 5 */
 6#include <asm/hwcap.h>
 7
 8#include <asm/vfp.h>
 9
10@ Macros to allow building with old toolkits (with no VFP support)
11	.macro	VFPFMRX, rd, sysreg, cond
12	MRC\cond	p10, 7, \rd, \sysreg, cr0, 0	@ FMRX	\rd, \sysreg
13	.endm
14
15	.macro	VFPFMXR, sysreg, rd, cond
16	MCR\cond	p10, 7, \rd, \sysreg, cr0, 0	@ FMXR	\sysreg, \rd
17	.endm
18
19	@ read all the working registers back into the VFP
20	.macro	VFPFLDMIA, base, tmp
21#if __LINUX_ARM_ARCH__ < 6
22	LDC	p11, cr0, [\base],#33*4		    @ FLDMIAX \base!, {d0-d15}
23#else
24	LDC	p11, cr0, [\base],#32*4		    @ FLDMIAD \base!, {d0-d15}
25#endif
26#ifdef CONFIG_VFPv3
27#if __LINUX_ARM_ARCH__ <= 6
28	ldr	\tmp, =elf_hwcap		    @ may not have MVFR regs
29	ldr	\tmp, [\tmp, #0]
30	tst	\tmp, #HWCAP_VFPD32
31	ldcnel	p11, cr0, [\base],#32*4		    @ FLDMIAD \base!, {d16-d31}
32	addeq	\base, \base, #32*4		    @ step over unused register space
33#else
34	VFPFMRX	\tmp, MVFR0			    @ Media and VFP Feature Register 0
35	and	\tmp, \tmp, #MVFR0_A_SIMD_MASK	    @ A_SIMD field
36	cmp	\tmp, #2			    @ 32 x 64bit registers?
37	ldceql	p11, cr0, [\base],#32*4		    @ FLDMIAD \base!, {d16-d31}
38	addne	\base, \base, #32*4		    @ step over unused register space
39#endif
40#endif
41	.endm
42
43	@ write all the working registers out of the VFP
44	.macro	VFPFSTMIA, base, tmp
45#if __LINUX_ARM_ARCH__ < 6
46	STC	p11, cr0, [\base],#33*4		    @ FSTMIAX \base!, {d0-d15}
47#else
48	STC	p11, cr0, [\base],#32*4		    @ FSTMIAD \base!, {d0-d15}
49#endif
50#ifdef CONFIG_VFPv3
51#if __LINUX_ARM_ARCH__ <= 6
52	ldr	\tmp, =elf_hwcap		    @ may not have MVFR regs
53	ldr	\tmp, [\tmp, #0]
54	tst	\tmp, #HWCAP_VFPD32
55	stcnel	p11, cr0, [\base],#32*4		    @ FSTMIAD \base!, {d16-d31}
56	addeq	\base, \base, #32*4		    @ step over unused register space
57#else
58	VFPFMRX	\tmp, MVFR0			    @ Media and VFP Feature Register 0
59	and	\tmp, \tmp, #MVFR0_A_SIMD_MASK	    @ A_SIMD field
60	cmp	\tmp, #2			    @ 32 x 64bit registers?
61	stceql	p11, cr0, [\base],#32*4		    @ FSTMIAD \base!, {d16-d31}
62	addne	\base, \base, #32*4		    @ step over unused register space
63#endif
64#endif
65	.endm