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1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/clock/qcom,gcc-msm8960.h>
5#include <dt-bindings/reset/qcom,gcc-msm8960.h>
6#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
7#include <dt-bindings/clock/qcom,rpmcc.h>
8#include <dt-bindings/soc/qcom,gsbi.h>
9#include <dt-bindings/interrupt-controller/irq.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11/ {
12 #address-cells = <1>;
13 #size-cells = <1>;
14 model = "Qualcomm APQ8064";
15 compatible = "qcom,apq8064";
16 interrupt-parent = <&intc>;
17
18 reserved-memory {
19 #address-cells = <1>;
20 #size-cells = <1>;
21 ranges;
22
23 smem_region: smem@80000000 {
24 reg = <0x80000000 0x200000>;
25 no-map;
26 };
27
28 wcnss_mem: wcnss@8f000000 {
29 reg = <0x8f000000 0x700000>;
30 no-map;
31 };
32 };
33
34 cpus {
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 CPU0: cpu@0 {
39 compatible = "qcom,krait";
40 enable-method = "qcom,kpss-acc-v1";
41 device_type = "cpu";
42 reg = <0>;
43 next-level-cache = <&L2>;
44 qcom,acc = <&acc0>;
45 qcom,saw = <&saw0>;
46 cpu-idle-states = <&CPU_SPC>;
47 };
48
49 CPU1: cpu@1 {
50 compatible = "qcom,krait";
51 enable-method = "qcom,kpss-acc-v1";
52 device_type = "cpu";
53 reg = <1>;
54 next-level-cache = <&L2>;
55 qcom,acc = <&acc1>;
56 qcom,saw = <&saw1>;
57 cpu-idle-states = <&CPU_SPC>;
58 };
59
60 CPU2: cpu@2 {
61 compatible = "qcom,krait";
62 enable-method = "qcom,kpss-acc-v1";
63 device_type = "cpu";
64 reg = <2>;
65 next-level-cache = <&L2>;
66 qcom,acc = <&acc2>;
67 qcom,saw = <&saw2>;
68 cpu-idle-states = <&CPU_SPC>;
69 };
70
71 CPU3: cpu@3 {
72 compatible = "qcom,krait";
73 enable-method = "qcom,kpss-acc-v1";
74 device_type = "cpu";
75 reg = <3>;
76 next-level-cache = <&L2>;
77 qcom,acc = <&acc3>;
78 qcom,saw = <&saw3>;
79 cpu-idle-states = <&CPU_SPC>;
80 };
81
82 L2: l2-cache {
83 compatible = "cache";
84 cache-level = <2>;
85 };
86
87 idle-states {
88 CPU_SPC: spc {
89 compatible = "qcom,idle-state-spc",
90 "arm,idle-state";
91 entry-latency-us = <400>;
92 exit-latency-us = <900>;
93 min-residency-us = <3000>;
94 };
95 };
96 };
97
98 memory {
99 device_type = "memory";
100 reg = <0x0 0x0>;
101 };
102
103 thermal-zones {
104 cpu-thermal0 {
105 polling-delay-passive = <250>;
106 polling-delay = <1000>;
107
108 thermal-sensors = <&gcc 7>;
109 coefficients = <1199 0>;
110
111 trips {
112 cpu_alert0: trip0 {
113 temperature = <75000>;
114 hysteresis = <2000>;
115 type = "passive";
116 };
117 cpu_crit0: trip1 {
118 temperature = <110000>;
119 hysteresis = <2000>;
120 type = "critical";
121 };
122 };
123 };
124
125 cpu-thermal1 {
126 polling-delay-passive = <250>;
127 polling-delay = <1000>;
128
129 thermal-sensors = <&gcc 8>;
130 coefficients = <1132 0>;
131
132 trips {
133 cpu_alert1: trip0 {
134 temperature = <75000>;
135 hysteresis = <2000>;
136 type = "passive";
137 };
138 cpu_crit1: trip1 {
139 temperature = <110000>;
140 hysteresis = <2000>;
141 type = "critical";
142 };
143 };
144 };
145
146 cpu-thermal2 {
147 polling-delay-passive = <250>;
148 polling-delay = <1000>;
149
150 thermal-sensors = <&gcc 9>;
151 coefficients = <1199 0>;
152
153 trips {
154 cpu_alert2: trip0 {
155 temperature = <75000>;
156 hysteresis = <2000>;
157 type = "passive";
158 };
159 cpu_crit2: trip1 {
160 temperature = <110000>;
161 hysteresis = <2000>;
162 type = "critical";
163 };
164 };
165 };
166
167 cpu-thermal3 {
168 polling-delay-passive = <250>;
169 polling-delay = <1000>;
170
171 thermal-sensors = <&gcc 10>;
172 coefficients = <1132 0>;
173
174 trips {
175 cpu_alert3: trip0 {
176 temperature = <75000>;
177 hysteresis = <2000>;
178 type = "passive";
179 };
180 cpu_crit3: trip1 {
181 temperature = <110000>;
182 hysteresis = <2000>;
183 type = "critical";
184 };
185 };
186 };
187 };
188
189 cpu-pmu {
190 compatible = "qcom,krait-pmu";
191 interrupts = <1 10 0x304>;
192 };
193
194 clocks {
195 cxo_board: cxo_board {
196 compatible = "fixed-clock";
197 #clock-cells = <0>;
198 clock-frequency = <19200000>;
199 };
200
201 pxo_board {
202 compatible = "fixed-clock";
203 #clock-cells = <0>;
204 clock-frequency = <27000000>;
205 };
206
207 sleep_clk: sleep_clk {
208 compatible = "fixed-clock";
209 #clock-cells = <0>;
210 clock-frequency = <32768>;
211 };
212 };
213
214 sfpb_mutex: hwmutex {
215 compatible = "qcom,sfpb-mutex";
216 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
217 #hwlock-cells = <1>;
218 };
219
220 smem {
221 compatible = "qcom,smem";
222 memory-region = <&smem_region>;
223
224 hwlocks = <&sfpb_mutex 3>;
225 };
226
227 smd {
228 compatible = "qcom,smd";
229
230 modem@0 {
231 interrupts = <0 37 IRQ_TYPE_EDGE_RISING>;
232
233 qcom,ipc = <&l2cc 8 3>;
234 qcom,smd-edge = <0>;
235
236 status = "disabled";
237 };
238
239 q6@1 {
240 interrupts = <0 90 IRQ_TYPE_EDGE_RISING>;
241
242 qcom,ipc = <&l2cc 8 15>;
243 qcom,smd-edge = <1>;
244
245 status = "disabled";
246 };
247
248 dsps@3 {
249 interrupts = <0 138 IRQ_TYPE_EDGE_RISING>;
250
251 qcom,ipc = <&sps_sic_non_secure 0x4080 0>;
252 qcom,smd-edge = <3>;
253
254 status = "disabled";
255 };
256
257 riva@6 {
258 interrupts = <0 198 IRQ_TYPE_EDGE_RISING>;
259
260 qcom,ipc = <&l2cc 8 25>;
261 qcom,smd-edge = <6>;
262
263 status = "disabled";
264 };
265 };
266
267 smsm {
268 compatible = "qcom,smsm";
269
270 #address-cells = <1>;
271 #size-cells = <0>;
272
273 qcom,ipc-1 = <&l2cc 8 4>;
274 qcom,ipc-2 = <&l2cc 8 14>;
275 qcom,ipc-3 = <&l2cc 8 23>;
276 qcom,ipc-4 = <&sps_sic_non_secure 0x4094 0>;
277
278 apps_smsm: apps@0 {
279 reg = <0>;
280 #qcom,smem-state-cells = <1>;
281 };
282
283 modem_smsm: modem@1 {
284 reg = <1>;
285 interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
286
287 interrupt-controller;
288 #interrupt-cells = <2>;
289 };
290
291 q6_smsm: q6@2 {
292 reg = <2>;
293 interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
294
295 interrupt-controller;
296 #interrupt-cells = <2>;
297 };
298
299 wcnss_smsm: wcnss@3 {
300 reg = <3>;
301 interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
302
303 interrupt-controller;
304 #interrupt-cells = <2>;
305 };
306
307 dsps_smsm: dsps@4 {
308 reg = <4>;
309 interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
310
311 interrupt-controller;
312 #interrupt-cells = <2>;
313 };
314 };
315
316 firmware {
317 scm {
318 compatible = "qcom,scm-apq8064";
319
320 clocks = <&rpmcc RPM_DAYTONA_FABRIC_CLK>;
321 clock-names = "core";
322 };
323 };
324
325
326 /*
327 * These channels from the ADC are simply hardware monitors.
328 * That is why the ADC is referred to as "HKADC" - HouseKeeping
329 * ADC.
330 */
331 iio-hwmon {
332 compatible = "iio-hwmon";
333 io-channels = <&xoadc 0x00 0x01>, /* Battery */
334 <&xoadc 0x00 0x02>, /* DC in (charger) */
335 <&xoadc 0x00 0x04>, /* VPH the main system voltage */
336 <&xoadc 0x00 0x0b>, /* Die temperature */
337 <&xoadc 0x00 0x0c>, /* Reference voltage 1.25V */
338 <&xoadc 0x00 0x0d>, /* Reference voltage 0.625V */
339 <&xoadc 0x00 0x0e>; /* Charger temperature */
340 };
341
342 soc: soc {
343 #address-cells = <1>;
344 #size-cells = <1>;
345 ranges;
346 compatible = "simple-bus";
347
348 tlmm_pinmux: pinctrl@800000 {
349 compatible = "qcom,apq8064-pinctrl";
350 reg = <0x800000 0x4000>;
351
352 gpio-controller;
353 #gpio-cells = <2>;
354 interrupt-controller;
355 #interrupt-cells = <2>;
356 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
357
358 pinctrl-names = "default";
359 pinctrl-0 = <&ps_hold>;
360 };
361
362 sfpb_wrapper_mutex: syscon@1200000 {
363 compatible = "syscon";
364 reg = <0x01200000 0x8000>;
365 };
366
367 intc: interrupt-controller@2000000 {
368 compatible = "qcom,msm-qgic2";
369 interrupt-controller;
370 #interrupt-cells = <3>;
371 reg = <0x02000000 0x1000>,
372 <0x02002000 0x1000>;
373 };
374
375 timer@200a000 {
376 compatible = "qcom,kpss-timer",
377 "qcom,kpss-wdt-apq8064", "qcom,msm-timer";
378 interrupts = <1 1 0x301>,
379 <1 2 0x301>,
380 <1 3 0x301>;
381 reg = <0x0200a000 0x100>;
382 clock-frequency = <27000000>,
383 <32768>;
384 cpu-offset = <0x80000>;
385 };
386
387 acc0: clock-controller@2088000 {
388 compatible = "qcom,kpss-acc-v1";
389 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
390 };
391
392 acc1: clock-controller@2098000 {
393 compatible = "qcom,kpss-acc-v1";
394 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
395 };
396
397 acc2: clock-controller@20a8000 {
398 compatible = "qcom,kpss-acc-v1";
399 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
400 };
401
402 acc3: clock-controller@20b8000 {
403 compatible = "qcom,kpss-acc-v1";
404 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
405 };
406
407 saw0: power-controller@2089000 {
408 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
409 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
410 regulator;
411 };
412
413 saw1: power-controller@2099000 {
414 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
415 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
416 regulator;
417 };
418
419 saw2: power-controller@20a9000 {
420 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
421 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
422 regulator;
423 };
424
425 saw3: power-controller@20b9000 {
426 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
427 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
428 regulator;
429 };
430
431 sps_sic_non_secure: sps-sic-non-secure@12100000 {
432 compatible = "syscon";
433 reg = <0x12100000 0x10000>;
434 };
435
436 gsbi1: gsbi@12440000 {
437 status = "disabled";
438 compatible = "qcom,gsbi-v1.0.0";
439 cell-index = <1>;
440 reg = <0x12440000 0x100>;
441 clocks = <&gcc GSBI1_H_CLK>;
442 clock-names = "iface";
443 #address-cells = <1>;
444 #size-cells = <1>;
445 ranges;
446
447 syscon-tcsr = <&tcsr>;
448
449 gsbi1_serial: serial@12450000 {
450 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
451 reg = <0x12450000 0x100>,
452 <0x12400000 0x03>;
453 interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
454 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
455 clock-names = "core", "iface";
456 status = "disabled";
457 };
458
459 gsbi1_i2c: i2c@12460000 {
460 compatible = "qcom,i2c-qup-v1.1.1";
461 pinctrl-0 = <&i2c1_pins>;
462 pinctrl-1 = <&i2c1_pins_sleep>;
463 pinctrl-names = "default", "sleep";
464 reg = <0x12460000 0x1000>;
465 interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
466 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
467 clock-names = "core", "iface";
468 #address-cells = <1>;
469 #size-cells = <0>;
470 status = "disabled";
471 };
472
473 };
474
475 gsbi2: gsbi@12480000 {
476 status = "disabled";
477 compatible = "qcom,gsbi-v1.0.0";
478 cell-index = <2>;
479 reg = <0x12480000 0x100>;
480 clocks = <&gcc GSBI2_H_CLK>;
481 clock-names = "iface";
482 #address-cells = <1>;
483 #size-cells = <1>;
484 ranges;
485
486 syscon-tcsr = <&tcsr>;
487
488 gsbi2_i2c: i2c@124a0000 {
489 compatible = "qcom,i2c-qup-v1.1.1";
490 reg = <0x124a0000 0x1000>;
491 pinctrl-0 = <&i2c2_pins>;
492 pinctrl-1 = <&i2c2_pins_sleep>;
493 pinctrl-names = "default", "sleep";
494 interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
495 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
496 clock-names = "core", "iface";
497 #address-cells = <1>;
498 #size-cells = <0>;
499 status = "disabled";
500 };
501 };
502
503 gsbi3: gsbi@16200000 {
504 status = "disabled";
505 compatible = "qcom,gsbi-v1.0.0";
506 cell-index = <3>;
507 reg = <0x16200000 0x100>;
508 clocks = <&gcc GSBI3_H_CLK>;
509 clock-names = "iface";
510 #address-cells = <1>;
511 #size-cells = <1>;
512 ranges;
513 gsbi3_i2c: i2c@16280000 {
514 compatible = "qcom,i2c-qup-v1.1.1";
515 pinctrl-0 = <&i2c3_pins>;
516 pinctrl-1 = <&i2c3_pins_sleep>;
517 pinctrl-names = "default", "sleep";
518 reg = <0x16280000 0x1000>;
519 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
520 clocks = <&gcc GSBI3_QUP_CLK>,
521 <&gcc GSBI3_H_CLK>;
522 clock-names = "core", "iface";
523 #address-cells = <1>;
524 #size-cells = <0>;
525 status = "disabled";
526 };
527 };
528
529 gsbi4: gsbi@16300000 {
530 status = "disabled";
531 compatible = "qcom,gsbi-v1.0.0";
532 cell-index = <4>;
533 reg = <0x16300000 0x03>;
534 clocks = <&gcc GSBI4_H_CLK>;
535 clock-names = "iface";
536 #address-cells = <1>;
537 #size-cells = <1>;
538 ranges;
539
540 gsbi4_i2c: i2c@16380000 {
541 compatible = "qcom,i2c-qup-v1.1.1";
542 pinctrl-0 = <&i2c4_pins>;
543 pinctrl-1 = <&i2c4_pins_sleep>;
544 pinctrl-names = "default", "sleep";
545 reg = <0x16380000 0x1000>;
546 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&gcc GSBI4_QUP_CLK>,
548 <&gcc GSBI4_H_CLK>;
549 clock-names = "core", "iface";
550 status = "disabled";
551 };
552 };
553
554 gsbi5: gsbi@1a200000 {
555 status = "disabled";
556 compatible = "qcom,gsbi-v1.0.0";
557 cell-index = <5>;
558 reg = <0x1a200000 0x03>;
559 clocks = <&gcc GSBI5_H_CLK>;
560 clock-names = "iface";
561 #address-cells = <1>;
562 #size-cells = <1>;
563 ranges;
564
565 gsbi5_serial: serial@1a240000 {
566 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
567 reg = <0x1a240000 0x100>,
568 <0x1a200000 0x03>;
569 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
570 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
571 clock-names = "core", "iface";
572 status = "disabled";
573 };
574
575 gsbi5_spi: spi@1a280000 {
576 compatible = "qcom,spi-qup-v1.1.1";
577 reg = <0x1a280000 0x1000>;
578 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
579 pinctrl-0 = <&spi5_default>;
580 pinctrl-1 = <&spi5_sleep>;
581 pinctrl-names = "default", "sleep";
582 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
583 clock-names = "core", "iface";
584 status = "disabled";
585 #address-cells = <1>;
586 #size-cells = <0>;
587 };
588 };
589
590 gsbi6: gsbi@16500000 {
591 status = "disabled";
592 compatible = "qcom,gsbi-v1.0.0";
593 cell-index = <6>;
594 reg = <0x16500000 0x03>;
595 clocks = <&gcc GSBI6_H_CLK>;
596 clock-names = "iface";
597 #address-cells = <1>;
598 #size-cells = <1>;
599 ranges;
600
601 gsbi6_serial: serial@16540000 {
602 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
603 reg = <0x16540000 0x100>,
604 <0x16500000 0x03>;
605 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
606 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
607 clock-names = "core", "iface";
608 status = "disabled";
609 };
610
611 gsbi6_i2c: i2c@16580000 {
612 compatible = "qcom,i2c-qup-v1.1.1";
613 pinctrl-0 = <&i2c6_pins>;
614 pinctrl-1 = <&i2c6_pins_sleep>;
615 pinctrl-names = "default", "sleep";
616 reg = <0x16580000 0x1000>;
617 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
618 clocks = <&gcc GSBI6_QUP_CLK>,
619 <&gcc GSBI6_H_CLK>;
620 clock-names = "core", "iface";
621 status = "disabled";
622 };
623 };
624
625 gsbi7: gsbi@16600000 {
626 status = "disabled";
627 compatible = "qcom,gsbi-v1.0.0";
628 cell-index = <7>;
629 reg = <0x16600000 0x100>;
630 clocks = <&gcc GSBI7_H_CLK>;
631 clock-names = "iface";
632 #address-cells = <1>;
633 #size-cells = <1>;
634 ranges;
635 syscon-tcsr = <&tcsr>;
636
637 gsbi7_serial: serial@16640000 {
638 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
639 reg = <0x16640000 0x1000>,
640 <0x16600000 0x1000>;
641 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
642 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
643 clock-names = "core", "iface";
644 status = "disabled";
645 };
646
647 gsbi7_i2c: i2c@16680000 {
648 compatible = "qcom,i2c-qup-v1.1.1";
649 pinctrl-0 = <&i2c7_pins>;
650 pinctrl-1 = <&i2c7_pins_sleep>;
651 pinctrl-names = "default", "sleep";
652 reg = <0x16680000 0x1000>;
653 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
654 clocks = <&gcc GSBI7_QUP_CLK>,
655 <&gcc GSBI7_H_CLK>;
656 clock-names = "core", "iface";
657 status = "disabled";
658 };
659 };
660
661 rng@1a500000 {
662 compatible = "qcom,prng";
663 reg = <0x1a500000 0x200>;
664 clocks = <&gcc PRNG_CLK>;
665 clock-names = "core";
666 };
667
668 ssbi@c00000 {
669 compatible = "qcom,ssbi";
670 reg = <0x00c00000 0x1000>;
671 qcom,controller-type = "pmic-arbiter";
672
673 pm8821: pmic@1 {
674 compatible = "qcom,pm8821";
675 interrupt-parent = <&tlmm_pinmux>;
676 interrupts = <76 IRQ_TYPE_LEVEL_LOW>;
677 #interrupt-cells = <2>;
678 interrupt-controller;
679 #address-cells = <1>;
680 #size-cells = <0>;
681
682 pm8821_mpps: mpps@50 {
683 compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp";
684 reg = <0x50>;
685 interrupts = <24 IRQ_TYPE_NONE>,
686 <25 IRQ_TYPE_NONE>,
687 <26 IRQ_TYPE_NONE>,
688 <27 IRQ_TYPE_NONE>;
689 gpio-controller;
690 #gpio-cells = <2>;
691 };
692 };
693 };
694
695 qcom,ssbi@500000 {
696 compatible = "qcom,ssbi";
697 reg = <0x00500000 0x1000>;
698 qcom,controller-type = "pmic-arbiter";
699
700 pmicintc: pmic@0 {
701 compatible = "qcom,pm8921";
702 interrupt-parent = <&tlmm_pinmux>;
703 interrupts = <74 8>;
704 #interrupt-cells = <2>;
705 interrupt-controller;
706 #address-cells = <1>;
707 #size-cells = <0>;
708
709 pm8921_gpio: gpio@150 {
710
711 compatible = "qcom,pm8921-gpio",
712 "qcom,ssbi-gpio";
713 reg = <0x150>;
714 interrupt-controller;
715 #interrupt-cells = <2>;
716 gpio-controller;
717 gpio-ranges = <&pm8921_gpio 0 0 44>;
718 #gpio-cells = <2>;
719
720 };
721
722 pm8921_mpps: mpps@50 {
723 compatible = "qcom,pm8921-mpp",
724 "qcom,ssbi-mpp";
725 reg = <0x50>;
726 gpio-controller;
727 #gpio-cells = <2>;
728 interrupts =
729 <128 IRQ_TYPE_NONE>,
730 <129 IRQ_TYPE_NONE>,
731 <130 IRQ_TYPE_NONE>,
732 <131 IRQ_TYPE_NONE>,
733 <132 IRQ_TYPE_NONE>,
734 <133 IRQ_TYPE_NONE>,
735 <134 IRQ_TYPE_NONE>,
736 <135 IRQ_TYPE_NONE>,
737 <136 IRQ_TYPE_NONE>,
738 <137 IRQ_TYPE_NONE>,
739 <138 IRQ_TYPE_NONE>,
740 <139 IRQ_TYPE_NONE>;
741 };
742
743 rtc@11d {
744 compatible = "qcom,pm8921-rtc";
745 interrupt-parent = <&pmicintc>;
746 interrupts = <39 1>;
747 reg = <0x11d>;
748 allow-set-time;
749 };
750
751 pwrkey@1c {
752 compatible = "qcom,pm8921-pwrkey";
753 reg = <0x1c>;
754 interrupt-parent = <&pmicintc>;
755 interrupts = <50 1>, <51 1>;
756 debounce = <15625>;
757 pull-up;
758 };
759
760 xoadc: xoadc@197 {
761 compatible = "qcom,pm8921-adc";
762 reg = <197>;
763 interrupts-extended = <&pmicintc 78 IRQ_TYPE_EDGE_RISING>;
764 #address-cells = <2>;
765 #size-cells = <0>;
766 #io-channel-cells = <2>;
767
768 vcoin: adc-channel@00 {
769 reg = <0x00 0x00>;
770 };
771 vbat: adc-channel@01 {
772 reg = <0x00 0x01>;
773 };
774 dcin: adc-channel@02 {
775 reg = <0x00 0x02>;
776 };
777 vph_pwr: adc-channel@04 {
778 reg = <0x00 0x04>;
779 };
780 batt_therm: adc-channel@08 {
781 reg = <0x00 0x08>;
782 };
783 batt_id: adc-channel@09 {
784 reg = <0x00 0x09>;
785 };
786 usb_vbus: adc-channel@0a {
787 reg = <0x00 0x0a>;
788 };
789 die_temp: adc-channel@0b {
790 reg = <0x00 0x0b>;
791 };
792 ref_625mv: adc-channel@0c {
793 reg = <0x00 0x0c>;
794 };
795 ref_1250mv: adc-channel@0d {
796 reg = <0x00 0x0d>;
797 };
798 chg_temp: adc-channel@0e {
799 reg = <0x00 0x0e>;
800 };
801 ref_muxoff: adc-channel@0f {
802 reg = <0x00 0x0f>;
803 };
804 };
805 };
806 };
807
808 qfprom: qfprom@700000 {
809 compatible = "qcom,qfprom";
810 reg = <0x00700000 0x1000>;
811 #address-cells = <1>;
812 #size-cells = <1>;
813 ranges;
814 tsens_calib: calib {
815 reg = <0x404 0x10>;
816 };
817 tsens_backup: backup_calib {
818 reg = <0x414 0x10>;
819 };
820 };
821
822 gcc: clock-controller@900000 {
823 compatible = "qcom,gcc-apq8064";
824 reg = <0x00900000 0x4000>;
825 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
826 nvmem-cell-names = "calib", "calib_backup";
827 #clock-cells = <1>;
828 #reset-cells = <1>;
829 #thermal-sensor-cells = <1>;
830 };
831
832 lcc: clock-controller@28000000 {
833 compatible = "qcom,lcc-apq8064";
834 reg = <0x28000000 0x1000>;
835 #clock-cells = <1>;
836 #reset-cells = <1>;
837 };
838
839 mmcc: clock-controller@4000000 {
840 compatible = "qcom,mmcc-apq8064";
841 reg = <0x4000000 0x1000>;
842 #clock-cells = <1>;
843 #reset-cells = <1>;
844 };
845
846 l2cc: clock-controller@2011000 {
847 compatible = "syscon";
848 reg = <0x2011000 0x1000>;
849 };
850
851 rpm@108000 {
852 compatible = "qcom,rpm-apq8064";
853 reg = <0x108000 0x1000>;
854 qcom,ipc = <&l2cc 0x8 2>;
855
856 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
857 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
858 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
859 interrupt-names = "ack", "err", "wakeup";
860
861 rpmcc: clock-controller {
862 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
863 #clock-cells = <1>;
864 };
865
866 regulators {
867 compatible = "qcom,rpm-pm8921-regulators";
868
869 pm8921_s1: s1 {};
870 pm8921_s2: s2 {};
871 pm8921_s3: s3 {};
872 pm8921_s4: s4 {};
873 pm8921_s7: s7 {};
874 pm8921_s8: s8 {};
875
876 pm8921_l1: l1 {};
877 pm8921_l2: l2 {};
878 pm8921_l3: l3 {};
879 pm8921_l4: l4 {};
880 pm8921_l5: l5 {};
881 pm8921_l6: l6 {};
882 pm8921_l7: l7 {};
883 pm8921_l8: l8 {};
884 pm8921_l9: l9 {};
885 pm8921_l10: l10 {};
886 pm8921_l11: l11 {};
887 pm8921_l12: l12 {};
888 pm8921_l14: l14 {};
889 pm8921_l15: l15 {};
890 pm8921_l16: l16 {};
891 pm8921_l17: l17 {};
892 pm8921_l18: l18 {};
893 pm8921_l21: l21 {};
894 pm8921_l22: l22 {};
895 pm8921_l23: l23 {};
896 pm8921_l24: l24 {};
897 pm8921_l25: l25 {};
898 pm8921_l26: l26 {};
899 pm8921_l27: l27 {};
900 pm8921_l28: l28 {};
901 pm8921_l29: l29 {};
902
903 pm8921_lvs1: lvs1 {};
904 pm8921_lvs2: lvs2 {};
905 pm8921_lvs3: lvs3 {};
906 pm8921_lvs4: lvs4 {};
907 pm8921_lvs5: lvs5 {};
908 pm8921_lvs6: lvs6 {};
909 pm8921_lvs7: lvs7 {};
910
911 pm8921_usb_switch: usb-switch {};
912
913 pm8921_hdmi_switch: hdmi-switch {
914 bias-pull-down;
915 };
916
917 pm8921_ncp: ncp {};
918 };
919 };
920
921 usb1: usb@12500000 {
922 compatible = "qcom,ci-hdrc";
923 reg = <0x12500000 0x200>,
924 <0x12500200 0x200>;
925 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
926 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
927 clock-names = "core", "iface";
928 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
929 assigned-clock-rates = <60000000>;
930 resets = <&gcc USB_HS1_RESET>;
931 reset-names = "core";
932 phy_type = "ulpi";
933 ahb-burst-config = <0>;
934 phys = <&usb_hs1_phy>;
935 phy-names = "usb-phy";
936 status = "disabled";
937 #reset-cells = <1>;
938
939 ulpi {
940 usb_hs1_phy: phy {
941 compatible = "qcom,usb-hs-phy-apq8064",
942 "qcom,usb-hs-phy";
943 clocks = <&sleep_clk>, <&cxo_board>;
944 clock-names = "sleep", "ref";
945 resets = <&usb1 0>;
946 reset-names = "por";
947 #phy-cells = <0>;
948 };
949 };
950 };
951
952 usb3: usb@12520000 {
953 compatible = "qcom,ci-hdrc";
954 reg = <0x12520000 0x200>,
955 <0x12520200 0x200>;
956 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
957 clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>;
958 clock-names = "core", "iface";
959 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
960 assigned-clock-rates = <60000000>;
961 resets = <&gcc USB_HS3_RESET>;
962 reset-names = "core";
963 phy_type = "ulpi";
964 ahb-burst-config = <0>;
965 phys = <&usb_hs3_phy>;
966 phy-names = "usb-phy";
967 status = "disabled";
968 #reset-cells = <1>;
969
970 ulpi {
971 usb_hs3_phy: phy {
972 compatible = "qcom,usb-hs-phy-apq8064",
973 "qcom,usb-hs-phy";
974 #phy-cells = <0>;
975 clocks = <&sleep_clk>, <&cxo_board>;
976 clock-names = "sleep", "ref";
977 resets = <&usb3 0>;
978 reset-names = "por";
979 };
980 };
981 };
982
983 usb4: usb@12530000 {
984 compatible = "qcom,ci-hdrc";
985 reg = <0x12530000 0x200>,
986 <0x12530200 0x200>;
987 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
988 clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>;
989 clock-names = "core", "iface";
990 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
991 assigned-clock-rates = <60000000>;
992 resets = <&gcc USB_HS4_RESET>;
993 reset-names = "core";
994 phy_type = "ulpi";
995 ahb-burst-config = <0>;
996 phys = <&usb_hs4_phy>;
997 phy-names = "usb-phy";
998 status = "disabled";
999 #reset-cells = <1>;
1000
1001 ulpi {
1002 usb_hs4_phy: phy {
1003 compatible = "qcom,usb-hs-phy-apq8064",
1004 "qcom,usb-hs-phy";
1005 #phy-cells = <0>;
1006 clocks = <&sleep_clk>, <&cxo_board>;
1007 clock-names = "sleep", "ref";
1008 resets = <&usb4 0>;
1009 reset-names = "por";
1010 };
1011 };
1012 };
1013
1014 sata_phy0: phy@1b400000 {
1015 compatible = "qcom,apq8064-sata-phy";
1016 status = "disabled";
1017 reg = <0x1b400000 0x200>;
1018 reg-names = "phy_mem";
1019 clocks = <&gcc SATA_PHY_CFG_CLK>;
1020 clock-names = "cfg";
1021 #phy-cells = <0>;
1022 };
1023
1024 sata0: sata@29000000 {
1025 compatible = "qcom,apq8064-ahci", "generic-ahci";
1026 status = "disabled";
1027 reg = <0x29000000 0x180>;
1028 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
1029
1030 clocks = <&gcc SFAB_SATA_S_H_CLK>,
1031 <&gcc SATA_H_CLK>,
1032 <&gcc SATA_A_CLK>,
1033 <&gcc SATA_RXOOB_CLK>,
1034 <&gcc SATA_PMALIVE_CLK>;
1035 clock-names = "slave_iface",
1036 "iface",
1037 "bus",
1038 "rxoob",
1039 "core_pmalive";
1040
1041 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
1042 <&gcc SATA_PMALIVE_CLK>;
1043 assigned-clock-rates = <100000000>, <100000000>;
1044
1045 phys = <&sata_phy0>;
1046 phy-names = "sata-phy";
1047 ports-implemented = <0x1>;
1048 };
1049
1050 /* Temporary fixed regulator */
1051 sdcc1bam:dma@12402000{
1052 compatible = "qcom,bam-v1.3.0";
1053 reg = <0x12402000 0x8000>;
1054 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
1055 clocks = <&gcc SDC1_H_CLK>;
1056 clock-names = "bam_clk";
1057 #dma-cells = <1>;
1058 qcom,ee = <0>;
1059 };
1060
1061 sdcc3bam:dma@12182000{
1062 compatible = "qcom,bam-v1.3.0";
1063 reg = <0x12182000 0x8000>;
1064 interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
1065 clocks = <&gcc SDC3_H_CLK>;
1066 clock-names = "bam_clk";
1067 #dma-cells = <1>;
1068 qcom,ee = <0>;
1069 };
1070
1071 sdcc4bam:dma@121c2000{
1072 compatible = "qcom,bam-v1.3.0";
1073 reg = <0x121c2000 0x8000>;
1074 interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
1075 clocks = <&gcc SDC4_H_CLK>;
1076 clock-names = "bam_clk";
1077 #dma-cells = <1>;
1078 qcom,ee = <0>;
1079 };
1080
1081 amba {
1082 compatible = "simple-bus";
1083 #address-cells = <1>;
1084 #size-cells = <1>;
1085 ranges;
1086 sdcc1: sdcc@12400000 {
1087 status = "disabled";
1088 compatible = "arm,pl18x", "arm,primecell";
1089 pinctrl-names = "default";
1090 pinctrl-0 = <&sdcc1_pins>;
1091 arm,primecell-periphid = <0x00051180>;
1092 reg = <0x12400000 0x2000>;
1093 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1094 interrupt-names = "cmd_irq";
1095 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1096 clock-names = "mclk", "apb_pclk";
1097 bus-width = <8>;
1098 max-frequency = <96000000>;
1099 non-removable;
1100 cap-sd-highspeed;
1101 cap-mmc-highspeed;
1102 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1103 dma-names = "tx", "rx";
1104 };
1105
1106 sdcc3: sdcc@12180000 {
1107 compatible = "arm,pl18x", "arm,primecell";
1108 arm,primecell-periphid = <0x00051180>;
1109 status = "disabled";
1110 reg = <0x12180000 0x2000>;
1111 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1112 interrupt-names = "cmd_irq";
1113 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1114 clock-names = "mclk", "apb_pclk";
1115 bus-width = <4>;
1116 cap-sd-highspeed;
1117 cap-mmc-highspeed;
1118 max-frequency = <192000000>;
1119 no-1-8-v;
1120 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1121 dma-names = "tx", "rx";
1122 };
1123
1124 sdcc4: sdcc@121c0000 {
1125 compatible = "arm,pl18x", "arm,primecell";
1126 arm,primecell-periphid = <0x00051180>;
1127 status = "disabled";
1128 reg = <0x121c0000 0x2000>;
1129 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1130 interrupt-names = "cmd_irq";
1131 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1132 clock-names = "mclk", "apb_pclk";
1133 bus-width = <4>;
1134 cap-sd-highspeed;
1135 cap-mmc-highspeed;
1136 max-frequency = <48000000>;
1137 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
1138 dma-names = "tx", "rx";
1139 pinctrl-names = "default";
1140 pinctrl-0 = <&sdc4_gpios>;
1141 };
1142 };
1143
1144 tcsr: syscon@1a400000 {
1145 compatible = "qcom,tcsr-apq8064", "syscon";
1146 reg = <0x1a400000 0x100>;
1147 };
1148
1149 gpu: adreno-3xx@4300000 {
1150 compatible = "qcom,adreno-3xx";
1151 reg = <0x04300000 0x20000>;
1152 reg-names = "kgsl_3d0_reg_memory";
1153 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1154 interrupt-names = "kgsl_3d0_irq";
1155 clock-names =
1156 "core_clk",
1157 "iface_clk",
1158 "mem_clk",
1159 "mem_iface_clk";
1160 clocks =
1161 <&mmcc GFX3D_CLK>,
1162 <&mmcc GFX3D_AHB_CLK>,
1163 <&mmcc GFX3D_AXI_CLK>,
1164 <&mmcc MMSS_IMEM_AHB_CLK>;
1165 qcom,chipid = <0x03020002>;
1166
1167 iommus = <&gfx3d 0
1168 &gfx3d 1
1169 &gfx3d 2
1170 &gfx3d 3
1171 &gfx3d 4
1172 &gfx3d 5
1173 &gfx3d 6
1174 &gfx3d 7
1175 &gfx3d 8
1176 &gfx3d 9
1177 &gfx3d 10
1178 &gfx3d 11
1179 &gfx3d 12
1180 &gfx3d 13
1181 &gfx3d 14
1182 &gfx3d 15
1183 &gfx3d 16
1184 &gfx3d 17
1185 &gfx3d 18
1186 &gfx3d 19
1187 &gfx3d 20
1188 &gfx3d 21
1189 &gfx3d 22
1190 &gfx3d 23
1191 &gfx3d 24
1192 &gfx3d 25
1193 &gfx3d 26
1194 &gfx3d 27
1195 &gfx3d 28
1196 &gfx3d 29
1197 &gfx3d 30
1198 &gfx3d 31
1199 &gfx3d1 0
1200 &gfx3d1 1
1201 &gfx3d1 2
1202 &gfx3d1 3
1203 &gfx3d1 4
1204 &gfx3d1 5
1205 &gfx3d1 6
1206 &gfx3d1 7
1207 &gfx3d1 8
1208 &gfx3d1 9
1209 &gfx3d1 10
1210 &gfx3d1 11
1211 &gfx3d1 12
1212 &gfx3d1 13
1213 &gfx3d1 14
1214 &gfx3d1 15
1215 &gfx3d1 16
1216 &gfx3d1 17
1217 &gfx3d1 18
1218 &gfx3d1 19
1219 &gfx3d1 20
1220 &gfx3d1 21
1221 &gfx3d1 22
1222 &gfx3d1 23
1223 &gfx3d1 24
1224 &gfx3d1 25
1225 &gfx3d1 26
1226 &gfx3d1 27
1227 &gfx3d1 28
1228 &gfx3d1 29
1229 &gfx3d1 30
1230 &gfx3d1 31>;
1231
1232 qcom,gpu-pwrlevels {
1233 compatible = "qcom,gpu-pwrlevels";
1234 qcom,gpu-pwrlevel@0 {
1235 qcom,gpu-freq = <450000000>;
1236 };
1237 qcom,gpu-pwrlevel@1 {
1238 qcom,gpu-freq = <27000000>;
1239 };
1240 };
1241 };
1242
1243 mmss_sfpb: syscon@5700000 {
1244 compatible = "syscon";
1245 reg = <0x5700000 0x70>;
1246 };
1247
1248 dsi0: mdss_dsi@4700000 {
1249 compatible = "qcom,mdss-dsi-ctrl";
1250 label = "MDSS DSI CTRL->0";
1251 #address-cells = <1>;
1252 #size-cells = <0>;
1253 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
1254 reg = <0x04700000 0x200>;
1255 reg-names = "dsi_ctrl";
1256
1257 clocks = <&mmcc DSI_M_AHB_CLK>,
1258 <&mmcc DSI_S_AHB_CLK>,
1259 <&mmcc AMP_AHB_CLK>,
1260 <&mmcc DSI_CLK>,
1261 <&mmcc DSI1_BYTE_CLK>,
1262 <&mmcc DSI_PIXEL_CLK>,
1263 <&mmcc DSI1_ESC_CLK>;
1264 clock-names = "iface_clk", "bus_clk", "core_mmss_clk",
1265 "src_clk", "byte_clk", "pixel_clk",
1266 "core_clk";
1267
1268 assigned-clocks = <&mmcc DSI1_BYTE_SRC>,
1269 <&mmcc DSI1_ESC_SRC>,
1270 <&mmcc DSI_SRC>,
1271 <&mmcc DSI_PIXEL_SRC>;
1272 assigned-clock-parents = <&dsi0_phy 0>,
1273 <&dsi0_phy 0>,
1274 <&dsi0_phy 1>,
1275 <&dsi0_phy 1>;
1276 syscon-sfpb = <&mmss_sfpb>;
1277 phys = <&dsi0_phy>;
1278 ports {
1279 #address-cells = <1>;
1280 #size-cells = <0>;
1281
1282 port@0 {
1283 reg = <0>;
1284 dsi0_in: endpoint {
1285 };
1286 };
1287
1288 port@1 {
1289 reg = <1>;
1290 dsi0_out: endpoint {
1291 };
1292 };
1293 };
1294 };
1295
1296
1297 dsi0_phy: dsi-phy@4700200 {
1298 compatible = "qcom,dsi-phy-28nm-8960";
1299 #clock-cells = <1>;
1300 #phy-cells = <0>;
1301
1302 reg = <0x04700200 0x100>,
1303 <0x04700300 0x200>,
1304 <0x04700500 0x5c>;
1305 reg-names = "dsi_pll", "dsi_phy", "dsi_phy_regulator";
1306 clock-names = "iface_clk", "ref";
1307 clocks = <&mmcc DSI_M_AHB_CLK>,
1308 <&cxo_board>;
1309 };
1310
1311
1312 mdp_port0: iommu@7500000 {
1313 compatible = "qcom,apq8064-iommu";
1314 #iommu-cells = <1>;
1315 clock-names =
1316 "smmu_pclk",
1317 "iommu_clk";
1318 clocks =
1319 <&mmcc SMMU_AHB_CLK>,
1320 <&mmcc MDP_AXI_CLK>;
1321 reg = <0x07500000 0x100000>;
1322 interrupts =
1323 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
1324 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
1325 qcom,ncb = <2>;
1326 };
1327
1328 mdp_port1: iommu@7600000 {
1329 compatible = "qcom,apq8064-iommu";
1330 #iommu-cells = <1>;
1331 clock-names =
1332 "smmu_pclk",
1333 "iommu_clk";
1334 clocks =
1335 <&mmcc SMMU_AHB_CLK>,
1336 <&mmcc MDP_AXI_CLK>;
1337 reg = <0x07600000 0x100000>;
1338 interrupts =
1339 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
1340 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
1341 qcom,ncb = <2>;
1342 };
1343
1344 gfx3d: iommu@7c00000 {
1345 compatible = "qcom,apq8064-iommu";
1346 #iommu-cells = <1>;
1347 clock-names =
1348 "smmu_pclk",
1349 "iommu_clk";
1350 clocks =
1351 <&mmcc SMMU_AHB_CLK>,
1352 <&mmcc GFX3D_AXI_CLK>;
1353 reg = <0x07c00000 0x100000>;
1354 interrupts =
1355 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1356 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
1357 qcom,ncb = <3>;
1358 };
1359
1360 gfx3d1: iommu@7d00000 {
1361 compatible = "qcom,apq8064-iommu";
1362 #iommu-cells = <1>;
1363 clock-names =
1364 "smmu_pclk",
1365 "iommu_clk";
1366 clocks =
1367 <&mmcc SMMU_AHB_CLK>,
1368 <&mmcc GFX3D_AXI_CLK>;
1369 reg = <0x07d00000 0x100000>;
1370 interrupts =
1371 <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
1372 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
1373 qcom,ncb = <3>;
1374 };
1375
1376 pcie: pci@1b500000 {
1377 compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
1378 reg = <0x1b500000 0x1000
1379 0x1b502000 0x80
1380 0x1b600000 0x100
1381 0x0ff00000 0x100000>;
1382 reg-names = "dbi", "elbi", "parf", "config";
1383 device_type = "pci";
1384 linux,pci-domain = <0>;
1385 bus-range = <0x00 0xff>;
1386 num-lanes = <1>;
1387 #address-cells = <3>;
1388 #size-cells = <2>;
1389 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
1390 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* memory */
1391 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
1392 interrupt-names = "msi";
1393 #interrupt-cells = <1>;
1394 interrupt-map-mask = <0 0 0 0x7>;
1395 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1396 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1397 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1398 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1399 clocks = <&gcc PCIE_A_CLK>,
1400 <&gcc PCIE_H_CLK>,
1401 <&gcc PCIE_PHY_REF_CLK>;
1402 clock-names = "core", "iface", "phy";
1403 resets = <&gcc PCIE_ACLK_RESET>,
1404 <&gcc PCIE_HCLK_RESET>,
1405 <&gcc PCIE_POR_RESET>,
1406 <&gcc PCIE_PCI_RESET>,
1407 <&gcc PCIE_PHY_RESET>;
1408 reset-names = "axi", "ahb", "por", "pci", "phy";
1409 status = "disabled";
1410 };
1411
1412 hdmi: hdmi-tx@4a00000 {
1413 compatible = "qcom,hdmi-tx-8960";
1414 pinctrl-names = "default";
1415 pinctrl-0 = <&hdmi_pinctrl>;
1416 reg = <0x04a00000 0x2f0>;
1417 reg-names = "core_physical";
1418 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
1419 clocks = <&mmcc HDMI_APP_CLK>,
1420 <&mmcc HDMI_M_AHB_CLK>,
1421 <&mmcc HDMI_S_AHB_CLK>;
1422 clock-names = "core_clk",
1423 "master_iface_clk",
1424 "slave_iface_clk";
1425
1426 phys = <&hdmi_phy>;
1427 phy-names = "hdmi-phy";
1428
1429 ports {
1430 #address-cells = <1>;
1431 #size-cells = <0>;
1432
1433 port@0 {
1434 reg = <0>;
1435 hdmi_in: endpoint {
1436 };
1437 };
1438
1439 port@1 {
1440 reg = <1>;
1441 hdmi_out: endpoint {
1442 };
1443 };
1444 };
1445 };
1446
1447 hdmi_phy: hdmi-phy@4a00400 {
1448 compatible = "qcom,hdmi-phy-8960";
1449 reg = <0x4a00400 0x60>,
1450 <0x4a00500 0x100>;
1451 reg-names = "hdmi_phy",
1452 "hdmi_pll";
1453
1454 clocks = <&mmcc HDMI_S_AHB_CLK>;
1455 clock-names = "slave_iface_clk";
1456 #phy-cells = <0>;
1457 };
1458
1459 mdp: mdp@5100000 {
1460 compatible = "qcom,mdp4";
1461 reg = <0x05100000 0xf0000>;
1462 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1463 clocks = <&mmcc MDP_CLK>,
1464 <&mmcc MDP_AHB_CLK>,
1465 <&mmcc MDP_AXI_CLK>,
1466 <&mmcc MDP_LUT_CLK>,
1467 <&mmcc HDMI_TV_CLK>,
1468 <&mmcc MDP_TV_CLK>;
1469 clock-names = "core_clk",
1470 "iface_clk",
1471 "bus_clk",
1472 "lut_clk",
1473 "hdmi_clk",
1474 "tv_clk";
1475
1476 iommus = <&mdp_port0 0
1477 &mdp_port0 2
1478 &mdp_port1 0
1479 &mdp_port1 2>;
1480
1481 ports {
1482 #address-cells = <1>;
1483 #size-cells = <0>;
1484
1485 port@0 {
1486 reg = <0>;
1487 mdp_lvds_out: endpoint {
1488 };
1489 };
1490
1491 port@1 {
1492 reg = <1>;
1493 mdp_dsi1_out: endpoint {
1494 };
1495 };
1496
1497 port@2 {
1498 reg = <2>;
1499 mdp_dsi2_out: endpoint {
1500 };
1501 };
1502
1503 port@3 {
1504 reg = <3>;
1505 mdp_dtv_out: endpoint {
1506 };
1507 };
1508 };
1509 };
1510
1511 riva: riva-pil@3204000 {
1512 compatible = "qcom,riva-pil";
1513
1514 reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
1515 reg-names = "ccu", "dxe", "pmu";
1516
1517 interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
1518 <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>;
1519 interrupt-names = "wdog", "fatal";
1520
1521 memory-region = <&wcnss_mem>;
1522
1523 vddcx-supply = <&pm8921_s3>;
1524 vddmx-supply = <&pm8921_l24>;
1525 vddpx-supply = <&pm8921_s4>;
1526
1527 status = "disabled";
1528
1529 iris {
1530 compatible = "qcom,wcn3660";
1531
1532 clocks = <&cxo_board>;
1533 clock-names = "xo";
1534
1535 vddxo-supply = <&pm8921_l4>;
1536 vddrfa-supply = <&pm8921_s2>;
1537 vddpa-supply = <&pm8921_l10>;
1538 vdddig-supply = <&pm8921_lvs2>;
1539 };
1540
1541 smd-edge {
1542 interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
1543
1544 qcom,ipc = <&l2cc 8 25>;
1545 qcom,smd-edge = <6>;
1546
1547 label = "riva";
1548
1549 wcnss {
1550 compatible = "qcom,wcnss";
1551 qcom,smd-channels = "WCNSS_CTRL";
1552
1553 qcom,mmio = <&riva>;
1554
1555 bt {
1556 compatible = "qcom,wcnss-bt";
1557 };
1558
1559 wifi {
1560 compatible = "qcom,wcnss-wlan";
1561
1562 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
1563 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
1564 interrupt-names = "tx", "rx";
1565
1566 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
1567 qcom,smem-state-names = "tx-enable", "tx-rings-empty";
1568 };
1569 };
1570 };
1571 };
1572
1573 etb@1a01000 {
1574 compatible = "coresight-etb10", "arm,primecell";
1575 reg = <0x1a01000 0x1000>;
1576
1577 clocks = <&rpmcc RPM_QDSS_CLK>;
1578 clock-names = "apb_pclk";
1579
1580 in-ports {
1581 port {
1582 etb_in: endpoint {
1583 remote-endpoint = <&replicator_out0>;
1584 };
1585 };
1586 };
1587 };
1588
1589 tpiu@1a03000 {
1590 compatible = "arm,coresight-tpiu", "arm,primecell";
1591 reg = <0x1a03000 0x1000>;
1592
1593 clocks = <&rpmcc RPM_QDSS_CLK>;
1594 clock-names = "apb_pclk";
1595
1596 in-ports {
1597 port {
1598 tpiu_in: endpoint {
1599 remote-endpoint = <&replicator_out1>;
1600 };
1601 };
1602 };
1603 };
1604
1605 replicator {
1606 compatible = "arm,coresight-static-replicator";
1607
1608 clocks = <&rpmcc RPM_QDSS_CLK>;
1609 clock-names = "apb_pclk";
1610
1611 out-ports {
1612 #address-cells = <1>;
1613 #size-cells = <0>;
1614
1615 port@0 {
1616 reg = <0>;
1617 replicator_out0: endpoint {
1618 remote-endpoint = <&etb_in>;
1619 };
1620 };
1621 port@1 {
1622 reg = <1>;
1623 replicator_out1: endpoint {
1624 remote-endpoint = <&tpiu_in>;
1625 };
1626 };
1627 };
1628
1629 in-ports {
1630 port {
1631 replicator_in: endpoint {
1632 remote-endpoint = <&funnel_out>;
1633 };
1634 };
1635 };
1636 };
1637
1638 funnel@1a04000 {
1639 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1640 reg = <0x1a04000 0x1000>;
1641
1642 clocks = <&rpmcc RPM_QDSS_CLK>;
1643 clock-names = "apb_pclk";
1644
1645 in-ports {
1646 #address-cells = <1>;
1647 #size-cells = <0>;
1648
1649 /*
1650 * Not described input ports:
1651 * 2 - connected to STM component
1652 * 3 - not-connected
1653 * 6 - not-connected
1654 * 7 - not-connected
1655 */
1656 port@0 {
1657 reg = <0>;
1658 funnel_in0: endpoint {
1659 remote-endpoint = <&etm0_out>;
1660 };
1661 };
1662 port@1 {
1663 reg = <1>;
1664 funnel_in1: endpoint {
1665 remote-endpoint = <&etm1_out>;
1666 };
1667 };
1668 port@4 {
1669 reg = <4>;
1670 funnel_in4: endpoint {
1671 remote-endpoint = <&etm2_out>;
1672 };
1673 };
1674 port@5 {
1675 reg = <5>;
1676 funnel_in5: endpoint {
1677 remote-endpoint = <&etm3_out>;
1678 };
1679 };
1680 };
1681
1682 out-ports {
1683 port {
1684 funnel_out: endpoint {
1685 remote-endpoint = <&replicator_in>;
1686 };
1687 };
1688 };
1689 };
1690
1691 etm@1a1c000 {
1692 compatible = "arm,coresight-etm3x", "arm,primecell";
1693 reg = <0x1a1c000 0x1000>;
1694
1695 clocks = <&rpmcc RPM_QDSS_CLK>;
1696 clock-names = "apb_pclk";
1697
1698 cpu = <&CPU0>;
1699
1700 out-ports {
1701 port {
1702 etm0_out: endpoint {
1703 remote-endpoint = <&funnel_in0>;
1704 };
1705 };
1706 };
1707 };
1708
1709 etm@1a1d000 {
1710 compatible = "arm,coresight-etm3x", "arm,primecell";
1711 reg = <0x1a1d000 0x1000>;
1712
1713 clocks = <&rpmcc RPM_QDSS_CLK>;
1714 clock-names = "apb_pclk";
1715
1716 cpu = <&CPU1>;
1717
1718 out-ports {
1719 port {
1720 etm1_out: endpoint {
1721 remote-endpoint = <&funnel_in1>;
1722 };
1723 };
1724 };
1725 };
1726
1727 etm@1a1e000 {
1728 compatible = "arm,coresight-etm3x", "arm,primecell";
1729 reg = <0x1a1e000 0x1000>;
1730
1731 clocks = <&rpmcc RPM_QDSS_CLK>;
1732 clock-names = "apb_pclk";
1733
1734 cpu = <&CPU2>;
1735
1736 out-ports {
1737 port {
1738 etm2_out: endpoint {
1739 remote-endpoint = <&funnel_in4>;
1740 };
1741 };
1742 };
1743 };
1744
1745 etm@1a1f000 {
1746 compatible = "arm,coresight-etm3x", "arm,primecell";
1747 reg = <0x1a1f000 0x1000>;
1748
1749 clocks = <&rpmcc RPM_QDSS_CLK>;
1750 clock-names = "apb_pclk";
1751
1752 cpu = <&CPU3>;
1753
1754 out-ports {
1755 port {
1756 etm3_out: endpoint {
1757 remote-endpoint = <&funnel_in5>;
1758 };
1759 };
1760 };
1761 };
1762 };
1763};
1764#include "qcom-apq8064-pins.dtsi"
1/dts-v1/;
2
3#include "skeleton.dtsi"
4#include <dt-bindings/clock/qcom,gcc-msm8960.h>
5#include <dt-bindings/reset/qcom,gcc-msm8960.h>
6#include <dt-bindings/clock/qcom,mmcc-msm8960.h>
7#include <dt-bindings/soc/qcom,gsbi.h>
8#include <dt-bindings/interrupt-controller/arm-gic.h>
9/ {
10 model = "Qualcomm APQ8064";
11 compatible = "qcom,apq8064";
12 interrupt-parent = <&intc>;
13
14 reserved-memory {
15 #address-cells = <1>;
16 #size-cells = <1>;
17 ranges;
18
19 smem_region: smem@80000000 {
20 reg = <0x80000000 0x200000>;
21 no-map;
22 };
23 };
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 cpu@0 {
30 compatible = "qcom,krait";
31 enable-method = "qcom,kpss-acc-v1";
32 device_type = "cpu";
33 reg = <0>;
34 next-level-cache = <&L2>;
35 qcom,acc = <&acc0>;
36 qcom,saw = <&saw0>;
37 cpu-idle-states = <&CPU_SPC>;
38 };
39
40 cpu@1 {
41 compatible = "qcom,krait";
42 enable-method = "qcom,kpss-acc-v1";
43 device_type = "cpu";
44 reg = <1>;
45 next-level-cache = <&L2>;
46 qcom,acc = <&acc1>;
47 qcom,saw = <&saw1>;
48 cpu-idle-states = <&CPU_SPC>;
49 };
50
51 cpu@2 {
52 compatible = "qcom,krait";
53 enable-method = "qcom,kpss-acc-v1";
54 device_type = "cpu";
55 reg = <2>;
56 next-level-cache = <&L2>;
57 qcom,acc = <&acc2>;
58 qcom,saw = <&saw2>;
59 cpu-idle-states = <&CPU_SPC>;
60 };
61
62 cpu@3 {
63 compatible = "qcom,krait";
64 enable-method = "qcom,kpss-acc-v1";
65 device_type = "cpu";
66 reg = <3>;
67 next-level-cache = <&L2>;
68 qcom,acc = <&acc3>;
69 qcom,saw = <&saw3>;
70 cpu-idle-states = <&CPU_SPC>;
71 };
72
73 L2: l2-cache {
74 compatible = "cache";
75 cache-level = <2>;
76 };
77
78 idle-states {
79 CPU_SPC: spc {
80 compatible = "qcom,idle-state-spc",
81 "arm,idle-state";
82 entry-latency-us = <400>;
83 exit-latency-us = <900>;
84 min-residency-us = <3000>;
85 };
86 };
87 };
88
89 cpu-pmu {
90 compatible = "qcom,krait-pmu";
91 interrupts = <1 10 0x304>;
92 };
93
94 clocks {
95 cxo_board {
96 compatible = "fixed-clock";
97 #clock-cells = <0>;
98 clock-frequency = <19200000>;
99 };
100
101 pxo_board {
102 compatible = "fixed-clock";
103 #clock-cells = <0>;
104 clock-frequency = <27000000>;
105 };
106
107 sleep_clk {
108 compatible = "fixed-clock";
109 #clock-cells = <0>;
110 clock-frequency = <32768>;
111 };
112 };
113
114 sfpb_mutex: hwmutex {
115 compatible = "qcom,sfpb-mutex";
116 syscon = <&sfpb_wrapper_mutex 0x604 0x4>;
117 #hwlock-cells = <1>;
118 };
119
120 smem {
121 compatible = "qcom,smem";
122 memory-region = <&smem_region>;
123
124 hwlocks = <&sfpb_mutex 3>;
125 };
126
127 soc: soc {
128 #address-cells = <1>;
129 #size-cells = <1>;
130 ranges;
131 compatible = "simple-bus";
132
133 tlmm_pinmux: pinctrl@800000 {
134 compatible = "qcom,apq8064-pinctrl";
135 reg = <0x800000 0x4000>;
136
137 gpio-controller;
138 #gpio-cells = <2>;
139 interrupt-controller;
140 #interrupt-cells = <2>;
141 interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
142
143 pinctrl-names = "default";
144 pinctrl-0 = <&ps_hold>;
145 };
146
147 sfpb_wrapper_mutex: syscon@1200000 {
148 compatible = "syscon";
149 reg = <0x01200000 0x8000>;
150 };
151
152 intc: interrupt-controller@2000000 {
153 compatible = "qcom,msm-qgic2";
154 interrupt-controller;
155 #interrupt-cells = <3>;
156 reg = <0x02000000 0x1000>,
157 <0x02002000 0x1000>;
158 };
159
160 timer@200a000 {
161 compatible = "qcom,kpss-timer", "qcom,msm-timer";
162 interrupts = <1 1 0x301>,
163 <1 2 0x301>,
164 <1 3 0x301>;
165 reg = <0x0200a000 0x100>;
166 clock-frequency = <27000000>,
167 <32768>;
168 cpu-offset = <0x80000>;
169 };
170
171 acc0: clock-controller@2088000 {
172 compatible = "qcom,kpss-acc-v1";
173 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
174 };
175
176 acc1: clock-controller@2098000 {
177 compatible = "qcom,kpss-acc-v1";
178 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
179 };
180
181 acc2: clock-controller@20a8000 {
182 compatible = "qcom,kpss-acc-v1";
183 reg = <0x020a8000 0x1000>, <0x02008000 0x1000>;
184 };
185
186 acc3: clock-controller@20b8000 {
187 compatible = "qcom,kpss-acc-v1";
188 reg = <0x020b8000 0x1000>, <0x02008000 0x1000>;
189 };
190
191 saw0: power-controller@2089000 {
192 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
193 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
194 regulator;
195 };
196
197 saw1: power-controller@2099000 {
198 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
199 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
200 regulator;
201 };
202
203 saw2: power-controller@20a9000 {
204 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
205 reg = <0x020a9000 0x1000>, <0x02009000 0x1000>;
206 regulator;
207 };
208
209 saw3: power-controller@20b9000 {
210 compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2";
211 reg = <0x020b9000 0x1000>, <0x02009000 0x1000>;
212 regulator;
213 };
214
215 gsbi1: gsbi@12440000 {
216 status = "disabled";
217 compatible = "qcom,gsbi-v1.0.0";
218 cell-index = <1>;
219 reg = <0x12440000 0x100>;
220 clocks = <&gcc GSBI1_H_CLK>;
221 clock-names = "iface";
222 #address-cells = <1>;
223 #size-cells = <1>;
224 ranges;
225
226 syscon-tcsr = <&tcsr>;
227
228 gsbi1_i2c: i2c@12460000 {
229 compatible = "qcom,i2c-qup-v1.1.1";
230 pinctrl-0 = <&i2c1_pins &i2c1_pins_sleep>;
231 pinctrl-names = "default", "sleep";
232 reg = <0x12460000 0x1000>;
233 interrupts = <0 194 IRQ_TYPE_NONE>;
234 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
235 clock-names = "core", "iface";
236 #address-cells = <1>;
237 #size-cells = <0>;
238 };
239
240 };
241
242 gsbi2: gsbi@12480000 {
243 status = "disabled";
244 compatible = "qcom,gsbi-v1.0.0";
245 cell-index = <2>;
246 reg = <0x12480000 0x100>;
247 clocks = <&gcc GSBI2_H_CLK>;
248 clock-names = "iface";
249 #address-cells = <1>;
250 #size-cells = <1>;
251 ranges;
252
253 syscon-tcsr = <&tcsr>;
254
255 gsbi2_i2c: i2c@124a0000 {
256 compatible = "qcom,i2c-qup-v1.1.1";
257 reg = <0x124a0000 0x1000>;
258 pinctrl-0 = <&i2c2_pins &i2c2_pins_sleep>;
259 pinctrl-names = "default", "sleep";
260 interrupts = <0 196 IRQ_TYPE_NONE>;
261 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
262 clock-names = "core", "iface";
263 #address-cells = <1>;
264 #size-cells = <0>;
265 };
266 };
267
268 gsbi3: gsbi@16200000 {
269 status = "disabled";
270 compatible = "qcom,gsbi-v1.0.0";
271 cell-index = <3>;
272 reg = <0x16200000 0x100>;
273 clocks = <&gcc GSBI3_H_CLK>;
274 clock-names = "iface";
275 #address-cells = <1>;
276 #size-cells = <1>;
277 ranges;
278 gsbi3_i2c: i2c@16280000 {
279 compatible = "qcom,i2c-qup-v1.1.1";
280 pinctrl-0 = <&i2c3_pins &i2c3_pins_sleep>;
281 pinctrl-names = "default", "sleep";
282 reg = <0x16280000 0x1000>;
283 interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
284 clocks = <&gcc GSBI3_QUP_CLK>,
285 <&gcc GSBI3_H_CLK>;
286 clock-names = "core", "iface";
287 #address-cells = <1>;
288 #size-cells = <0>;
289 };
290 };
291
292 gsbi4: gsbi@16300000 {
293 status = "disabled";
294 compatible = "qcom,gsbi-v1.0.0";
295 cell-index = <4>;
296 reg = <0x16300000 0x03>;
297 clocks = <&gcc GSBI4_H_CLK>;
298 clock-names = "iface";
299 #address-cells = <1>;
300 #size-cells = <1>;
301 ranges;
302
303 gsbi4_i2c: i2c@16380000 {
304 compatible = "qcom,i2c-qup-v1.1.1";
305 pinctrl-0 = <&i2c4_pins &i2c4_pins_sleep>;
306 pinctrl-names = "default", "sleep";
307 reg = <0x16380000 0x1000>;
308 interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
309 clocks = <&gcc GSBI4_QUP_CLK>,
310 <&gcc GSBI4_H_CLK>;
311 clock-names = "core", "iface";
312 };
313 };
314
315 gsbi5: gsbi@1a200000 {
316 status = "disabled";
317 compatible = "qcom,gsbi-v1.0.0";
318 cell-index = <5>;
319 reg = <0x1a200000 0x03>;
320 clocks = <&gcc GSBI5_H_CLK>;
321 clock-names = "iface";
322 #address-cells = <1>;
323 #size-cells = <1>;
324 ranges;
325
326 gsbi5_serial: serial@1a240000 {
327 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
328 reg = <0x1a240000 0x100>,
329 <0x1a200000 0x03>;
330 interrupts = <0 154 0x0>;
331 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
332 clock-names = "core", "iface";
333 status = "disabled";
334 };
335
336 gsbi5_spi: spi@1a280000 {
337 compatible = "qcom,spi-qup-v1.1.1";
338 reg = <0x1a280000 0x1000>;
339 interrupts = <0 155 0>;
340 pinctrl-0 = <&spi5_default &spi5_sleep>;
341 pinctrl-names = "default", "sleep";
342 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
343 clock-names = "core", "iface";
344 status = "disabled";
345 #address-cells = <1>;
346 #size-cells = <0>;
347 };
348 };
349
350 gsbi6: gsbi@16500000 {
351 status = "disabled";
352 compatible = "qcom,gsbi-v1.0.0";
353 cell-index = <6>;
354 reg = <0x16500000 0x03>;
355 clocks = <&gcc GSBI6_H_CLK>;
356 clock-names = "iface";
357 #address-cells = <1>;
358 #size-cells = <1>;
359 ranges;
360
361 gsbi6_serial: serial@16540000 {
362 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
363 reg = <0x16540000 0x100>,
364 <0x16500000 0x03>;
365 interrupts = <0 156 0x0>;
366 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
367 clock-names = "core", "iface";
368 status = "disabled";
369 };
370
371 gsbi6_i2c: i2c@16580000 {
372 compatible = "qcom,i2c-qup-v1.1.1";
373 pinctrl-0 = <&i2c6_pins &i2c6_pins_sleep>;
374 pinctrl-names = "default", "sleep";
375 reg = <0x16580000 0x1000>;
376 interrupts = <GIC_SPI 157 IRQ_TYPE_NONE>;
377 clocks = <&gcc GSBI6_QUP_CLK>,
378 <&gcc GSBI6_H_CLK>;
379 clock-names = "core", "iface";
380 };
381 };
382
383 gsbi7: gsbi@16600000 {
384 status = "disabled";
385 compatible = "qcom,gsbi-v1.0.0";
386 cell-index = <7>;
387 reg = <0x16600000 0x100>;
388 clocks = <&gcc GSBI7_H_CLK>;
389 clock-names = "iface";
390 #address-cells = <1>;
391 #size-cells = <1>;
392 ranges;
393 syscon-tcsr = <&tcsr>;
394
395 gsbi7_serial: serial@16640000 {
396 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
397 reg = <0x16640000 0x1000>,
398 <0x16600000 0x1000>;
399 interrupts = <0 158 0x0>;
400 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
401 clock-names = "core", "iface";
402 status = "disabled";
403 };
404 };
405
406 rng@1a500000 {
407 compatible = "qcom,prng";
408 reg = <0x1a500000 0x200>;
409 clocks = <&gcc PRNG_CLK>;
410 clock-names = "core";
411 };
412
413 qcom,ssbi@500000 {
414 compatible = "qcom,ssbi";
415 reg = <0x00500000 0x1000>;
416 qcom,controller-type = "pmic-arbiter";
417
418 pmicintc: pmic@0 {
419 compatible = "qcom,pm8921";
420 interrupt-parent = <&tlmm_pinmux>;
421 interrupts = <74 8>;
422 #interrupt-cells = <2>;
423 interrupt-controller;
424 #address-cells = <1>;
425 #size-cells = <0>;
426
427 pm8921_gpio: gpio@150 {
428
429 compatible = "qcom,pm8921-gpio",
430 "qcom,ssbi-gpio";
431 reg = <0x150>;
432 interrupts = <192 1>, <193 1>, <194 1>,
433 <195 1>, <196 1>, <197 1>,
434 <198 1>, <199 1>, <200 1>,
435 <201 1>, <202 1>, <203 1>,
436 <204 1>, <205 1>, <206 1>,
437 <207 1>, <208 1>, <209 1>,
438 <210 1>, <211 1>, <212 1>,
439 <213 1>, <214 1>, <215 1>,
440 <216 1>, <217 1>, <218 1>,
441 <219 1>, <220 1>, <221 1>,
442 <222 1>, <223 1>, <224 1>,
443 <225 1>, <226 1>, <227 1>,
444 <228 1>, <229 1>, <230 1>,
445 <231 1>, <232 1>, <233 1>,
446 <234 1>, <235 1>;
447
448 gpio-controller;
449 #gpio-cells = <2>;
450
451 };
452
453 pm8921_mpps: mpps@50 {
454 compatible = "qcom,pm8921-mpp",
455 "qcom,ssbi-mpp";
456 reg = <0x50>;
457 gpio-controller;
458 #gpio-cells = <2>;
459 interrupts =
460 <128 1>, <129 1>, <130 1>, <131 1>,
461 <132 1>, <133 1>, <134 1>, <135 1>,
462 <136 1>, <137 1>, <138 1>, <139 1>;
463 };
464
465 rtc@11d {
466 compatible = "qcom,pm8921-rtc";
467 interrupt-parent = <&pmicintc>;
468 interrupts = <39 1>;
469 reg = <0x11d>;
470 allow-set-time;
471 };
472
473 pwrkey@1c {
474 compatible = "qcom,pm8921-pwrkey";
475 reg = <0x1c>;
476 interrupt-parent = <&pmicintc>;
477 interrupts = <50 1>, <51 1>;
478 debounce = <15625>;
479 pull-up;
480 };
481 };
482 };
483
484 gcc: clock-controller@900000 {
485 compatible = "qcom,gcc-apq8064";
486 reg = <0x00900000 0x4000>;
487 #clock-cells = <1>;
488 #reset-cells = <1>;
489 };
490
491 lcc: clock-controller@28000000 {
492 compatible = "qcom,lcc-apq8064";
493 reg = <0x28000000 0x1000>;
494 #clock-cells = <1>;
495 #reset-cells = <1>;
496 };
497
498 mmcc: clock-controller@4000000 {
499 compatible = "qcom,mmcc-apq8064";
500 reg = <0x4000000 0x1000>;
501 #clock-cells = <1>;
502 #reset-cells = <1>;
503 };
504
505 l2cc: clock-controller@2011000 {
506 compatible = "syscon";
507 reg = <0x2011000 0x1000>;
508 };
509
510 rpm@108000 {
511 compatible = "qcom,rpm-apq8064";
512 reg = <0x108000 0x1000>;
513 qcom,ipc = <&l2cc 0x8 2>;
514
515 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>,
516 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>,
517 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>;
518 interrupt-names = "ack", "err", "wakeup";
519
520 rpmcc: clock-controller {
521 compatible = "qcom,rpmcc-apq8064", "qcom,rpmcc";
522 #clock-cells = <1>;
523 };
524
525 regulators {
526 compatible = "qcom,rpm-pm8921-regulators";
527
528 pm8921_s1: s1 {};
529 pm8921_s2: s2 {};
530 pm8921_s3: s3 {};
531 pm8921_s4: s4 {};
532 pm8921_s7: s7 {};
533 pm8921_s8: s8 {};
534
535 pm8921_l1: l1 {};
536 pm8921_l2: l2 {};
537 pm8921_l3: l3 {};
538 pm8921_l4: l4 {};
539 pm8921_l5: l5 {};
540 pm8921_l6: l6 {};
541 pm8921_l7: l7 {};
542 pm8921_l8: l8 {};
543 pm8921_l9: l9 {};
544 pm8921_l10: l10 {};
545 pm8921_l11: l11 {};
546 pm8921_l12: l12 {};
547 pm8921_l14: l14 {};
548 pm8921_l15: l15 {};
549 pm8921_l16: l16 {};
550 pm8921_l17: l17 {};
551 pm8921_l18: l18 {};
552 pm8921_l21: l21 {};
553 pm8921_l22: l22 {};
554 pm8921_l23: l23 {};
555 pm8921_l24: l24 {};
556 pm8921_l25: l25 {};
557 pm8921_l26: l26 {};
558 pm8921_l27: l27 {};
559 pm8921_l28: l28 {};
560 pm8921_l29: l29 {};
561
562 pm8921_lvs1: lvs1 {};
563 pm8921_lvs2: lvs2 {};
564 pm8921_lvs3: lvs3 {};
565 pm8921_lvs4: lvs4 {};
566 pm8921_lvs5: lvs5 {};
567 pm8921_lvs6: lvs6 {};
568 pm8921_lvs7: lvs7 {};
569
570 pm8921_usb_switch: usb-switch {};
571
572 pm8921_hdmi_switch: hdmi-switch {
573 bias-pull-down;
574 };
575
576 pm8921_ncp: ncp {};
577 };
578 };
579
580 usb1_phy: phy@12500000 {
581 compatible = "qcom,usb-otg-ci";
582 reg = <0x12500000 0x400>;
583 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
584 status = "disabled";
585 dr_mode = "host";
586
587 clocks = <&gcc USB_HS1_XCVR_CLK>,
588 <&gcc USB_HS1_H_CLK>;
589 clock-names = "core", "iface";
590
591 resets = <&gcc USB_HS1_RESET>;
592 reset-names = "link";
593 };
594
595 usb3_phy: phy@12520000 {
596 compatible = "qcom,usb-otg-ci";
597 reg = <0x12520000 0x400>;
598 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
599 status = "disabled";
600 dr_mode = "host";
601
602 clocks = <&gcc USB_HS3_XCVR_CLK>,
603 <&gcc USB_HS3_H_CLK>;
604 clock-names = "core", "iface";
605
606 resets = <&gcc USB_HS3_RESET>;
607 reset-names = "link";
608 };
609
610 usb4_phy: phy@12530000 {
611 compatible = "qcom,usb-otg-ci";
612 reg = <0x12530000 0x400>;
613 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
614 status = "disabled";
615 dr_mode = "host";
616
617 clocks = <&gcc USB_HS4_XCVR_CLK>,
618 <&gcc USB_HS4_H_CLK>;
619 clock-names = "core", "iface";
620
621 resets = <&gcc USB_HS4_RESET>;
622 reset-names = "link";
623 };
624
625 gadget1: gadget@12500000 {
626 compatible = "qcom,ci-hdrc";
627 reg = <0x12500000 0x400>;
628 status = "disabled";
629 dr_mode = "peripheral";
630 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
631 usb-phy = <&usb1_phy>;
632 };
633
634 usb1: usb@12500000 {
635 compatible = "qcom,ehci-host";
636 reg = <0x12500000 0x400>;
637 interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>;
638 status = "disabled";
639 usb-phy = <&usb1_phy>;
640 };
641
642 usb3: usb@12520000 {
643 compatible = "qcom,ehci-host";
644 reg = <0x12520000 0x400>;
645 interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
646 status = "disabled";
647 usb-phy = <&usb3_phy>;
648 };
649
650 usb4: usb@12530000 {
651 compatible = "qcom,ehci-host";
652 reg = <0x12530000 0x400>;
653 interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>;
654 status = "disabled";
655 usb-phy = <&usb4_phy>;
656 };
657
658 sata_phy0: phy@1b400000 {
659 compatible = "qcom,apq8064-sata-phy";
660 status = "disabled";
661 reg = <0x1b400000 0x200>;
662 reg-names = "phy_mem";
663 clocks = <&gcc SATA_PHY_CFG_CLK>;
664 clock-names = "cfg";
665 #phy-cells = <0>;
666 };
667
668 sata0: sata@29000000 {
669 compatible = "qcom,apq8064-ahci", "generic-ahci";
670 status = "disabled";
671 reg = <0x29000000 0x180>;
672 interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>;
673
674 clocks = <&gcc SFAB_SATA_S_H_CLK>,
675 <&gcc SATA_H_CLK>,
676 <&gcc SATA_A_CLK>,
677 <&gcc SATA_RXOOB_CLK>,
678 <&gcc SATA_PMALIVE_CLK>;
679 clock-names = "slave_iface",
680 "iface",
681 "bus",
682 "rxoob",
683 "core_pmalive";
684
685 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
686 <&gcc SATA_PMALIVE_CLK>;
687 assigned-clock-rates = <100000000>, <100000000>;
688
689 phys = <&sata_phy0>;
690 phy-names = "sata-phy";
691 ports-implemented = <0x1>;
692 };
693
694 /* Temporary fixed regulator */
695 sdcc1bam:dma@12402000{
696 compatible = "qcom,bam-v1.3.0";
697 reg = <0x12402000 0x8000>;
698 interrupts = <0 98 0>;
699 clocks = <&gcc SDC1_H_CLK>;
700 clock-names = "bam_clk";
701 #dma-cells = <1>;
702 qcom,ee = <0>;
703 };
704
705 sdcc3bam:dma@12182000{
706 compatible = "qcom,bam-v1.3.0";
707 reg = <0x12182000 0x8000>;
708 interrupts = <0 96 0>;
709 clocks = <&gcc SDC3_H_CLK>;
710 clock-names = "bam_clk";
711 #dma-cells = <1>;
712 qcom,ee = <0>;
713 };
714
715 sdcc4bam:dma@121c2000{
716 compatible = "qcom,bam-v1.3.0";
717 reg = <0x121c2000 0x8000>;
718 interrupts = <0 95 0>;
719 clocks = <&gcc SDC4_H_CLK>;
720 clock-names = "bam_clk";
721 #dma-cells = <1>;
722 qcom,ee = <0>;
723 };
724
725 amba {
726 compatible = "simple-bus";
727 #address-cells = <1>;
728 #size-cells = <1>;
729 ranges;
730 sdcc1: sdcc@12400000 {
731 status = "disabled";
732 compatible = "arm,pl18x", "arm,primecell";
733 arm,primecell-periphid = <0x00051180>;
734 reg = <0x12400000 0x2000>;
735 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
736 interrupt-names = "cmd_irq";
737 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
738 clock-names = "mclk", "apb_pclk";
739 bus-width = <8>;
740 max-frequency = <96000000>;
741 non-removable;
742 cap-sd-highspeed;
743 cap-mmc-highspeed;
744 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
745 dma-names = "tx", "rx";
746 };
747
748 sdcc3: sdcc@12180000 {
749 compatible = "arm,pl18x", "arm,primecell";
750 arm,primecell-periphid = <0x00051180>;
751 status = "disabled";
752 reg = <0x12180000 0x2000>;
753 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
754 interrupt-names = "cmd_irq";
755 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
756 clock-names = "mclk", "apb_pclk";
757 bus-width = <4>;
758 cap-sd-highspeed;
759 cap-mmc-highspeed;
760 max-frequency = <192000000>;
761 no-1-8-v;
762 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
763 dma-names = "tx", "rx";
764 };
765
766 sdcc4: sdcc@121c0000 {
767 compatible = "arm,pl18x", "arm,primecell";
768 arm,primecell-periphid = <0x00051180>;
769 status = "disabled";
770 reg = <0x121c0000 0x2000>;
771 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
772 interrupt-names = "cmd_irq";
773 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
774 clock-names = "mclk", "apb_pclk";
775 bus-width = <4>;
776 cap-sd-highspeed;
777 cap-mmc-highspeed;
778 max-frequency = <48000000>;
779 dmas = <&sdcc4bam 2>, <&sdcc4bam 1>;
780 dma-names = "tx", "rx";
781 pinctrl-names = "default";
782 pinctrl-0 = <&sdc4_gpios>;
783 };
784 };
785
786 tcsr: syscon@1a400000 {
787 compatible = "qcom,tcsr-apq8064", "syscon";
788 reg = <0x1a400000 0x100>;
789 };
790
791 pcie: pci@1b500000 {
792 compatible = "qcom,pcie-apq8064", "snps,dw-pcie";
793 reg = <0x1b500000 0x1000
794 0x1b502000 0x80
795 0x1b600000 0x100
796 0x0ff00000 0x100000>;
797 reg-names = "dbi", "elbi", "parf", "config";
798 device_type = "pci";
799 linux,pci-domain = <0>;
800 bus-range = <0x00 0xff>;
801 num-lanes = <1>;
802 #address-cells = <3>;
803 #size-cells = <2>;
804 ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* I/O */
805 0x82000000 0 0 0x08000000 0 0x07e00000>; /* memory */
806 interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
807 interrupt-names = "msi";
808 #interrupt-cells = <1>;
809 interrupt-map-mask = <0 0 0 0x7>;
810 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
811 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
812 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
813 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
814 clocks = <&gcc PCIE_A_CLK>,
815 <&gcc PCIE_H_CLK>,
816 <&gcc PCIE_PHY_REF_CLK>;
817 clock-names = "core", "iface", "phy";
818 resets = <&gcc PCIE_ACLK_RESET>,
819 <&gcc PCIE_HCLK_RESET>,
820 <&gcc PCIE_POR_RESET>,
821 <&gcc PCIE_PCI_RESET>,
822 <&gcc PCIE_PHY_RESET>;
823 reset-names = "axi", "ahb", "por", "pci", "phy";
824 status = "disabled";
825 };
826 };
827};
828#include "qcom-apq8064-pins.dtsi"