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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2011 Picochip, Jamie Iles
4 */
5/ {
6 model = "Picochip picoXcell PC3X3";
7 compatible = "picochip,pc3x3";
8 #address-cells = <1>;
9 #size-cells = <1>;
10
11 cpus {
12 #address-cells = <0>;
13 #size-cells = <0>;
14
15 cpu {
16 compatible = "arm,arm1176jz-s";
17 device_type = "cpu";
18 cpu-clock = <&arm_clk>, "cpu";
19 d-cache-line-size = <32>;
20 d-cache-size = <32768>;
21 i-cache-line-size = <32>;
22 i-cache-size = <32768>;
23 };
24 };
25
26 clocks {
27 #address-cells = <1>;
28 #size-cells = <1>;
29 ranges;
30
31 clkgate: clkgate@800a0048 {
32 #address-cells = <1>;
33 #size-cells = <0>;
34 reg = <0x800a0048 4>;
35 compatible = "picochip,pc3x3-clk-gate";
36
37 tzprot_clk: clock@0 {
38 compatible = "picochip,pc3x3-gated-clk";
39 clock-outputs = "bus";
40 picochip,clk-disable-bit = <0>;
41 clock-frequency = <200000000>;
42 ref-clock = <&ref_clk>, "ref";
43 };
44
45 spi_clk: clock@1 {
46 compatible = "picochip,pc3x3-gated-clk";
47 clock-outputs = "bus";
48 picochip,clk-disable-bit = <1>;
49 clock-frequency = <200000000>;
50 ref-clock = <&ref_clk>, "ref";
51 };
52
53 dmac0_clk: clock@2 {
54 compatible = "picochip,pc3x3-gated-clk";
55 clock-outputs = "bus";
56 picochip,clk-disable-bit = <2>;
57 clock-frequency = <200000000>;
58 ref-clock = <&ref_clk>, "ref";
59 };
60
61 dmac1_clk: clock@3 {
62 compatible = "picochip,pc3x3-gated-clk";
63 clock-outputs = "bus";
64 picochip,clk-disable-bit = <3>;
65 clock-frequency = <200000000>;
66 ref-clock = <&ref_clk>, "ref";
67 };
68
69 ebi_clk: clock@4 {
70 compatible = "picochip,pc3x3-gated-clk";
71 clock-outputs = "bus";
72 picochip,clk-disable-bit = <4>;
73 clock-frequency = <200000000>;
74 ref-clock = <&ref_clk>, "ref";
75 };
76
77 ipsec_clk: clock@5 {
78 compatible = "picochip,pc3x3-gated-clk";
79 clock-outputs = "bus";
80 picochip,clk-disable-bit = <5>;
81 clock-frequency = <200000000>;
82 ref-clock = <&ref_clk>, "ref";
83 };
84
85 l2_clk: clock@6 {
86 compatible = "picochip,pc3x3-gated-clk";
87 clock-outputs = "bus";
88 picochip,clk-disable-bit = <6>;
89 clock-frequency = <200000000>;
90 ref-clock = <&ref_clk>, "ref";
91 };
92
93 trng_clk: clock@7 {
94 compatible = "picochip,pc3x3-gated-clk";
95 clock-outputs = "bus";
96 picochip,clk-disable-bit = <7>;
97 clock-frequency = <200000000>;
98 ref-clock = <&ref_clk>, "ref";
99 };
100
101 fuse_clk: clock@8 {
102 compatible = "picochip,pc3x3-gated-clk";
103 clock-outputs = "bus";
104 picochip,clk-disable-bit = <8>;
105 clock-frequency = <200000000>;
106 ref-clock = <&ref_clk>, "ref";
107 };
108
109 otp_clk: clock@9 {
110 compatible = "picochip,pc3x3-gated-clk";
111 clock-outputs = "bus";
112 picochip,clk-disable-bit = <9>;
113 clock-frequency = <200000000>;
114 ref-clock = <&ref_clk>, "ref";
115 };
116 };
117
118 arm_clk: clock@11 {
119 compatible = "picochip,pc3x3-pll";
120 reg = <0x800a0050 0x8>;
121 picochip,min-freq = <140000000>;
122 picochip,max-freq = <700000000>;
123 ref-clock = <&ref_clk>, "ref";
124 clock-outputs = "cpu";
125 };
126
127 pclk: clock@12 {
128 compatible = "fixed-clock";
129 clock-outputs = "bus", "pclk";
130 clock-frequency = <200000000>;
131 ref-clock = <&ref_clk>, "ref";
132 };
133 };
134
135 paxi {
136 compatible = "simple-bus";
137 #address-cells = <1>;
138 #size-cells = <1>;
139 ranges = <0 0x80000000 0x400000>;
140
141 emac: gem@30000 {
142 compatible = "cadence,gem";
143 reg = <0x30000 0x10000>;
144 interrupt-parent = <&vic0>;
145 interrupts = <31>;
146 };
147
148 dmac1: dmac@40000 {
149 compatible = "snps,dw-dmac";
150 reg = <0x40000 0x10000>;
151 interrupt-parent = <&vic0>;
152 interrupts = <25>;
153 };
154
155 dmac2: dmac@50000 {
156 compatible = "snps,dw-dmac";
157 reg = <0x50000 0x10000>;
158 interrupt-parent = <&vic0>;
159 interrupts = <26>;
160 };
161
162 vic0: interrupt-controller@60000 {
163 compatible = "arm,pl192-vic";
164 interrupt-controller;
165 reg = <0x60000 0x1000>;
166 #interrupt-cells = <1>;
167 };
168
169 vic1: interrupt-controller@64000 {
170 compatible = "arm,pl192-vic";
171 interrupt-controller;
172 reg = <0x64000 0x1000>;
173 #interrupt-cells = <1>;
174 };
175
176 fuse: picoxcell-fuse@80000 {
177 compatible = "picoxcell,fuse-pc3x3";
178 reg = <0x80000 0x10000>;
179 };
180
181 ssi: picoxcell-spi@90000 {
182 compatible = "picoxcell,spi";
183 reg = <0x90000 0x10000>;
184 interrupt-parent = <&vic0>;
185 interrupts = <10>;
186 };
187
188 ipsec: spacc@100000 {
189 compatible = "picochip,spacc-ipsec";
190 reg = <0x100000 0x10000>;
191 interrupt-parent = <&vic0>;
192 interrupts = <24>;
193 ref-clock = <&ipsec_clk>, "ref";
194 };
195
196 srtp: spacc@140000 {
197 compatible = "picochip,spacc-srtp";
198 reg = <0x140000 0x10000>;
199 interrupt-parent = <&vic0>;
200 interrupts = <23>;
201 };
202
203 l2_engine: spacc@180000 {
204 compatible = "picochip,spacc-l2";
205 reg = <0x180000 0x10000>;
206 interrupt-parent = <&vic0>;
207 interrupts = <22>;
208 ref-clock = <&l2_clk>, "ref";
209 };
210
211 apb {
212 compatible = "simple-bus";
213 #address-cells = <1>;
214 #size-cells = <1>;
215 ranges = <0 0x200000 0x80000>;
216
217 rtc0: rtc@0 {
218 compatible = "picochip,pc3x2-rtc";
219 clock-freq = <200000000>;
220 reg = <0x00000 0xf>;
221 interrupt-parent = <&vic0>;
222 interrupts = <8>;
223 };
224
225 timer0: timer@10000 {
226 compatible = "picochip,pc3x2-timer";
227 interrupt-parent = <&vic0>;
228 interrupts = <4>;
229 clock-freq = <200000000>;
230 reg = <0x10000 0x14>;
231 };
232
233 timer1: timer@10014 {
234 compatible = "picochip,pc3x2-timer";
235 interrupt-parent = <&vic0>;
236 interrupts = <5>;
237 clock-freq = <200000000>;
238 reg = <0x10014 0x14>;
239 };
240
241 gpio: gpio@20000 {
242 compatible = "snps,dw-apb-gpio";
243 reg = <0x20000 0x1000>;
244 #address-cells = <1>;
245 #size-cells = <0>;
246 reg-io-width = <4>;
247
248 banka: gpio-controller@0 {
249 compatible = "snps,dw-apb-gpio-bank";
250 gpio-controller;
251 #gpio-cells = <2>;
252 gpio-generic,nr-gpio = <8>;
253
254 regoffset-dat = <0x50>;
255 regoffset-set = <0x00>;
256 regoffset-dirout = <0x04>;
257 };
258
259 bankb: gpio-controller@1 {
260 compatible = "snps,dw-apb-gpio-bank";
261 gpio-controller;
262 #gpio-cells = <2>;
263 gpio-generic,nr-gpio = <16>;
264
265 regoffset-dat = <0x54>;
266 regoffset-set = <0x0c>;
267 regoffset-dirout = <0x10>;
268 };
269
270 bankd: gpio-controller@2 {
271 compatible = "snps,dw-apb-gpio-bank";
272 gpio-controller;
273 #gpio-cells = <2>;
274 gpio-generic,nr-gpio = <30>;
275
276 regoffset-dat = <0x5c>;
277 regoffset-set = <0x24>;
278 regoffset-dirout = <0x28>;
279 };
280 };
281
282 uart0: uart@30000 {
283 compatible = "snps,dw-apb-uart";
284 reg = <0x30000 0x1000>;
285 interrupt-parent = <&vic1>;
286 interrupts = <10>;
287 clock-frequency = <3686400>;
288 reg-shift = <2>;
289 reg-io-width = <4>;
290 };
291
292 uart1: uart@40000 {
293 compatible = "snps,dw-apb-uart";
294 reg = <0x40000 0x1000>;
295 interrupt-parent = <&vic1>;
296 interrupts = <9>;
297 clock-frequency = <3686400>;
298 reg-shift = <2>;
299 reg-io-width = <4>;
300 };
301
302 wdog: watchdog@50000 {
303 compatible = "snps,dw-apb-wdg";
304 reg = <0x50000 0x10000>;
305 interrupt-parent = <&vic0>;
306 interrupts = <11>;
307 bus-clock = <&pclk>, "bus";
308 };
309
310 timer2: timer@60000 {
311 compatible = "picochip,pc3x2-timer";
312 interrupt-parent = <&vic0>;
313 interrupts = <6>;
314 clock-freq = <200000000>;
315 reg = <0x60000 0x14>;
316 };
317
318 timer3: timer@60014 {
319 compatible = "picochip,pc3x2-timer";
320 interrupt-parent = <&vic0>;
321 interrupts = <7>;
322 clock-freq = <200000000>;
323 reg = <0x60014 0x14>;
324 };
325 };
326 };
327
328 rwid-axi {
329 #address-cells = <1>;
330 #size-cells = <1>;
331 compatible = "simple-bus";
332 ranges;
333
334 ebi@50000000 {
335 compatible = "simple-bus";
336 #address-cells = <2>;
337 #size-cells = <1>;
338 ranges = <0 0 0x40000000 0x08000000
339 1 0 0x48000000 0x08000000
340 2 0 0x50000000 0x08000000
341 3 0 0x58000000 0x08000000>;
342 };
343
344 axi2pico@c0000000 {
345 compatible = "picochip,axi2pico-pc3x3";
346 reg = <0xc0000000 0x10000>;
347 interrupt-parent = <&vic0>;
348 interrupts = <13 14 15 16 17 18 19 20 21>;
349 };
350
351 otp@ffff8000 {
352 compatible = "picochip,otp-pc3x3";
353 reg = <0xffff8000 0x8000>;
354 };
355 };
356};
1/*
2 * Copyright (C) 2011 Picochip, Jamie Iles
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13/include/ "skeleton.dtsi"
14/ {
15 model = "Picochip picoXcell PC3X3";
16 compatible = "picochip,pc3x3";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 cpus {
21 #address-cells = <0>;
22 #size-cells = <0>;
23
24 cpu {
25 compatible = "arm,arm1176jz-s";
26 device_type = "cpu";
27 cpu-clock = <&arm_clk>, "cpu";
28 d-cache-line-size = <32>;
29 d-cache-size = <32768>;
30 i-cache-line-size = <32>;
31 i-cache-size = <32768>;
32 };
33 };
34
35 clocks {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 ranges;
39
40 clkgate: clkgate@800a0048 {
41 #address-cells = <1>;
42 #size-cells = <0>;
43 reg = <0x800a0048 4>;
44 compatible = "picochip,pc3x3-clk-gate";
45
46 tzprot_clk: clock@0 {
47 compatible = "picochip,pc3x3-gated-clk";
48 clock-outputs = "bus";
49 picochip,clk-disable-bit = <0>;
50 clock-frequency = <200000000>;
51 ref-clock = <&ref_clk>, "ref";
52 };
53
54 spi_clk: clock@1 {
55 compatible = "picochip,pc3x3-gated-clk";
56 clock-outputs = "bus";
57 picochip,clk-disable-bit = <1>;
58 clock-frequency = <200000000>;
59 ref-clock = <&ref_clk>, "ref";
60 };
61
62 dmac0_clk: clock@2 {
63 compatible = "picochip,pc3x3-gated-clk";
64 clock-outputs = "bus";
65 picochip,clk-disable-bit = <2>;
66 clock-frequency = <200000000>;
67 ref-clock = <&ref_clk>, "ref";
68 };
69
70 dmac1_clk: clock@3 {
71 compatible = "picochip,pc3x3-gated-clk";
72 clock-outputs = "bus";
73 picochip,clk-disable-bit = <3>;
74 clock-frequency = <200000000>;
75 ref-clock = <&ref_clk>, "ref";
76 };
77
78 ebi_clk: clock@4 {
79 compatible = "picochip,pc3x3-gated-clk";
80 clock-outputs = "bus";
81 picochip,clk-disable-bit = <4>;
82 clock-frequency = <200000000>;
83 ref-clock = <&ref_clk>, "ref";
84 };
85
86 ipsec_clk: clock@5 {
87 compatible = "picochip,pc3x3-gated-clk";
88 clock-outputs = "bus";
89 picochip,clk-disable-bit = <5>;
90 clock-frequency = <200000000>;
91 ref-clock = <&ref_clk>, "ref";
92 };
93
94 l2_clk: clock@6 {
95 compatible = "picochip,pc3x3-gated-clk";
96 clock-outputs = "bus";
97 picochip,clk-disable-bit = <6>;
98 clock-frequency = <200000000>;
99 ref-clock = <&ref_clk>, "ref";
100 };
101
102 trng_clk: clock@7 {
103 compatible = "picochip,pc3x3-gated-clk";
104 clock-outputs = "bus";
105 picochip,clk-disable-bit = <7>;
106 clock-frequency = <200000000>;
107 ref-clock = <&ref_clk>, "ref";
108 };
109
110 fuse_clk: clock@8 {
111 compatible = "picochip,pc3x3-gated-clk";
112 clock-outputs = "bus";
113 picochip,clk-disable-bit = <8>;
114 clock-frequency = <200000000>;
115 ref-clock = <&ref_clk>, "ref";
116 };
117
118 otp_clk: clock@9 {
119 compatible = "picochip,pc3x3-gated-clk";
120 clock-outputs = "bus";
121 picochip,clk-disable-bit = <9>;
122 clock-frequency = <200000000>;
123 ref-clock = <&ref_clk>, "ref";
124 };
125 };
126
127 arm_clk: clock@11 {
128 compatible = "picochip,pc3x3-pll";
129 reg = <0x800a0050 0x8>;
130 picochip,min-freq = <140000000>;
131 picochip,max-freq = <700000000>;
132 ref-clock = <&ref_clk>, "ref";
133 clock-outputs = "cpu";
134 };
135
136 pclk: clock@12 {
137 compatible = "fixed-clock";
138 clock-outputs = "bus", "pclk";
139 clock-frequency = <200000000>;
140 ref-clock = <&ref_clk>, "ref";
141 };
142 };
143
144 paxi {
145 compatible = "simple-bus";
146 #address-cells = <1>;
147 #size-cells = <1>;
148 ranges = <0 0x80000000 0x400000>;
149
150 emac: gem@30000 {
151 compatible = "cadence,gem";
152 reg = <0x30000 0x10000>;
153 interrupt-parent = <&vic0>;
154 interrupts = <31>;
155 };
156
157 dmac1: dmac@40000 {
158 compatible = "snps,dw-dmac";
159 reg = <0x40000 0x10000>;
160 interrupt-parent = <&vic0>;
161 interrupts = <25>;
162 };
163
164 dmac2: dmac@50000 {
165 compatible = "snps,dw-dmac";
166 reg = <0x50000 0x10000>;
167 interrupt-parent = <&vic0>;
168 interrupts = <26>;
169 };
170
171 vic0: interrupt-controller@60000 {
172 compatible = "arm,pl192-vic";
173 interrupt-controller;
174 reg = <0x60000 0x1000>;
175 #interrupt-cells = <1>;
176 };
177
178 vic1: interrupt-controller@64000 {
179 compatible = "arm,pl192-vic";
180 interrupt-controller;
181 reg = <0x64000 0x1000>;
182 #interrupt-cells = <1>;
183 };
184
185 fuse: picoxcell-fuse@80000 {
186 compatible = "picoxcell,fuse-pc3x3";
187 reg = <0x80000 0x10000>;
188 };
189
190 ssi: picoxcell-spi@90000 {
191 compatible = "picoxcell,spi";
192 reg = <0x90000 0x10000>;
193 interrupt-parent = <&vic0>;
194 interrupts = <10>;
195 };
196
197 ipsec: spacc@100000 {
198 compatible = "picochip,spacc-ipsec";
199 reg = <0x100000 0x10000>;
200 interrupt-parent = <&vic0>;
201 interrupts = <24>;
202 ref-clock = <&ipsec_clk>, "ref";
203 };
204
205 srtp: spacc@140000 {
206 compatible = "picochip,spacc-srtp";
207 reg = <0x140000 0x10000>;
208 interrupt-parent = <&vic0>;
209 interrupts = <23>;
210 };
211
212 l2_engine: spacc@180000 {
213 compatible = "picochip,spacc-l2";
214 reg = <0x180000 0x10000>;
215 interrupt-parent = <&vic0>;
216 interrupts = <22>;
217 ref-clock = <&l2_clk>, "ref";
218 };
219
220 apb {
221 compatible = "simple-bus";
222 #address-cells = <1>;
223 #size-cells = <1>;
224 ranges = <0 0x200000 0x80000>;
225
226 rtc0: rtc@00000 {
227 compatible = "picochip,pc3x2-rtc";
228 clock-freq = <200000000>;
229 reg = <0x00000 0xf>;
230 interrupt-parent = <&vic0>;
231 interrupts = <8>;
232 };
233
234 timer0: timer@10000 {
235 compatible = "picochip,pc3x2-timer";
236 interrupt-parent = <&vic0>;
237 interrupts = <4>;
238 clock-freq = <200000000>;
239 reg = <0x10000 0x14>;
240 };
241
242 timer1: timer@10014 {
243 compatible = "picochip,pc3x2-timer";
244 interrupt-parent = <&vic0>;
245 interrupts = <5>;
246 clock-freq = <200000000>;
247 reg = <0x10014 0x14>;
248 };
249
250 gpio: gpio@20000 {
251 compatible = "snps,dw-apb-gpio";
252 reg = <0x20000 0x1000>;
253 #address-cells = <1>;
254 #size-cells = <0>;
255 reg-io-width = <4>;
256
257 banka: gpio-controller@0 {
258 compatible = "snps,dw-apb-gpio-bank";
259 gpio-controller;
260 #gpio-cells = <2>;
261 gpio-generic,nr-gpio = <8>;
262
263 regoffset-dat = <0x50>;
264 regoffset-set = <0x00>;
265 regoffset-dirout = <0x04>;
266 };
267
268 bankb: gpio-controller@1 {
269 compatible = "snps,dw-apb-gpio-bank";
270 gpio-controller;
271 #gpio-cells = <2>;
272 gpio-generic,nr-gpio = <16>;
273
274 regoffset-dat = <0x54>;
275 regoffset-set = <0x0c>;
276 regoffset-dirout = <0x10>;
277 };
278
279 bankd: gpio-controller@2 {
280 compatible = "snps,dw-apb-gpio-bank";
281 gpio-controller;
282 #gpio-cells = <2>;
283 gpio-generic,nr-gpio = <30>;
284
285 regoffset-dat = <0x5c>;
286 regoffset-set = <0x24>;
287 regoffset-dirout = <0x28>;
288 };
289 };
290
291 uart0: uart@30000 {
292 compatible = "snps,dw-apb-uart";
293 reg = <0x30000 0x1000>;
294 interrupt-parent = <&vic1>;
295 interrupts = <10>;
296 clock-frequency = <3686400>;
297 reg-shift = <2>;
298 reg-io-width = <4>;
299 };
300
301 uart1: uart@40000 {
302 compatible = "snps,dw-apb-uart";
303 reg = <0x40000 0x1000>;
304 interrupt-parent = <&vic1>;
305 interrupts = <9>;
306 clock-frequency = <3686400>;
307 reg-shift = <2>;
308 reg-io-width = <4>;
309 };
310
311 wdog: watchdog@50000 {
312 compatible = "snps,dw-apb-wdg";
313 reg = <0x50000 0x10000>;
314 interrupt-parent = <&vic0>;
315 interrupts = <11>;
316 bus-clock = <&pclk>, "bus";
317 };
318
319 timer2: timer@60000 {
320 compatible = "picochip,pc3x2-timer";
321 interrupt-parent = <&vic0>;
322 interrupts = <6>;
323 clock-freq = <200000000>;
324 reg = <0x60000 0x14>;
325 };
326
327 timer3: timer@60014 {
328 compatible = "picochip,pc3x2-timer";
329 interrupt-parent = <&vic0>;
330 interrupts = <7>;
331 clock-freq = <200000000>;
332 reg = <0x60014 0x14>;
333 };
334 };
335 };
336
337 rwid-axi {
338 #address-cells = <1>;
339 #size-cells = <1>;
340 compatible = "simple-bus";
341 ranges;
342
343 ebi@50000000 {
344 compatible = "simple-bus";
345 #address-cells = <2>;
346 #size-cells = <1>;
347 ranges = <0 0 0x40000000 0x08000000
348 1 0 0x48000000 0x08000000
349 2 0 0x50000000 0x08000000
350 3 0 0x58000000 0x08000000>;
351 };
352
353 axi2pico@c0000000 {
354 compatible = "picochip,axi2pico-pc3x3";
355 reg = <0xc0000000 0x10000>;
356 interrupt-parent = <&vic0>;
357 interrupts = <13 14 15 16 17 18 19 20 21>;
358 };
359
360 otp@ffff8000 {
361 compatible = "picochip,otp-pc3x3";
362 reg = <0xffff8000 0x8000>;
363 };
364 };
365};