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1/*
2 * Device Tree Source for OMAP34xx/OMAP35xx SoC
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/bus/ti-sysc.h>
12#include <dt-bindings/media/omap3-isp.h>
13
14#include "omap3.dtsi"
15
16/ {
17 cpus {
18 cpu: cpu@0 {
19 /* OMAP343x/OMAP35xx variants OPP1-5 */
20 operating-points = <
21 /* kHz uV */
22 125000 975000
23 250000 1075000
24 500000 1200000
25 550000 1270000
26 600000 1350000
27 >;
28 clock-latency = <300000>; /* From legacy driver */
29 };
30 };
31
32 ocp@68000000 {
33 omap3_pmx_core2: pinmux@480025d8 {
34 compatible = "ti,omap3-padconf", "pinctrl-single";
35 reg = <0x480025d8 0x24>;
36 #address-cells = <1>;
37 #size-cells = <0>;
38 #pinctrl-cells = <1>;
39 #interrupt-cells = <1>;
40 interrupt-controller;
41 pinctrl-single,register-width = <16>;
42 pinctrl-single,function-mask = <0xff1f>;
43 };
44
45 isp: isp@480bc000 {
46 compatible = "ti,omap3-isp";
47 reg = <0x480bc000 0x12fc
48 0x480bd800 0x017c>;
49 interrupts = <24>;
50 iommus = <&mmu_isp>;
51 syscon = <&scm_conf 0x6c>;
52 ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>;
53 #clock-cells = <1>;
54 ports {
55 #address-cells = <1>;
56 #size-cells = <0>;
57 };
58 };
59
60 bandgap: bandgap@48002524 {
61 reg = <0x48002524 0x4>;
62 compatible = "ti,omap34xx-bandgap";
63 #thermal-sensor-cells = <0>;
64 };
65
66 target-module@480cb000 {
67 compatible = "ti,sysc-omap3430-sr", "ti,sysc";
68 ti,hwmods = "smartreflex_core";
69 reg = <0x480cb024 0x4>;
70 reg-names = "sysc";
71 ti,sysc-mask = <SYSC_OMAP2_CLOCKACTIVITY>;
72 clocks = <&sr2_fck>;
73 clock-names = "fck";
74 #address-cells = <1>;
75 #size-cells = <1>;
76 ranges = <0 0x480cb000 0x001000>;
77
78 smartreflex_core: smartreflex@0 {
79 compatible = "ti,omap3-smartreflex-core";
80 reg = <0 0x400>;
81 interrupts = <19>;
82 };
83 };
84
85 target-module@480c9000 {
86 compatible = "ti,sysc-omap3430-sr", "ti,sysc";
87 ti,hwmods = "smartreflex_mpu_iva";
88 reg = <0x480c9024 0x4>;
89 reg-names = "sysc";
90 ti,sysc-mask = <SYSC_OMAP2_CLOCKACTIVITY>;
91 clocks = <&sr1_fck>;
92 clock-names = "fck";
93 #address-cells = <1>;
94 #size-cells = <1>;
95 ranges = <0 0x480c9000 0x001000>;
96
97 smartreflex_mpu_iva: smartreflex@480c9000 {
98 compatible = "ti,omap3-smartreflex-mpu-iva";
99 reg = <0 0x400>;
100 interrupts = <18>;
101 };
102 };
103
104 /*
105 * On omap34xx the OCP registers do not seem to be accessible
106 * at all unlike on 36xx. Maybe SGX is permanently set to
107 * "OCP bypass mode", or maybe there is OCP_SYSCONFIG that is
108 * write-only at 0x50000e10. We detect SGX based on the SGX
109 * revision register instead of the unreadable OCP revision
110 * register. Also note that on early 34xx es1 revision there
111 * are also different clocks, but we do not have any dts users
112 * for it.
113 */
114 sgx_module: target-module@50000000 {
115 compatible = "ti,sysc-omap2", "ti,sysc";
116 reg = <0x50000014 0x4>;
117 reg-names = "rev";
118 clocks = <&sgx_fck>, <&sgx_ick>;
119 clock-names = "fck", "ick";
120 #address-cells = <1>;
121 #size-cells = <1>;
122 ranges = <0 0x50000000 0x4000>;
123
124 /*
125 * Closed source PowerVR driver, no child device
126 * binding or driver in mainline
127 */
128 };
129 };
130
131 thermal_zones: thermal-zones {
132 #include "omap3-cpu-thermal.dtsi"
133 };
134};
135
136&ssi {
137 status = "ok";
138
139 clocks = <&ssi_ssr_fck>,
140 <&ssi_sst_fck>,
141 <&ssi_ick>;
142 clock-names = "ssi_ssr_fck",
143 "ssi_sst_fck",
144 "ssi_ick";
145};
146
147/include/ "omap34xx-omap36xx-clocks.dtsi"
148/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
149/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
1/*
2 * Device Tree Source for OMAP34xx/OMAP35xx SoC
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/media/omap3-isp.h>
12
13#include "omap3.dtsi"
14
15/ {
16 cpus {
17 cpu@0 {
18 /* OMAP343x/OMAP35xx variants OPP1-5 */
19 operating-points = <
20 /* kHz uV */
21 125000 975000
22 250000 1075000
23 500000 1200000
24 550000 1270000
25 600000 1350000
26 >;
27 clock-latency = <300000>; /* From legacy driver */
28 };
29 };
30
31 ocp {
32 omap3_pmx_core2: pinmux@480025d8 {
33 compatible = "ti,omap3-padconf", "pinctrl-single";
34 reg = <0x480025d8 0x24>;
35 #address-cells = <1>;
36 #size-cells = <0>;
37 #interrupt-cells = <1>;
38 interrupt-controller;
39 pinctrl-single,register-width = <16>;
40 pinctrl-single,function-mask = <0xff1f>;
41 };
42
43 isp: isp@480bc000 {
44 compatible = "ti,omap3-isp";
45 reg = <0x480bc000 0x12fc
46 0x480bd800 0x017c>;
47 interrupts = <24>;
48 iommus = <&mmu_isp>;
49 syscon = <&scm_conf 0x6c>;
50 ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>;
51 #clock-cells = <1>;
52 ports {
53 #address-cells = <1>;
54 #size-cells = <0>;
55 };
56 };
57
58 bandgap {
59 reg = <0x48002524 0x4>;
60 compatible = "ti,omap34xx-bandgap";
61 #thermal-sensor-cells = <0>;
62 };
63 };
64};
65
66&ssi {
67 status = "ok";
68
69 clocks = <&ssi_ssr_fck>,
70 <&ssi_sst_fck>,
71 <&ssi_ick>;
72 clock-names = "ssi_ssr_fck",
73 "ssi_sst_fck",
74 "ssi_ick";
75};
76
77/include/ "omap34xx-omap36xx-clocks.dtsi"
78/include/ "omap36xx-omap3430es2plus-clocks.dtsi"
79/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"