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1// SPDX-License-Identifier: GPL-2.0 OR MIT
2/*
3 * Copyright 2015 Endless Mobile, Inc.
4 * Author: Carlo Caione <carlo@endlessm.com>
5 */
6
7#include <dt-bindings/clock/meson8b-clkc.h>
8#include <dt-bindings/gpio/meson8b-gpio.h>
9#include <dt-bindings/reset/amlogic,meson8b-reset.h>
10#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
11#include "meson.dtsi"
12
13/ {
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 cpu0: cpu@200 {
19 device_type = "cpu";
20 compatible = "arm,cortex-a5";
21 next-level-cache = <&L2>;
22 reg = <0x200>;
23 enable-method = "amlogic,meson8b-smp";
24 resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
25 operating-points-v2 = <&cpu_opp_table>;
26 clocks = <&clkc CLKID_CPUCLK>;
27 };
28
29 cpu1: cpu@201 {
30 device_type = "cpu";
31 compatible = "arm,cortex-a5";
32 next-level-cache = <&L2>;
33 reg = <0x201>;
34 enable-method = "amlogic,meson8b-smp";
35 resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
36 operating-points-v2 = <&cpu_opp_table>;
37 clocks = <&clkc CLKID_CPUCLK>;
38 };
39
40 cpu2: cpu@202 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a5";
43 next-level-cache = <&L2>;
44 reg = <0x202>;
45 enable-method = "amlogic,meson8b-smp";
46 resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
47 operating-points-v2 = <&cpu_opp_table>;
48 clocks = <&clkc CLKID_CPUCLK>;
49 };
50
51 cpu3: cpu@203 {
52 device_type = "cpu";
53 compatible = "arm,cortex-a5";
54 next-level-cache = <&L2>;
55 reg = <0x203>;
56 enable-method = "amlogic,meson8b-smp";
57 resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
58 operating-points-v2 = <&cpu_opp_table>;
59 clocks = <&clkc CLKID_CPUCLK>;
60 };
61 };
62
63 cpu_opp_table: opp-table {
64 compatible = "operating-points-v2";
65 opp-shared;
66
67 opp-96000000 {
68 opp-hz = /bits/ 64 <96000000>;
69 opp-microvolt = <860000>;
70 };
71 opp-192000000 {
72 opp-hz = /bits/ 64 <192000000>;
73 opp-microvolt = <860000>;
74 };
75 opp-312000000 {
76 opp-hz = /bits/ 64 <312000000>;
77 opp-microvolt = <860000>;
78 };
79 opp-408000000 {
80 opp-hz = /bits/ 64 <408000000>;
81 opp-microvolt = <860000>;
82 };
83 opp-504000000 {
84 opp-hz = /bits/ 64 <504000000>;
85 opp-microvolt = <860000>;
86 };
87 opp-600000000 {
88 opp-hz = /bits/ 64 <600000000>;
89 opp-microvolt = <860000>;
90 };
91 opp-720000000 {
92 opp-hz = /bits/ 64 <720000000>;
93 opp-microvolt = <860000>;
94 };
95 opp-816000000 {
96 opp-hz = /bits/ 64 <816000000>;
97 opp-microvolt = <900000>;
98 };
99 opp-1008000000 {
100 opp-hz = /bits/ 64 <1008000000>;
101 opp-microvolt = <1140000>;
102 };
103 opp-1200000000 {
104 opp-hz = /bits/ 64 <1200000000>;
105 opp-microvolt = <1140000>;
106 };
107 opp-1320000000 {
108 opp-hz = /bits/ 64 <1320000000>;
109 opp-microvolt = <1140000>;
110 };
111 opp-1488000000 {
112 opp-hz = /bits/ 64 <1488000000>;
113 opp-microvolt = <1140000>;
114 };
115 opp-1536000000 {
116 opp-hz = /bits/ 64 <1536000000>;
117 opp-microvolt = <1140000>;
118 };
119 };
120
121 gpu_opp_table: gpu-opp-table {
122 compatible = "operating-points-v2";
123
124 opp-255000000 {
125 opp-hz = /bits/ 64 <255000000>;
126 opp-microvolt = <1100000>;
127 };
128 opp-364300000 {
129 opp-hz = /bits/ 64 <364300000>;
130 opp-microvolt = <1100000>;
131 };
132 opp-425000000 {
133 opp-hz = /bits/ 64 <425000000>;
134 opp-microvolt = <1100000>;
135 };
136 opp-510000000 {
137 opp-hz = /bits/ 64 <510000000>;
138 opp-microvolt = <1100000>;
139 };
140 opp-637500000 {
141 opp-hz = /bits/ 64 <637500000>;
142 opp-microvolt = <1100000>;
143 turbo-mode;
144 };
145 };
146
147 pmu {
148 compatible = "arm,cortex-a5-pmu";
149 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
150 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
151 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
152 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
153 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
154 };
155
156 reserved-memory {
157 #address-cells = <1>;
158 #size-cells = <1>;
159 ranges;
160
161 /* 2 MiB reserved for Hardware ROM Firmware? */
162 hwrom@0 {
163 reg = <0x0 0x200000>;
164 no-map;
165 };
166 };
167
168 mmcbus: bus@c8000000 {
169 compatible = "simple-bus";
170 reg = <0xc8000000 0x8000>;
171 #address-cells = <1>;
172 #size-cells = <1>;
173 ranges = <0x0 0xc8000000 0x8000>;
174
175 dmcbus: bus@6000 {
176 compatible = "simple-bus";
177 reg = <0x6000 0x400>;
178 #address-cells = <1>;
179 #size-cells = <1>;
180 ranges = <0x0 0x6000 0x400>;
181
182 canvas: video-lut@48 {
183 compatible = "amlogic,meson8b-canvas",
184 "amlogic,canvas";
185 reg = <0x48 0x14>;
186 };
187 };
188 };
189
190 apb: bus@d0000000 {
191 compatible = "simple-bus";
192 reg = <0xd0000000 0x200000>;
193 #address-cells = <1>;
194 #size-cells = <1>;
195 ranges = <0x0 0xd0000000 0x200000>;
196
197 mali: gpu@c0000 {
198 compatible = "amlogic,meson8b-mali", "arm,mali-450";
199 reg = <0xc0000 0x40000>;
200 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
208 interrupt-names = "gp", "gpmmu", "pp", "pmu",
209 "pp0", "ppmmu0", "pp1", "ppmmu1";
210 resets = <&reset RESET_MALI>;
211 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
212 clock-names = "bus", "core";
213 operating-points-v2 = <&gpu_opp_table>;
214 };
215 };
216}; /* end of / */
217
218&aobus {
219 pmu: pmu@e0 {
220 compatible = "amlogic,meson8b-pmu", "syscon";
221 reg = <0xe0 0x18>;
222 };
223
224 pinctrl_aobus: pinctrl@84 {
225 compatible = "amlogic,meson8b-aobus-pinctrl";
226 reg = <0x84 0xc>;
227 #address-cells = <1>;
228 #size-cells = <1>;
229 ranges;
230
231 gpio_ao: ao-bank@14 {
232 reg = <0x14 0x4>,
233 <0x2c 0x4>,
234 <0x24 0x8>;
235 reg-names = "mux", "pull", "gpio";
236 gpio-controller;
237 #gpio-cells = <2>;
238 gpio-ranges = <&pinctrl_aobus 0 0 16>;
239 };
240
241 uart_ao_a_pins: uart_ao_a {
242 mux {
243 groups = "uart_tx_ao_a", "uart_rx_ao_a";
244 function = "uart_ao";
245 bias-disable;
246 };
247 };
248
249 ir_recv_pins: remote {
250 mux {
251 groups = "remote_input";
252 function = "remote";
253 bias-disable;
254 };
255 };
256 };
257};
258
259&cbus {
260 reset: reset-controller@4404 {
261 compatible = "amlogic,meson8b-reset";
262 reg = <0x4404 0x9c>;
263 #reset-cells = <1>;
264 };
265
266 analog_top: analog-top@81a8 {
267 compatible = "amlogic,meson8b-analog-top", "syscon";
268 reg = <0x81a8 0x14>;
269 };
270
271 pwm_ef: pwm@86c0 {
272 compatible = "amlogic,meson8b-pwm";
273 reg = <0x86c0 0x10>;
274 #pwm-cells = <3>;
275 status = "disabled";
276 };
277
278 clock-measure@8758 {
279 compatible = "amlogic,meson8b-clk-measure";
280 reg = <0x8758 0x1c>;
281 };
282
283 pinctrl_cbus: pinctrl@9880 {
284 compatible = "amlogic,meson8b-cbus-pinctrl";
285 reg = <0x9880 0x10>;
286 #address-cells = <1>;
287 #size-cells = <1>;
288 ranges;
289
290 gpio: banks@80b0 {
291 reg = <0x80b0 0x28>,
292 <0x80e8 0x18>,
293 <0x8120 0x18>,
294 <0x8030 0x38>;
295 reg-names = "mux", "pull", "pull-enable", "gpio";
296 gpio-controller;
297 #gpio-cells = <2>;
298 gpio-ranges = <&pinctrl_cbus 0 0 83>;
299 };
300
301 eth_rgmii_pins: eth-rgmii {
302 mux {
303 groups = "eth_tx_clk",
304 "eth_tx_en",
305 "eth_txd1_0",
306 "eth_txd0_0",
307 "eth_rx_clk",
308 "eth_rx_dv",
309 "eth_rxd1",
310 "eth_rxd0",
311 "eth_mdio_en",
312 "eth_mdc",
313 "eth_ref_clk",
314 "eth_txd2",
315 "eth_txd3",
316 "eth_rxd3",
317 "eth_rxd2";
318 function = "ethernet";
319 bias-disable;
320 };
321 };
322
323 eth_rmii_pins: eth-rmii {
324 mux {
325 groups = "eth_tx_en",
326 "eth_txd1_0",
327 "eth_txd0_0",
328 "eth_rx_clk",
329 "eth_rx_dv",
330 "eth_rxd1",
331 "eth_rxd0",
332 "eth_mdio_en",
333 "eth_mdc";
334 function = "ethernet";
335 bias-disable;
336 };
337 };
338
339 i2c_a_pins: i2c-a {
340 mux {
341 groups = "i2c_sda_a", "i2c_sck_a";
342 function = "i2c_a";
343 bias-disable;
344 };
345 };
346
347 sd_b_pins: sd-b {
348 mux {
349 groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
350 "sd_d3_b", "sd_clk_b", "sd_cmd_b";
351 function = "sd_b";
352 bias-disable;
353 };
354 };
355
356 pwm_c1_pins: pwm-c1 {
357 mux {
358 groups = "pwm_c1";
359 function = "pwm_c";
360 bias-disable;
361 };
362 };
363
364 pwm_d_pins: pwm-d {
365 mux {
366 groups = "pwm_d";
367 function = "pwm_d";
368 bias-disable;
369 };
370 };
371
372 uart_b0_pins: uart-b0 {
373 mux {
374 groups = "uart_tx_b0",
375 "uart_rx_b0";
376 function = "uart_b";
377 bias-disable;
378 };
379 };
380
381 uart_b0_cts_rts_pins: uart-b0-cts-rts {
382 mux {
383 groups = "uart_cts_b0",
384 "uart_rts_b0";
385 function = "uart_b";
386 bias-disable;
387 };
388 };
389 };
390};
391
392&ahb_sram {
393 smp-sram@1ff80 {
394 compatible = "amlogic,meson8b-smp-sram";
395 reg = <0x1ff80 0x8>;
396 };
397};
398
399
400&efuse {
401 compatible = "amlogic,meson8b-efuse";
402 clocks = <&clkc CLKID_EFUSE>;
403 clock-names = "core";
404
405 temperature_calib: calib@1f4 {
406 /* only the upper two bytes are relevant */
407 reg = <0x1f4 0x4>;
408 };
409};
410
411ðmac {
412 compatible = "amlogic,meson8b-dwmac", "snps,dwmac-3.70a", "snps,dwmac";
413
414 reg = <0xc9410000 0x10000
415 0xc1108140 0x4>;
416
417 clocks = <&clkc CLKID_ETH>,
418 <&clkc CLKID_MPLL2>,
419 <&clkc CLKID_MPLL2>;
420 clock-names = "stmmaceth", "clkin0", "clkin1";
421 rx-fifo-depth = <4096>;
422 tx-fifo-depth = <2048>;
423
424 resets = <&reset RESET_ETHERNET>;
425 reset-names = "stmmaceth";
426};
427
428&gpio_intc {
429 compatible = "amlogic,meson-gpio-intc",
430 "amlogic,meson8b-gpio-intc";
431 status = "okay";
432};
433
434&hhi {
435 clkc: clock-controller {
436 compatible = "amlogic,meson8-clkc";
437 #clock-cells = <1>;
438 #reset-cells = <1>;
439 };
440};
441
442&hwrng {
443 compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
444 clocks = <&clkc CLKID_RNG0>;
445 clock-names = "core";
446};
447
448&i2c_AO {
449 clocks = <&clkc CLKID_CLK81>;
450};
451
452&i2c_A {
453 clocks = <&clkc CLKID_I2C>;
454};
455
456&i2c_B {
457 clocks = <&clkc CLKID_I2C>;
458};
459
460&L2 {
461 arm,data-latency = <3 3 3>;
462 arm,tag-latency = <2 2 2>;
463 arm,filter-ranges = <0x100000 0xc0000000>;
464 prefetch-data = <1>;
465 prefetch-instr = <1>;
466 arm,shared-override;
467};
468
469&periph {
470 scu@0 {
471 compatible = "arm,cortex-a5-scu";
472 reg = <0x0 0x100>;
473 };
474
475 timer@200 {
476 compatible = "arm,cortex-a5-global-timer";
477 reg = <0x200 0x20>;
478 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
479 clocks = <&clkc CLKID_PERIPH>;
480
481 /*
482 * the arm_global_timer driver currently does not handle clock
483 * rate changes. Keep it disabled for now.
484 */
485 status = "disabled";
486 };
487
488 timer@600 {
489 compatible = "arm,cortex-a5-twd-timer";
490 reg = <0x600 0x20>;
491 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
492 clocks = <&clkc CLKID_PERIPH>;
493 };
494};
495
496&pwm_ab {
497 compatible = "amlogic,meson8b-pwm";
498};
499
500&pwm_cd {
501 compatible = "amlogic,meson8b-pwm";
502};
503
504&rtc {
505 compatible = "amlogic,meson8b-rtc";
506 resets = <&reset RESET_RTC>;
507};
508
509&saradc {
510 compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
511 clocks = <&clkc CLKID_XTAL>,
512 <&clkc CLKID_SAR_ADC>;
513 clock-names = "clkin", "core";
514 amlogic,hhi-sysctrl = <&hhi>;
515 nvmem-cells = <&temperature_calib>;
516 nvmem-cell-names = "temperature_calib";
517};
518
519&sdio {
520 compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio";
521 clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
522 clock-names = "core", "clkin";
523};
524
525&timer_abcde {
526 clocks = <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
527 clock-names = "xtal", "pclk";
528};
529
530&uart_AO {
531 compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
532 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
533 clock-names = "baud", "xtal", "pclk";
534};
535
536&uart_A {
537 compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
538 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>;
539 clock-names = "baud", "xtal", "pclk";
540};
541
542&uart_B {
543 compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
544 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>;
545 clock-names = "baud", "xtal", "pclk";
546};
547
548&uart_C {
549 compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
550 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>;
551 clock-names = "baud", "xtal", "pclk";
552};
553
554&usb0 {
555 compatible = "amlogic,meson8b-usb", "snps,dwc2";
556 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
557 clock-names = "otg";
558};
559
560&usb1 {
561 compatible = "amlogic,meson8b-usb", "snps,dwc2";
562 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
563 clock-names = "otg";
564};
565
566&usb0_phy {
567 compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
568 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
569 clock-names = "usb_general", "usb";
570 resets = <&reset RESET_USB_OTG>;
571};
572
573&usb1_phy {
574 compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
575 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
576 clock-names = "usb_general", "usb";
577 resets = <&reset RESET_USB_OTG>;
578};
579
580&wdt {
581 compatible = "amlogic,meson8b-wdt";
582};
1/*
2 * Copyright 2015 Endless Mobile, Inc.
3 * Author: Carlo Caione <carlo@endlessm.com>
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This library is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of the
13 * License, or (at your option) any later version.
14 *
15 * This library is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 *
23 * Or, alternatively,
24 *
25 * b) Permission is hereby granted, free of charge, to any person
26 * obtaining a copy of this software and associated documentation
27 * files (the "Software"), to deal in the Software without
28 * restriction, including without limitation the rights to use,
29 * copy, modify, merge, publish, distribute, sublicense, and/or
30 * sell copies of the Software, and to permit persons to whom the
31 * Software is furnished to do so, subject to the following
32 * conditions:
33 *
34 * The above copyright notice and this permission notice shall be
35 * included in all copies or substantial portions of the Software.
36 *
37 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
39 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
40 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
41 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
42 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 * OTHER DEALINGS IN THE SOFTWARE.
45 */
46
47#include <dt-bindings/clock/meson8b-clkc.h>
48#include <dt-bindings/gpio/meson8b-gpio.h>
49#include "skeleton.dtsi"
50
51/ {
52 interrupt-parent = <&gic>;
53
54 cpus {
55 #address-cells = <1>;
56 #size-cells = <0>;
57
58 cpu@200 {
59 device_type = "cpu";
60 compatible = "arm,cortex-a5";
61 next-level-cache = <&L2>;
62 reg = <0x200>;
63 };
64
65 cpu@201 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a5";
68 next-level-cache = <&L2>;
69 reg = <0x201>;
70 };
71
72 cpu@202 {
73 device_type = "cpu";
74 compatible = "arm,cortex-a5";
75 next-level-cache = <&L2>;
76 reg = <0x202>;
77 };
78
79 cpu@203 {
80 device_type = "cpu";
81 compatible = "arm,cortex-a5";
82 next-level-cache = <&L2>;
83 reg = <0x203>;
84 };
85 };
86
87 soc {
88 compatible = "simple-bus";
89 #address-cells = <1>;
90 #size-cells = <1>;
91 ranges;
92
93 L2: l2-cache-controller@c4200000 {
94 compatible = "arm,pl310-cache";
95 reg = <0xc4200000 0x1000>;
96 cache-unified;
97 cache-level = <2>;
98 };
99
100 gic: interrupt-controller@c4301000 {
101 compatible = "arm,cortex-a9-gic";
102 reg = <0xc4301000 0x1000>,
103 <0xc4300100 0x0100>;
104 interrupt-controller;
105 #interrupt-cells = <3>;
106 };
107
108 wdt: watchdog@c1109900 {
109 compatible = "amlogic,meson8b-wdt";
110 reg = <0xc1109900 0x8>;
111 interrupts = <0 0 1>;
112 };
113
114 timer@c1109940 {
115 compatible = "amlogic,meson6-timer";
116 reg = <0xc1109940 0x18>;
117 interrupts = <0 10 1>;
118 };
119
120 uart_AO: serial@c81004c0 {
121 compatible = "amlogic,meson-uart";
122 reg = <0xc81004c0 0x18>;
123 interrupts = <0 90 1>;
124 clocks = <&clkc CLKID_CLK81>;
125 status = "disabled";
126 };
127
128 uart_A: serial@c11084c0 {
129 compatible = "amlogic,meson-uart";
130 reg = <0xc11084c0 0x18>;
131 interrupts = <0 26 1>;
132 clocks = <&clkc CLKID_CLK81>;
133 status = "disabled";
134 };
135
136 uart_B: serial@c11084dc {
137 compatible = "amlogic,meson-uart";
138 reg = <0xc11084dc 0x18>;
139 interrupts = <0 75 1>;
140 clocks = <&clkc CLKID_CLK81>;
141 status = "disabled";
142 };
143
144 uart_C: serial@c1108700 {
145 compatible = "amlogic,meson-uart";
146 reg = <0xc1108700 0x18>;
147 interrupts = <0 93 1>;
148 clocks = <&clkc CLKID_CLK81>;
149 status = "disabled";
150 };
151
152 clkc: clock-controller@c1104000 {
153 #clock-cells = <1>;
154 compatible = "amlogic,meson8b-clkc";
155 reg = <0xc1108000 0x4>, <0xc1104000 0x460>;
156 };
157
158 pinctrl_cbus: pinctrl@c1109880 {
159 compatible = "amlogic,meson8b-cbus-pinctrl";
160 reg = <0xc1109880 0x10>;
161 #address-cells = <1>;
162 #size-cells = <1>;
163 ranges;
164
165 gpio: banks@c11080b0 {
166 reg = <0xc11080b0 0x28>,
167 <0xc11080e8 0x18>,
168 <0xc1108120 0x18>,
169 <0xc1108030 0x38>;
170 reg-names = "mux", "pull", "pull-enable", "gpio";
171 gpio-controller;
172 #gpio-cells = <2>;
173 };
174 };
175
176 pinctrl_aobus: pinctrl@c8100084 {
177 compatible = "amlogic,meson8b-aobus-pinctrl";
178 reg = <0xc8100084 0xc>;
179 #address-cells = <1>;
180 #size-cells = <1>;
181 ranges;
182
183 gpio_ao: ao-bank@c1108030 {
184 reg = <0xc8100014 0x4>,
185 <0xc810002c 0x4>,
186 <0xc8100024 0x8>;
187 reg-names = "mux", "pull", "gpio";
188 gpio-controller;
189 #gpio-cells = <2>;
190 };
191
192 uart_ao_a_pins: uart_ao_a {
193 mux {
194 groups = "uart_tx_ao_a", "uart_rx_ao_a";
195 function = "uart_ao";
196 };
197 };
198 };
199 };
200}; /* end of / */