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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2016 Christoph Fritz <chf.fritz@googlemail.com>
4 */
5
6/dts-v1/;
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/input.h>
10#include "imx6sx.dtsi"
11
12/ {
13 model = "Softing VIN|ING 2000";
14 compatible = "samtec,imx6sx-vining-2000", "fsl,imx6sx";
15
16 chosen {
17 stdout-path = &uart1;
18 };
19
20 memory@80000000 {
21 device_type = "memory";
22 reg = <0x80000000 0x40000000>;
23 };
24
25 reg_usb_otg1_vbus: regulator-usb_otg1_vbus {
26 compatible = "regulator-fixed";
27 regulator-name = "usb_otg1_vbus";
28 pinctrl-names = "default";
29 pinctrl-0 = <&pinctrl_usb_otg1>;
30 regulator-min-microvolt = <5000000>;
31 regulator-max-microvolt = <5000000>;
32 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
33 enable-active-high;
34 };
35
36 reg_peri_3v3: regulator-peri_3v3 {
37 compatible = "regulator-fixed";
38 regulator-name = "peri_3v3";
39 regulator-min-microvolt = <3300000>;
40 regulator-max-microvolt = <3300000>;
41 };
42
43 pwmleds {
44 compatible = "pwm-leds";
45
46 red {
47 label = "red";
48 max-brightness = <255>;
49 pwms = <&pwm6 0 50000>;
50 };
51
52 green {
53 label = "green";
54 max-brightness = <255>;
55 pwms = <&pwm2 0 50000>;
56 };
57
58 blue {
59 label = "blue";
60 max-brightness = <255>;
61 pwms = <&pwm1 0 50000>;
62 };
63 };
64};
65
66&adc1 {
67 vref-supply = <®_peri_3v3>;
68 status = "okay";
69};
70
71&cpu0 {
72 /*
73 * This board has a shared rail of reg_arm and reg_soc (supplied by
74 * sw1a_reg) which is modeled below, but still this module behaves
75 * unstable without higher voltages. Hence, set higher voltages here.
76 */
77 operating-points = <
78 /* kHz uV */
79 996000 1250000
80 792000 1175000
81 396000 1175000
82 198000 1175000
83 >;
84 fsl,soc-operating-points = <
85 /* ARM kHz SOC uV */
86 996000 1250000
87 792000 1175000
88 396000 1175000
89 198000 1175000
90 >;
91};
92
93&ecspi4 {
94 pinctrl-names = "default";
95 pinctrl-0 = <&pinctrl_ecspi4>;
96 cs-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>;
97 status = "okay";
98};
99
100&fec1 {
101 pinctrl-names = "default";
102 pinctrl-0 = <&pinctrl_enet1>;
103 phy-supply = <®_peri_3v3>;
104 phy-reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
105 phy-reset-duration = <5>;
106 phy-mode = "rmii";
107 phy-handle = <ðphy0>;
108 status = "okay";
109
110 mdio {
111 #address-cells = <1>;
112 #size-cells = <0>;
113
114 ethphy0: ethernet0-phy@0 {
115 reg = <0>;
116 max-speed = <100>;
117 interrupt-parent = <&gpio2>;
118 interrupts = <17 IRQ_TYPE_LEVEL_LOW>;
119 };
120 };
121};
122
123&fec2 {
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_enet2>;
126 phy-supply = <®_peri_3v3>;
127 phy-reset-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>;
128 phy-reset-duration = <5>;
129 phy-mode = "rmii";
130 phy-handle = <ðphy1>;
131 status = "okay";
132
133 mdio {
134 #address-cells = <1>;
135 #size-cells = <0>;
136
137 ethphy1: ethernet1-phy@0 {
138 reg = <0>;
139 max-speed = <100>;
140 interrupt-parent = <&gpio2>;
141 interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
142 };
143 };
144};
145
146&flexcan1 {
147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_flexcan1>;
149 status = "okay";
150};
151
152&flexcan2 {
153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_flexcan2>;
155 status = "okay";
156};
157
158&i2c1 {
159 clock-frequency = <100000>;
160 pinctrl-names = "default";
161 pinctrl-0 = <&pinctrl_i2c1>;
162 status = "okay";
163
164 proximity: sx9500@28 {
165 compatible = "semtech,sx9500";
166 reg = <0x28>;
167 pinctrl-names = "default";
168 pinctrl-0 = <&pinctrl_sx9500>;
169 interrupt-parent = <&gpio2>;
170 interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
171 reset-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
172 };
173
174 pmic: pfuze100@8 {
175 compatible = "fsl,pfuze200";
176 reg = <0x08>;
177
178 regulators {
179 sw1a_reg: sw1ab {
180 regulator-min-microvolt = <300000>;
181 regulator-max-microvolt = <1875000>;
182 regulator-boot-on;
183 regulator-always-on;
184 regulator-ramp-delay = <6250>;
185 };
186
187 sw2_reg: sw2 {
188 regulator-min-microvolt = <800000>;
189 regulator-max-microvolt = <3300000>;
190 regulator-boot-on;
191 regulator-always-on;
192 };
193
194 sw3a_reg: sw3a {
195 regulator-min-microvolt = <400000>;
196 regulator-max-microvolt = <1975000>;
197 regulator-boot-on;
198 regulator-always-on;
199 };
200
201 sw3b_reg: sw3b {
202 regulator-min-microvolt = <400000>;
203 regulator-max-microvolt = <1975000>;
204 regulator-boot-on;
205 regulator-always-on;
206 };
207
208 snvs_reg: vsnvs {
209 regulator-min-microvolt = <1000000>;
210 regulator-max-microvolt = <3000000>;
211 regulator-boot-on;
212 regulator-always-on;
213 };
214
215 vref_reg: vrefddr {
216 regulator-boot-on;
217 regulator-always-on;
218 };
219
220 vgen1_reg: vgen1 {
221 regulator-min-microvolt = <800000>;
222 regulator-max-microvolt = <1550000>;
223 regulator-always-on;
224 };
225
226 vgen2_reg: vgen2 {
227 regulator-min-microvolt = <800000>;
228 regulator-max-microvolt = <1550000>;
229 };
230
231 vgen3_reg: vgen3 {
232 regulator-min-microvolt = <1800000>;
233 regulator-max-microvolt = <3300000>;
234 regulator-always-on;
235 };
236
237 vgen4_reg: vgen4 {
238 regulator-min-microvolt = <1800000>;
239 regulator-max-microvolt = <3300000>;
240 regulator-always-on;
241 };
242
243 vgen5_reg: vgen5 {
244 regulator-min-microvolt = <1800000>;
245 regulator-max-microvolt = <3300000>;
246 regulator-always-on;
247 };
248
249 vgen6_reg: vgen6 {
250 regulator-min-microvolt = <1800000>;
251 regulator-max-microvolt = <3300000>;
252 regulator-always-on;
253 };
254 };
255 };
256};
257
258&i2c3 {
259 clock-frequency = <100000>;
260 pinctrl-names = "default";
261 pinctrl-0 = <&pinctrl_i2c3>;
262 status = "okay";
263};
264
265&iomuxc {
266 pinctrl-names = "default";
267 pinctrl-0 = <&pinctrl_gpios>;
268
269 pinctrl_ecspi4: ecspi4grp {
270 fsl,pins = <
271 MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x130b1
272 MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x130b1
273 MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x130b1
274 MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x30b0
275 >;
276 };
277
278 pinctrl_enet1: enet1grp {
279 fsl,pins = <
280 MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x30c1
281 MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x30c1
282 MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0f9
283 MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0f9
284 MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x30c1
285 MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0f9
286 MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4000a038
287 /* LAN8720 PHY Reset */
288 MX6SX_PAD_RGMII1_TD3__GPIO5_IO_9 0x10b0
289 /* MDIO */
290 MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0f9
291 MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0f9
292 /* IRQ from PHY */
293 MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x10b0
294 >;
295 };
296
297 pinctrl_enet2: enet2grp {
298 fsl,pins = <
299 MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x1b0b0
300 MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x1b0b0
301 MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x1b0b0
302 MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x1b0b0
303 MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x1b0b0
304 MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x1b0b0
305 MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4000a038
306 /* LAN8720 PHY Reset */
307 MX6SX_PAD_RGMII2_TD3__GPIO5_IO_21 0x10b0
308 /* MDIO */
309 MX6SX_PAD_ENET1_COL__ENET2_MDC 0xa0f9
310 MX6SX_PAD_ENET1_CRS__ENET2_MDIO 0xa0f9
311 /* IRQ from PHY */
312 MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x10b0
313 >;
314 };
315
316 pinctrl_flexcan1: flexcan1grp {
317 fsl,pins = <
318 MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x1b0b0
319 MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x1b0b0
320 >;
321 };
322
323 pinctrl_flexcan2: flexcan2grp {
324 fsl,pins = <
325 MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x1b0b0
326 MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x1b0b0
327 >;
328 };
329
330 pinctrl_gpios: gpiosgrp {
331 fsl,pins = <
332 /* reset external uC */
333 MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x10b0
334 /* IRQ from external uC */
335 MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x10b0
336 /* overcurrent detection */
337 MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x10b0
338 >;
339 };
340
341 pinctrl_i2c1: i2c1grp {
342 fsl,pins = <
343 MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
344 MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
345 >;
346 };
347
348 pinctrl_i2c3: i2c3grp {
349 fsl,pins = <
350 MX6SX_PAD_NAND_ALE__I2C3_SDA 0x4001b8b1
351 MX6SX_PAD_NAND_CLE__I2C3_SCL 0x4001b8b1
352 >;
353 };
354
355 pinctrl_pwm1: pwm1grp-1 {
356 fsl,pins = <
357 /* blue LED */
358 MX6SX_PAD_RGMII2_RD3__PWM1_OUT 0x1b0b1
359 >;
360 };
361
362 pinctrl_pwm2: pwm2grp-1 {
363 fsl,pins = <
364 /* green LED */
365 MX6SX_PAD_RGMII2_RD2__PWM2_OUT 0x1b0b1
366 >;
367 };
368
369 pinctrl_pwm6: pwm6grp-1 {
370 fsl,pins = <
371 /* red LED */
372 MX6SX_PAD_RGMII2_TD2__PWM6_OUT 0x1b0b1
373 >;
374 };
375
376 pinctrl_sx9500: sx9500grp {
377 fsl,pins = <
378 /* Reset */
379 MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x838
380 /* IRQ */
381 MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x70e0
382 >;
383 };
384
385 pinctrl_uart1: uart1grp {
386 fsl,pins = <
387 MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
388 MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
389 >;
390 };
391
392 pinctrl_uart2: uart2grp {
393 fsl,pins = <
394 MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1
395 MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1
396 >;
397 };
398
399 pinctrl_usb_otg1: usbotg1grp {
400 fsl,pins = <
401 MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0
402 >;
403 };
404
405 pinctrl_usb_otg1_id: usbotg1idgrp {
406 fsl,pins = <
407 MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
408 >;
409 };
410
411 pinctrl_usdhc2_50mhz: usdhc2grp-50mhz {
412 fsl,pins = <
413 MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
414 MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
415 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
416 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
417 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
418 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
419 MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x1b000
420 MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x10b0
421 >;
422 };
423
424 pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
425 fsl,pins = <
426 MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x100b9
427 MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x170b9
428 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x170b9
429 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x170b9
430 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x170b9
431 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x170b9
432 >;
433 };
434
435 pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
436 fsl,pins = <
437 MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x100f9
438 MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x170f9
439 MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x170f9
440 MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x170f9
441 MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x170f9
442 MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x170f9
443 >;
444 };
445
446 pinctrl_usdhc4_50mhz: usdhc4grp-50mhz {
447 fsl,pins = <
448 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
449 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
450 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
451 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
452 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
453 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
454 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059
455 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059
456 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059
457 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059
458 MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x17068
459 >;
460 };
461
462 pinctrl_usdhc4_100mhz: usdhc4-100mhz {
463 fsl,pins = <
464 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100b9
465 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170b9
466 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170b9
467 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170b9
468 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170b9
469 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170b9
470 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170b9
471 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170b9
472 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170b9
473 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170b9
474 >;
475 };
476
477 pinctrl_usdhc4_200mhz: usdhc4-200mhz {
478 fsl,pins = <
479 MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x100f9
480 MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x170f9
481 MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x170f9
482 MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x170f9
483 MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x170f9
484 MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x170f9
485 MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x170f9
486 MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x170f9
487 MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x170f9
488 MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x170f9
489 >;
490 };
491};
492
493&pwm1 {
494 pinctrl-names = "default";
495 pinctrl-0 = <&pinctrl_pwm1>;
496 status = "okay";
497};
498
499&pwm2 {
500 pinctrl-names = "default";
501 pinctrl-0 = <&pinctrl_pwm2>;
502 status = "okay";
503};
504
505&pwm6 {
506 pinctrl-names = "default";
507 pinctrl-0 = <&pinctrl_pwm6>;
508 status = "okay";
509};
510
511®_arm {
512 vin-supply = <&sw1a_reg>;
513};
514
515®_soc {
516 vin-supply = <&sw1a_reg>;
517};
518
519&snvs_poweroff {
520 status = "okay";
521};
522
523&uart1 {
524 pinctrl-names = "default";
525 pinctrl-0 = <&pinctrl_uart1>;
526 status = "okay";
527};
528
529&uart2 {
530 pinctrl-names = "default";
531 pinctrl-0 = <&pinctrl_uart2>;
532 status = "okay";
533};
534
535&usbotg1 {
536 vbus-supply = <®_usb_otg1_vbus>;
537 pinctrl-names = "default";
538 pinctrl-0 = <&pinctrl_usb_otg1_id>;
539 status = "okay";
540};
541
542&usbotg2 {
543 dr_mode = "host";
544 status = "okay";
545};
546
547&usdhc2 {
548 pinctrl-names = "default", "state_100mhz", "state_200mhz";
549 pinctrl-0 = <&pinctrl_usdhc2_50mhz>;
550 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
551 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
552 cd-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>;
553 keep-power-in-suspend;
554 status = "okay";
555};
556
557&usdhc4 {
558 /* hs200-mode is currently unsupported because Vccq is on 3.1V, but
559 * not on necessary 1.8V.
560 */
561 pinctrl-names = "default", "state_100mhz", "state_200mhz";
562 pinctrl-0 = <&pinctrl_usdhc4_50mhz>;
563 pinctrl-1 = <&pinctrl_usdhc4_100mhz>;
564 pinctrl-2 = <&pinctrl_usdhc4_200mhz>;
565 bus-width = <8>;
566 keep-power-in-suspend;
567 non-removable;
568 cap-mmc-hw-reset;
569 status = "okay";
570};