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1/*
2 * SAMSUNG EXYNOS5440 SoC device tree source
3 *
4 * Copyright (c) 2012 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <dt-bindings/clock/exynos5440.h>
13#include "skeleton.dtsi"
14
15/ {
16 compatible = "samsung,exynos5440", "samsung,exynos5";
17
18 interrupt-parent = <&gic>;
19
20 aliases {
21 serial0 = &serial_0;
22 serial1 = &serial_1;
23 spi0 = &spi_0;
24 tmuctrl0 = &tmuctrl_0;
25 tmuctrl1 = &tmuctrl_1;
26 tmuctrl2 = &tmuctrl_2;
27 };
28
29 clock: clock-controller@160000 {
30 compatible = "samsung,exynos5440-clock";
31 reg = <0x160000 0x1000>;
32 #clock-cells = <1>;
33 };
34
35 gic: interrupt-controller@2E0000 {
36 compatible = "arm,cortex-a15-gic";
37 #interrupt-cells = <3>;
38 interrupt-controller;
39 reg = <0x2E1000 0x1000>,
40 <0x2E2000 0x1000>,
41 <0x2E4000 0x2000>,
42 <0x2E6000 0x2000>;
43 interrupts = <1 9 0xf04>;
44 };
45
46 cpus {
47 #address-cells = <1>;
48 #size-cells = <0>;
49
50 cpu@0 {
51 device_type = "cpu";
52 compatible = "arm,cortex-a15";
53 reg = <0>;
54 };
55 cpu@1 {
56 device_type = "cpu";
57 compatible = "arm,cortex-a15";
58 reg = <1>;
59 };
60 cpu@2 {
61 device_type = "cpu";
62 compatible = "arm,cortex-a15";
63 reg = <2>;
64 };
65 cpu@3 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a15";
68 reg = <3>;
69 };
70 };
71
72 arm-pmu {
73 compatible = "arm,cortex-a15-pmu", "arm,cortex-a9-pmu";
74 interrupts = <0 52 4>,
75 <0 53 4>,
76 <0 54 4>,
77 <0 55 4>;
78 };
79
80 timer {
81 compatible = "arm,cortex-a15-timer",
82 "arm,armv7-timer";
83 interrupts = <1 13 0xf08>,
84 <1 14 0xf08>,
85 <1 11 0xf08>,
86 <1 10 0xf08>;
87 clock-frequency = <50000000>;
88 };
89
90 cpufreq@160000 {
91 compatible = "samsung,exynos5440-cpufreq";
92 reg = <0x160000 0x1000>;
93 interrupts = <0 57 0>;
94 operating-points = <
95 /* KHz uV */
96 1500000 1100000
97 1400000 1075000
98 1300000 1050000
99 1200000 1025000
100 1100000 1000000
101 1000000 975000
102 900000 950000
103 800000 925000
104 >;
105 };
106
107 serial_0: serial@B0000 {
108 compatible = "samsung,exynos4210-uart";
109 reg = <0xB0000 0x1000>;
110 interrupts = <0 2 0>;
111 clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
112 clock-names = "uart", "clk_uart_baud0";
113 };
114
115 serial_1: serial@C0000 {
116 compatible = "samsung,exynos4210-uart";
117 reg = <0xC0000 0x1000>;
118 interrupts = <0 3 0>;
119 clocks = <&clock CLK_B_125>, <&clock CLK_B_125>;
120 clock-names = "uart", "clk_uart_baud0";
121 };
122
123 spi_0: spi@D0000 {
124 compatible = "samsung,exynos5440-spi";
125 reg = <0xD0000 0x100>;
126 interrupts = <0 4 0>;
127 #address-cells = <1>;
128 #size-cells = <0>;
129 samsung,spi-src-clk = <0>;
130 num-cs = <1>;
131 clocks = <&clock CLK_B_125>, <&clock CLK_SPI_BAUD>;
132 clock-names = "spi", "spi_busclk0";
133 };
134
135 pin_ctrl: pinctrl {
136 compatible = "samsung,exynos5440-pinctrl";
137 reg = <0xE0000 0x1000>;
138 interrupts = <0 37 0>, <0 38 0>, <0 39 0>, <0 40 0>,
139 <0 41 0>, <0 42 0>, <0 43 0>, <0 44 0>;
140 interrupt-controller;
141 #interrupt-cells = <2>;
142 #gpio-cells = <2>;
143
144 fan: fan {
145 samsung,exynos5440-pin-function = <1>;
146 };
147
148 hdd_led0: hdd_led0 {
149 samsung,exynos5440-pin-function = <2>;
150 };
151
152 hdd_led1: hdd_led1 {
153 samsung,exynos5440-pin-function = <3>;
154 };
155
156 uart1: uart1 {
157 samsung,exynos5440-pin-function = <4>;
158 };
159 };
160
161 i2c@F0000 {
162 compatible = "samsung,exynos5440-i2c";
163 reg = <0xF0000 0x1000>;
164 interrupts = <0 5 0>;
165 #address-cells = <1>;
166 #size-cells = <0>;
167 clocks = <&clock CLK_B_125>;
168 clock-names = "i2c";
169 };
170
171 i2c@100000 {
172 compatible = "samsung,exynos5440-i2c";
173 reg = <0x100000 0x1000>;
174 interrupts = <0 6 0>;
175 #address-cells = <1>;
176 #size-cells = <0>;
177 clocks = <&clock CLK_B_125>;
178 clock-names = "i2c";
179 };
180
181 watchdog@110000 {
182 compatible = "samsung,s3c2410-wdt";
183 reg = <0x110000 0x1000>;
184 interrupts = <0 1 0>;
185 clocks = <&clock CLK_B_125>;
186 clock-names = "watchdog";
187 };
188
189 gmac: ethernet@00230000 {
190 compatible = "snps,dwmac-3.70a";
191 reg = <0x00230000 0x8000>;
192 interrupt-parent = <&gic>;
193 interrupts = <0 31 4>;
194 interrupt-names = "macirq";
195 phy-mode = "sgmii";
196 clocks = <&clock CLK_GMAC0>;
197 clock-names = "stmmaceth";
198 };
199
200 amba {
201 #address-cells = <1>;
202 #size-cells = <1>;
203 compatible = "simple-bus";
204 interrupt-parent = <&gic>;
205 ranges;
206 };
207
208 rtc {
209 compatible = "samsung,s3c6410-rtc";
210 reg = <0x130000 0x1000>;
211 interrupts = <0 17 0>, <0 16 0>;
212 clocks = <&clock CLK_B_125>;
213 clock-names = "rtc";
214 };
215
216 tmuctrl_0: tmuctrl@160118 {
217 compatible = "samsung,exynos5440-tmu";
218 reg = <0x160118 0x230>, <0x160368 0x10>;
219 interrupts = <0 58 0>;
220 clocks = <&clock CLK_B_125>;
221 clock-names = "tmu_apbif";
222 #include "exynos5440-tmu-sensor-conf.dtsi"
223 };
224
225 tmuctrl_1: tmuctrl@16011C {
226 compatible = "samsung,exynos5440-tmu";
227 reg = <0x16011C 0x230>, <0x160368 0x10>;
228 interrupts = <0 58 0>;
229 clocks = <&clock CLK_B_125>;
230 clock-names = "tmu_apbif";
231 #include "exynos5440-tmu-sensor-conf.dtsi"
232 };
233
234 tmuctrl_2: tmuctrl@160120 {
235 compatible = "samsung,exynos5440-tmu";
236 reg = <0x160120 0x230>, <0x160368 0x10>;
237 interrupts = <0 58 0>;
238 clocks = <&clock CLK_B_125>;
239 clock-names = "tmu_apbif";
240 #include "exynos5440-tmu-sensor-conf.dtsi"
241 };
242
243 thermal-zones {
244 cpu0_thermal: cpu0-thermal {
245 thermal-sensors = <&tmuctrl_0>;
246 #include "exynos5440-trip-points.dtsi"
247 };
248 cpu1_thermal: cpu1-thermal {
249 thermal-sensors = <&tmuctrl_1>;
250 #include "exynos5440-trip-points.dtsi"
251 };
252 cpu2_thermal: cpu2-thermal {
253 thermal-sensors = <&tmuctrl_2>;
254 #include "exynos5440-trip-points.dtsi"
255 };
256 };
257
258 sata@210000 {
259 compatible = "snps,exynos5440-ahci";
260 reg = <0x210000 0x10000>;
261 interrupts = <0 30 0>;
262 clocks = <&clock CLK_SATA>;
263 clock-names = "sata";
264 };
265
266 ohci@220000 {
267 compatible = "samsung,exynos5440-ohci";
268 reg = <0x220000 0x1000>;
269 interrupts = <0 29 0>;
270 clocks = <&clock CLK_USB>;
271 clock-names = "usbhost";
272 };
273
274 ehci@221000 {
275 compatible = "samsung,exynos5440-ehci";
276 reg = <0x221000 0x1000>;
277 interrupts = <0 29 0>;
278 clocks = <&clock CLK_USB>;
279 clock-names = "usbhost";
280 };
281
282 pcie_0: pcie@290000 {
283 compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
284 reg = <0x290000 0x1000
285 0x270000 0x1000
286 0x271000 0x40>;
287 interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
288 clocks = <&clock CLK_PR0_250_O>, <&clock CLK_PB0_250_O>;
289 clock-names = "pcie", "pcie_bus";
290 #address-cells = <3>;
291 #size-cells = <2>;
292 device_type = "pci";
293 ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */
294 0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
295 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
296 #interrupt-cells = <1>;
297 interrupt-map-mask = <0 0 0 0>;
298 interrupt-map = <0x0 0 &gic 53>;
299 num-lanes = <4>;
300 status = "disabled";
301 };
302
303 pcie_1: pcie@2a0000 {
304 compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
305 reg = <0x2a0000 0x1000
306 0x272000 0x1000
307 0x271040 0x40>;
308 interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
309 clocks = <&clock CLK_PR1_250_O>, <&clock CLK_PB0_250_O>;
310 clock-names = "pcie", "pcie_bus";
311 #address-cells = <3>;
312 #size-cells = <2>;
313 device_type = "pci";
314 ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */
315 0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
316 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
317 #interrupt-cells = <1>;
318 interrupt-map-mask = <0 0 0 0>;
319 interrupt-map = <0x0 0 &gic 56>;
320 num-lanes = <4>;
321 status = "disabled";
322 };
323};