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1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree file for Marvell RD-AXPWiFiAP.
4 *
5 * Note: this board is shipped with a new generation boot loader that
6 * remaps internal registers at 0xf1000000. Therefore, if earlyprintk
7 * is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option or the
8 * CONFIG_DEBUG_MVEBU_UART1_ALTERNATE option should be used.
9 *
10 * Copyright (C) 2013 Marvell
11 *
12 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 */
14
15/dts-v1/;
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/input/input.h>
18#include "armada-xp-mv78230.dtsi"
19
20/ {
21 model = "Marvell RD-AXPWiFiAP";
22 compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
23
24 chosen {
25 stdout-path = "serial0:115200n8";
26 };
27
28 memory@0 {
29 device_type = "memory";
30 reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */
31 };
32
33 soc {
34 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
35 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
36 MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
37 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
38
39 internal-regs {
40 /* UART0 */
41 serial@12000 {
42 status = "okay";
43 };
44
45 /* UART1 */
46 serial@12100 {
47 status = "okay";
48 };
49
50 sata@a0000 {
51 nr-ports = <1>;
52 status = "okay";
53 };
54
55 ethernet@70000 {
56 pinctrl-0 = <&ge0_rgmii_pins>;
57 pinctrl-names = "default";
58 status = "okay";
59 phy = <&phy0>;
60 phy-mode = "rgmii-id";
61 };
62 ethernet@74000 {
63 pinctrl-0 = <&ge1_rgmii_pins>;
64 pinctrl-names = "default";
65 status = "okay";
66 phy = <&phy1>;
67 phy-mode = "rgmii-id";
68 };
69 };
70 };
71
72 gpio_keys {
73 compatible = "gpio-keys";
74 #address-cells = <1>;
75 #size-cells = <0>;
76 pinctrl-0 = <&keys_pin>;
77 pinctrl-names = "default";
78
79 reset {
80 label = "Factory Reset Button";
81 linux,code = <KEY_SETUP>;
82 gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
83 };
84 };
85};
86
87&mdio {
88 phy0: ethernet-phy@0 {
89 reg = <0>;
90 };
91
92 phy1: ethernet-phy@1 {
93 reg = <1>;
94 };
95};
96
97&pciec {
98 status = "okay";
99
100 /* First mini-PCIe port */
101 pcie@1,0 {
102 /* Port 0, Lane 0 */
103 status = "okay";
104 };
105
106 /* Second mini-PCIe port */
107 pcie@2,0 {
108 /* Port 0, Lane 1 */
109 status = "okay";
110 };
111
112 /* Renesas uPD720202 USB 3.0 controller */
113 pcie@3,0 {
114 /* Port 0, Lane 3 */
115 status = "okay";
116 };
117};
118
119&pinctrl {
120 pinctrl-0 = <&phy_int_pin>;
121 pinctrl-names = "default";
122
123 keys_pin: keys-pin {
124 marvell,pins = "mpp33";
125 marvell,function = "gpio";
126 };
127
128 phy_int_pin: phy-int-pin {
129 marvell,pins = "mpp32";
130 marvell,function = "gpio";
131 };
132};
133
134&spi0 {
135 status = "okay";
136
137 spi-flash@0 {
138 #address-cells = <1>;
139 #size-cells = <1>;
140 compatible = "n25q128a13", "jedec,spi-nor";
141 reg = <0>; /* Chip select 0 */
142 spi-max-frequency = <108000000>;
143 };
144};
1/*
2 * Device Tree file for Marvell RD-AXPWiFiAP.
3 *
4 * Note: this board is shipped with a new generation boot loader that
5 * remaps internal registers at 0xf1000000. Therefore, if earlyprintk
6 * is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option or the
7 * CONFIG_DEBUG_MVEBU_UART1_ALTERNATE option should be used.
8 *
9 * Copyright (C) 2013 Marvell
10 *
11 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
12 *
13 * This file is dual-licensed: you can use it either under the terms
14 * of the GPL or the X11 license, at your option. Note that this dual
15 * licensing only applies to this file, and not this project as a
16 * whole.
17 *
18 * a) This file is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of the
21 * License, or (at your option) any later version.
22 *
23 * This file is distributed in the hope that it will be useful
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * Or, alternatively
29 *
30 * b) Permission is hereby granted, free of charge, to any person
31 * obtaining a copy of this software and associated documentation
32 * files (the "Software"), to deal in the Software without
33 * restriction, including without limitation the rights to use
34 * copy, modify, merge, publish, distribute, sublicense, and/or
35 * sell copies of the Software, and to permit persons to whom the
36 * Software is furnished to do so, subject to the following
37 * conditions:
38 *
39 * The above copyright notice and this permission notice shall be
40 * included in all copies or substantial portions of the Software.
41 *
42 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
43 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
44 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
45 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
46 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
47 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
48 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
49 * OTHER DEALINGS IN THE SOFTWARE.
50 */
51
52/dts-v1/;
53#include <dt-bindings/gpio/gpio.h>
54#include <dt-bindings/input/input.h>
55#include "armada-xp-mv78230.dtsi"
56
57/ {
58 model = "Marvell RD-AXPWiFiAP";
59 compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
60
61 chosen {
62 stdout-path = "serial0:115200n8";
63 };
64
65 memory {
66 device_type = "memory";
67 reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */
68 };
69
70 soc {
71 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
72 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
73 MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000
74 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>;
75
76 pcie-controller {
77 status = "okay";
78
79 /* First mini-PCIe port */
80 pcie@1,0 {
81 /* Port 0, Lane 0 */
82 status = "okay";
83 };
84
85 /* Second mini-PCIe port */
86 pcie@2,0 {
87 /* Port 0, Lane 1 */
88 status = "okay";
89 };
90
91 /* Renesas uPD720202 USB 3.0 controller */
92 pcie@3,0 {
93 /* Port 0, Lane 3 */
94 status = "okay";
95 };
96 };
97
98 internal-regs {
99 /* UART0 */
100 serial@12000 {
101 status = "okay";
102 };
103
104 /* UART1 */
105 serial@12100 {
106 status = "okay";
107 };
108
109 sata@a0000 {
110 nr-ports = <1>;
111 status = "okay";
112 };
113
114 mdio {
115 phy0: ethernet-phy@0 {
116 reg = <0>;
117 };
118
119 phy1: ethernet-phy@1 {
120 reg = <1>;
121 };
122 };
123
124 ethernet@70000 {
125 pinctrl-0 = <&ge0_rgmii_pins>;
126 pinctrl-names = "default";
127 status = "okay";
128 phy = <&phy0>;
129 phy-mode = "rgmii-id";
130 };
131 ethernet@74000 {
132 pinctrl-0 = <&ge1_rgmii_pins>;
133 pinctrl-names = "default";
134 status = "okay";
135 phy = <&phy1>;
136 phy-mode = "rgmii-id";
137 };
138
139 spi0: spi@10600 {
140 status = "okay";
141
142 spi-flash@0 {
143 #address-cells = <1>;
144 #size-cells = <1>;
145 compatible = "n25q128a13", "jedec,spi-nor";
146 reg = <0>; /* Chip select 0 */
147 spi-max-frequency = <108000000>;
148 };
149 };
150 };
151 };
152
153 gpio_keys {
154 compatible = "gpio-keys";
155 #address-cells = <1>;
156 #size-cells = <0>;
157 pinctrl-0 = <&keys_pin>;
158 pinctrl-names = "default";
159
160 button@1 {
161 label = "Factory Reset Button";
162 linux,code = <KEY_SETUP>;
163 gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
164 };
165 };
166};
167
168&pinctrl {
169 pinctrl-0 = <&phy_int_pin>;
170 pinctrl-names = "default";
171
172 keys_pin: keys-pin {
173 marvell,pins = "mpp33";
174 marvell,function = "gpio";
175 };
176
177 phy_int_pin: phy-int-pin {
178 marvell,pins = "mpp32";
179 marvell,function = "gpio";
180 };
181};