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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
4 */
5
6/*
7 * VScom OnRISC
8 * http://www.vscom.de
9 */
10
11/dts-v1/;
12
13#include "am335x-baltos.dtsi"
14#include "am335x-baltos-leds.dtsi"
15
16/ {
17 model = "OnRISC Baltos iR 5221";
18};
19
20&am33xx_pinmux {
21 tca6416_pins: pinmux_tca6416_pins {
22 pinctrl-single,pins = <
23 AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT_PULLUP, MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */
24 >;
25 };
26
27
28 dcan1_pins: pinmux_dcan1_pins {
29 pinctrl-single,pins = <
30 AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart0_ctsn.dcan1_tx_mux0 */
31 AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE2) /* uart0_rtsn.dcan1_rx_mux0 */
32 >;
33 };
34
35 uart1_pins: pinmux_uart1_pins {
36 pinctrl-single,pins = <
37 AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0)
38 AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_INPUT, MUX_MODE0)
39 AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0)
40 AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
41 AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */
42 AM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */
43 AM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */
44 AM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */
45 >;
46 };
47
48 uart2_pins: pinmux_uart2_pins {
49 pinctrl-single,pins = <
50 AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1) /* spi0_sclk.uart2_rxd_mux3 */
51 AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1) /* spi0_d0.uart2_txd_mux3 */
52 AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLDOWN, MUX_MODE2) /* i2c0_sda.uart2_ctsn_mux0 */
53 AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_OUTPUT_PULLDOWN, MUX_MODE2) /* i2c0_scl.uart2_rtsn_mux0 */
54 AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad12.gpio1[12] DTR */
55 AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad13.gpio1[13] DSR */
56 AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad14.gpio1[14] DCD */
57 AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7) /* gpmc_ad15.gpio1[15] RI */
58
59 AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_INPUT_PULLUP, MUX_MODE7) /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */
60 >;
61 };
62
63 mmc1_pins: pinmux_mmc1_pins {
64 pinctrl-single,pins = <
65 AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE7) /* MMC1 CD */
66 >;
67 };
68};
69
70&uart1 {
71 pinctrl-names = "default";
72 pinctrl-0 = <&uart1_pins>;
73 dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
74 dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
75 dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
76 rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;
77
78 status = "okay";
79};
80
81&uart2 {
82 pinctrl-names = "default";
83 pinctrl-0 = <&uart2_pins>;
84 dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
85 dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
86 dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
87 rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
88
89 status = "okay";
90};
91
92&i2c1 {
93 tca6416: gpio@20 {
94 compatible = "ti,tca6416";
95 reg = <0x20>;
96 gpio-controller;
97 #gpio-cells = <2>;
98 interrupt-parent = <&gpio0>;
99 interrupts = <20 IRQ_TYPE_EDGE_RISING>;
100 pinctrl-names = "default";
101 pinctrl-0 = <&tca6416_pins>;
102 };
103};
104
105&usb0_phy {
106 status = "okay";
107};
108
109&usb1_phy {
110 status = "okay";
111};
112
113&usb0 {
114 status = "okay";
115 dr_mode = "host";
116};
117
118&usb1 {
119 status = "okay";
120 dr_mode = "host";
121};
122
123&cpsw_emac0 {
124 phy-mode = "rmii";
125 dual_emac_res_vlan = <1>;
126 fixed-link {
127 speed = <100>;
128 full-duplex;
129 };
130};
131
132&cpsw_emac1 {
133 phy-mode = "rgmii-id";
134 dual_emac_res_vlan = <2>;
135 phy-handle = <&phy1>;
136};
137
138&dcan1 {
139 pinctrl-names = "default";
140 pinctrl-0 = <&dcan1_pins>;
141
142 status = "okay";
143};
144
145&mmc1 {
146 pinctrl-names = "default";
147 pinctrl-0 = <&mmc1_pins>;
148 cd-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>;
149};
1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * VScom OnRISC
11 * http://www.vscom.de
12 */
13
14/dts-v1/;
15
16#include "am33xx.dtsi"
17#include <dt-bindings/pwm/pwm.h>
18#include <dt-bindings/interrupt-controller/irq.h>
19
20/ {
21 model = "OnRISC Baltos iR 5221";
22 compatible = "vscom,onrisc", "ti,am33xx";
23
24 cpus {
25 cpu@0 {
26 cpu0-supply = <&vdd1_reg>;
27 };
28 };
29
30 memory {
31 device_type = "memory";
32 reg = <0x80000000 0x10000000>; /* 256 MB */
33 };
34
35 vbat: fixedregulator@0 {
36 compatible = "regulator-fixed";
37 regulator-name = "vbat";
38 regulator-min-microvolt = <5000000>;
39 regulator-max-microvolt = <5000000>;
40 regulator-boot-on;
41 };
42
43 wl12xx_vmmc: fixedregulator@2 {
44 pinctrl-names = "default";
45 pinctrl-0 = <&wl12xx_gpio>;
46 compatible = "regulator-fixed";
47 regulator-name = "vwl1271";
48 regulator-min-microvolt = <3300000>;
49 regulator-max-microvolt = <3300000>;
50 gpio = <&gpio3 8 0>;
51 startup-delay-us = <70000>;
52 enable-active-high;
53 };
54};
55
56&am33xx_pinmux {
57 mmc2_pins: pinmux_mmc2_pins {
58 pinctrl-single,pins = <
59 AM33XX_IOPAD(0x820, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad8.mmc1_dat0_mux0 */
60 AM33XX_IOPAD(0x824, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad9.mmc1_dat1_mux0 */
61 AM33XX_IOPAD(0x828, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad10.mmc1_dat2_mux0 */
62 AM33XX_IOPAD(0x82c, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_ad11.mmc1_dat3_mux0 */
63 AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk_mux0 */
64 AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd_mux0 */
65 AM33XX_IOPAD(0x9e4, PIN_INPUT_PULLUP | MUX_MODE7) /* emu0.gpio3[7] */
66 >;
67 };
68
69 wl12xx_gpio: pinmux_wl12xx_gpio {
70 pinctrl-single,pins = <
71 AM33XX_IOPAD(0x9e8, PIN_OUTPUT_PULLUP | MUX_MODE7) /* emu1.gpio3[8] */
72 >;
73 };
74
75 tps65910_pins: pinmux_tps65910_pins {
76 pinctrl-single,pins = <
77 AM33XX_IOPAD(0x878, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_ben1.gpio1[28] */
78 >;
79 };
80
81 tca6416_pins: pinmux_tca6416_pins {
82 pinctrl-single,pins = <
83 AM33XX_IOPAD(0x9b4, PIN_INPUT_PULLUP | MUX_MODE7) /* xdma_event_intr1.gpio0[20] tca6416 stuff */
84 >;
85 };
86
87 i2c1_pins: pinmux_i2c1_pins {
88 pinctrl-single,pins = <
89 AM33XX_IOPAD(0x958, PIN_INPUT | MUX_MODE2) /* spi0_d1.i2c1_sda_mux3 */
90 AM33XX_IOPAD(0x95c, PIN_INPUT | MUX_MODE2) /* spi0_cs0.i2c1_scl_mux3 */
91 >;
92 };
93
94 dcan1_pins: pinmux_dcan1_pins {
95 pinctrl-single,pins = <
96 AM33XX_IOPAD(0x968, PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.dcan1_tx_mux0 */
97 AM33XX_IOPAD(0x96c, PIN_INPUT | MUX_MODE2) /* uart0_rtsn.dcan1_rx_mux0 */
98 >;
99 };
100
101 uart0_pins: pinmux_uart0_pins {
102 pinctrl-single,pins = <
103 AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
104 AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
105 >;
106 };
107
108 uart1_pins: pinmux_uart1_pins {
109 pinctrl-single,pins = <
110 AM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0) /* uart1_rxd */
111 AM33XX_IOPAD(0x984, PIN_INPUT | MUX_MODE0) /* uart1_txd */
112 AM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE7) /* uart1_ctsn, INPUT | MODE0 */
113 AM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* uart1_rtsn, OUTPUT | MODE0 */
114 AM33XX_IOPAD(0x8e0, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.gpio2[22] DTR */
115 AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.gpio2[23] DSR */
116 AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.gpio2[24] DCD */
117 AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.gpio2[25] RI */
118 >;
119 };
120
121 uart2_pins: pinmux_uart2_pins {
122 pinctrl-single,pins = <
123 AM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd_mux3 */
124 AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd_mux3 */
125 AM33XX_IOPAD(0x988, PIN_INPUT_PULLDOWN | MUX_MODE7) /* i2c0_sda.uart2_ctsn_mux0 */
126 AM33XX_IOPAD(0x98c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* i2c0_scl.uart2_rtsn_mux0 */
127 AM33XX_IOPAD(0x830, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.gpio1[12] DTR */
128 AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.gpio1[13] DSR */
129 AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.gpio1[14] DCD */
130 AM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.gpio1[15] RI */
131
132 AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3[18], INPUT_PULLDOWN | MODE7 */
133 >;
134 };
135
136 cpsw_default: cpsw_default {
137 pinctrl-single,pins = <
138 /* Slave 1 */
139 AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
140 AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_tx_en.rmii1_txen */
141 AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
142 AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
143 AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
144 AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
145 AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_ref_clk.rmii1_refclk */
146
147
148 /* Slave 2 */
149 AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
150 AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */
151 AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
152 AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
153 AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
154 AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
155 AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
156 AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
157 AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
158 AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
159 AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
160 AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
161 >;
162 };
163
164 cpsw_sleep: cpsw_sleep {
165 pinctrl-single,pins = <
166 /* Slave 1 reset value */
167 AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
168 AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
169 AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
170 AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
171 AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
172 AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
173 AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
174
175 /* Slave 2 reset value*/
176 AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7)
177 AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7)
178 AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7)
179 AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7)
180 AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7)
181 AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7)
182 AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7)
183 AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7)
184 AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7)
185 AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)
186 AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)
187 AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)
188 >;
189 };
190
191 davinci_mdio_default: davinci_mdio_default {
192 pinctrl-single,pins = <
193 /* MDIO */
194 AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
195 AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
196 >;
197 };
198
199 davinci_mdio_sleep: davinci_mdio_sleep {
200 pinctrl-single,pins = <
201 /* MDIO reset value */
202 AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
203 AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
204 >;
205 };
206
207 nandflash_pins_s0: nandflash_pins_s0 {
208 pinctrl-single,pins = <
209 AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
210 AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
211 AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
212 AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
213 AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
214 AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
215 AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
216 AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
217 AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
218 AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
219 AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
220 AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
221 AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
222 AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
223 AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
224 >;
225 };
226};
227
228&elm {
229 status = "okay";
230};
231
232&gpmc {
233 pinctrl-names = "default";
234 pinctrl-0 = <&nandflash_pins_s0>;
235 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
236 status = "okay";
237
238 nand@0,0 {
239 compatible = "ti,omap2-nand";
240 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
241 interrupt-parent = <&gpmc>;
242 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
243 <1 IRQ_TYPE_NONE>; /* termcount */
244 nand-bus-width = <8>;
245 ti,nand-ecc-opt = "bch8";
246 ti,nand-xfer-type = "polled";
247
248 gpmc,device-nand = "true";
249 gpmc,device-width = <1>;
250 gpmc,sync-clk-ps = <0>;
251 gpmc,cs-on-ns = <0>;
252 gpmc,cs-rd-off-ns = <44>;
253 gpmc,cs-wr-off-ns = <44>;
254 gpmc,adv-on-ns = <6>;
255 gpmc,adv-rd-off-ns = <34>;
256 gpmc,adv-wr-off-ns = <44>;
257 gpmc,we-on-ns = <0>;
258 gpmc,we-off-ns = <40>;
259 gpmc,oe-on-ns = <0>;
260 gpmc,oe-off-ns = <54>;
261 gpmc,access-ns = <64>;
262 gpmc,rd-cycle-ns = <82>;
263 gpmc,wr-cycle-ns = <82>;
264 gpmc,bus-turnaround-ns = <0>;
265 gpmc,cycle2cycle-delay-ns = <0>;
266 gpmc,clk-activation-ns = <0>;
267 gpmc,wr-access-ns = <40>;
268 gpmc,wr-data-mux-bus-ns = <0>;
269
270 #address-cells = <1>;
271 #size-cells = <1>;
272 elm_id = <&elm>;
273 };
274};
275
276&uart0 {
277 pinctrl-names = "default";
278 pinctrl-0 = <&uart0_pins>;
279
280 status = "okay";
281};
282
283&uart1 {
284 pinctrl-names = "default";
285 pinctrl-0 = <&uart1_pins>;
286 dtr-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
287 dsr-gpios = <&gpio2 23 GPIO_ACTIVE_LOW>;
288 dcd-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>;
289 rng-gpios = <&gpio2 25 GPIO_ACTIVE_LOW>;
290 cts-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
291 rts-gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
292
293 status = "okay";
294};
295
296&uart2 {
297 pinctrl-names = "default";
298 pinctrl-0 = <&uart2_pins>;
299 dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
300 dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
301 dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
302 rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
303 cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
304 rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
305
306 status = "okay";
307};
308
309&i2c1 {
310 pinctrl-names = "default";
311 pinctrl-0 = <&i2c1_pins>;
312
313 status = "okay";
314 clock-frequency = <400000>;
315
316 tps: tps@2d {
317 reg = <0x2d>;
318 gpio-controller;
319 #gpio-cells = <2>;
320 interrupt-parent = <&gpio1>;
321 interrupts = <28 GPIO_ACTIVE_LOW>;
322 pinctrl-names = "default";
323 pinctrl-0 = <&tps65910_pins>;
324 };
325
326 at24@50 {
327 compatible = "at24,24c02";
328 pagesize = <8>;
329 reg = <0x50>;
330 };
331
332 tca6416: gpio@20 {
333 compatible = "ti,tca6416";
334 reg = <0x20>;
335 gpio-controller;
336 #gpio-cells = <2>;
337 interrupt-parent = <&gpio0>;
338 interrupts = <20 GPIO_ACTIVE_LOW>;
339 pinctrl-names = "default";
340 pinctrl-0 = <&tca6416_pins>;
341 };
342};
343
344&usb {
345 status = "okay";
346};
347
348&usb_ctrl_mod {
349 status = "okay";
350};
351
352&usb0_phy {
353 status = "okay";
354};
355
356&usb1_phy {
357 status = "okay";
358};
359
360&usb0 {
361 status = "okay";
362 dr_mode = "host";
363};
364
365&usb1 {
366 status = "okay";
367 dr_mode = "otg";
368};
369
370&cppi41dma {
371 status = "okay";
372};
373
374#include "tps65910.dtsi"
375
376&tps {
377 vcc1-supply = <&vbat>;
378 vcc2-supply = <&vbat>;
379 vcc3-supply = <&vbat>;
380 vcc4-supply = <&vbat>;
381 vcc5-supply = <&vbat>;
382 vcc6-supply = <&vbat>;
383 vcc7-supply = <&vbat>;
384 vccio-supply = <&vbat>;
385
386 ti,en-ck32k-xtal = <1>;
387
388 regulators {
389 vrtc_reg: regulator@0 {
390 regulator-always-on;
391 };
392
393 vio_reg: regulator@1 {
394 regulator-always-on;
395 };
396
397 vdd1_reg: regulator@2 {
398 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
399 regulator-name = "vdd_mpu";
400 regulator-min-microvolt = <912500>;
401 regulator-max-microvolt = <1312500>;
402 regulator-boot-on;
403 regulator-always-on;
404 };
405
406 vdd2_reg: regulator@3 {
407 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
408 regulator-name = "vdd_core";
409 regulator-min-microvolt = <912500>;
410 regulator-max-microvolt = <1150000>;
411 regulator-boot-on;
412 regulator-always-on;
413 };
414
415 vdd3_reg: regulator@4 {
416 regulator-always-on;
417 };
418
419 vdig1_reg: regulator@5 {
420 regulator-always-on;
421 };
422
423 vdig2_reg: regulator@6 {
424 regulator-always-on;
425 };
426
427 vpll_reg: regulator@7 {
428 regulator-always-on;
429 };
430
431 vdac_reg: regulator@8 {
432 regulator-always-on;
433 };
434
435 vaux1_reg: regulator@9 {
436 regulator-always-on;
437 };
438
439 vaux2_reg: regulator@10 {
440 regulator-always-on;
441 };
442
443 vaux33_reg: regulator@11 {
444 regulator-always-on;
445 };
446
447 vmmc_reg: regulator@12 {
448 regulator-min-microvolt = <1800000>;
449 regulator-max-microvolt = <3300000>;
450 regulator-always-on;
451 };
452 };
453};
454
455&mac {
456 pinctrl-names = "default", "sleep";
457 pinctrl-0 = <&cpsw_default>;
458 pinctrl-1 = <&cpsw_sleep>;
459 dual_emac = <1>;
460
461 status = "okay";
462};
463
464&davinci_mdio {
465 pinctrl-names = "default", "sleep";
466 pinctrl-0 = <&davinci_mdio_default>;
467 pinctrl-1 = <&davinci_mdio_sleep>;
468
469 status = "okay";
470};
471
472&cpsw_emac0 {
473 phy-mode = "rmii";
474 dual_emac_res_vlan = <1>;
475 fixed-link {
476 speed = <100>;
477 full-duplex;
478 };
479};
480
481&cpsw_emac1 {
482 phy_id = <&davinci_mdio>, <7>;
483 phy-mode = "rgmii-txid";
484 dual_emac_res_vlan = <2>;
485};
486
487&phy_sel {
488 rmii-clock-ext = <1>;
489};
490
491&mmc1 {
492 vmmc-supply = <&vmmc_reg>;
493 status = "okay";
494};
495
496&mmc2 {
497 status = "okay";
498 vmmc-supply = <&wl12xx_vmmc>;
499 ti,non-removable;
500 bus-width = <4>;
501 cap-power-off-card;
502 pinctrl-names = "default";
503 pinctrl-0 = <&mmc2_pins>;
504
505 #address-cells = <1>;
506 #size-cells = <0>;
507 wlcore: wlcore@2 {
508 compatible = "ti,wl1835";
509 reg = <2>;
510 interrupt-parent = <&gpio3>;
511 interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
512 };
513};
514
515&sham {
516 status = "okay";
517};
518
519&aes {
520 status = "okay";
521};
522
523&gpio0 {
524 ti,no-reset-on-init;
525};
526
527&dcan1 {
528 pinctrl-names = "default";
529 pinctrl-0 = <&dcan1_pins>;
530
531 status = "okay";
532};