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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
4 *
5 * Authors: Shlomi Gridish <gridish@freescale.com>
6 * Li Yang <leoli@freescale.com>
7 *
8 * Description:
9 * QE IC external definitions and structure.
10 */
11#ifndef _ASM_POWERPC_QE_IC_H
12#define _ASM_POWERPC_QE_IC_H
13
14#include <linux/irq.h>
15
16struct device_node;
17struct qe_ic;
18
19#define NUM_OF_QE_IC_GROUPS 6
20
21/* Flags when we init the QE IC */
22#define QE_IC_SPREADMODE_GRP_W 0x00000001
23#define QE_IC_SPREADMODE_GRP_X 0x00000002
24#define QE_IC_SPREADMODE_GRP_Y 0x00000004
25#define QE_IC_SPREADMODE_GRP_Z 0x00000008
26#define QE_IC_SPREADMODE_GRP_RISCA 0x00000010
27#define QE_IC_SPREADMODE_GRP_RISCB 0x00000020
28
29#define QE_IC_LOW_SIGNAL 0x00000100
30#define QE_IC_HIGH_SIGNAL 0x00000200
31
32#define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH 0x00001000
33#define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH 0x00002000
34#define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH 0x00004000
35#define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH 0x00008000
36#define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH 0x00010000
37#define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH 0x00020000
38#define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH 0x00040000
39#define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH 0x00080000
40#define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH 0x00100000
41#define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH 0x00200000
42#define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH 0x00400000
43#define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH 0x00800000
44#define QE_IC_GRP_W_DEST_SIGNAL_SHIFT (12)
45
46/* QE interrupt sources groups */
47enum qe_ic_grp_id {
48 QE_IC_GRP_W = 0, /* QE interrupt controller group W */
49 QE_IC_GRP_X, /* QE interrupt controller group X */
50 QE_IC_GRP_Y, /* QE interrupt controller group Y */
51 QE_IC_GRP_Z, /* QE interrupt controller group Z */
52 QE_IC_GRP_RISCA, /* QE interrupt controller RISC group A */
53 QE_IC_GRP_RISCB /* QE interrupt controller RISC group B */
54};
55
56#ifdef CONFIG_QUICC_ENGINE
57void qe_ic_init(struct device_node *node, unsigned int flags,
58 void (*low_handler)(struct irq_desc *desc),
59 void (*high_handler)(struct irq_desc *desc));
60unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic);
61unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic);
62#else
63static inline void qe_ic_init(struct device_node *node, unsigned int flags,
64 void (*low_handler)(struct irq_desc *desc),
65 void (*high_handler)(struct irq_desc *desc))
66{}
67static inline unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
68{ return 0; }
69static inline unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
70{ return 0; }
71#endif /* CONFIG_QUICC_ENGINE */
72
73void qe_ic_set_highest_priority(unsigned int virq, int high);
74int qe_ic_set_priority(unsigned int virq, unsigned int priority);
75int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);
76
77static inline void qe_ic_cascade_low_ipic(struct irq_desc *desc)
78{
79 struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
80 unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
81
82 if (cascade_irq != NO_IRQ)
83 generic_handle_irq(cascade_irq);
84}
85
86static inline void qe_ic_cascade_high_ipic(struct irq_desc *desc)
87{
88 struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
89 unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
90
91 if (cascade_irq != NO_IRQ)
92 generic_handle_irq(cascade_irq);
93}
94
95static inline void qe_ic_cascade_low_mpic(struct irq_desc *desc)
96{
97 struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
98 unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
99 struct irq_chip *chip = irq_desc_get_chip(desc);
100
101 if (cascade_irq != NO_IRQ)
102 generic_handle_irq(cascade_irq);
103
104 chip->irq_eoi(&desc->irq_data);
105}
106
107static inline void qe_ic_cascade_high_mpic(struct irq_desc *desc)
108{
109 struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
110 unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
111 struct irq_chip *chip = irq_desc_get_chip(desc);
112
113 if (cascade_irq != NO_IRQ)
114 generic_handle_irq(cascade_irq);
115
116 chip->irq_eoi(&desc->irq_data);
117}
118
119static inline void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
120{
121 struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
122 unsigned int cascade_irq;
123 struct irq_chip *chip = irq_desc_get_chip(desc);
124
125 cascade_irq = qe_ic_get_high_irq(qe_ic);
126 if (cascade_irq == NO_IRQ)
127 cascade_irq = qe_ic_get_low_irq(qe_ic);
128
129 if (cascade_irq != NO_IRQ)
130 generic_handle_irq(cascade_irq);
131
132 chip->irq_eoi(&desc->irq_data);
133}
134
135#endif /* _ASM_POWERPC_QE_IC_H */
1/*
2 * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
3 *
4 * Authors: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
6 *
7 * Description:
8 * QE IC external definitions and structure.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15#ifndef _ASM_POWERPC_QE_IC_H
16#define _ASM_POWERPC_QE_IC_H
17
18#include <linux/irq.h>
19
20struct device_node;
21struct qe_ic;
22
23#define NUM_OF_QE_IC_GROUPS 6
24
25/* Flags when we init the QE IC */
26#define QE_IC_SPREADMODE_GRP_W 0x00000001
27#define QE_IC_SPREADMODE_GRP_X 0x00000002
28#define QE_IC_SPREADMODE_GRP_Y 0x00000004
29#define QE_IC_SPREADMODE_GRP_Z 0x00000008
30#define QE_IC_SPREADMODE_GRP_RISCA 0x00000010
31#define QE_IC_SPREADMODE_GRP_RISCB 0x00000020
32
33#define QE_IC_LOW_SIGNAL 0x00000100
34#define QE_IC_HIGH_SIGNAL 0x00000200
35
36#define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH 0x00001000
37#define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH 0x00002000
38#define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH 0x00004000
39#define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH 0x00008000
40#define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH 0x00010000
41#define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH 0x00020000
42#define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH 0x00040000
43#define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH 0x00080000
44#define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH 0x00100000
45#define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH 0x00200000
46#define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH 0x00400000
47#define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH 0x00800000
48#define QE_IC_GRP_W_DEST_SIGNAL_SHIFT (12)
49
50/* QE interrupt sources groups */
51enum qe_ic_grp_id {
52 QE_IC_GRP_W = 0, /* QE interrupt controller group W */
53 QE_IC_GRP_X, /* QE interrupt controller group X */
54 QE_IC_GRP_Y, /* QE interrupt controller group Y */
55 QE_IC_GRP_Z, /* QE interrupt controller group Z */
56 QE_IC_GRP_RISCA, /* QE interrupt controller RISC group A */
57 QE_IC_GRP_RISCB /* QE interrupt controller RISC group B */
58};
59
60#ifdef CONFIG_QUICC_ENGINE
61void qe_ic_init(struct device_node *node, unsigned int flags,
62 void (*low_handler)(struct irq_desc *desc),
63 void (*high_handler)(struct irq_desc *desc));
64unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic);
65unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic);
66#else
67static inline void qe_ic_init(struct device_node *node, unsigned int flags,
68 void (*low_handler)(struct irq_desc *desc),
69 void (*high_handler)(struct irq_desc *desc))
70{}
71static inline unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
72{ return 0; }
73static inline unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
74{ return 0; }
75#endif /* CONFIG_QUICC_ENGINE */
76
77void qe_ic_set_highest_priority(unsigned int virq, int high);
78int qe_ic_set_priority(unsigned int virq, unsigned int priority);
79int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);
80
81static inline void qe_ic_cascade_low_ipic(struct irq_desc *desc)
82{
83 struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
84 unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
85
86 if (cascade_irq != NO_IRQ)
87 generic_handle_irq(cascade_irq);
88}
89
90static inline void qe_ic_cascade_high_ipic(struct irq_desc *desc)
91{
92 struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
93 unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
94
95 if (cascade_irq != NO_IRQ)
96 generic_handle_irq(cascade_irq);
97}
98
99static inline void qe_ic_cascade_low_mpic(struct irq_desc *desc)
100{
101 struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
102 unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
103 struct irq_chip *chip = irq_desc_get_chip(desc);
104
105 if (cascade_irq != NO_IRQ)
106 generic_handle_irq(cascade_irq);
107
108 chip->irq_eoi(&desc->irq_data);
109}
110
111static inline void qe_ic_cascade_high_mpic(struct irq_desc *desc)
112{
113 struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
114 unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
115 struct irq_chip *chip = irq_desc_get_chip(desc);
116
117 if (cascade_irq != NO_IRQ)
118 generic_handle_irq(cascade_irq);
119
120 chip->irq_eoi(&desc->irq_data);
121}
122
123static inline void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
124{
125 struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
126 unsigned int cascade_irq;
127 struct irq_chip *chip = irq_desc_get_chip(desc);
128
129 cascade_irq = qe_ic_get_high_irq(qe_ic);
130 if (cascade_irq == NO_IRQ)
131 cascade_irq = qe_ic_get_low_irq(qe_ic);
132
133 if (cascade_irq != NO_IRQ)
134 generic_handle_irq(cascade_irq);
135
136 chip->irq_eoi(&desc->irq_data);
137}
138
139#endif /* _ASM_POWERPC_QE_IC_H */