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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * drivers/net/phy/micrel.c
4 *
5 * Driver for Micrel PHYs
6 *
7 * Author: David J. Choi
8 *
9 * Copyright (c) 2010-2013 Micrel, Inc.
10 * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
11 *
12 * Support : Micrel Phys:
13 * Giga phys: ksz9021, ksz9031, ksz9131
14 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
15 * ksz8021, ksz8031, ksz8051,
16 * ksz8081, ksz8091,
17 * ksz8061,
18 * Switch : ksz8873, ksz886x
19 * ksz9477
20 */
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/phy.h>
25#include <linux/micrel_phy.h>
26#include <linux/of.h>
27#include <linux/clk.h>
28
29/* Operation Mode Strap Override */
30#define MII_KSZPHY_OMSO 0x16
31#define KSZPHY_OMSO_FACTORY_TEST BIT(15)
32#define KSZPHY_OMSO_B_CAST_OFF BIT(9)
33#define KSZPHY_OMSO_NAND_TREE_ON BIT(5)
34#define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
35#define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
36
37/* general Interrupt control/status reg in vendor specific block. */
38#define MII_KSZPHY_INTCS 0x1B
39#define KSZPHY_INTCS_JABBER BIT(15)
40#define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
41#define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
42#define KSZPHY_INTCS_PARELLEL BIT(12)
43#define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
44#define KSZPHY_INTCS_LINK_DOWN BIT(10)
45#define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
46#define KSZPHY_INTCS_LINK_UP BIT(8)
47#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
48 KSZPHY_INTCS_LINK_DOWN)
49
50/* PHY Control 1 */
51#define MII_KSZPHY_CTRL_1 0x1e
52
53/* PHY Control 2 / PHY Control (if no PHY Control 1) */
54#define MII_KSZPHY_CTRL_2 0x1f
55#define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
56/* bitmap of PHY register to set interrupt mode */
57#define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
58#define KSZPHY_RMII_REF_CLK_SEL BIT(7)
59
60/* Write/read to/from extended registers */
61#define MII_KSZPHY_EXTREG 0x0b
62#define KSZPHY_EXTREG_WRITE 0x8000
63
64#define MII_KSZPHY_EXTREG_WRITE 0x0c
65#define MII_KSZPHY_EXTREG_READ 0x0d
66
67/* Extended registers */
68#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
69#define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
70#define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
71
72#define PS_TO_REG 200
73
74struct kszphy_hw_stat {
75 const char *string;
76 u8 reg;
77 u8 bits;
78};
79
80static struct kszphy_hw_stat kszphy_hw_stats[] = {
81 { "phy_receive_errors", 21, 16},
82 { "phy_idle_errors", 10, 8 },
83};
84
85struct kszphy_type {
86 u32 led_mode_reg;
87 u16 interrupt_level_mask;
88 bool has_broadcast_disable;
89 bool has_nand_tree_disable;
90 bool has_rmii_ref_clk_sel;
91};
92
93struct kszphy_priv {
94 const struct kszphy_type *type;
95 int led_mode;
96 bool rmii_ref_clk_sel;
97 bool rmii_ref_clk_sel_val;
98 u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
99};
100
101static const struct kszphy_type ksz8021_type = {
102 .led_mode_reg = MII_KSZPHY_CTRL_2,
103 .has_broadcast_disable = true,
104 .has_nand_tree_disable = true,
105 .has_rmii_ref_clk_sel = true,
106};
107
108static const struct kszphy_type ksz8041_type = {
109 .led_mode_reg = MII_KSZPHY_CTRL_1,
110};
111
112static const struct kszphy_type ksz8051_type = {
113 .led_mode_reg = MII_KSZPHY_CTRL_2,
114 .has_nand_tree_disable = true,
115};
116
117static const struct kszphy_type ksz8081_type = {
118 .led_mode_reg = MII_KSZPHY_CTRL_2,
119 .has_broadcast_disable = true,
120 .has_nand_tree_disable = true,
121 .has_rmii_ref_clk_sel = true,
122};
123
124static const struct kszphy_type ks8737_type = {
125 .interrupt_level_mask = BIT(14),
126};
127
128static const struct kszphy_type ksz9021_type = {
129 .interrupt_level_mask = BIT(14),
130};
131
132static int kszphy_extended_write(struct phy_device *phydev,
133 u32 regnum, u16 val)
134{
135 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
136 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
137}
138
139static int kszphy_extended_read(struct phy_device *phydev,
140 u32 regnum)
141{
142 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
143 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
144}
145
146static int kszphy_ack_interrupt(struct phy_device *phydev)
147{
148 /* bit[7..0] int status, which is a read and clear register. */
149 int rc;
150
151 rc = phy_read(phydev, MII_KSZPHY_INTCS);
152
153 return (rc < 0) ? rc : 0;
154}
155
156static int kszphy_config_intr(struct phy_device *phydev)
157{
158 const struct kszphy_type *type = phydev->drv->driver_data;
159 int temp;
160 u16 mask;
161
162 if (type && type->interrupt_level_mask)
163 mask = type->interrupt_level_mask;
164 else
165 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
166
167 /* set the interrupt pin active low */
168 temp = phy_read(phydev, MII_KSZPHY_CTRL);
169 if (temp < 0)
170 return temp;
171 temp &= ~mask;
172 phy_write(phydev, MII_KSZPHY_CTRL, temp);
173
174 /* enable / disable interrupts */
175 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
176 temp = KSZPHY_INTCS_ALL;
177 else
178 temp = 0;
179
180 return phy_write(phydev, MII_KSZPHY_INTCS, temp);
181}
182
183static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
184{
185 int ctrl;
186
187 ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
188 if (ctrl < 0)
189 return ctrl;
190
191 if (val)
192 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
193 else
194 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
195
196 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
197}
198
199static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
200{
201 int rc, temp, shift;
202
203 switch (reg) {
204 case MII_KSZPHY_CTRL_1:
205 shift = 14;
206 break;
207 case MII_KSZPHY_CTRL_2:
208 shift = 4;
209 break;
210 default:
211 return -EINVAL;
212 }
213
214 temp = phy_read(phydev, reg);
215 if (temp < 0) {
216 rc = temp;
217 goto out;
218 }
219
220 temp &= ~(3 << shift);
221 temp |= val << shift;
222 rc = phy_write(phydev, reg, temp);
223out:
224 if (rc < 0)
225 phydev_err(phydev, "failed to set led mode\n");
226
227 return rc;
228}
229
230/* Disable PHY address 0 as the broadcast address, so that it can be used as a
231 * unique (non-broadcast) address on a shared bus.
232 */
233static int kszphy_broadcast_disable(struct phy_device *phydev)
234{
235 int ret;
236
237 ret = phy_read(phydev, MII_KSZPHY_OMSO);
238 if (ret < 0)
239 goto out;
240
241 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
242out:
243 if (ret)
244 phydev_err(phydev, "failed to disable broadcast address\n");
245
246 return ret;
247}
248
249static int kszphy_nand_tree_disable(struct phy_device *phydev)
250{
251 int ret;
252
253 ret = phy_read(phydev, MII_KSZPHY_OMSO);
254 if (ret < 0)
255 goto out;
256
257 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
258 return 0;
259
260 ret = phy_write(phydev, MII_KSZPHY_OMSO,
261 ret & ~KSZPHY_OMSO_NAND_TREE_ON);
262out:
263 if (ret)
264 phydev_err(phydev, "failed to disable NAND tree mode\n");
265
266 return ret;
267}
268
269/* Some config bits need to be set again on resume, handle them here. */
270static int kszphy_config_reset(struct phy_device *phydev)
271{
272 struct kszphy_priv *priv = phydev->priv;
273 int ret;
274
275 if (priv->rmii_ref_clk_sel) {
276 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
277 if (ret) {
278 phydev_err(phydev,
279 "failed to set rmii reference clock\n");
280 return ret;
281 }
282 }
283
284 if (priv->led_mode >= 0)
285 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
286
287 return 0;
288}
289
290static int kszphy_config_init(struct phy_device *phydev)
291{
292 struct kszphy_priv *priv = phydev->priv;
293 const struct kszphy_type *type;
294
295 if (!priv)
296 return 0;
297
298 type = priv->type;
299
300 if (type->has_broadcast_disable)
301 kszphy_broadcast_disable(phydev);
302
303 if (type->has_nand_tree_disable)
304 kszphy_nand_tree_disable(phydev);
305
306 return kszphy_config_reset(phydev);
307}
308
309static int ksz8041_config_init(struct phy_device *phydev)
310{
311 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
312
313 struct device_node *of_node = phydev->mdio.dev.of_node;
314
315 /* Limit supported and advertised modes in fiber mode */
316 if (of_property_read_bool(of_node, "micrel,fiber-mode")) {
317 phydev->dev_flags |= MICREL_PHY_FXEN;
318 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
319 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
320
321 linkmode_and(phydev->supported, phydev->supported, mask);
322 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
323 phydev->supported);
324 linkmode_and(phydev->advertising, phydev->advertising, mask);
325 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
326 phydev->advertising);
327 phydev->autoneg = AUTONEG_DISABLE;
328 }
329
330 return kszphy_config_init(phydev);
331}
332
333static int ksz8041_config_aneg(struct phy_device *phydev)
334{
335 /* Skip auto-negotiation in fiber mode */
336 if (phydev->dev_flags & MICREL_PHY_FXEN) {
337 phydev->speed = SPEED_100;
338 return 0;
339 }
340
341 return genphy_config_aneg(phydev);
342}
343
344static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev,
345 const u32 ksz_phy_id)
346{
347 int ret;
348
349 if ((phydev->phy_id & MICREL_PHY_ID_MASK) != ksz_phy_id)
350 return 0;
351
352 ret = phy_read(phydev, MII_BMSR);
353 if (ret < 0)
354 return ret;
355
356 /* KSZ8051 PHY and KSZ8794/KSZ8795/KSZ8765 switch share the same
357 * exact PHY ID. However, they can be told apart by the extended
358 * capability registers presence. The KSZ8051 PHY has them while
359 * the switch does not.
360 */
361 ret &= BMSR_ERCAP;
362 if (ksz_phy_id == PHY_ID_KSZ8051)
363 return ret;
364 else
365 return !ret;
366}
367
368static int ksz8051_match_phy_device(struct phy_device *phydev)
369{
370 return ksz8051_ksz8795_match_phy_device(phydev, PHY_ID_KSZ8051);
371}
372
373static int ksz8081_config_init(struct phy_device *phydev)
374{
375 /* KSZPHY_OMSO_FACTORY_TEST is set at de-assertion of the reset line
376 * based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a
377 * pull-down is missing, the factory test mode should be cleared by
378 * manually writing a 0.
379 */
380 phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST);
381
382 return kszphy_config_init(phydev);
383}
384
385static int ksz8061_config_init(struct phy_device *phydev)
386{
387 int ret;
388
389 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
390 if (ret)
391 return ret;
392
393 return kszphy_config_init(phydev);
394}
395
396static int ksz8795_match_phy_device(struct phy_device *phydev)
397{
398 return ksz8051_ksz8795_match_phy_device(phydev, PHY_ID_KSZ87XX);
399}
400
401static int ksz9021_load_values_from_of(struct phy_device *phydev,
402 const struct device_node *of_node,
403 u16 reg,
404 const char *field1, const char *field2,
405 const char *field3, const char *field4)
406{
407 int val1 = -1;
408 int val2 = -2;
409 int val3 = -3;
410 int val4 = -4;
411 int newval;
412 int matches = 0;
413
414 if (!of_property_read_u32(of_node, field1, &val1))
415 matches++;
416
417 if (!of_property_read_u32(of_node, field2, &val2))
418 matches++;
419
420 if (!of_property_read_u32(of_node, field3, &val3))
421 matches++;
422
423 if (!of_property_read_u32(of_node, field4, &val4))
424 matches++;
425
426 if (!matches)
427 return 0;
428
429 if (matches < 4)
430 newval = kszphy_extended_read(phydev, reg);
431 else
432 newval = 0;
433
434 if (val1 != -1)
435 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
436
437 if (val2 != -2)
438 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
439
440 if (val3 != -3)
441 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
442
443 if (val4 != -4)
444 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
445
446 return kszphy_extended_write(phydev, reg, newval);
447}
448
449static int ksz9021_config_init(struct phy_device *phydev)
450{
451 const struct device *dev = &phydev->mdio.dev;
452 const struct device_node *of_node = dev->of_node;
453 const struct device *dev_walker;
454
455 /* The Micrel driver has a deprecated option to place phy OF
456 * properties in the MAC node. Walk up the tree of devices to
457 * find a device with an OF node.
458 */
459 dev_walker = &phydev->mdio.dev;
460 do {
461 of_node = dev_walker->of_node;
462 dev_walker = dev_walker->parent;
463
464 } while (!of_node && dev_walker);
465
466 if (of_node) {
467 ksz9021_load_values_from_of(phydev, of_node,
468 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
469 "txen-skew-ps", "txc-skew-ps",
470 "rxdv-skew-ps", "rxc-skew-ps");
471 ksz9021_load_values_from_of(phydev, of_node,
472 MII_KSZPHY_RX_DATA_PAD_SKEW,
473 "rxd0-skew-ps", "rxd1-skew-ps",
474 "rxd2-skew-ps", "rxd3-skew-ps");
475 ksz9021_load_values_from_of(phydev, of_node,
476 MII_KSZPHY_TX_DATA_PAD_SKEW,
477 "txd0-skew-ps", "txd1-skew-ps",
478 "txd2-skew-ps", "txd3-skew-ps");
479 }
480 return 0;
481}
482
483#define KSZ9031_PS_TO_REG 60
484
485/* Extended registers */
486/* MMD Address 0x0 */
487#define MII_KSZ9031RN_FLP_BURST_TX_LO 3
488#define MII_KSZ9031RN_FLP_BURST_TX_HI 4
489
490/* MMD Address 0x2 */
491#define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
492#define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
493#define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
494#define MII_KSZ9031RN_CLK_PAD_SKEW 8
495
496/* MMD Address 0x1C */
497#define MII_KSZ9031RN_EDPD 0x23
498#define MII_KSZ9031RN_EDPD_ENABLE BIT(0)
499
500static int ksz9031_of_load_skew_values(struct phy_device *phydev,
501 const struct device_node *of_node,
502 u16 reg, size_t field_sz,
503 const char *field[], u8 numfields)
504{
505 int val[4] = {-1, -2, -3, -4};
506 int matches = 0;
507 u16 mask;
508 u16 maxval;
509 u16 newval;
510 int i;
511
512 for (i = 0; i < numfields; i++)
513 if (!of_property_read_u32(of_node, field[i], val + i))
514 matches++;
515
516 if (!matches)
517 return 0;
518
519 if (matches < numfields)
520 newval = phy_read_mmd(phydev, 2, reg);
521 else
522 newval = 0;
523
524 maxval = (field_sz == 4) ? 0xf : 0x1f;
525 for (i = 0; i < numfields; i++)
526 if (val[i] != -(i + 1)) {
527 mask = 0xffff;
528 mask ^= maxval << (field_sz * i);
529 newval = (newval & mask) |
530 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
531 << (field_sz * i));
532 }
533
534 return phy_write_mmd(phydev, 2, reg, newval);
535}
536
537/* Center KSZ9031RNX FLP timing at 16ms. */
538static int ksz9031_center_flp_timing(struct phy_device *phydev)
539{
540 int result;
541
542 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI,
543 0x0006);
544 if (result)
545 return result;
546
547 result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO,
548 0x1A80);
549 if (result)
550 return result;
551
552 return genphy_restart_aneg(phydev);
553}
554
555/* Enable energy-detect power-down mode */
556static int ksz9031_enable_edpd(struct phy_device *phydev)
557{
558 int reg;
559
560 reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD);
561 if (reg < 0)
562 return reg;
563 return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD,
564 reg | MII_KSZ9031RN_EDPD_ENABLE);
565}
566
567static int ksz9031_config_init(struct phy_device *phydev)
568{
569 const struct device *dev = &phydev->mdio.dev;
570 const struct device_node *of_node = dev->of_node;
571 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
572 static const char *rx_data_skews[4] = {
573 "rxd0-skew-ps", "rxd1-skew-ps",
574 "rxd2-skew-ps", "rxd3-skew-ps"
575 };
576 static const char *tx_data_skews[4] = {
577 "txd0-skew-ps", "txd1-skew-ps",
578 "txd2-skew-ps", "txd3-skew-ps"
579 };
580 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
581 const struct device *dev_walker;
582 int result;
583
584 result = ksz9031_enable_edpd(phydev);
585 if (result < 0)
586 return result;
587
588 /* The Micrel driver has a deprecated option to place phy OF
589 * properties in the MAC node. Walk up the tree of devices to
590 * find a device with an OF node.
591 */
592 dev_walker = &phydev->mdio.dev;
593 do {
594 of_node = dev_walker->of_node;
595 dev_walker = dev_walker->parent;
596 } while (!of_node && dev_walker);
597
598 if (of_node) {
599 ksz9031_of_load_skew_values(phydev, of_node,
600 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
601 clk_skews, 2);
602
603 ksz9031_of_load_skew_values(phydev, of_node,
604 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
605 control_skews, 2);
606
607 ksz9031_of_load_skew_values(phydev, of_node,
608 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
609 rx_data_skews, 4);
610
611 ksz9031_of_load_skew_values(phydev, of_node,
612 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
613 tx_data_skews, 4);
614
615 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
616 * When the device links in the 1000BASE-T slave mode only,
617 * the optional 125MHz reference output clock (CLK125_NDO)
618 * has wide duty cycle variation.
619 *
620 * The optional CLK125_NDO clock does not meet the RGMII
621 * 45/55 percent (min/max) duty cycle requirement and therefore
622 * cannot be used directly by the MAC side for clocking
623 * applications that have setup/hold time requirements on
624 * rising and falling clock edges.
625 *
626 * Workaround:
627 * Force the phy to be the master to receive a stable clock
628 * which meets the duty cycle requirement.
629 */
630 if (of_property_read_bool(of_node, "micrel,force-master")) {
631 result = phy_read(phydev, MII_CTRL1000);
632 if (result < 0)
633 goto err_force_master;
634
635 /* enable master mode, config & prefer master */
636 result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER;
637 result = phy_write(phydev, MII_CTRL1000, result);
638 if (result < 0)
639 goto err_force_master;
640 }
641 }
642
643 return ksz9031_center_flp_timing(phydev);
644
645err_force_master:
646 phydev_err(phydev, "failed to force the phy to master mode\n");
647 return result;
648}
649
650#define KSZ9131_SKEW_5BIT_MAX 2400
651#define KSZ9131_SKEW_4BIT_MAX 800
652#define KSZ9131_OFFSET 700
653#define KSZ9131_STEP 100
654
655static int ksz9131_of_load_skew_values(struct phy_device *phydev,
656 struct device_node *of_node,
657 u16 reg, size_t field_sz,
658 char *field[], u8 numfields)
659{
660 int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET),
661 -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)};
662 int skewval, skewmax = 0;
663 int matches = 0;
664 u16 maxval;
665 u16 newval;
666 u16 mask;
667 int i;
668
669 /* psec properties in dts should mean x pico seconds */
670 if (field_sz == 5)
671 skewmax = KSZ9131_SKEW_5BIT_MAX;
672 else
673 skewmax = KSZ9131_SKEW_4BIT_MAX;
674
675 for (i = 0; i < numfields; i++)
676 if (!of_property_read_s32(of_node, field[i], &skewval)) {
677 if (skewval < -KSZ9131_OFFSET)
678 skewval = -KSZ9131_OFFSET;
679 else if (skewval > skewmax)
680 skewval = skewmax;
681
682 val[i] = skewval + KSZ9131_OFFSET;
683 matches++;
684 }
685
686 if (!matches)
687 return 0;
688
689 if (matches < numfields)
690 newval = phy_read_mmd(phydev, 2, reg);
691 else
692 newval = 0;
693
694 maxval = (field_sz == 4) ? 0xf : 0x1f;
695 for (i = 0; i < numfields; i++)
696 if (val[i] != -(i + 1 + KSZ9131_OFFSET)) {
697 mask = 0xffff;
698 mask ^= maxval << (field_sz * i);
699 newval = (newval & mask) |
700 (((val[i] / KSZ9131_STEP) & maxval)
701 << (field_sz * i));
702 }
703
704 return phy_write_mmd(phydev, 2, reg, newval);
705}
706
707static int ksz9131_config_init(struct phy_device *phydev)
708{
709 const struct device *dev = &phydev->mdio.dev;
710 struct device_node *of_node = dev->of_node;
711 char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"};
712 char *rx_data_skews[4] = {
713 "rxd0-skew-psec", "rxd1-skew-psec",
714 "rxd2-skew-psec", "rxd3-skew-psec"
715 };
716 char *tx_data_skews[4] = {
717 "txd0-skew-psec", "txd1-skew-psec",
718 "txd2-skew-psec", "txd3-skew-psec"
719 };
720 char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"};
721 const struct device *dev_walker;
722 int ret;
723
724 dev_walker = &phydev->mdio.dev;
725 do {
726 of_node = dev_walker->of_node;
727 dev_walker = dev_walker->parent;
728 } while (!of_node && dev_walker);
729
730 if (!of_node)
731 return 0;
732
733 ret = ksz9131_of_load_skew_values(phydev, of_node,
734 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
735 clk_skews, 2);
736 if (ret < 0)
737 return ret;
738
739 ret = ksz9131_of_load_skew_values(phydev, of_node,
740 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
741 control_skews, 2);
742 if (ret < 0)
743 return ret;
744
745 ret = ksz9131_of_load_skew_values(phydev, of_node,
746 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
747 rx_data_skews, 4);
748 if (ret < 0)
749 return ret;
750
751 ret = ksz9131_of_load_skew_values(phydev, of_node,
752 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
753 tx_data_skews, 4);
754 if (ret < 0)
755 return ret;
756
757 return 0;
758}
759
760#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
761#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
762#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
763static int ksz8873mll_read_status(struct phy_device *phydev)
764{
765 int regval;
766
767 /* dummy read */
768 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
769
770 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
771
772 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
773 phydev->duplex = DUPLEX_HALF;
774 else
775 phydev->duplex = DUPLEX_FULL;
776
777 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
778 phydev->speed = SPEED_10;
779 else
780 phydev->speed = SPEED_100;
781
782 phydev->link = 1;
783 phydev->pause = phydev->asym_pause = 0;
784
785 return 0;
786}
787
788static int ksz9031_get_features(struct phy_device *phydev)
789{
790 int ret;
791
792 ret = genphy_read_abilities(phydev);
793 if (ret < 0)
794 return ret;
795
796 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
797 * Whenever the device's Asymmetric Pause capability is set to 1,
798 * link-up may fail after a link-up to link-down transition.
799 *
800 * The Errata Sheet is for ksz9031, but ksz9021 has the same issue
801 *
802 * Workaround:
803 * Do not enable the Asymmetric Pause capability bit.
804 */
805 linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
806
807 /* We force setting the Pause capability as the core will force the
808 * Asymmetric Pause capability to 1 otherwise.
809 */
810 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
811
812 return 0;
813}
814
815static int ksz9031_read_status(struct phy_device *phydev)
816{
817 int err;
818 int regval;
819
820 err = genphy_read_status(phydev);
821 if (err)
822 return err;
823
824 /* Make sure the PHY is not broken. Read idle error count,
825 * and reset the PHY if it is maxed out.
826 */
827 regval = phy_read(phydev, MII_STAT1000);
828 if ((regval & 0xFF) == 0xFF) {
829 phy_init_hw(phydev);
830 phydev->link = 0;
831 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
832 phydev->drv->config_intr(phydev);
833 return genphy_config_aneg(phydev);
834 }
835
836 return 0;
837}
838
839static int ksz8873mll_config_aneg(struct phy_device *phydev)
840{
841 return 0;
842}
843
844static int kszphy_get_sset_count(struct phy_device *phydev)
845{
846 return ARRAY_SIZE(kszphy_hw_stats);
847}
848
849static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
850{
851 int i;
852
853 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
854 strlcpy(data + i * ETH_GSTRING_LEN,
855 kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
856 }
857}
858
859static u64 kszphy_get_stat(struct phy_device *phydev, int i)
860{
861 struct kszphy_hw_stat stat = kszphy_hw_stats[i];
862 struct kszphy_priv *priv = phydev->priv;
863 int val;
864 u64 ret;
865
866 val = phy_read(phydev, stat.reg);
867 if (val < 0) {
868 ret = U64_MAX;
869 } else {
870 val = val & ((1 << stat.bits) - 1);
871 priv->stats[i] += val;
872 ret = priv->stats[i];
873 }
874
875 return ret;
876}
877
878static void kszphy_get_stats(struct phy_device *phydev,
879 struct ethtool_stats *stats, u64 *data)
880{
881 int i;
882
883 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
884 data[i] = kszphy_get_stat(phydev, i);
885}
886
887static int kszphy_suspend(struct phy_device *phydev)
888{
889 /* Disable PHY Interrupts */
890 if (phy_interrupt_is_valid(phydev)) {
891 phydev->interrupts = PHY_INTERRUPT_DISABLED;
892 if (phydev->drv->config_intr)
893 phydev->drv->config_intr(phydev);
894 }
895
896 return genphy_suspend(phydev);
897}
898
899static int kszphy_resume(struct phy_device *phydev)
900{
901 int ret;
902
903 genphy_resume(phydev);
904
905 ret = kszphy_config_reset(phydev);
906 if (ret)
907 return ret;
908
909 /* Enable PHY Interrupts */
910 if (phy_interrupt_is_valid(phydev)) {
911 phydev->interrupts = PHY_INTERRUPT_ENABLED;
912 if (phydev->drv->config_intr)
913 phydev->drv->config_intr(phydev);
914 }
915
916 return 0;
917}
918
919static int kszphy_probe(struct phy_device *phydev)
920{
921 const struct kszphy_type *type = phydev->drv->driver_data;
922 const struct device_node *np = phydev->mdio.dev.of_node;
923 struct kszphy_priv *priv;
924 struct clk *clk;
925 int ret;
926
927 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
928 if (!priv)
929 return -ENOMEM;
930
931 phydev->priv = priv;
932
933 priv->type = type;
934
935 if (type->led_mode_reg) {
936 ret = of_property_read_u32(np, "micrel,led-mode",
937 &priv->led_mode);
938 if (ret)
939 priv->led_mode = -1;
940
941 if (priv->led_mode > 3) {
942 phydev_err(phydev, "invalid led mode: 0x%02x\n",
943 priv->led_mode);
944 priv->led_mode = -1;
945 }
946 } else {
947 priv->led_mode = -1;
948 }
949
950 clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
951 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
952 if (!IS_ERR_OR_NULL(clk)) {
953 unsigned long rate = clk_get_rate(clk);
954 bool rmii_ref_clk_sel_25_mhz;
955
956 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
957 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
958 "micrel,rmii-reference-clock-select-25-mhz");
959
960 if (rate > 24500000 && rate < 25500000) {
961 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
962 } else if (rate > 49500000 && rate < 50500000) {
963 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
964 } else {
965 phydev_err(phydev, "Clock rate out of range: %ld\n",
966 rate);
967 return -EINVAL;
968 }
969 }
970
971 /* Support legacy board-file configuration */
972 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
973 priv->rmii_ref_clk_sel = true;
974 priv->rmii_ref_clk_sel_val = true;
975 }
976
977 return 0;
978}
979
980static struct phy_driver ksphy_driver[] = {
981{
982 .phy_id = PHY_ID_KS8737,
983 .phy_id_mask = MICREL_PHY_ID_MASK,
984 .name = "Micrel KS8737",
985 /* PHY_BASIC_FEATURES */
986 .driver_data = &ks8737_type,
987 .config_init = kszphy_config_init,
988 .ack_interrupt = kszphy_ack_interrupt,
989 .config_intr = kszphy_config_intr,
990 .suspend = genphy_suspend,
991 .resume = genphy_resume,
992}, {
993 .phy_id = PHY_ID_KSZ8021,
994 .phy_id_mask = 0x00ffffff,
995 .name = "Micrel KSZ8021 or KSZ8031",
996 /* PHY_BASIC_FEATURES */
997 .driver_data = &ksz8021_type,
998 .probe = kszphy_probe,
999 .config_init = kszphy_config_init,
1000 .ack_interrupt = kszphy_ack_interrupt,
1001 .config_intr = kszphy_config_intr,
1002 .get_sset_count = kszphy_get_sset_count,
1003 .get_strings = kszphy_get_strings,
1004 .get_stats = kszphy_get_stats,
1005 .suspend = genphy_suspend,
1006 .resume = genphy_resume,
1007}, {
1008 .phy_id = PHY_ID_KSZ8031,
1009 .phy_id_mask = 0x00ffffff,
1010 .name = "Micrel KSZ8031",
1011 /* PHY_BASIC_FEATURES */
1012 .driver_data = &ksz8021_type,
1013 .probe = kszphy_probe,
1014 .config_init = kszphy_config_init,
1015 .ack_interrupt = kszphy_ack_interrupt,
1016 .config_intr = kszphy_config_intr,
1017 .get_sset_count = kszphy_get_sset_count,
1018 .get_strings = kszphy_get_strings,
1019 .get_stats = kszphy_get_stats,
1020 .suspend = genphy_suspend,
1021 .resume = genphy_resume,
1022}, {
1023 .phy_id = PHY_ID_KSZ8041,
1024 .phy_id_mask = MICREL_PHY_ID_MASK,
1025 .name = "Micrel KSZ8041",
1026 /* PHY_BASIC_FEATURES */
1027 .driver_data = &ksz8041_type,
1028 .probe = kszphy_probe,
1029 .config_init = ksz8041_config_init,
1030 .config_aneg = ksz8041_config_aneg,
1031 .ack_interrupt = kszphy_ack_interrupt,
1032 .config_intr = kszphy_config_intr,
1033 .get_sset_count = kszphy_get_sset_count,
1034 .get_strings = kszphy_get_strings,
1035 .get_stats = kszphy_get_stats,
1036 .suspend = genphy_suspend,
1037 .resume = genphy_resume,
1038}, {
1039 .phy_id = PHY_ID_KSZ8041RNLI,
1040 .phy_id_mask = MICREL_PHY_ID_MASK,
1041 .name = "Micrel KSZ8041RNLI",
1042 /* PHY_BASIC_FEATURES */
1043 .driver_data = &ksz8041_type,
1044 .probe = kszphy_probe,
1045 .config_init = kszphy_config_init,
1046 .ack_interrupt = kszphy_ack_interrupt,
1047 .config_intr = kszphy_config_intr,
1048 .get_sset_count = kszphy_get_sset_count,
1049 .get_strings = kszphy_get_strings,
1050 .get_stats = kszphy_get_stats,
1051 .suspend = genphy_suspend,
1052 .resume = genphy_resume,
1053}, {
1054 .name = "Micrel KSZ8051",
1055 /* PHY_BASIC_FEATURES */
1056 .driver_data = &ksz8051_type,
1057 .probe = kszphy_probe,
1058 .config_init = kszphy_config_init,
1059 .ack_interrupt = kszphy_ack_interrupt,
1060 .config_intr = kszphy_config_intr,
1061 .get_sset_count = kszphy_get_sset_count,
1062 .get_strings = kszphy_get_strings,
1063 .get_stats = kszphy_get_stats,
1064 .match_phy_device = ksz8051_match_phy_device,
1065 .suspend = genphy_suspend,
1066 .resume = genphy_resume,
1067}, {
1068 .phy_id = PHY_ID_KSZ8001,
1069 .name = "Micrel KSZ8001 or KS8721",
1070 .phy_id_mask = 0x00fffffc,
1071 /* PHY_BASIC_FEATURES */
1072 .driver_data = &ksz8041_type,
1073 .probe = kszphy_probe,
1074 .config_init = kszphy_config_init,
1075 .ack_interrupt = kszphy_ack_interrupt,
1076 .config_intr = kszphy_config_intr,
1077 .get_sset_count = kszphy_get_sset_count,
1078 .get_strings = kszphy_get_strings,
1079 .get_stats = kszphy_get_stats,
1080 .suspend = genphy_suspend,
1081 .resume = genphy_resume,
1082}, {
1083 .phy_id = PHY_ID_KSZ8081,
1084 .name = "Micrel KSZ8081 or KSZ8091",
1085 .phy_id_mask = MICREL_PHY_ID_MASK,
1086 /* PHY_BASIC_FEATURES */
1087 .driver_data = &ksz8081_type,
1088 .probe = kszphy_probe,
1089 .config_init = ksz8081_config_init,
1090 .ack_interrupt = kszphy_ack_interrupt,
1091 .config_intr = kszphy_config_intr,
1092 .get_sset_count = kszphy_get_sset_count,
1093 .get_strings = kszphy_get_strings,
1094 .get_stats = kszphy_get_stats,
1095 .suspend = kszphy_suspend,
1096 .resume = kszphy_resume,
1097}, {
1098 .phy_id = PHY_ID_KSZ8061,
1099 .name = "Micrel KSZ8061",
1100 .phy_id_mask = MICREL_PHY_ID_MASK,
1101 /* PHY_BASIC_FEATURES */
1102 .config_init = ksz8061_config_init,
1103 .ack_interrupt = kszphy_ack_interrupt,
1104 .config_intr = kszphy_config_intr,
1105 .suspend = genphy_suspend,
1106 .resume = genphy_resume,
1107}, {
1108 .phy_id = PHY_ID_KSZ9021,
1109 .phy_id_mask = 0x000ffffe,
1110 .name = "Micrel KSZ9021 Gigabit PHY",
1111 /* PHY_GBIT_FEATURES */
1112 .driver_data = &ksz9021_type,
1113 .probe = kszphy_probe,
1114 .get_features = ksz9031_get_features,
1115 .config_init = ksz9021_config_init,
1116 .ack_interrupt = kszphy_ack_interrupt,
1117 .config_intr = kszphy_config_intr,
1118 .get_sset_count = kszphy_get_sset_count,
1119 .get_strings = kszphy_get_strings,
1120 .get_stats = kszphy_get_stats,
1121 .suspend = genphy_suspend,
1122 .resume = genphy_resume,
1123 .read_mmd = genphy_read_mmd_unsupported,
1124 .write_mmd = genphy_write_mmd_unsupported,
1125}, {
1126 .phy_id = PHY_ID_KSZ9031,
1127 .phy_id_mask = MICREL_PHY_ID_MASK,
1128 .name = "Micrel KSZ9031 Gigabit PHY",
1129 .driver_data = &ksz9021_type,
1130 .probe = kszphy_probe,
1131 .get_features = ksz9031_get_features,
1132 .config_init = ksz9031_config_init,
1133 .soft_reset = genphy_soft_reset,
1134 .read_status = ksz9031_read_status,
1135 .ack_interrupt = kszphy_ack_interrupt,
1136 .config_intr = kszphy_config_intr,
1137 .get_sset_count = kszphy_get_sset_count,
1138 .get_strings = kszphy_get_strings,
1139 .get_stats = kszphy_get_stats,
1140 .suspend = genphy_suspend,
1141 .resume = kszphy_resume,
1142}, {
1143 .phy_id = PHY_ID_KSZ9131,
1144 .phy_id_mask = MICREL_PHY_ID_MASK,
1145 .name = "Microchip KSZ9131 Gigabit PHY",
1146 /* PHY_GBIT_FEATURES */
1147 .driver_data = &ksz9021_type,
1148 .probe = kszphy_probe,
1149 .config_init = ksz9131_config_init,
1150 .read_status = ksz9031_read_status,
1151 .ack_interrupt = kszphy_ack_interrupt,
1152 .config_intr = kszphy_config_intr,
1153 .get_sset_count = kszphy_get_sset_count,
1154 .get_strings = kszphy_get_strings,
1155 .get_stats = kszphy_get_stats,
1156 .suspend = genphy_suspend,
1157 .resume = kszphy_resume,
1158}, {
1159 .phy_id = PHY_ID_KSZ8873MLL,
1160 .phy_id_mask = MICREL_PHY_ID_MASK,
1161 .name = "Micrel KSZ8873MLL Switch",
1162 /* PHY_BASIC_FEATURES */
1163 .config_init = kszphy_config_init,
1164 .config_aneg = ksz8873mll_config_aneg,
1165 .read_status = ksz8873mll_read_status,
1166 .suspend = genphy_suspend,
1167 .resume = genphy_resume,
1168}, {
1169 .phy_id = PHY_ID_KSZ886X,
1170 .phy_id_mask = MICREL_PHY_ID_MASK,
1171 .name = "Micrel KSZ886X Switch",
1172 /* PHY_BASIC_FEATURES */
1173 .config_init = kszphy_config_init,
1174 .suspend = genphy_suspend,
1175 .resume = genphy_resume,
1176}, {
1177 .name = "Micrel KSZ87XX Switch",
1178 /* PHY_BASIC_FEATURES */
1179 .config_init = kszphy_config_init,
1180 .config_aneg = ksz8873mll_config_aneg,
1181 .read_status = ksz8873mll_read_status,
1182 .match_phy_device = ksz8795_match_phy_device,
1183 .suspend = genphy_suspend,
1184 .resume = genphy_resume,
1185}, {
1186 .phy_id = PHY_ID_KSZ9477,
1187 .phy_id_mask = MICREL_PHY_ID_MASK,
1188 .name = "Microchip KSZ9477",
1189 /* PHY_GBIT_FEATURES */
1190 .config_init = kszphy_config_init,
1191 .suspend = genphy_suspend,
1192 .resume = genphy_resume,
1193} };
1194
1195module_phy_driver(ksphy_driver);
1196
1197MODULE_DESCRIPTION("Micrel PHY driver");
1198MODULE_AUTHOR("David J. Choi");
1199MODULE_LICENSE("GPL");
1200
1201static struct mdio_device_id __maybe_unused micrel_tbl[] = {
1202 { PHY_ID_KSZ9021, 0x000ffffe },
1203 { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
1204 { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK },
1205 { PHY_ID_KSZ8001, 0x00fffffc },
1206 { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
1207 { PHY_ID_KSZ8021, 0x00ffffff },
1208 { PHY_ID_KSZ8031, 0x00ffffff },
1209 { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
1210 { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
1211 { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
1212 { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
1213 { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
1214 { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
1215 { }
1216};
1217
1218MODULE_DEVICE_TABLE(mdio, micrel_tbl);
1/*
2 * drivers/net/phy/micrel.c
3 *
4 * Driver for Micrel PHYs
5 *
6 * Author: David J. Choi
7 *
8 * Copyright (c) 2010-2013 Micrel, Inc.
9 * Copyright (c) 2014 Johan Hovold <johan@kernel.org>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * Support : Micrel Phys:
17 * Giga phys: ksz9021, ksz9031
18 * 100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
19 * ksz8021, ksz8031, ksz8051,
20 * ksz8081, ksz8091,
21 * ksz8061,
22 * Switch : ksz8873, ksz886x
23 */
24
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/phy.h>
28#include <linux/micrel_phy.h>
29#include <linux/of.h>
30#include <linux/clk.h>
31
32/* Operation Mode Strap Override */
33#define MII_KSZPHY_OMSO 0x16
34#define KSZPHY_OMSO_B_CAST_OFF BIT(9)
35#define KSZPHY_OMSO_NAND_TREE_ON BIT(5)
36#define KSZPHY_OMSO_RMII_OVERRIDE BIT(1)
37#define KSZPHY_OMSO_MII_OVERRIDE BIT(0)
38
39/* general Interrupt control/status reg in vendor specific block. */
40#define MII_KSZPHY_INTCS 0x1B
41#define KSZPHY_INTCS_JABBER BIT(15)
42#define KSZPHY_INTCS_RECEIVE_ERR BIT(14)
43#define KSZPHY_INTCS_PAGE_RECEIVE BIT(13)
44#define KSZPHY_INTCS_PARELLEL BIT(12)
45#define KSZPHY_INTCS_LINK_PARTNER_ACK BIT(11)
46#define KSZPHY_INTCS_LINK_DOWN BIT(10)
47#define KSZPHY_INTCS_REMOTE_FAULT BIT(9)
48#define KSZPHY_INTCS_LINK_UP BIT(8)
49#define KSZPHY_INTCS_ALL (KSZPHY_INTCS_LINK_UP |\
50 KSZPHY_INTCS_LINK_DOWN)
51
52/* PHY Control 1 */
53#define MII_KSZPHY_CTRL_1 0x1e
54
55/* PHY Control 2 / PHY Control (if no PHY Control 1) */
56#define MII_KSZPHY_CTRL_2 0x1f
57#define MII_KSZPHY_CTRL MII_KSZPHY_CTRL_2
58/* bitmap of PHY register to set interrupt mode */
59#define KSZPHY_CTRL_INT_ACTIVE_HIGH BIT(9)
60#define KSZPHY_RMII_REF_CLK_SEL BIT(7)
61
62/* Write/read to/from extended registers */
63#define MII_KSZPHY_EXTREG 0x0b
64#define KSZPHY_EXTREG_WRITE 0x8000
65
66#define MII_KSZPHY_EXTREG_WRITE 0x0c
67#define MII_KSZPHY_EXTREG_READ 0x0d
68
69/* Extended registers */
70#define MII_KSZPHY_CLK_CONTROL_PAD_SKEW 0x104
71#define MII_KSZPHY_RX_DATA_PAD_SKEW 0x105
72#define MII_KSZPHY_TX_DATA_PAD_SKEW 0x106
73
74#define PS_TO_REG 200
75
76struct kszphy_hw_stat {
77 const char *string;
78 u8 reg;
79 u8 bits;
80};
81
82static struct kszphy_hw_stat kszphy_hw_stats[] = {
83 { "phy_receive_errors", 21, 16},
84 { "phy_idle_errors", 10, 8 },
85};
86
87struct kszphy_type {
88 u32 led_mode_reg;
89 u16 interrupt_level_mask;
90 bool has_broadcast_disable;
91 bool has_nand_tree_disable;
92 bool has_rmii_ref_clk_sel;
93};
94
95struct kszphy_priv {
96 const struct kszphy_type *type;
97 int led_mode;
98 bool rmii_ref_clk_sel;
99 bool rmii_ref_clk_sel_val;
100 u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
101};
102
103static const struct kszphy_type ksz8021_type = {
104 .led_mode_reg = MII_KSZPHY_CTRL_2,
105 .has_broadcast_disable = true,
106 .has_nand_tree_disable = true,
107 .has_rmii_ref_clk_sel = true,
108};
109
110static const struct kszphy_type ksz8041_type = {
111 .led_mode_reg = MII_KSZPHY_CTRL_1,
112};
113
114static const struct kszphy_type ksz8051_type = {
115 .led_mode_reg = MII_KSZPHY_CTRL_2,
116 .has_nand_tree_disable = true,
117};
118
119static const struct kszphy_type ksz8081_type = {
120 .led_mode_reg = MII_KSZPHY_CTRL_2,
121 .has_broadcast_disable = true,
122 .has_nand_tree_disable = true,
123 .has_rmii_ref_clk_sel = true,
124};
125
126static const struct kszphy_type ks8737_type = {
127 .interrupt_level_mask = BIT(14),
128};
129
130static const struct kszphy_type ksz9021_type = {
131 .interrupt_level_mask = BIT(14),
132};
133
134static int kszphy_extended_write(struct phy_device *phydev,
135 u32 regnum, u16 val)
136{
137 phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
138 return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
139}
140
141static int kszphy_extended_read(struct phy_device *phydev,
142 u32 regnum)
143{
144 phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
145 return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
146}
147
148static int kszphy_ack_interrupt(struct phy_device *phydev)
149{
150 /* bit[7..0] int status, which is a read and clear register. */
151 int rc;
152
153 rc = phy_read(phydev, MII_KSZPHY_INTCS);
154
155 return (rc < 0) ? rc : 0;
156}
157
158static int kszphy_config_intr(struct phy_device *phydev)
159{
160 const struct kszphy_type *type = phydev->drv->driver_data;
161 int temp;
162 u16 mask;
163
164 if (type && type->interrupt_level_mask)
165 mask = type->interrupt_level_mask;
166 else
167 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
168
169 /* set the interrupt pin active low */
170 temp = phy_read(phydev, MII_KSZPHY_CTRL);
171 if (temp < 0)
172 return temp;
173 temp &= ~mask;
174 phy_write(phydev, MII_KSZPHY_CTRL, temp);
175
176 /* enable / disable interrupts */
177 if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
178 temp = KSZPHY_INTCS_ALL;
179 else
180 temp = 0;
181
182 return phy_write(phydev, MII_KSZPHY_INTCS, temp);
183}
184
185static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
186{
187 int ctrl;
188
189 ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
190 if (ctrl < 0)
191 return ctrl;
192
193 if (val)
194 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
195 else
196 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
197
198 return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
199}
200
201static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
202{
203 int rc, temp, shift;
204
205 switch (reg) {
206 case MII_KSZPHY_CTRL_1:
207 shift = 14;
208 break;
209 case MII_KSZPHY_CTRL_2:
210 shift = 4;
211 break;
212 default:
213 return -EINVAL;
214 }
215
216 temp = phy_read(phydev, reg);
217 if (temp < 0) {
218 rc = temp;
219 goto out;
220 }
221
222 temp &= ~(3 << shift);
223 temp |= val << shift;
224 rc = phy_write(phydev, reg, temp);
225out:
226 if (rc < 0)
227 phydev_err(phydev, "failed to set led mode\n");
228
229 return rc;
230}
231
232/* Disable PHY address 0 as the broadcast address, so that it can be used as a
233 * unique (non-broadcast) address on a shared bus.
234 */
235static int kszphy_broadcast_disable(struct phy_device *phydev)
236{
237 int ret;
238
239 ret = phy_read(phydev, MII_KSZPHY_OMSO);
240 if (ret < 0)
241 goto out;
242
243 ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
244out:
245 if (ret)
246 phydev_err(phydev, "failed to disable broadcast address\n");
247
248 return ret;
249}
250
251static int kszphy_nand_tree_disable(struct phy_device *phydev)
252{
253 int ret;
254
255 ret = phy_read(phydev, MII_KSZPHY_OMSO);
256 if (ret < 0)
257 goto out;
258
259 if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
260 return 0;
261
262 ret = phy_write(phydev, MII_KSZPHY_OMSO,
263 ret & ~KSZPHY_OMSO_NAND_TREE_ON);
264out:
265 if (ret)
266 phydev_err(phydev, "failed to disable NAND tree mode\n");
267
268 return ret;
269}
270
271static int kszphy_config_init(struct phy_device *phydev)
272{
273 struct kszphy_priv *priv = phydev->priv;
274 const struct kszphy_type *type;
275 int ret;
276
277 if (!priv)
278 return 0;
279
280 type = priv->type;
281
282 if (type->has_broadcast_disable)
283 kszphy_broadcast_disable(phydev);
284
285 if (type->has_nand_tree_disable)
286 kszphy_nand_tree_disable(phydev);
287
288 if (priv->rmii_ref_clk_sel) {
289 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
290 if (ret) {
291 phydev_err(phydev,
292 "failed to set rmii reference clock\n");
293 return ret;
294 }
295 }
296
297 if (priv->led_mode >= 0)
298 kszphy_setup_led(phydev, type->led_mode_reg, priv->led_mode);
299
300 if (phy_interrupt_is_valid(phydev)) {
301 int ctl = phy_read(phydev, MII_BMCR);
302
303 if (ctl < 0)
304 return ctl;
305
306 ret = phy_write(phydev, MII_BMCR, ctl & ~BMCR_ANENABLE);
307 if (ret < 0)
308 return ret;
309 }
310
311 return 0;
312}
313
314static int ksz9021_load_values_from_of(struct phy_device *phydev,
315 const struct device_node *of_node,
316 u16 reg,
317 const char *field1, const char *field2,
318 const char *field3, const char *field4)
319{
320 int val1 = -1;
321 int val2 = -2;
322 int val3 = -3;
323 int val4 = -4;
324 int newval;
325 int matches = 0;
326
327 if (!of_property_read_u32(of_node, field1, &val1))
328 matches++;
329
330 if (!of_property_read_u32(of_node, field2, &val2))
331 matches++;
332
333 if (!of_property_read_u32(of_node, field3, &val3))
334 matches++;
335
336 if (!of_property_read_u32(of_node, field4, &val4))
337 matches++;
338
339 if (!matches)
340 return 0;
341
342 if (matches < 4)
343 newval = kszphy_extended_read(phydev, reg);
344 else
345 newval = 0;
346
347 if (val1 != -1)
348 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
349
350 if (val2 != -2)
351 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
352
353 if (val3 != -3)
354 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
355
356 if (val4 != -4)
357 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
358
359 return kszphy_extended_write(phydev, reg, newval);
360}
361
362static int ksz9021_config_init(struct phy_device *phydev)
363{
364 const struct device *dev = &phydev->mdio.dev;
365 const struct device_node *of_node = dev->of_node;
366 const struct device *dev_walker;
367
368 /* The Micrel driver has a deprecated option to place phy OF
369 * properties in the MAC node. Walk up the tree of devices to
370 * find a device with an OF node.
371 */
372 dev_walker = &phydev->mdio.dev;
373 do {
374 of_node = dev_walker->of_node;
375 dev_walker = dev_walker->parent;
376
377 } while (!of_node && dev_walker);
378
379 if (of_node) {
380 ksz9021_load_values_from_of(phydev, of_node,
381 MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
382 "txen-skew-ps", "txc-skew-ps",
383 "rxdv-skew-ps", "rxc-skew-ps");
384 ksz9021_load_values_from_of(phydev, of_node,
385 MII_KSZPHY_RX_DATA_PAD_SKEW,
386 "rxd0-skew-ps", "rxd1-skew-ps",
387 "rxd2-skew-ps", "rxd3-skew-ps");
388 ksz9021_load_values_from_of(phydev, of_node,
389 MII_KSZPHY_TX_DATA_PAD_SKEW,
390 "txd0-skew-ps", "txd1-skew-ps",
391 "txd2-skew-ps", "txd3-skew-ps");
392 }
393 return 0;
394}
395
396#define MII_KSZ9031RN_MMD_CTRL_REG 0x0d
397#define MII_KSZ9031RN_MMD_REGDATA_REG 0x0e
398#define OP_DATA 1
399#define KSZ9031_PS_TO_REG 60
400
401/* Extended registers */
402/* MMD Address 0x0 */
403#define MII_KSZ9031RN_FLP_BURST_TX_LO 3
404#define MII_KSZ9031RN_FLP_BURST_TX_HI 4
405
406/* MMD Address 0x2 */
407#define MII_KSZ9031RN_CONTROL_PAD_SKEW 4
408#define MII_KSZ9031RN_RX_DATA_PAD_SKEW 5
409#define MII_KSZ9031RN_TX_DATA_PAD_SKEW 6
410#define MII_KSZ9031RN_CLK_PAD_SKEW 8
411
412static int ksz9031_extended_write(struct phy_device *phydev,
413 u8 mode, u32 dev_addr, u32 regnum, u16 val)
414{
415 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
416 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
417 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
418 return phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, val);
419}
420
421static int ksz9031_extended_read(struct phy_device *phydev,
422 u8 mode, u32 dev_addr, u32 regnum)
423{
424 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, dev_addr);
425 phy_write(phydev, MII_KSZ9031RN_MMD_REGDATA_REG, regnum);
426 phy_write(phydev, MII_KSZ9031RN_MMD_CTRL_REG, (mode << 14) | dev_addr);
427 return phy_read(phydev, MII_KSZ9031RN_MMD_REGDATA_REG);
428}
429
430static int ksz9031_of_load_skew_values(struct phy_device *phydev,
431 const struct device_node *of_node,
432 u16 reg, size_t field_sz,
433 const char *field[], u8 numfields)
434{
435 int val[4] = {-1, -2, -3, -4};
436 int matches = 0;
437 u16 mask;
438 u16 maxval;
439 u16 newval;
440 int i;
441
442 for (i = 0; i < numfields; i++)
443 if (!of_property_read_u32(of_node, field[i], val + i))
444 matches++;
445
446 if (!matches)
447 return 0;
448
449 if (matches < numfields)
450 newval = ksz9031_extended_read(phydev, OP_DATA, 2, reg);
451 else
452 newval = 0;
453
454 maxval = (field_sz == 4) ? 0xf : 0x1f;
455 for (i = 0; i < numfields; i++)
456 if (val[i] != -(i + 1)) {
457 mask = 0xffff;
458 mask ^= maxval << (field_sz * i);
459 newval = (newval & mask) |
460 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
461 << (field_sz * i));
462 }
463
464 return ksz9031_extended_write(phydev, OP_DATA, 2, reg, newval);
465}
466
467static int ksz9031_center_flp_timing(struct phy_device *phydev)
468{
469 int result;
470
471 /* Center KSZ9031RNX FLP timing at 16ms. */
472 result = ksz9031_extended_write(phydev, OP_DATA, 0,
473 MII_KSZ9031RN_FLP_BURST_TX_HI, 0x0006);
474 result = ksz9031_extended_write(phydev, OP_DATA, 0,
475 MII_KSZ9031RN_FLP_BURST_TX_LO, 0x1A80);
476
477 if (result)
478 return result;
479
480 return genphy_restart_aneg(phydev);
481}
482
483static int ksz9031_config_init(struct phy_device *phydev)
484{
485 const struct device *dev = &phydev->mdio.dev;
486 const struct device_node *of_node = dev->of_node;
487 static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
488 static const char *rx_data_skews[4] = {
489 "rxd0-skew-ps", "rxd1-skew-ps",
490 "rxd2-skew-ps", "rxd3-skew-ps"
491 };
492 static const char *tx_data_skews[4] = {
493 "txd0-skew-ps", "txd1-skew-ps",
494 "txd2-skew-ps", "txd3-skew-ps"
495 };
496 static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
497 const struct device *dev_walker;
498
499 /* The Micrel driver has a deprecated option to place phy OF
500 * properties in the MAC node. Walk up the tree of devices to
501 * find a device with an OF node.
502 */
503 dev_walker = &phydev->mdio.dev;
504 do {
505 of_node = dev_walker->of_node;
506 dev_walker = dev_walker->parent;
507 } while (!of_node && dev_walker);
508
509 if (of_node) {
510 ksz9031_of_load_skew_values(phydev, of_node,
511 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
512 clk_skews, 2);
513
514 ksz9031_of_load_skew_values(phydev, of_node,
515 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
516 control_skews, 2);
517
518 ksz9031_of_load_skew_values(phydev, of_node,
519 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
520 rx_data_skews, 4);
521
522 ksz9031_of_load_skew_values(phydev, of_node,
523 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
524 tx_data_skews, 4);
525 }
526
527 return ksz9031_center_flp_timing(phydev);
528}
529
530#define KSZ8873MLL_GLOBAL_CONTROL_4 0x06
531#define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX BIT(6)
532#define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED BIT(4)
533static int ksz8873mll_read_status(struct phy_device *phydev)
534{
535 int regval;
536
537 /* dummy read */
538 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
539
540 regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
541
542 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
543 phydev->duplex = DUPLEX_HALF;
544 else
545 phydev->duplex = DUPLEX_FULL;
546
547 if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
548 phydev->speed = SPEED_10;
549 else
550 phydev->speed = SPEED_100;
551
552 phydev->link = 1;
553 phydev->pause = phydev->asym_pause = 0;
554
555 return 0;
556}
557
558static int ksz9031_read_status(struct phy_device *phydev)
559{
560 int err;
561 int regval;
562
563 err = genphy_read_status(phydev);
564 if (err)
565 return err;
566
567 /* Make sure the PHY is not broken. Read idle error count,
568 * and reset the PHY if it is maxed out.
569 */
570 regval = phy_read(phydev, MII_STAT1000);
571 if ((regval & 0xFF) == 0xFF) {
572 phy_init_hw(phydev);
573 phydev->link = 0;
574 }
575
576 return 0;
577}
578
579static int ksz8873mll_config_aneg(struct phy_device *phydev)
580{
581 return 0;
582}
583
584/* This routine returns -1 as an indication to the caller that the
585 * Micrel ksz9021 10/100/1000 PHY does not support standard IEEE
586 * MMD extended PHY registers.
587 */
588static int
589ksz9021_rd_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
590 int regnum)
591{
592 return -1;
593}
594
595/* This routine does nothing since the Micrel ksz9021 does not support
596 * standard IEEE MMD extended PHY registers.
597 */
598static void
599ksz9021_wr_mmd_phyreg(struct phy_device *phydev, int ptrad, int devnum,
600 int regnum, u32 val)
601{
602}
603
604static int kszphy_get_sset_count(struct phy_device *phydev)
605{
606 return ARRAY_SIZE(kszphy_hw_stats);
607}
608
609static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
610{
611 int i;
612
613 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
614 memcpy(data + i * ETH_GSTRING_LEN,
615 kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
616 }
617}
618
619#ifndef UINT64_MAX
620#define UINT64_MAX (u64)(~((u64)0))
621#endif
622static u64 kszphy_get_stat(struct phy_device *phydev, int i)
623{
624 struct kszphy_hw_stat stat = kszphy_hw_stats[i];
625 struct kszphy_priv *priv = phydev->priv;
626 int val;
627 u64 ret;
628
629 val = phy_read(phydev, stat.reg);
630 if (val < 0) {
631 ret = UINT64_MAX;
632 } else {
633 val = val & ((1 << stat.bits) - 1);
634 priv->stats[i] += val;
635 ret = priv->stats[i];
636 }
637
638 return ret;
639}
640
641static void kszphy_get_stats(struct phy_device *phydev,
642 struct ethtool_stats *stats, u64 *data)
643{
644 int i;
645
646 for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
647 data[i] = kszphy_get_stat(phydev, i);
648}
649
650static int kszphy_resume(struct phy_device *phydev)
651{
652 int value;
653
654 mutex_lock(&phydev->lock);
655
656 value = phy_read(phydev, MII_BMCR);
657 phy_write(phydev, MII_BMCR, value & ~BMCR_PDOWN);
658
659 kszphy_config_intr(phydev);
660 mutex_unlock(&phydev->lock);
661
662 return 0;
663}
664
665static int kszphy_probe(struct phy_device *phydev)
666{
667 const struct kszphy_type *type = phydev->drv->driver_data;
668 const struct device_node *np = phydev->mdio.dev.of_node;
669 struct kszphy_priv *priv;
670 struct clk *clk;
671 int ret;
672
673 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
674 if (!priv)
675 return -ENOMEM;
676
677 phydev->priv = priv;
678
679 priv->type = type;
680
681 if (type->led_mode_reg) {
682 ret = of_property_read_u32(np, "micrel,led-mode",
683 &priv->led_mode);
684 if (ret)
685 priv->led_mode = -1;
686
687 if (priv->led_mode > 3) {
688 phydev_err(phydev, "invalid led mode: 0x%02x\n",
689 priv->led_mode);
690 priv->led_mode = -1;
691 }
692 } else {
693 priv->led_mode = -1;
694 }
695
696 clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
697 /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
698 if (!IS_ERR_OR_NULL(clk)) {
699 unsigned long rate = clk_get_rate(clk);
700 bool rmii_ref_clk_sel_25_mhz;
701
702 priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
703 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
704 "micrel,rmii-reference-clock-select-25-mhz");
705
706 if (rate > 24500000 && rate < 25500000) {
707 priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
708 } else if (rate > 49500000 && rate < 50500000) {
709 priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
710 } else {
711 phydev_err(phydev, "Clock rate out of range: %ld\n",
712 rate);
713 return -EINVAL;
714 }
715 }
716
717 /* Support legacy board-file configuration */
718 if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
719 priv->rmii_ref_clk_sel = true;
720 priv->rmii_ref_clk_sel_val = true;
721 }
722
723 return 0;
724}
725
726static struct phy_driver ksphy_driver[] = {
727{
728 .phy_id = PHY_ID_KS8737,
729 .phy_id_mask = 0x00fffff0,
730 .name = "Micrel KS8737",
731 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
732 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
733 .driver_data = &ks8737_type,
734 .config_init = kszphy_config_init,
735 .config_aneg = genphy_config_aneg,
736 .read_status = genphy_read_status,
737 .ack_interrupt = kszphy_ack_interrupt,
738 .config_intr = kszphy_config_intr,
739 .get_sset_count = kszphy_get_sset_count,
740 .get_strings = kszphy_get_strings,
741 .get_stats = kszphy_get_stats,
742 .suspend = genphy_suspend,
743 .resume = genphy_resume,
744}, {
745 .phy_id = PHY_ID_KSZ8021,
746 .phy_id_mask = 0x00ffffff,
747 .name = "Micrel KSZ8021 or KSZ8031",
748 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
749 SUPPORTED_Asym_Pause),
750 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
751 .driver_data = &ksz8021_type,
752 .probe = kszphy_probe,
753 .config_init = kszphy_config_init,
754 .config_aneg = genphy_config_aneg,
755 .read_status = genphy_read_status,
756 .ack_interrupt = kszphy_ack_interrupt,
757 .config_intr = kszphy_config_intr,
758 .get_sset_count = kszphy_get_sset_count,
759 .get_strings = kszphy_get_strings,
760 .get_stats = kszphy_get_stats,
761 .suspend = genphy_suspend,
762 .resume = genphy_resume,
763}, {
764 .phy_id = PHY_ID_KSZ8031,
765 .phy_id_mask = 0x00ffffff,
766 .name = "Micrel KSZ8031",
767 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause |
768 SUPPORTED_Asym_Pause),
769 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
770 .driver_data = &ksz8021_type,
771 .probe = kszphy_probe,
772 .config_init = kszphy_config_init,
773 .config_aneg = genphy_config_aneg,
774 .read_status = genphy_read_status,
775 .ack_interrupt = kszphy_ack_interrupt,
776 .config_intr = kszphy_config_intr,
777 .get_sset_count = kszphy_get_sset_count,
778 .get_strings = kszphy_get_strings,
779 .get_stats = kszphy_get_stats,
780 .suspend = genphy_suspend,
781 .resume = genphy_resume,
782}, {
783 .phy_id = PHY_ID_KSZ8041,
784 .phy_id_mask = 0x00fffff0,
785 .name = "Micrel KSZ8041",
786 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
787 | SUPPORTED_Asym_Pause),
788 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
789 .driver_data = &ksz8041_type,
790 .probe = kszphy_probe,
791 .config_init = kszphy_config_init,
792 .config_aneg = genphy_config_aneg,
793 .read_status = genphy_read_status,
794 .ack_interrupt = kszphy_ack_interrupt,
795 .config_intr = kszphy_config_intr,
796 .get_sset_count = kszphy_get_sset_count,
797 .get_strings = kszphy_get_strings,
798 .get_stats = kszphy_get_stats,
799 .suspend = genphy_suspend,
800 .resume = genphy_resume,
801}, {
802 .phy_id = PHY_ID_KSZ8041RNLI,
803 .phy_id_mask = 0x00fffff0,
804 .name = "Micrel KSZ8041RNLI",
805 .features = PHY_BASIC_FEATURES |
806 SUPPORTED_Pause | SUPPORTED_Asym_Pause,
807 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
808 .driver_data = &ksz8041_type,
809 .probe = kszphy_probe,
810 .config_init = kszphy_config_init,
811 .config_aneg = genphy_config_aneg,
812 .read_status = genphy_read_status,
813 .ack_interrupt = kszphy_ack_interrupt,
814 .config_intr = kszphy_config_intr,
815 .get_sset_count = kszphy_get_sset_count,
816 .get_strings = kszphy_get_strings,
817 .get_stats = kszphy_get_stats,
818 .suspend = genphy_suspend,
819 .resume = genphy_resume,
820}, {
821 .phy_id = PHY_ID_KSZ8051,
822 .phy_id_mask = 0x00fffff0,
823 .name = "Micrel KSZ8051",
824 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause
825 | SUPPORTED_Asym_Pause),
826 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
827 .driver_data = &ksz8051_type,
828 .probe = kszphy_probe,
829 .config_init = kszphy_config_init,
830 .config_aneg = genphy_config_aneg,
831 .read_status = genphy_read_status,
832 .ack_interrupt = kszphy_ack_interrupt,
833 .config_intr = kszphy_config_intr,
834 .get_sset_count = kszphy_get_sset_count,
835 .get_strings = kszphy_get_strings,
836 .get_stats = kszphy_get_stats,
837 .suspend = genphy_suspend,
838 .resume = genphy_resume,
839}, {
840 .phy_id = PHY_ID_KSZ8001,
841 .name = "Micrel KSZ8001 or KS8721",
842 .phy_id_mask = 0x00ffffff,
843 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
844 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
845 .driver_data = &ksz8041_type,
846 .probe = kszphy_probe,
847 .config_init = kszphy_config_init,
848 .config_aneg = genphy_config_aneg,
849 .read_status = genphy_read_status,
850 .ack_interrupt = kszphy_ack_interrupt,
851 .config_intr = kszphy_config_intr,
852 .get_sset_count = kszphy_get_sset_count,
853 .get_strings = kszphy_get_strings,
854 .get_stats = kszphy_get_stats,
855 .suspend = genphy_suspend,
856 .resume = genphy_resume,
857}, {
858 .phy_id = PHY_ID_KSZ8081,
859 .name = "Micrel KSZ8081 or KSZ8091",
860 .phy_id_mask = 0x00fffff0,
861 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
862 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
863 .driver_data = &ksz8081_type,
864 .probe = kszphy_probe,
865 .config_init = kszphy_config_init,
866 .config_aneg = genphy_config_aneg,
867 .read_status = genphy_read_status,
868 .ack_interrupt = kszphy_ack_interrupt,
869 .config_intr = kszphy_config_intr,
870 .get_sset_count = kszphy_get_sset_count,
871 .get_strings = kszphy_get_strings,
872 .get_stats = kszphy_get_stats,
873 .suspend = genphy_suspend,
874 .resume = kszphy_resume,
875}, {
876 .phy_id = PHY_ID_KSZ8061,
877 .name = "Micrel KSZ8061",
878 .phy_id_mask = 0x00fffff0,
879 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
880 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
881 .config_init = kszphy_config_init,
882 .config_aneg = genphy_config_aneg,
883 .read_status = genphy_read_status,
884 .ack_interrupt = kszphy_ack_interrupt,
885 .config_intr = kszphy_config_intr,
886 .get_sset_count = kszphy_get_sset_count,
887 .get_strings = kszphy_get_strings,
888 .get_stats = kszphy_get_stats,
889 .suspend = genphy_suspend,
890 .resume = genphy_resume,
891}, {
892 .phy_id = PHY_ID_KSZ9021,
893 .phy_id_mask = 0x000ffffe,
894 .name = "Micrel KSZ9021 Gigabit PHY",
895 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
896 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
897 .driver_data = &ksz9021_type,
898 .config_init = ksz9021_config_init,
899 .config_aneg = genphy_config_aneg,
900 .read_status = genphy_read_status,
901 .ack_interrupt = kszphy_ack_interrupt,
902 .config_intr = kszphy_config_intr,
903 .get_sset_count = kszphy_get_sset_count,
904 .get_strings = kszphy_get_strings,
905 .get_stats = kszphy_get_stats,
906 .suspend = genphy_suspend,
907 .resume = genphy_resume,
908 .read_mmd_indirect = ksz9021_rd_mmd_phyreg,
909 .write_mmd_indirect = ksz9021_wr_mmd_phyreg,
910}, {
911 .phy_id = PHY_ID_KSZ9031,
912 .phy_id_mask = 0x00fffff0,
913 .name = "Micrel KSZ9031 Gigabit PHY",
914 .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
915 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
916 .driver_data = &ksz9021_type,
917 .config_init = ksz9031_config_init,
918 .config_aneg = genphy_config_aneg,
919 .read_status = ksz9031_read_status,
920 .ack_interrupt = kszphy_ack_interrupt,
921 .config_intr = kszphy_config_intr,
922 .get_sset_count = kszphy_get_sset_count,
923 .get_strings = kszphy_get_strings,
924 .get_stats = kszphy_get_stats,
925 .suspend = genphy_suspend,
926 .resume = genphy_resume,
927}, {
928 .phy_id = PHY_ID_KSZ8873MLL,
929 .phy_id_mask = 0x00fffff0,
930 .name = "Micrel KSZ8873MLL Switch",
931 .features = (SUPPORTED_Pause | SUPPORTED_Asym_Pause),
932 .flags = PHY_HAS_MAGICANEG,
933 .config_init = kszphy_config_init,
934 .config_aneg = ksz8873mll_config_aneg,
935 .read_status = ksz8873mll_read_status,
936 .get_sset_count = kszphy_get_sset_count,
937 .get_strings = kszphy_get_strings,
938 .get_stats = kszphy_get_stats,
939 .suspend = genphy_suspend,
940 .resume = genphy_resume,
941}, {
942 .phy_id = PHY_ID_KSZ886X,
943 .phy_id_mask = 0x00fffff0,
944 .name = "Micrel KSZ886X Switch",
945 .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause),
946 .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
947 .config_init = kszphy_config_init,
948 .config_aneg = genphy_config_aneg,
949 .read_status = genphy_read_status,
950 .get_sset_count = kszphy_get_sset_count,
951 .get_strings = kszphy_get_strings,
952 .get_stats = kszphy_get_stats,
953 .suspend = genphy_suspend,
954 .resume = genphy_resume,
955} };
956
957module_phy_driver(ksphy_driver);
958
959MODULE_DESCRIPTION("Micrel PHY driver");
960MODULE_AUTHOR("David J. Choi");
961MODULE_LICENSE("GPL");
962
963static struct mdio_device_id __maybe_unused micrel_tbl[] = {
964 { PHY_ID_KSZ9021, 0x000ffffe },
965 { PHY_ID_KSZ9031, 0x00fffff0 },
966 { PHY_ID_KSZ8001, 0x00ffffff },
967 { PHY_ID_KS8737, 0x00fffff0 },
968 { PHY_ID_KSZ8021, 0x00ffffff },
969 { PHY_ID_KSZ8031, 0x00ffffff },
970 { PHY_ID_KSZ8041, 0x00fffff0 },
971 { PHY_ID_KSZ8051, 0x00fffff0 },
972 { PHY_ID_KSZ8061, 0x00fffff0 },
973 { PHY_ID_KSZ8081, 0x00fffff0 },
974 { PHY_ID_KSZ8873MLL, 0x00fffff0 },
975 { PHY_ID_KSZ886X, 0x00fffff0 },
976 { }
977};
978
979MODULE_DEVICE_TABLE(mdio, micrel_tbl);