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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * TSC frequency enumeration via MSR
4 *
5 * Copyright (C) 2013, 2018 Intel Corporation
6 * Author: Bin Gao <bin.gao@intel.com>
7 */
8
9#include <linux/kernel.h>
10
11#include <asm/apic.h>
12#include <asm/cpu_device_id.h>
13#include <asm/intel-family.h>
14#include <asm/msr.h>
15#include <asm/param.h>
16#include <asm/tsc.h>
17
18#define MAX_NUM_FREQS 9
19
20/*
21 * If MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
22 * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
23 * Unfortunately some Intel Atom SoCs aren't quite compliant to this,
24 * so we need manually differentiate SoC families. This is what the
25 * field msr_plat does.
26 */
27struct freq_desc {
28 u8 msr_plat; /* 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
29 u32 freqs[MAX_NUM_FREQS];
30};
31
32/*
33 * Penwell and Clovertrail use spread spectrum clock,
34 * so the freq number is not exactly the same as reported
35 * by MSR based on SDM.
36 */
37static const struct freq_desc freq_desc_pnw = {
38 0, { 0, 0, 0, 0, 0, 99840, 0, 83200 }
39};
40
41static const struct freq_desc freq_desc_clv = {
42 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200 }
43};
44
45static const struct freq_desc freq_desc_byt = {
46 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0 }
47};
48
49static const struct freq_desc freq_desc_cht = {
50 1, { 83300, 100000, 133300, 116700, 80000, 93300, 90000, 88900, 87500 }
51};
52
53static const struct freq_desc freq_desc_tng = {
54 1, { 0, 100000, 133300, 0, 0, 0, 0, 0 }
55};
56
57static const struct freq_desc freq_desc_ann = {
58 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0 }
59};
60
61static const struct freq_desc freq_desc_lgm = {
62 1, { 78000, 78000, 78000, 78000, 78000, 78000, 78000, 78000 }
63};
64
65static const struct x86_cpu_id tsc_msr_cpu_ids[] = {
66 INTEL_CPU_FAM6(ATOM_SALTWELL_MID, freq_desc_pnw),
67 INTEL_CPU_FAM6(ATOM_SALTWELL_TABLET, freq_desc_clv),
68 INTEL_CPU_FAM6(ATOM_SILVERMONT, freq_desc_byt),
69 INTEL_CPU_FAM6(ATOM_SILVERMONT_MID, freq_desc_tng),
70 INTEL_CPU_FAM6(ATOM_AIRMONT, freq_desc_cht),
71 INTEL_CPU_FAM6(ATOM_AIRMONT_MID, freq_desc_ann),
72 INTEL_CPU_FAM6(ATOM_AIRMONT_NP, freq_desc_lgm),
73 {}
74};
75
76/*
77 * MSR-based CPU/TSC frequency discovery for certain CPUs.
78 *
79 * Set global "lapic_timer_period" to bus_clock_cycles/jiffy
80 * Return processor base frequency in KHz, or 0 on failure.
81 */
82unsigned long cpu_khz_from_msr(void)
83{
84 u32 lo, hi, ratio, freq;
85 const struct freq_desc *freq_desc;
86 const struct x86_cpu_id *id;
87 unsigned long res;
88
89 id = x86_match_cpu(tsc_msr_cpu_ids);
90 if (!id)
91 return 0;
92
93 freq_desc = (struct freq_desc *)id->driver_data;
94 if (freq_desc->msr_plat) {
95 rdmsr(MSR_PLATFORM_INFO, lo, hi);
96 ratio = (lo >> 8) & 0xff;
97 } else {
98 rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
99 ratio = (hi >> 8) & 0x1f;
100 }
101
102 /* Get FSB FREQ ID */
103 rdmsr(MSR_FSB_FREQ, lo, hi);
104
105 /* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
106 freq = freq_desc->freqs[lo & 0x7];
107
108 /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
109 res = freq * ratio;
110
111#ifdef CONFIG_X86_LOCAL_APIC
112 lapic_timer_period = (freq * 1000) / HZ;
113#endif
114
115 /*
116 * TSC frequency determined by MSR is always considered "known"
117 * because it is reported by HW.
118 * Another fact is that on MSR capable platforms, PIT/HPET is
119 * generally not available so calibration won't work at all.
120 */
121 setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
122
123 /*
124 * Unfortunately there is no way for hardware to tell whether the
125 * TSC is reliable. We were told by silicon design team that TSC
126 * on Atom SoCs are always "reliable". TSC is also the only
127 * reliable clocksource on these SoCs (HPET is either not present
128 * or not functional) so mark TSC reliable which removes the
129 * requirement for a watchdog clocksource.
130 */
131 setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
132
133 return res;
134}
1/*
2 * tsc_msr.c - MSR based TSC calibration on Intel Atom SoC platforms.
3 *
4 * TSC in Intel Atom SoC runs at a constant rate which can be figured
5 * by this formula:
6 * <maximum core-clock to bus-clock ratio> * <maximum resolved frequency>
7 * See Intel 64 and IA-32 System Programming Guid section 16.12 and 30.11.5
8 * for details.
9 * Especially some Intel Atom SoCs don't have PIT(i8254) or HPET, so MSR
10 * based calibration is the only option.
11 *
12 *
13 * Copyright (C) 2013 Intel Corporation
14 * Author: Bin Gao <bin.gao@intel.com>
15 *
16 * This file is released under the GPLv2.
17 */
18
19#include <linux/kernel.h>
20#include <asm/processor.h>
21#include <asm/setup.h>
22#include <asm/apic.h>
23#include <asm/param.h>
24
25/* CPU reference clock frequency: in KHz */
26#define FREQ_83 83200
27#define FREQ_100 99840
28#define FREQ_133 133200
29#define FREQ_166 166400
30
31#define MAX_NUM_FREQS 8
32
33/*
34 * According to Intel 64 and IA-32 System Programming Guide,
35 * if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
36 * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40].
37 * Unfortunately some Intel Atom SoCs aren't quite compliant to this,
38 * so we need manually differentiate SoC families. This is what the
39 * field msr_plat does.
40 */
41struct freq_desc {
42 u8 x86_family; /* CPU family */
43 u8 x86_model; /* model */
44 u8 msr_plat; /* 1: use MSR_PLATFORM_INFO, 0: MSR_IA32_PERF_STATUS */
45 u32 freqs[MAX_NUM_FREQS];
46};
47
48static struct freq_desc freq_desc_tables[] = {
49 /* PNW */
50 { 6, 0x27, 0, { 0, 0, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
51 /* CLV+ */
52 { 6, 0x35, 0, { 0, FREQ_133, 0, 0, 0, FREQ_100, 0, FREQ_83 } },
53 /* TNG */
54 { 6, 0x4a, 1, { 0, FREQ_100, FREQ_133, 0, 0, 0, 0, 0 } },
55 /* VLV2 */
56 { 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },
57 /* ANN */
58 { 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } },
59};
60
61static int match_cpu(u8 family, u8 model)
62{
63 int i;
64
65 for (i = 0; i < ARRAY_SIZE(freq_desc_tables); i++) {
66 if ((family == freq_desc_tables[i].x86_family) &&
67 (model == freq_desc_tables[i].x86_model))
68 return i;
69 }
70
71 return -1;
72}
73
74/* Map CPU reference clock freq ID(0-7) to CPU reference clock freq(KHz) */
75#define id_to_freq(cpu_index, freq_id) \
76 (freq_desc_tables[cpu_index].freqs[freq_id])
77
78/*
79 * Do MSR calibration only for known/supported CPUs.
80 *
81 * Returns the calibration value or 0 if MSR calibration failed.
82 */
83unsigned long try_msr_calibrate_tsc(void)
84{
85 u32 lo, hi, ratio, freq_id, freq;
86 unsigned long res;
87 int cpu_index;
88
89 cpu_index = match_cpu(boot_cpu_data.x86, boot_cpu_data.x86_model);
90 if (cpu_index < 0)
91 return 0;
92
93 if (freq_desc_tables[cpu_index].msr_plat) {
94 rdmsr(MSR_PLATFORM_INFO, lo, hi);
95 ratio = (lo >> 8) & 0xff;
96 } else {
97 rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
98 ratio = (hi >> 8) & 0x1f;
99 }
100 pr_info("Maximum core-clock to bus-clock ratio: 0x%x\n", ratio);
101
102 if (!ratio)
103 goto fail;
104
105 /* Get FSB FREQ ID */
106 rdmsr(MSR_FSB_FREQ, lo, hi);
107 freq_id = lo & 0x7;
108 freq = id_to_freq(cpu_index, freq_id);
109 pr_info("Resolved frequency ID: %u, frequency: %u KHz\n",
110 freq_id, freq);
111 if (!freq)
112 goto fail;
113
114 /* TSC frequency = maximum resolved freq * maximum resolved bus ratio */
115 res = freq * ratio;
116 pr_info("TSC runs at %lu KHz\n", res);
117
118#ifdef CONFIG_X86_LOCAL_APIC
119 lapic_timer_frequency = (freq * 1000) / HZ;
120 pr_info("lapic_timer_frequency = %d\n", lapic_timer_frequency);
121#endif
122 return res;
123
124fail:
125 pr_warn("Fast TSC calibration using MSR failed\n");
126 return 0;
127}