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1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Fault injection for both 32 and 64bit guests.
4 *
5 * Copyright (C) 2012,2013 - ARM Ltd
6 * Author: Marc Zyngier <marc.zyngier@arm.com>
7 *
8 * Based on arch/arm/kvm/emulate.c
9 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
10 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
11 */
12
13#include <linux/kvm_host.h>
14#include <asm/kvm_emulate.h>
15#include <asm/esr.h>
16
17#define PSTATE_FAULT_BITS_64 (PSR_MODE_EL1h | PSR_A_BIT | PSR_F_BIT | \
18 PSR_I_BIT | PSR_D_BIT)
19
20#define CURRENT_EL_SP_EL0_VECTOR 0x0
21#define CURRENT_EL_SP_ELx_VECTOR 0x200
22#define LOWER_EL_AArch64_VECTOR 0x400
23#define LOWER_EL_AArch32_VECTOR 0x600
24
25enum exception_type {
26 except_type_sync = 0,
27 except_type_irq = 0x80,
28 except_type_fiq = 0x100,
29 except_type_serror = 0x180,
30};
31
32static u64 get_except_vector(struct kvm_vcpu *vcpu, enum exception_type type)
33{
34 u64 exc_offset;
35
36 switch (*vcpu_cpsr(vcpu) & (PSR_MODE_MASK | PSR_MODE32_BIT)) {
37 case PSR_MODE_EL1t:
38 exc_offset = CURRENT_EL_SP_EL0_VECTOR;
39 break;
40 case PSR_MODE_EL1h:
41 exc_offset = CURRENT_EL_SP_ELx_VECTOR;
42 break;
43 case PSR_MODE_EL0t:
44 exc_offset = LOWER_EL_AArch64_VECTOR;
45 break;
46 default:
47 exc_offset = LOWER_EL_AArch32_VECTOR;
48 }
49
50 return vcpu_read_sys_reg(vcpu, VBAR_EL1) + exc_offset + type;
51}
52
53static void inject_abt64(struct kvm_vcpu *vcpu, bool is_iabt, unsigned long addr)
54{
55 unsigned long cpsr = *vcpu_cpsr(vcpu);
56 bool is_aarch32 = vcpu_mode_is_32bit(vcpu);
57 u32 esr = 0;
58
59 vcpu_write_elr_el1(vcpu, *vcpu_pc(vcpu));
60 *vcpu_pc(vcpu) = get_except_vector(vcpu, except_type_sync);
61
62 *vcpu_cpsr(vcpu) = PSTATE_FAULT_BITS_64;
63 vcpu_write_spsr(vcpu, cpsr);
64
65 vcpu_write_sys_reg(vcpu, addr, FAR_EL1);
66
67 /*
68 * Build an {i,d}abort, depending on the level and the
69 * instruction set. Report an external synchronous abort.
70 */
71 if (kvm_vcpu_trap_il_is32bit(vcpu))
72 esr |= ESR_ELx_IL;
73
74 /*
75 * Here, the guest runs in AArch64 mode when in EL1. If we get
76 * an AArch32 fault, it means we managed to trap an EL0 fault.
77 */
78 if (is_aarch32 || (cpsr & PSR_MODE_MASK) == PSR_MODE_EL0t)
79 esr |= (ESR_ELx_EC_IABT_LOW << ESR_ELx_EC_SHIFT);
80 else
81 esr |= (ESR_ELx_EC_IABT_CUR << ESR_ELx_EC_SHIFT);
82
83 if (!is_iabt)
84 esr |= ESR_ELx_EC_DABT_LOW << ESR_ELx_EC_SHIFT;
85
86 vcpu_write_sys_reg(vcpu, esr | ESR_ELx_FSC_EXTABT, ESR_EL1);
87}
88
89static void inject_undef64(struct kvm_vcpu *vcpu)
90{
91 unsigned long cpsr = *vcpu_cpsr(vcpu);
92 u32 esr = (ESR_ELx_EC_UNKNOWN << ESR_ELx_EC_SHIFT);
93
94 vcpu_write_elr_el1(vcpu, *vcpu_pc(vcpu));
95 *vcpu_pc(vcpu) = get_except_vector(vcpu, except_type_sync);
96
97 *vcpu_cpsr(vcpu) = PSTATE_FAULT_BITS_64;
98 vcpu_write_spsr(vcpu, cpsr);
99
100 /*
101 * Build an unknown exception, depending on the instruction
102 * set.
103 */
104 if (kvm_vcpu_trap_il_is32bit(vcpu))
105 esr |= ESR_ELx_IL;
106
107 vcpu_write_sys_reg(vcpu, esr, ESR_EL1);
108}
109
110/**
111 * kvm_inject_dabt - inject a data abort into the guest
112 * @vcpu: The VCPU to receive the undefined exception
113 * @addr: The address to report in the DFAR
114 *
115 * It is assumed that this code is called from the VCPU thread and that the
116 * VCPU therefore is not currently executing guest code.
117 */
118void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr)
119{
120 if (vcpu_el1_is_32bit(vcpu))
121 kvm_inject_dabt32(vcpu, addr);
122 else
123 inject_abt64(vcpu, false, addr);
124}
125
126/**
127 * kvm_inject_pabt - inject a prefetch abort into the guest
128 * @vcpu: The VCPU to receive the undefined exception
129 * @addr: The address to report in the DFAR
130 *
131 * It is assumed that this code is called from the VCPU thread and that the
132 * VCPU therefore is not currently executing guest code.
133 */
134void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr)
135{
136 if (vcpu_el1_is_32bit(vcpu))
137 kvm_inject_pabt32(vcpu, addr);
138 else
139 inject_abt64(vcpu, true, addr);
140}
141
142/**
143 * kvm_inject_undefined - inject an undefined instruction into the guest
144 *
145 * It is assumed that this code is called from the VCPU thread and that the
146 * VCPU therefore is not currently executing guest code.
147 */
148void kvm_inject_undefined(struct kvm_vcpu *vcpu)
149{
150 if (vcpu_el1_is_32bit(vcpu))
151 kvm_inject_undef32(vcpu);
152 else
153 inject_undef64(vcpu);
154}
155
156void kvm_set_sei_esr(struct kvm_vcpu *vcpu, u64 esr)
157{
158 vcpu_set_vsesr(vcpu, esr & ESR_ELx_ISS_MASK);
159 *vcpu_hcr(vcpu) |= HCR_VSE;
160}
161
162/**
163 * kvm_inject_vabt - inject an async abort / SError into the guest
164 * @vcpu: The VCPU to receive the exception
165 *
166 * It is assumed that this code is called from the VCPU thread and that the
167 * VCPU therefore is not currently executing guest code.
168 *
169 * Systems with the RAS Extensions specify an imp-def ESR (ISV/IDS = 1) with
170 * the remaining ISS all-zeros so that this error is not interpreted as an
171 * uncategorized RAS error. Without the RAS Extensions we can't specify an ESR
172 * value, so the CPU generates an imp-def value.
173 */
174void kvm_inject_vabt(struct kvm_vcpu *vcpu)
175{
176 kvm_set_sei_esr(vcpu, ESR_ELx_ISV);
177}
1/*
2 * Fault injection for both 32 and 64bit guests.
3 *
4 * Copyright (C) 2012,2013 - ARM Ltd
5 * Author: Marc Zyngier <marc.zyngier@arm.com>
6 *
7 * Based on arch/arm/kvm/emulate.c
8 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
9 * Author: Christoffer Dall <c.dall@virtualopensystems.com>
10 *
11 * This program is free software: you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 */
23
24#include <linux/kvm_host.h>
25#include <asm/kvm_emulate.h>
26#include <asm/esr.h>
27
28#define PSTATE_FAULT_BITS_64 (PSR_MODE_EL1h | PSR_A_BIT | PSR_F_BIT | \
29 PSR_I_BIT | PSR_D_BIT)
30
31#define CURRENT_EL_SP_EL0_VECTOR 0x0
32#define CURRENT_EL_SP_ELx_VECTOR 0x200
33#define LOWER_EL_AArch64_VECTOR 0x400
34#define LOWER_EL_AArch32_VECTOR 0x600
35
36static void prepare_fault32(struct kvm_vcpu *vcpu, u32 mode, u32 vect_offset)
37{
38 unsigned long cpsr;
39 unsigned long new_spsr_value = *vcpu_cpsr(vcpu);
40 bool is_thumb = (new_spsr_value & COMPAT_PSR_T_BIT);
41 u32 return_offset = (is_thumb) ? 4 : 0;
42 u32 sctlr = vcpu_cp15(vcpu, c1_SCTLR);
43
44 cpsr = mode | COMPAT_PSR_I_BIT;
45
46 if (sctlr & (1 << 30))
47 cpsr |= COMPAT_PSR_T_BIT;
48 if (sctlr & (1 << 25))
49 cpsr |= COMPAT_PSR_E_BIT;
50
51 *vcpu_cpsr(vcpu) = cpsr;
52
53 /* Note: These now point to the banked copies */
54 *vcpu_spsr(vcpu) = new_spsr_value;
55 *vcpu_reg32(vcpu, 14) = *vcpu_pc(vcpu) + return_offset;
56
57 /* Branch to exception vector */
58 if (sctlr & (1 << 13))
59 vect_offset += 0xffff0000;
60 else /* always have security exceptions */
61 vect_offset += vcpu_cp15(vcpu, c12_VBAR);
62
63 *vcpu_pc(vcpu) = vect_offset;
64}
65
66static void inject_undef32(struct kvm_vcpu *vcpu)
67{
68 prepare_fault32(vcpu, COMPAT_PSR_MODE_UND, 4);
69}
70
71/*
72 * Modelled after TakeDataAbortException() and TakePrefetchAbortException
73 * pseudocode.
74 */
75static void inject_abt32(struct kvm_vcpu *vcpu, bool is_pabt,
76 unsigned long addr)
77{
78 u32 vect_offset;
79 u32 *far, *fsr;
80 bool is_lpae;
81
82 if (is_pabt) {
83 vect_offset = 12;
84 far = &vcpu_cp15(vcpu, c6_IFAR);
85 fsr = &vcpu_cp15(vcpu, c5_IFSR);
86 } else { /* !iabt */
87 vect_offset = 16;
88 far = &vcpu_cp15(vcpu, c6_DFAR);
89 fsr = &vcpu_cp15(vcpu, c5_DFSR);
90 }
91
92 prepare_fault32(vcpu, COMPAT_PSR_MODE_ABT | COMPAT_PSR_A_BIT, vect_offset);
93
94 *far = addr;
95
96 /* Give the guest an IMPLEMENTATION DEFINED exception */
97 is_lpae = (vcpu_cp15(vcpu, c2_TTBCR) >> 31);
98 if (is_lpae)
99 *fsr = 1 << 9 | 0x34;
100 else
101 *fsr = 0x14;
102}
103
104enum exception_type {
105 except_type_sync = 0,
106 except_type_irq = 0x80,
107 except_type_fiq = 0x100,
108 except_type_serror = 0x180,
109};
110
111static u64 get_except_vector(struct kvm_vcpu *vcpu, enum exception_type type)
112{
113 u64 exc_offset;
114
115 switch (*vcpu_cpsr(vcpu) & (PSR_MODE_MASK | PSR_MODE32_BIT)) {
116 case PSR_MODE_EL1t:
117 exc_offset = CURRENT_EL_SP_EL0_VECTOR;
118 break;
119 case PSR_MODE_EL1h:
120 exc_offset = CURRENT_EL_SP_ELx_VECTOR;
121 break;
122 case PSR_MODE_EL0t:
123 exc_offset = LOWER_EL_AArch64_VECTOR;
124 break;
125 default:
126 exc_offset = LOWER_EL_AArch32_VECTOR;
127 }
128
129 return vcpu_sys_reg(vcpu, VBAR_EL1) + exc_offset + type;
130}
131
132static void inject_abt64(struct kvm_vcpu *vcpu, bool is_iabt, unsigned long addr)
133{
134 unsigned long cpsr = *vcpu_cpsr(vcpu);
135 bool is_aarch32;
136 u32 esr = 0;
137
138 is_aarch32 = vcpu_mode_is_32bit(vcpu);
139
140 *vcpu_spsr(vcpu) = cpsr;
141 *vcpu_elr_el1(vcpu) = *vcpu_pc(vcpu);
142
143 *vcpu_pc(vcpu) = get_except_vector(vcpu, except_type_sync);
144 *vcpu_cpsr(vcpu) = PSTATE_FAULT_BITS_64;
145
146 vcpu_sys_reg(vcpu, FAR_EL1) = addr;
147
148 /*
149 * Build an {i,d}abort, depending on the level and the
150 * instruction set. Report an external synchronous abort.
151 */
152 if (kvm_vcpu_trap_il_is32bit(vcpu))
153 esr |= ESR_ELx_IL;
154
155 /*
156 * Here, the guest runs in AArch64 mode when in EL1. If we get
157 * an AArch32 fault, it means we managed to trap an EL0 fault.
158 */
159 if (is_aarch32 || (cpsr & PSR_MODE_MASK) == PSR_MODE_EL0t)
160 esr |= (ESR_ELx_EC_IABT_LOW << ESR_ELx_EC_SHIFT);
161 else
162 esr |= (ESR_ELx_EC_IABT_CUR << ESR_ELx_EC_SHIFT);
163
164 if (!is_iabt)
165 esr |= ESR_ELx_EC_DABT_LOW;
166
167 vcpu_sys_reg(vcpu, ESR_EL1) = esr | ESR_ELx_FSC_EXTABT;
168}
169
170static void inject_undef64(struct kvm_vcpu *vcpu)
171{
172 unsigned long cpsr = *vcpu_cpsr(vcpu);
173 u32 esr = (ESR_ELx_EC_UNKNOWN << ESR_ELx_EC_SHIFT);
174
175 *vcpu_spsr(vcpu) = cpsr;
176 *vcpu_elr_el1(vcpu) = *vcpu_pc(vcpu);
177
178 *vcpu_pc(vcpu) = get_except_vector(vcpu, except_type_sync);
179 *vcpu_cpsr(vcpu) = PSTATE_FAULT_BITS_64;
180
181 /*
182 * Build an unknown exception, depending on the instruction
183 * set.
184 */
185 if (kvm_vcpu_trap_il_is32bit(vcpu))
186 esr |= ESR_ELx_IL;
187
188 vcpu_sys_reg(vcpu, ESR_EL1) = esr;
189}
190
191/**
192 * kvm_inject_dabt - inject a data abort into the guest
193 * @vcpu: The VCPU to receive the undefined exception
194 * @addr: The address to report in the DFAR
195 *
196 * It is assumed that this code is called from the VCPU thread and that the
197 * VCPU therefore is not currently executing guest code.
198 */
199void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr)
200{
201 if (!(vcpu->arch.hcr_el2 & HCR_RW))
202 inject_abt32(vcpu, false, addr);
203 else
204 inject_abt64(vcpu, false, addr);
205}
206
207/**
208 * kvm_inject_pabt - inject a prefetch abort into the guest
209 * @vcpu: The VCPU to receive the undefined exception
210 * @addr: The address to report in the DFAR
211 *
212 * It is assumed that this code is called from the VCPU thread and that the
213 * VCPU therefore is not currently executing guest code.
214 */
215void kvm_inject_pabt(struct kvm_vcpu *vcpu, unsigned long addr)
216{
217 if (!(vcpu->arch.hcr_el2 & HCR_RW))
218 inject_abt32(vcpu, true, addr);
219 else
220 inject_abt64(vcpu, true, addr);
221}
222
223/**
224 * kvm_inject_undefined - inject an undefined instruction into the guest
225 *
226 * It is assumed that this code is called from the VCPU thread and that the
227 * VCPU therefore is not currently executing guest code.
228 */
229void kvm_inject_undefined(struct kvm_vcpu *vcpu)
230{
231 if (!(vcpu->arch.hcr_el2 & HCR_RW))
232 inject_undef32(vcpu);
233 else
234 inject_undef64(vcpu);
235}