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1// SPDX-License-Identifier: GPL-2.0-or-later
2/**
3 * Microchip ENCX24J600 ethernet driver
4 *
5 * Copyright (C) 2015 Gridpoint
6 * Author: Jon Ringle <jringle@gridpoint.com>
7 */
8
9#include <linux/device.h>
10#include <linux/errno.h>
11#include <linux/etherdevice.h>
12#include <linux/ethtool.h>
13#include <linux/interrupt.h>
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/netdevice.h>
17#include <linux/regmap.h>
18#include <linux/skbuff.h>
19#include <linux/spi/spi.h>
20
21#include "encx24j600_hw.h"
22
23#define DRV_NAME "encx24j600"
24#define DRV_VERSION "1.0"
25
26#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
27static int debug = -1;
28module_param(debug, int, 0000);
29MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
30
31/* SRAM memory layout:
32 *
33 * 0x0000-0x05ff TX buffers 1.5KB (1*1536) reside in the GP area in SRAM
34 * 0x0600-0x5fff RX buffers 22.5KB (15*1536) reside in the RX area in SRAM
35 */
36#define ENC_TX_BUF_START 0x0000U
37#define ENC_RX_BUF_START 0x0600U
38#define ENC_RX_BUF_END 0x5fffU
39#define ENC_SRAM_SIZE 0x6000U
40
41enum {
42 RXFILTER_NORMAL,
43 RXFILTER_MULTI,
44 RXFILTER_PROMISC
45};
46
47struct encx24j600_priv {
48 struct net_device *ndev;
49 struct mutex lock; /* device access lock */
50 struct encx24j600_context ctx;
51 struct sk_buff *tx_skb;
52 struct task_struct *kworker_task;
53 struct kthread_worker kworker;
54 struct kthread_work tx_work;
55 struct kthread_work setrx_work;
56 u16 next_packet;
57 bool hw_enabled;
58 bool full_duplex;
59 bool autoneg;
60 u16 speed;
61 int rxfilter;
62 u32 msg_enable;
63};
64
65static void dump_packet(const char *msg, int len, const char *data)
66{
67 pr_debug(DRV_NAME ": %s - packet len:%d\n", msg, len);
68 print_hex_dump_bytes("pk data: ", DUMP_PREFIX_OFFSET, data, len);
69}
70
71static void encx24j600_dump_rsv(struct encx24j600_priv *priv, const char *msg,
72 struct rsv *rsv)
73{
74 struct net_device *dev = priv->ndev;
75
76 netdev_info(dev, "RX packet Len:%d\n", rsv->len);
77 netdev_dbg(dev, "%s - NextPk: 0x%04x\n", msg,
78 rsv->next_packet);
79 netdev_dbg(dev, "RxOK: %d, DribbleNibble: %d\n",
80 RSV_GETBIT(rsv->rxstat, RSV_RXOK),
81 RSV_GETBIT(rsv->rxstat, RSV_DRIBBLENIBBLE));
82 netdev_dbg(dev, "CRCErr:%d, LenChkErr: %d, LenOutOfRange: %d\n",
83 RSV_GETBIT(rsv->rxstat, RSV_CRCERROR),
84 RSV_GETBIT(rsv->rxstat, RSV_LENCHECKERR),
85 RSV_GETBIT(rsv->rxstat, RSV_LENOUTOFRANGE));
86 netdev_dbg(dev, "Multicast: %d, Broadcast: %d, LongDropEvent: %d, CarrierEvent: %d\n",
87 RSV_GETBIT(rsv->rxstat, RSV_RXMULTICAST),
88 RSV_GETBIT(rsv->rxstat, RSV_RXBROADCAST),
89 RSV_GETBIT(rsv->rxstat, RSV_RXLONGEVDROPEV),
90 RSV_GETBIT(rsv->rxstat, RSV_CARRIEREV));
91 netdev_dbg(dev, "ControlFrame: %d, PauseFrame: %d, UnknownOp: %d, VLanTagFrame: %d\n",
92 RSV_GETBIT(rsv->rxstat, RSV_RXCONTROLFRAME),
93 RSV_GETBIT(rsv->rxstat, RSV_RXPAUSEFRAME),
94 RSV_GETBIT(rsv->rxstat, RSV_RXUNKNOWNOPCODE),
95 RSV_GETBIT(rsv->rxstat, RSV_RXTYPEVLAN));
96}
97
98static u16 encx24j600_read_reg(struct encx24j600_priv *priv, u8 reg)
99{
100 struct net_device *dev = priv->ndev;
101 unsigned int val = 0;
102 int ret = regmap_read(priv->ctx.regmap, reg, &val);
103
104 if (unlikely(ret))
105 netif_err(priv, drv, dev, "%s: error %d reading reg %02x\n",
106 __func__, ret, reg);
107 return val;
108}
109
110static void encx24j600_write_reg(struct encx24j600_priv *priv, u8 reg, u16 val)
111{
112 struct net_device *dev = priv->ndev;
113 int ret = regmap_write(priv->ctx.regmap, reg, val);
114
115 if (unlikely(ret))
116 netif_err(priv, drv, dev, "%s: error %d writing reg %02x=%04x\n",
117 __func__, ret, reg, val);
118}
119
120static void encx24j600_update_reg(struct encx24j600_priv *priv, u8 reg,
121 u16 mask, u16 val)
122{
123 struct net_device *dev = priv->ndev;
124 int ret = regmap_update_bits(priv->ctx.regmap, reg, mask, val);
125
126 if (unlikely(ret))
127 netif_err(priv, drv, dev, "%s: error %d updating reg %02x=%04x~%04x\n",
128 __func__, ret, reg, val, mask);
129}
130
131static u16 encx24j600_read_phy(struct encx24j600_priv *priv, u8 reg)
132{
133 struct net_device *dev = priv->ndev;
134 unsigned int val = 0;
135 int ret = regmap_read(priv->ctx.phymap, reg, &val);
136
137 if (unlikely(ret))
138 netif_err(priv, drv, dev, "%s: error %d reading %02x\n",
139 __func__, ret, reg);
140 return val;
141}
142
143static void encx24j600_write_phy(struct encx24j600_priv *priv, u8 reg, u16 val)
144{
145 struct net_device *dev = priv->ndev;
146 int ret = regmap_write(priv->ctx.phymap, reg, val);
147
148 if (unlikely(ret))
149 netif_err(priv, drv, dev, "%s: error %d writing reg %02x=%04x\n",
150 __func__, ret, reg, val);
151}
152
153static void encx24j600_clr_bits(struct encx24j600_priv *priv, u8 reg, u16 mask)
154{
155 encx24j600_update_reg(priv, reg, mask, 0);
156}
157
158static void encx24j600_set_bits(struct encx24j600_priv *priv, u8 reg, u16 mask)
159{
160 encx24j600_update_reg(priv, reg, mask, mask);
161}
162
163static void encx24j600_cmd(struct encx24j600_priv *priv, u8 cmd)
164{
165 struct net_device *dev = priv->ndev;
166 int ret = regmap_write(priv->ctx.regmap, cmd, 0);
167
168 if (unlikely(ret))
169 netif_err(priv, drv, dev, "%s: error %d with cmd %02x\n",
170 __func__, ret, cmd);
171}
172
173static int encx24j600_raw_read(struct encx24j600_priv *priv, u8 reg, u8 *data,
174 size_t count)
175{
176 int ret;
177
178 mutex_lock(&priv->ctx.mutex);
179 ret = regmap_encx24j600_spi_read(&priv->ctx, reg, data, count);
180 mutex_unlock(&priv->ctx.mutex);
181
182 return ret;
183}
184
185static int encx24j600_raw_write(struct encx24j600_priv *priv, u8 reg,
186 const u8 *data, size_t count)
187{
188 int ret;
189
190 mutex_lock(&priv->ctx.mutex);
191 ret = regmap_encx24j600_spi_write(&priv->ctx, reg, data, count);
192 mutex_unlock(&priv->ctx.mutex);
193
194 return ret;
195}
196
197static void encx24j600_update_phcon1(struct encx24j600_priv *priv)
198{
199 u16 phcon1 = encx24j600_read_phy(priv, PHCON1);
200
201 if (priv->autoneg == AUTONEG_ENABLE) {
202 phcon1 |= ANEN | RENEG;
203 } else {
204 phcon1 &= ~ANEN;
205 if (priv->speed == SPEED_100)
206 phcon1 |= SPD100;
207 else
208 phcon1 &= ~SPD100;
209
210 if (priv->full_duplex)
211 phcon1 |= PFULDPX;
212 else
213 phcon1 &= ~PFULDPX;
214 }
215 encx24j600_write_phy(priv, PHCON1, phcon1);
216}
217
218/* Waits for autonegotiation to complete. */
219static int encx24j600_wait_for_autoneg(struct encx24j600_priv *priv)
220{
221 struct net_device *dev = priv->ndev;
222 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
223 u16 phstat1;
224 u16 estat;
225 int ret = 0;
226
227 phstat1 = encx24j600_read_phy(priv, PHSTAT1);
228 while ((phstat1 & ANDONE) == 0) {
229 if (time_after(jiffies, timeout)) {
230 u16 phstat3;
231
232 netif_notice(priv, drv, dev, "timeout waiting for autoneg done\n");
233
234 priv->autoneg = AUTONEG_DISABLE;
235 phstat3 = encx24j600_read_phy(priv, PHSTAT3);
236 priv->speed = (phstat3 & PHY3SPD100)
237 ? SPEED_100 : SPEED_10;
238 priv->full_duplex = (phstat3 & PHY3DPX) ? 1 : 0;
239 encx24j600_update_phcon1(priv);
240 netif_notice(priv, drv, dev, "Using parallel detection: %s/%s",
241 priv->speed == SPEED_100 ? "100" : "10",
242 priv->full_duplex ? "Full" : "Half");
243
244 return -ETIMEDOUT;
245 }
246 cpu_relax();
247 phstat1 = encx24j600_read_phy(priv, PHSTAT1);
248 }
249
250 estat = encx24j600_read_reg(priv, ESTAT);
251 if (estat & PHYDPX) {
252 encx24j600_set_bits(priv, MACON2, FULDPX);
253 encx24j600_write_reg(priv, MABBIPG, 0x15);
254 } else {
255 encx24j600_clr_bits(priv, MACON2, FULDPX);
256 encx24j600_write_reg(priv, MABBIPG, 0x12);
257 /* Max retransmittions attempt */
258 encx24j600_write_reg(priv, MACLCON, 0x370f);
259 }
260
261 return ret;
262}
263
264/* Access the PHY to determine link status */
265static void encx24j600_check_link_status(struct encx24j600_priv *priv)
266{
267 struct net_device *dev = priv->ndev;
268 u16 estat;
269
270 estat = encx24j600_read_reg(priv, ESTAT);
271
272 if (estat & PHYLNK) {
273 if (priv->autoneg == AUTONEG_ENABLE)
274 encx24j600_wait_for_autoneg(priv);
275
276 netif_carrier_on(dev);
277 netif_info(priv, ifup, dev, "link up\n");
278 } else {
279 netif_info(priv, ifdown, dev, "link down\n");
280
281 /* Re-enable autoneg since we won't know what we might be
282 * connected to when the link is brought back up again.
283 */
284 priv->autoneg = AUTONEG_ENABLE;
285 priv->full_duplex = true;
286 priv->speed = SPEED_100;
287 netif_carrier_off(dev);
288 }
289}
290
291static void encx24j600_int_link_handler(struct encx24j600_priv *priv)
292{
293 struct net_device *dev = priv->ndev;
294
295 netif_dbg(priv, intr, dev, "%s", __func__);
296 encx24j600_check_link_status(priv);
297 encx24j600_clr_bits(priv, EIR, LINKIF);
298}
299
300static void encx24j600_tx_complete(struct encx24j600_priv *priv, bool err)
301{
302 struct net_device *dev = priv->ndev;
303
304 if (!priv->tx_skb) {
305 BUG();
306 return;
307 }
308
309 mutex_lock(&priv->lock);
310
311 if (err)
312 dev->stats.tx_errors++;
313 else
314 dev->stats.tx_packets++;
315
316 dev->stats.tx_bytes += priv->tx_skb->len;
317
318 encx24j600_clr_bits(priv, EIR, TXIF | TXABTIF);
319
320 netif_dbg(priv, tx_done, dev, "TX Done%s\n", err ? ": Err" : "");
321
322 dev_kfree_skb(priv->tx_skb);
323 priv->tx_skb = NULL;
324
325 netif_wake_queue(dev);
326
327 mutex_unlock(&priv->lock);
328}
329
330static int encx24j600_receive_packet(struct encx24j600_priv *priv,
331 struct rsv *rsv)
332{
333 struct net_device *dev = priv->ndev;
334 struct sk_buff *skb = netdev_alloc_skb(dev, rsv->len + NET_IP_ALIGN);
335
336 if (!skb) {
337 pr_err_ratelimited("RX: OOM: packet dropped\n");
338 dev->stats.rx_dropped++;
339 return -ENOMEM;
340 }
341 skb_reserve(skb, NET_IP_ALIGN);
342 encx24j600_raw_read(priv, RRXDATA, skb_put(skb, rsv->len), rsv->len);
343
344 if (netif_msg_pktdata(priv))
345 dump_packet("RX", skb->len, skb->data);
346
347 skb->dev = dev;
348 skb->protocol = eth_type_trans(skb, dev);
349 skb->ip_summed = CHECKSUM_COMPLETE;
350
351 /* Maintain stats */
352 dev->stats.rx_packets++;
353 dev->stats.rx_bytes += rsv->len;
354
355 netif_rx(skb);
356
357 return 0;
358}
359
360static void encx24j600_rx_packets(struct encx24j600_priv *priv, u8 packet_count)
361{
362 struct net_device *dev = priv->ndev;
363
364 while (packet_count--) {
365 struct rsv rsv;
366 u16 newrxtail;
367
368 encx24j600_write_reg(priv, ERXRDPT, priv->next_packet);
369 encx24j600_raw_read(priv, RRXDATA, (u8 *)&rsv, sizeof(rsv));
370
371 if (netif_msg_rx_status(priv))
372 encx24j600_dump_rsv(priv, __func__, &rsv);
373
374 if (!RSV_GETBIT(rsv.rxstat, RSV_RXOK) ||
375 (rsv.len > MAX_FRAMELEN)) {
376 netif_err(priv, rx_err, dev, "RX Error %04x\n",
377 rsv.rxstat);
378 dev->stats.rx_errors++;
379
380 if (RSV_GETBIT(rsv.rxstat, RSV_CRCERROR))
381 dev->stats.rx_crc_errors++;
382 if (RSV_GETBIT(rsv.rxstat, RSV_LENCHECKERR))
383 dev->stats.rx_frame_errors++;
384 if (rsv.len > MAX_FRAMELEN)
385 dev->stats.rx_over_errors++;
386 } else {
387 encx24j600_receive_packet(priv, &rsv);
388 }
389
390 priv->next_packet = rsv.next_packet;
391
392 newrxtail = priv->next_packet - 2;
393 if (newrxtail == ENC_RX_BUF_START)
394 newrxtail = SRAM_SIZE - 2;
395
396 encx24j600_cmd(priv, SETPKTDEC);
397 encx24j600_write_reg(priv, ERXTAIL, newrxtail);
398 }
399}
400
401static irqreturn_t encx24j600_isr(int irq, void *dev_id)
402{
403 struct encx24j600_priv *priv = dev_id;
404 struct net_device *dev = priv->ndev;
405 int eir;
406
407 /* Clear interrupts */
408 encx24j600_cmd(priv, CLREIE);
409
410 eir = encx24j600_read_reg(priv, EIR);
411
412 if (eir & LINKIF)
413 encx24j600_int_link_handler(priv);
414
415 if (eir & TXIF)
416 encx24j600_tx_complete(priv, false);
417
418 if (eir & TXABTIF)
419 encx24j600_tx_complete(priv, true);
420
421 if (eir & RXABTIF) {
422 if (eir & PCFULIF) {
423 /* Packet counter is full */
424 netif_err(priv, rx_err, dev, "Packet counter full\n");
425 }
426 dev->stats.rx_dropped++;
427 encx24j600_clr_bits(priv, EIR, RXABTIF);
428 }
429
430 if (eir & PKTIF) {
431 u8 packet_count;
432
433 mutex_lock(&priv->lock);
434
435 packet_count = encx24j600_read_reg(priv, ESTAT) & 0xff;
436 while (packet_count) {
437 encx24j600_rx_packets(priv, packet_count);
438 packet_count = encx24j600_read_reg(priv, ESTAT) & 0xff;
439 }
440
441 mutex_unlock(&priv->lock);
442 }
443
444 /* Enable interrupts */
445 encx24j600_cmd(priv, SETEIE);
446
447 return IRQ_HANDLED;
448}
449
450static int encx24j600_soft_reset(struct encx24j600_priv *priv)
451{
452 int ret = 0;
453 int timeout;
454 u16 eudast;
455
456 /* Write and verify a test value to EUDAST */
457 regcache_cache_bypass(priv->ctx.regmap, true);
458 timeout = 10;
459 do {
460 encx24j600_write_reg(priv, EUDAST, EUDAST_TEST_VAL);
461 eudast = encx24j600_read_reg(priv, EUDAST);
462 usleep_range(25, 100);
463 } while ((eudast != EUDAST_TEST_VAL) && --timeout);
464 regcache_cache_bypass(priv->ctx.regmap, false);
465
466 if (timeout == 0) {
467 ret = -ETIMEDOUT;
468 goto err_out;
469 }
470
471 /* Wait for CLKRDY to become set */
472 timeout = 10;
473 while (!(encx24j600_read_reg(priv, ESTAT) & CLKRDY) && --timeout)
474 usleep_range(25, 100);
475
476 if (timeout == 0) {
477 ret = -ETIMEDOUT;
478 goto err_out;
479 }
480
481 /* Issue a System Reset command */
482 encx24j600_cmd(priv, SETETHRST);
483 usleep_range(25, 100);
484
485 /* Confirm that EUDAST has 0000h after system reset */
486 if (encx24j600_read_reg(priv, EUDAST) != 0) {
487 ret = -EINVAL;
488 goto err_out;
489 }
490
491 /* Wait for PHY register and status bits to become available */
492 usleep_range(256, 1000);
493
494err_out:
495 return ret;
496}
497
498static int encx24j600_hw_reset(struct encx24j600_priv *priv)
499{
500 int ret;
501
502 mutex_lock(&priv->lock);
503 ret = encx24j600_soft_reset(priv);
504 mutex_unlock(&priv->lock);
505
506 return ret;
507}
508
509static void encx24j600_reset_hw_tx(struct encx24j600_priv *priv)
510{
511 encx24j600_set_bits(priv, ECON2, TXRST);
512 encx24j600_clr_bits(priv, ECON2, TXRST);
513}
514
515static void encx24j600_hw_init_tx(struct encx24j600_priv *priv)
516{
517 /* Reset TX */
518 encx24j600_reset_hw_tx(priv);
519
520 /* Clear the TXIF flag if were previously set */
521 encx24j600_clr_bits(priv, EIR, TXIF | TXABTIF);
522
523 /* Write the Tx Buffer pointer */
524 encx24j600_write_reg(priv, EGPWRPT, ENC_TX_BUF_START);
525}
526
527static void encx24j600_hw_init_rx(struct encx24j600_priv *priv)
528{
529 encx24j600_cmd(priv, DISABLERX);
530
531 /* Set up RX packet start address in the SRAM */
532 encx24j600_write_reg(priv, ERXST, ENC_RX_BUF_START);
533
534 /* Preload the RX Data pointer to the beginning of the RX area */
535 encx24j600_write_reg(priv, ERXRDPT, ENC_RX_BUF_START);
536
537 priv->next_packet = ENC_RX_BUF_START;
538
539 /* Set up RX end address in the SRAM */
540 encx24j600_write_reg(priv, ERXTAIL, ENC_SRAM_SIZE - 2);
541
542 /* Reset the user data pointers */
543 encx24j600_write_reg(priv, EUDAST, ENC_SRAM_SIZE);
544 encx24j600_write_reg(priv, EUDAND, ENC_SRAM_SIZE + 1);
545
546 /* Set Max Frame length */
547 encx24j600_write_reg(priv, MAMXFL, MAX_FRAMELEN);
548}
549
550static void encx24j600_dump_config(struct encx24j600_priv *priv,
551 const char *msg)
552{
553 pr_info(DRV_NAME ": %s\n", msg);
554
555 /* CHIP configuration */
556 pr_info(DRV_NAME " ECON1: %04X\n", encx24j600_read_reg(priv, ECON1));
557 pr_info(DRV_NAME " ECON2: %04X\n", encx24j600_read_reg(priv, ECON2));
558 pr_info(DRV_NAME " ERXFCON: %04X\n", encx24j600_read_reg(priv,
559 ERXFCON));
560 pr_info(DRV_NAME " ESTAT: %04X\n", encx24j600_read_reg(priv, ESTAT));
561 pr_info(DRV_NAME " EIR: %04X\n", encx24j600_read_reg(priv, EIR));
562 pr_info(DRV_NAME " EIDLED: %04X\n", encx24j600_read_reg(priv, EIDLED));
563
564 /* MAC layer configuration */
565 pr_info(DRV_NAME " MACON1: %04X\n", encx24j600_read_reg(priv, MACON1));
566 pr_info(DRV_NAME " MACON2: %04X\n", encx24j600_read_reg(priv, MACON2));
567 pr_info(DRV_NAME " MAIPG: %04X\n", encx24j600_read_reg(priv, MAIPG));
568 pr_info(DRV_NAME " MACLCON: %04X\n", encx24j600_read_reg(priv,
569 MACLCON));
570 pr_info(DRV_NAME " MABBIPG: %04X\n", encx24j600_read_reg(priv,
571 MABBIPG));
572
573 /* PHY configuation */
574 pr_info(DRV_NAME " PHCON1: %04X\n", encx24j600_read_phy(priv, PHCON1));
575 pr_info(DRV_NAME " PHCON2: %04X\n", encx24j600_read_phy(priv, PHCON2));
576 pr_info(DRV_NAME " PHANA: %04X\n", encx24j600_read_phy(priv, PHANA));
577 pr_info(DRV_NAME " PHANLPA: %04X\n", encx24j600_read_phy(priv,
578 PHANLPA));
579 pr_info(DRV_NAME " PHANE: %04X\n", encx24j600_read_phy(priv, PHANE));
580 pr_info(DRV_NAME " PHSTAT1: %04X\n", encx24j600_read_phy(priv,
581 PHSTAT1));
582 pr_info(DRV_NAME " PHSTAT2: %04X\n", encx24j600_read_phy(priv,
583 PHSTAT2));
584 pr_info(DRV_NAME " PHSTAT3: %04X\n", encx24j600_read_phy(priv,
585 PHSTAT3));
586}
587
588static void encx24j600_set_rxfilter_mode(struct encx24j600_priv *priv)
589{
590 switch (priv->rxfilter) {
591 case RXFILTER_PROMISC:
592 encx24j600_set_bits(priv, MACON1, PASSALL);
593 encx24j600_write_reg(priv, ERXFCON, UCEN | MCEN | NOTMEEN);
594 break;
595 case RXFILTER_MULTI:
596 encx24j600_clr_bits(priv, MACON1, PASSALL);
597 encx24j600_write_reg(priv, ERXFCON, UCEN | CRCEN | BCEN | MCEN);
598 break;
599 case RXFILTER_NORMAL:
600 default:
601 encx24j600_clr_bits(priv, MACON1, PASSALL);
602 encx24j600_write_reg(priv, ERXFCON, UCEN | CRCEN | BCEN);
603 break;
604 }
605}
606
607static int encx24j600_hw_init(struct encx24j600_priv *priv)
608{
609 int ret = 0;
610 u16 macon2;
611
612 priv->hw_enabled = false;
613
614 /* PHY Leds: link status,
615 * LEDA: Link State + collision events
616 * LEDB: Link State + transmit/receive events
617 */
618 encx24j600_update_reg(priv, EIDLED, 0xff00, 0xcb00);
619
620 /* Loopback disabled */
621 encx24j600_write_reg(priv, MACON1, 0x9);
622
623 /* interpacket gap value */
624 encx24j600_write_reg(priv, MAIPG, 0x0c12);
625
626 /* Write the auto negotiation pattern */
627 encx24j600_write_phy(priv, PHANA, PHANA_DEFAULT);
628
629 encx24j600_update_phcon1(priv);
630 encx24j600_check_link_status(priv);
631
632 macon2 = MACON2_RSV1 | TXCRCEN | PADCFG0 | PADCFG2 | MACON2_DEFER;
633 if ((priv->autoneg == AUTONEG_DISABLE) && priv->full_duplex)
634 macon2 |= FULDPX;
635
636 encx24j600_set_bits(priv, MACON2, macon2);
637
638 priv->rxfilter = RXFILTER_NORMAL;
639 encx24j600_set_rxfilter_mode(priv);
640
641 /* Program the Maximum frame length */
642 encx24j600_write_reg(priv, MAMXFL, MAX_FRAMELEN);
643
644 /* Init Tx pointers */
645 encx24j600_hw_init_tx(priv);
646
647 /* Init Rx pointers */
648 encx24j600_hw_init_rx(priv);
649
650 if (netif_msg_hw(priv))
651 encx24j600_dump_config(priv, "Hw is initialized");
652
653 return ret;
654}
655
656static void encx24j600_hw_enable(struct encx24j600_priv *priv)
657{
658 /* Clear the interrupt flags in case was set */
659 encx24j600_clr_bits(priv, EIR, (PCFULIF | RXABTIF | TXABTIF | TXIF |
660 PKTIF | LINKIF));
661
662 /* Enable the interrupts */
663 encx24j600_write_reg(priv, EIE, (PCFULIE | RXABTIE | TXABTIE | TXIE |
664 PKTIE | LINKIE | INTIE));
665
666 /* Enable RX */
667 encx24j600_cmd(priv, ENABLERX);
668
669 priv->hw_enabled = true;
670}
671
672static void encx24j600_hw_disable(struct encx24j600_priv *priv)
673{
674 /* Disable all interrupts */
675 encx24j600_write_reg(priv, EIE, 0);
676
677 /* Disable RX */
678 encx24j600_cmd(priv, DISABLERX);
679
680 priv->hw_enabled = false;
681}
682
683static int encx24j600_setlink(struct net_device *dev, u8 autoneg, u16 speed,
684 u8 duplex)
685{
686 struct encx24j600_priv *priv = netdev_priv(dev);
687 int ret = 0;
688
689 if (!priv->hw_enabled) {
690 /* link is in low power mode now; duplex setting
691 * will take effect on next encx24j600_hw_init()
692 */
693 if (speed == SPEED_10 || speed == SPEED_100) {
694 priv->autoneg = (autoneg == AUTONEG_ENABLE);
695 priv->full_duplex = (duplex == DUPLEX_FULL);
696 priv->speed = (speed == SPEED_100);
697 } else {
698 netif_warn(priv, link, dev, "unsupported link speed setting\n");
699 /*speeds other than SPEED_10 and SPEED_100 */
700 /*are not supported by chip */
701 ret = -EOPNOTSUPP;
702 }
703 } else {
704 netif_warn(priv, link, dev, "Warning: hw must be disabled to set link mode\n");
705 ret = -EBUSY;
706 }
707 return ret;
708}
709
710static void encx24j600_hw_get_macaddr(struct encx24j600_priv *priv,
711 unsigned char *ethaddr)
712{
713 unsigned short val;
714
715 val = encx24j600_read_reg(priv, MAADR1);
716
717 ethaddr[0] = val & 0x00ff;
718 ethaddr[1] = (val & 0xff00) >> 8;
719
720 val = encx24j600_read_reg(priv, MAADR2);
721
722 ethaddr[2] = val & 0x00ffU;
723 ethaddr[3] = (val & 0xff00U) >> 8;
724
725 val = encx24j600_read_reg(priv, MAADR3);
726
727 ethaddr[4] = val & 0x00ffU;
728 ethaddr[5] = (val & 0xff00U) >> 8;
729}
730
731/* Program the hardware MAC address from dev->dev_addr.*/
732static int encx24j600_set_hw_macaddr(struct net_device *dev)
733{
734 struct encx24j600_priv *priv = netdev_priv(dev);
735
736 if (priv->hw_enabled) {
737 netif_info(priv, drv, dev, "Hardware must be disabled to set Mac address\n");
738 return -EBUSY;
739 }
740
741 mutex_lock(&priv->lock);
742
743 netif_info(priv, drv, dev, "%s: Setting MAC address to %pM\n",
744 dev->name, dev->dev_addr);
745
746 encx24j600_write_reg(priv, MAADR3, (dev->dev_addr[4] |
747 dev->dev_addr[5] << 8));
748 encx24j600_write_reg(priv, MAADR2, (dev->dev_addr[2] |
749 dev->dev_addr[3] << 8));
750 encx24j600_write_reg(priv, MAADR1, (dev->dev_addr[0] |
751 dev->dev_addr[1] << 8));
752
753 mutex_unlock(&priv->lock);
754
755 return 0;
756}
757
758/* Store the new hardware address in dev->dev_addr, and update the MAC.*/
759static int encx24j600_set_mac_address(struct net_device *dev, void *addr)
760{
761 struct sockaddr *address = addr;
762
763 if (netif_running(dev))
764 return -EBUSY;
765 if (!is_valid_ether_addr(address->sa_data))
766 return -EADDRNOTAVAIL;
767
768 memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
769 return encx24j600_set_hw_macaddr(dev);
770}
771
772static int encx24j600_open(struct net_device *dev)
773{
774 struct encx24j600_priv *priv = netdev_priv(dev);
775
776 int ret = request_threaded_irq(priv->ctx.spi->irq, NULL, encx24j600_isr,
777 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
778 DRV_NAME, priv);
779 if (unlikely(ret < 0)) {
780 netdev_err(dev, "request irq %d failed (ret = %d)\n",
781 priv->ctx.spi->irq, ret);
782 return ret;
783 }
784
785 encx24j600_hw_disable(priv);
786 encx24j600_hw_init(priv);
787 encx24j600_hw_enable(priv);
788 netif_start_queue(dev);
789
790 return 0;
791}
792
793static int encx24j600_stop(struct net_device *dev)
794{
795 struct encx24j600_priv *priv = netdev_priv(dev);
796
797 netif_stop_queue(dev);
798 free_irq(priv->ctx.spi->irq, priv);
799 return 0;
800}
801
802static void encx24j600_setrx_proc(struct kthread_work *ws)
803{
804 struct encx24j600_priv *priv =
805 container_of(ws, struct encx24j600_priv, setrx_work);
806
807 mutex_lock(&priv->lock);
808 encx24j600_set_rxfilter_mode(priv);
809 mutex_unlock(&priv->lock);
810}
811
812static void encx24j600_set_multicast_list(struct net_device *dev)
813{
814 struct encx24j600_priv *priv = netdev_priv(dev);
815 int oldfilter = priv->rxfilter;
816
817 if (dev->flags & IFF_PROMISC) {
818 netif_dbg(priv, link, dev, "promiscuous mode\n");
819 priv->rxfilter = RXFILTER_PROMISC;
820 } else if ((dev->flags & IFF_ALLMULTI) || !netdev_mc_empty(dev)) {
821 netif_dbg(priv, link, dev, "%smulticast mode\n",
822 (dev->flags & IFF_ALLMULTI) ? "all-" : "");
823 priv->rxfilter = RXFILTER_MULTI;
824 } else {
825 netif_dbg(priv, link, dev, "normal mode\n");
826 priv->rxfilter = RXFILTER_NORMAL;
827 }
828
829 if (oldfilter != priv->rxfilter)
830 kthread_queue_work(&priv->kworker, &priv->setrx_work);
831}
832
833static void encx24j600_hw_tx(struct encx24j600_priv *priv)
834{
835 struct net_device *dev = priv->ndev;
836
837 netif_info(priv, tx_queued, dev, "TX Packet Len:%d\n",
838 priv->tx_skb->len);
839
840 if (netif_msg_pktdata(priv))
841 dump_packet("TX", priv->tx_skb->len, priv->tx_skb->data);
842
843 if (encx24j600_read_reg(priv, EIR) & TXABTIF)
844 /* Last transmition aborted due to error. Reset TX interface */
845 encx24j600_reset_hw_tx(priv);
846
847 /* Clear the TXIF flag if were previously set */
848 encx24j600_clr_bits(priv, EIR, TXIF);
849
850 /* Set the data pointer to the TX buffer address in the SRAM */
851 encx24j600_write_reg(priv, EGPWRPT, ENC_TX_BUF_START);
852
853 /* Copy the packet into the SRAM */
854 encx24j600_raw_write(priv, WGPDATA, (u8 *)priv->tx_skb->data,
855 priv->tx_skb->len);
856
857 /* Program the Tx buffer start pointer */
858 encx24j600_write_reg(priv, ETXST, ENC_TX_BUF_START);
859
860 /* Program the packet length */
861 encx24j600_write_reg(priv, ETXLEN, priv->tx_skb->len);
862
863 /* Start the transmission */
864 encx24j600_cmd(priv, SETTXRTS);
865}
866
867static void encx24j600_tx_proc(struct kthread_work *ws)
868{
869 struct encx24j600_priv *priv =
870 container_of(ws, struct encx24j600_priv, tx_work);
871
872 mutex_lock(&priv->lock);
873 encx24j600_hw_tx(priv);
874 mutex_unlock(&priv->lock);
875}
876
877static netdev_tx_t encx24j600_tx(struct sk_buff *skb, struct net_device *dev)
878{
879 struct encx24j600_priv *priv = netdev_priv(dev);
880
881 netif_stop_queue(dev);
882
883 /* save the timestamp */
884 netif_trans_update(dev);
885
886 /* Remember the skb for deferred processing */
887 priv->tx_skb = skb;
888
889 kthread_queue_work(&priv->kworker, &priv->tx_work);
890
891 return NETDEV_TX_OK;
892}
893
894/* Deal with a transmit timeout */
895static void encx24j600_tx_timeout(struct net_device *dev)
896{
897 struct encx24j600_priv *priv = netdev_priv(dev);
898
899 netif_err(priv, tx_err, dev, "TX timeout at %ld, latency %ld\n",
900 jiffies, jiffies - dev_trans_start(dev));
901
902 dev->stats.tx_errors++;
903 netif_wake_queue(dev);
904}
905
906static int encx24j600_get_regs_len(struct net_device *dev)
907{
908 return SFR_REG_COUNT;
909}
910
911static void encx24j600_get_regs(struct net_device *dev,
912 struct ethtool_regs *regs, void *p)
913{
914 struct encx24j600_priv *priv = netdev_priv(dev);
915 u16 *buff = p;
916 u8 reg;
917
918 regs->version = 1;
919 mutex_lock(&priv->lock);
920 for (reg = 0; reg < SFR_REG_COUNT; reg += 2) {
921 unsigned int val = 0;
922 /* ignore errors for unreadable registers */
923 regmap_read(priv->ctx.regmap, reg, &val);
924 buff[reg] = val & 0xffff;
925 }
926 mutex_unlock(&priv->lock);
927}
928
929static void encx24j600_get_drvinfo(struct net_device *dev,
930 struct ethtool_drvinfo *info)
931{
932 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
933 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
934 strlcpy(info->bus_info, dev_name(dev->dev.parent),
935 sizeof(info->bus_info));
936}
937
938static int encx24j600_get_link_ksettings(struct net_device *dev,
939 struct ethtool_link_ksettings *cmd)
940{
941 struct encx24j600_priv *priv = netdev_priv(dev);
942 u32 supported;
943
944 supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
945 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
946 SUPPORTED_Autoneg | SUPPORTED_TP;
947
948 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
949 supported);
950
951 cmd->base.speed = priv->speed;
952 cmd->base.duplex = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
953 cmd->base.port = PORT_TP;
954 cmd->base.autoneg = priv->autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
955
956 return 0;
957}
958
959static int
960encx24j600_set_link_ksettings(struct net_device *dev,
961 const struct ethtool_link_ksettings *cmd)
962{
963 return encx24j600_setlink(dev, cmd->base.autoneg,
964 cmd->base.speed, cmd->base.duplex);
965}
966
967static u32 encx24j600_get_msglevel(struct net_device *dev)
968{
969 struct encx24j600_priv *priv = netdev_priv(dev);
970
971 return priv->msg_enable;
972}
973
974static void encx24j600_set_msglevel(struct net_device *dev, u32 val)
975{
976 struct encx24j600_priv *priv = netdev_priv(dev);
977
978 priv->msg_enable = val;
979}
980
981static const struct ethtool_ops encx24j600_ethtool_ops = {
982 .get_drvinfo = encx24j600_get_drvinfo,
983 .get_msglevel = encx24j600_get_msglevel,
984 .set_msglevel = encx24j600_set_msglevel,
985 .get_regs_len = encx24j600_get_regs_len,
986 .get_regs = encx24j600_get_regs,
987 .get_link_ksettings = encx24j600_get_link_ksettings,
988 .set_link_ksettings = encx24j600_set_link_ksettings,
989};
990
991static const struct net_device_ops encx24j600_netdev_ops = {
992 .ndo_open = encx24j600_open,
993 .ndo_stop = encx24j600_stop,
994 .ndo_start_xmit = encx24j600_tx,
995 .ndo_set_rx_mode = encx24j600_set_multicast_list,
996 .ndo_set_mac_address = encx24j600_set_mac_address,
997 .ndo_tx_timeout = encx24j600_tx_timeout,
998 .ndo_validate_addr = eth_validate_addr,
999};
1000
1001static int encx24j600_spi_probe(struct spi_device *spi)
1002{
1003 int ret;
1004
1005 struct net_device *ndev;
1006 struct encx24j600_priv *priv;
1007 u16 eidled;
1008
1009 ndev = alloc_etherdev(sizeof(struct encx24j600_priv));
1010
1011 if (!ndev) {
1012 ret = -ENOMEM;
1013 goto error_out;
1014 }
1015
1016 priv = netdev_priv(ndev);
1017 spi_set_drvdata(spi, priv);
1018 dev_set_drvdata(&spi->dev, priv);
1019 SET_NETDEV_DEV(ndev, &spi->dev);
1020
1021 priv->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
1022 priv->ndev = ndev;
1023
1024 /* Default configuration PHY configuration */
1025 priv->full_duplex = true;
1026 priv->autoneg = AUTONEG_ENABLE;
1027 priv->speed = SPEED_100;
1028
1029 priv->ctx.spi = spi;
1030 devm_regmap_init_encx24j600(&spi->dev, &priv->ctx);
1031 ndev->irq = spi->irq;
1032 ndev->netdev_ops = &encx24j600_netdev_ops;
1033
1034 mutex_init(&priv->lock);
1035
1036 /* Reset device and check if it is connected */
1037 if (encx24j600_hw_reset(priv)) {
1038 netif_err(priv, probe, ndev,
1039 DRV_NAME ": Chip is not detected\n");
1040 ret = -EIO;
1041 goto out_free;
1042 }
1043
1044 /* Initialize the device HW to the consistent state */
1045 if (encx24j600_hw_init(priv)) {
1046 netif_err(priv, probe, ndev,
1047 DRV_NAME ": HW initialization error\n");
1048 ret = -EIO;
1049 goto out_free;
1050 }
1051
1052 kthread_init_worker(&priv->kworker);
1053 kthread_init_work(&priv->tx_work, encx24j600_tx_proc);
1054 kthread_init_work(&priv->setrx_work, encx24j600_setrx_proc);
1055
1056 priv->kworker_task = kthread_run(kthread_worker_fn, &priv->kworker,
1057 "encx24j600");
1058
1059 if (IS_ERR(priv->kworker_task)) {
1060 ret = PTR_ERR(priv->kworker_task);
1061 goto out_free;
1062 }
1063
1064 /* Get the MAC address from the chip */
1065 encx24j600_hw_get_macaddr(priv, ndev->dev_addr);
1066
1067 ndev->ethtool_ops = &encx24j600_ethtool_ops;
1068
1069 ret = register_netdev(ndev);
1070 if (unlikely(ret)) {
1071 netif_err(priv, probe, ndev, "Error %d initializing card encx24j600 card\n",
1072 ret);
1073 goto out_free;
1074 }
1075
1076 eidled = encx24j600_read_reg(priv, EIDLED);
1077 if (((eidled & DEVID_MASK) >> DEVID_SHIFT) != ENCX24J600_DEV_ID) {
1078 ret = -EINVAL;
1079 goto out_unregister;
1080 }
1081
1082 netif_info(priv, probe, ndev, "Silicon rev ID: 0x%02x\n",
1083 (eidled & REVID_MASK) >> REVID_SHIFT);
1084
1085 netif_info(priv, drv, priv->ndev, "MAC address %pM\n", ndev->dev_addr);
1086
1087 return ret;
1088
1089out_unregister:
1090 unregister_netdev(priv->ndev);
1091out_free:
1092 free_netdev(ndev);
1093
1094error_out:
1095 return ret;
1096}
1097
1098static int encx24j600_spi_remove(struct spi_device *spi)
1099{
1100 struct encx24j600_priv *priv = dev_get_drvdata(&spi->dev);
1101
1102 unregister_netdev(priv->ndev);
1103
1104 free_netdev(priv->ndev);
1105
1106 return 0;
1107}
1108
1109static const struct spi_device_id encx24j600_spi_id_table[] = {
1110 { .name = "encx24j600" },
1111 { /* sentinel */ }
1112};
1113MODULE_DEVICE_TABLE(spi, encx24j600_spi_id_table);
1114
1115static struct spi_driver encx24j600_spi_net_driver = {
1116 .driver = {
1117 .name = DRV_NAME,
1118 .owner = THIS_MODULE,
1119 .bus = &spi_bus_type,
1120 },
1121 .probe = encx24j600_spi_probe,
1122 .remove = encx24j600_spi_remove,
1123 .id_table = encx24j600_spi_id_table,
1124};
1125
1126static int __init encx24j600_init(void)
1127{
1128 return spi_register_driver(&encx24j600_spi_net_driver);
1129}
1130module_init(encx24j600_init);
1131
1132static void encx24j600_exit(void)
1133{
1134 spi_unregister_driver(&encx24j600_spi_net_driver);
1135}
1136module_exit(encx24j600_exit);
1137
1138MODULE_DESCRIPTION(DRV_NAME " ethernet driver");
1139MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1140MODULE_LICENSE("GPL");
1141MODULE_ALIAS("spi:" DRV_NAME);
1/**
2 * Microchip ENCX24J600 ethernet driver
3 *
4 * Copyright (C) 2015 Gridpoint
5 * Author: Jon Ringle <jringle@gridpoint.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 */
13
14#include <linux/device.h>
15#include <linux/errno.h>
16#include <linux/etherdevice.h>
17#include <linux/ethtool.h>
18#include <linux/interrupt.h>
19#include <linux/kernel.h>
20#include <linux/module.h>
21#include <linux/netdevice.h>
22#include <linux/regmap.h>
23#include <linux/skbuff.h>
24#include <linux/spi/spi.h>
25
26#include "encx24j600_hw.h"
27
28#define DRV_NAME "encx24j600"
29#define DRV_VERSION "1.0"
30
31#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
32static int debug = -1;
33module_param(debug, int, 0000);
34MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
35
36/* SRAM memory layout:
37 *
38 * 0x0000-0x05ff TX buffers 1.5KB (1*1536) reside in the GP area in SRAM
39 * 0x0600-0x5fff RX buffers 22.5KB (15*1536) reside in the RX area in SRAM
40 */
41#define ENC_TX_BUF_START 0x0000U
42#define ENC_RX_BUF_START 0x0600U
43#define ENC_RX_BUF_END 0x5fffU
44#define ENC_SRAM_SIZE 0x6000U
45
46enum {
47 RXFILTER_NORMAL,
48 RXFILTER_MULTI,
49 RXFILTER_PROMISC
50};
51
52struct encx24j600_priv {
53 struct net_device *ndev;
54 struct mutex lock; /* device access lock */
55 struct encx24j600_context ctx;
56 struct sk_buff *tx_skb;
57 struct task_struct *kworker_task;
58 struct kthread_worker kworker;
59 struct kthread_work tx_work;
60 struct kthread_work setrx_work;
61 u16 next_packet;
62 bool hw_enabled;
63 bool full_duplex;
64 bool autoneg;
65 u16 speed;
66 int rxfilter;
67 u32 msg_enable;
68};
69
70static void dump_packet(const char *msg, int len, const char *data)
71{
72 pr_debug(DRV_NAME ": %s - packet len:%d\n", msg, len);
73 print_hex_dump_bytes("pk data: ", DUMP_PREFIX_OFFSET, data, len);
74}
75
76static void encx24j600_dump_rsv(struct encx24j600_priv *priv, const char *msg,
77 struct rsv *rsv)
78{
79 struct net_device *dev = priv->ndev;
80
81 netdev_info(dev, "RX packet Len:%d\n", rsv->len);
82 netdev_dbg(dev, "%s - NextPk: 0x%04x\n", msg,
83 rsv->next_packet);
84 netdev_dbg(dev, "RxOK: %d, DribbleNibble: %d\n",
85 RSV_GETBIT(rsv->rxstat, RSV_RXOK),
86 RSV_GETBIT(rsv->rxstat, RSV_DRIBBLENIBBLE));
87 netdev_dbg(dev, "CRCErr:%d, LenChkErr: %d, LenOutOfRange: %d\n",
88 RSV_GETBIT(rsv->rxstat, RSV_CRCERROR),
89 RSV_GETBIT(rsv->rxstat, RSV_LENCHECKERR),
90 RSV_GETBIT(rsv->rxstat, RSV_LENOUTOFRANGE));
91 netdev_dbg(dev, "Multicast: %d, Broadcast: %d, LongDropEvent: %d, CarrierEvent: %d\n",
92 RSV_GETBIT(rsv->rxstat, RSV_RXMULTICAST),
93 RSV_GETBIT(rsv->rxstat, RSV_RXBROADCAST),
94 RSV_GETBIT(rsv->rxstat, RSV_RXLONGEVDROPEV),
95 RSV_GETBIT(rsv->rxstat, RSV_CARRIEREV));
96 netdev_dbg(dev, "ControlFrame: %d, PauseFrame: %d, UnknownOp: %d, VLanTagFrame: %d\n",
97 RSV_GETBIT(rsv->rxstat, RSV_RXCONTROLFRAME),
98 RSV_GETBIT(rsv->rxstat, RSV_RXPAUSEFRAME),
99 RSV_GETBIT(rsv->rxstat, RSV_RXUNKNOWNOPCODE),
100 RSV_GETBIT(rsv->rxstat, RSV_RXTYPEVLAN));
101}
102
103static u16 encx24j600_read_reg(struct encx24j600_priv *priv, u8 reg)
104{
105 struct net_device *dev = priv->ndev;
106 unsigned int val = 0;
107 int ret = regmap_read(priv->ctx.regmap, reg, &val);
108
109 if (unlikely(ret))
110 netif_err(priv, drv, dev, "%s: error %d reading reg %02x\n",
111 __func__, ret, reg);
112 return val;
113}
114
115static void encx24j600_write_reg(struct encx24j600_priv *priv, u8 reg, u16 val)
116{
117 struct net_device *dev = priv->ndev;
118 int ret = regmap_write(priv->ctx.regmap, reg, val);
119
120 if (unlikely(ret))
121 netif_err(priv, drv, dev, "%s: error %d writing reg %02x=%04x\n",
122 __func__, ret, reg, val);
123}
124
125static void encx24j600_update_reg(struct encx24j600_priv *priv, u8 reg,
126 u16 mask, u16 val)
127{
128 struct net_device *dev = priv->ndev;
129 int ret = regmap_update_bits(priv->ctx.regmap, reg, mask, val);
130
131 if (unlikely(ret))
132 netif_err(priv, drv, dev, "%s: error %d updating reg %02x=%04x~%04x\n",
133 __func__, ret, reg, val, mask);
134}
135
136static u16 encx24j600_read_phy(struct encx24j600_priv *priv, u8 reg)
137{
138 struct net_device *dev = priv->ndev;
139 unsigned int val = 0;
140 int ret = regmap_read(priv->ctx.phymap, reg, &val);
141
142 if (unlikely(ret))
143 netif_err(priv, drv, dev, "%s: error %d reading %02x\n",
144 __func__, ret, reg);
145 return val;
146}
147
148static void encx24j600_write_phy(struct encx24j600_priv *priv, u8 reg, u16 val)
149{
150 struct net_device *dev = priv->ndev;
151 int ret = regmap_write(priv->ctx.phymap, reg, val);
152
153 if (unlikely(ret))
154 netif_err(priv, drv, dev, "%s: error %d writing reg %02x=%04x\n",
155 __func__, ret, reg, val);
156}
157
158static void encx24j600_clr_bits(struct encx24j600_priv *priv, u8 reg, u16 mask)
159{
160 encx24j600_update_reg(priv, reg, mask, 0);
161}
162
163static void encx24j600_set_bits(struct encx24j600_priv *priv, u8 reg, u16 mask)
164{
165 encx24j600_update_reg(priv, reg, mask, mask);
166}
167
168static void encx24j600_cmd(struct encx24j600_priv *priv, u8 cmd)
169{
170 struct net_device *dev = priv->ndev;
171 int ret = regmap_write(priv->ctx.regmap, cmd, 0);
172
173 if (unlikely(ret))
174 netif_err(priv, drv, dev, "%s: error %d with cmd %02x\n",
175 __func__, ret, cmd);
176}
177
178static int encx24j600_raw_read(struct encx24j600_priv *priv, u8 reg, u8 *data,
179 size_t count)
180{
181 int ret;
182
183 mutex_lock(&priv->ctx.mutex);
184 ret = regmap_encx24j600_spi_read(&priv->ctx, reg, data, count);
185 mutex_unlock(&priv->ctx.mutex);
186
187 return ret;
188}
189
190static int encx24j600_raw_write(struct encx24j600_priv *priv, u8 reg,
191 const u8 *data, size_t count)
192{
193 int ret;
194
195 mutex_lock(&priv->ctx.mutex);
196 ret = regmap_encx24j600_spi_write(&priv->ctx, reg, data, count);
197 mutex_unlock(&priv->ctx.mutex);
198
199 return ret;
200}
201
202static void encx24j600_update_phcon1(struct encx24j600_priv *priv)
203{
204 u16 phcon1 = encx24j600_read_phy(priv, PHCON1);
205
206 if (priv->autoneg == AUTONEG_ENABLE) {
207 phcon1 |= ANEN | RENEG;
208 } else {
209 phcon1 &= ~ANEN;
210 if (priv->speed == SPEED_100)
211 phcon1 |= SPD100;
212 else
213 phcon1 &= ~SPD100;
214
215 if (priv->full_duplex)
216 phcon1 |= PFULDPX;
217 else
218 phcon1 &= ~PFULDPX;
219 }
220 encx24j600_write_phy(priv, PHCON1, phcon1);
221}
222
223/* Waits for autonegotiation to complete. */
224static int encx24j600_wait_for_autoneg(struct encx24j600_priv *priv)
225{
226 struct net_device *dev = priv->ndev;
227 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
228 u16 phstat1;
229 u16 estat;
230 int ret = 0;
231
232 phstat1 = encx24j600_read_phy(priv, PHSTAT1);
233 while ((phstat1 & ANDONE) == 0) {
234 if (time_after(jiffies, timeout)) {
235 u16 phstat3;
236
237 netif_notice(priv, drv, dev, "timeout waiting for autoneg done\n");
238
239 priv->autoneg = AUTONEG_DISABLE;
240 phstat3 = encx24j600_read_phy(priv, PHSTAT3);
241 priv->speed = (phstat3 & PHY3SPD100)
242 ? SPEED_100 : SPEED_10;
243 priv->full_duplex = (phstat3 & PHY3DPX) ? 1 : 0;
244 encx24j600_update_phcon1(priv);
245 netif_notice(priv, drv, dev, "Using parallel detection: %s/%s",
246 priv->speed == SPEED_100 ? "100" : "10",
247 priv->full_duplex ? "Full" : "Half");
248
249 return -ETIMEDOUT;
250 }
251 cpu_relax();
252 phstat1 = encx24j600_read_phy(priv, PHSTAT1);
253 }
254
255 estat = encx24j600_read_reg(priv, ESTAT);
256 if (estat & PHYDPX) {
257 encx24j600_set_bits(priv, MACON2, FULDPX);
258 encx24j600_write_reg(priv, MABBIPG, 0x15);
259 } else {
260 encx24j600_clr_bits(priv, MACON2, FULDPX);
261 encx24j600_write_reg(priv, MABBIPG, 0x12);
262 /* Max retransmittions attempt */
263 encx24j600_write_reg(priv, MACLCON, 0x370f);
264 }
265
266 return ret;
267}
268
269/* Access the PHY to determine link status */
270static void encx24j600_check_link_status(struct encx24j600_priv *priv)
271{
272 struct net_device *dev = priv->ndev;
273 u16 estat;
274
275 estat = encx24j600_read_reg(priv, ESTAT);
276
277 if (estat & PHYLNK) {
278 if (priv->autoneg == AUTONEG_ENABLE)
279 encx24j600_wait_for_autoneg(priv);
280
281 netif_carrier_on(dev);
282 netif_info(priv, ifup, dev, "link up\n");
283 } else {
284 netif_info(priv, ifdown, dev, "link down\n");
285
286 /* Re-enable autoneg since we won't know what we might be
287 * connected to when the link is brought back up again.
288 */
289 priv->autoneg = AUTONEG_ENABLE;
290 priv->full_duplex = true;
291 priv->speed = SPEED_100;
292 netif_carrier_off(dev);
293 }
294}
295
296static void encx24j600_int_link_handler(struct encx24j600_priv *priv)
297{
298 struct net_device *dev = priv->ndev;
299
300 netif_dbg(priv, intr, dev, "%s", __func__);
301 encx24j600_check_link_status(priv);
302 encx24j600_clr_bits(priv, EIR, LINKIF);
303}
304
305static void encx24j600_tx_complete(struct encx24j600_priv *priv, bool err)
306{
307 struct net_device *dev = priv->ndev;
308
309 if (!priv->tx_skb) {
310 BUG();
311 return;
312 }
313
314 mutex_lock(&priv->lock);
315
316 if (err)
317 dev->stats.tx_errors++;
318 else
319 dev->stats.tx_packets++;
320
321 dev->stats.tx_bytes += priv->tx_skb->len;
322
323 encx24j600_clr_bits(priv, EIR, TXIF | TXABTIF);
324
325 netif_dbg(priv, tx_done, dev, "TX Done%s\n", err ? ": Err" : "");
326
327 dev_kfree_skb(priv->tx_skb);
328 priv->tx_skb = NULL;
329
330 netif_wake_queue(dev);
331
332 mutex_unlock(&priv->lock);
333}
334
335static int encx24j600_receive_packet(struct encx24j600_priv *priv,
336 struct rsv *rsv)
337{
338 struct net_device *dev = priv->ndev;
339 struct sk_buff *skb = netdev_alloc_skb(dev, rsv->len + NET_IP_ALIGN);
340
341 if (!skb) {
342 pr_err_ratelimited("RX: OOM: packet dropped\n");
343 dev->stats.rx_dropped++;
344 return -ENOMEM;
345 }
346 skb_reserve(skb, NET_IP_ALIGN);
347 encx24j600_raw_read(priv, RRXDATA, skb_put(skb, rsv->len), rsv->len);
348
349 if (netif_msg_pktdata(priv))
350 dump_packet("RX", skb->len, skb->data);
351
352 skb->dev = dev;
353 skb->protocol = eth_type_trans(skb, dev);
354 skb->ip_summed = CHECKSUM_COMPLETE;
355
356 /* Maintain stats */
357 dev->stats.rx_packets++;
358 dev->stats.rx_bytes += rsv->len;
359
360 netif_rx(skb);
361
362 return 0;
363}
364
365static void encx24j600_rx_packets(struct encx24j600_priv *priv, u8 packet_count)
366{
367 struct net_device *dev = priv->ndev;
368
369 while (packet_count--) {
370 struct rsv rsv;
371 u16 newrxtail;
372
373 encx24j600_write_reg(priv, ERXRDPT, priv->next_packet);
374 encx24j600_raw_read(priv, RRXDATA, (u8 *)&rsv, sizeof(rsv));
375
376 if (netif_msg_rx_status(priv))
377 encx24j600_dump_rsv(priv, __func__, &rsv);
378
379 if (!RSV_GETBIT(rsv.rxstat, RSV_RXOK) ||
380 (rsv.len > MAX_FRAMELEN)) {
381 netif_err(priv, rx_err, dev, "RX Error %04x\n",
382 rsv.rxstat);
383 dev->stats.rx_errors++;
384
385 if (RSV_GETBIT(rsv.rxstat, RSV_CRCERROR))
386 dev->stats.rx_crc_errors++;
387 if (RSV_GETBIT(rsv.rxstat, RSV_LENCHECKERR))
388 dev->stats.rx_frame_errors++;
389 if (rsv.len > MAX_FRAMELEN)
390 dev->stats.rx_over_errors++;
391 } else {
392 encx24j600_receive_packet(priv, &rsv);
393 }
394
395 priv->next_packet = rsv.next_packet;
396
397 newrxtail = priv->next_packet - 2;
398 if (newrxtail == ENC_RX_BUF_START)
399 newrxtail = SRAM_SIZE - 2;
400
401 encx24j600_cmd(priv, SETPKTDEC);
402 encx24j600_write_reg(priv, ERXTAIL, newrxtail);
403 }
404}
405
406static irqreturn_t encx24j600_isr(int irq, void *dev_id)
407{
408 struct encx24j600_priv *priv = dev_id;
409 struct net_device *dev = priv->ndev;
410 int eir;
411
412 /* Clear interrupts */
413 encx24j600_cmd(priv, CLREIE);
414
415 eir = encx24j600_read_reg(priv, EIR);
416
417 if (eir & LINKIF)
418 encx24j600_int_link_handler(priv);
419
420 if (eir & TXIF)
421 encx24j600_tx_complete(priv, false);
422
423 if (eir & TXABTIF)
424 encx24j600_tx_complete(priv, true);
425
426 if (eir & RXABTIF) {
427 if (eir & PCFULIF) {
428 /* Packet counter is full */
429 netif_err(priv, rx_err, dev, "Packet counter full\n");
430 }
431 dev->stats.rx_dropped++;
432 encx24j600_clr_bits(priv, EIR, RXABTIF);
433 }
434
435 if (eir & PKTIF) {
436 u8 packet_count;
437
438 mutex_lock(&priv->lock);
439
440 packet_count = encx24j600_read_reg(priv, ESTAT) & 0xff;
441 while (packet_count) {
442 encx24j600_rx_packets(priv, packet_count);
443 packet_count = encx24j600_read_reg(priv, ESTAT) & 0xff;
444 }
445
446 mutex_unlock(&priv->lock);
447 }
448
449 /* Enable interrupts */
450 encx24j600_cmd(priv, SETEIE);
451
452 return IRQ_HANDLED;
453}
454
455static int encx24j600_soft_reset(struct encx24j600_priv *priv)
456{
457 int ret = 0;
458 int timeout;
459 u16 eudast;
460
461 /* Write and verify a test value to EUDAST */
462 regcache_cache_bypass(priv->ctx.regmap, true);
463 timeout = 10;
464 do {
465 encx24j600_write_reg(priv, EUDAST, EUDAST_TEST_VAL);
466 eudast = encx24j600_read_reg(priv, EUDAST);
467 usleep_range(25, 100);
468 } while ((eudast != EUDAST_TEST_VAL) && --timeout);
469 regcache_cache_bypass(priv->ctx.regmap, false);
470
471 if (timeout == 0) {
472 ret = -ETIMEDOUT;
473 goto err_out;
474 }
475
476 /* Wait for CLKRDY to become set */
477 timeout = 10;
478 while (!(encx24j600_read_reg(priv, ESTAT) & CLKRDY) && --timeout)
479 usleep_range(25, 100);
480
481 if (timeout == 0) {
482 ret = -ETIMEDOUT;
483 goto err_out;
484 }
485
486 /* Issue a System Reset command */
487 encx24j600_cmd(priv, SETETHRST);
488 usleep_range(25, 100);
489
490 /* Confirm that EUDAST has 0000h after system reset */
491 if (encx24j600_read_reg(priv, EUDAST) != 0) {
492 ret = -EINVAL;
493 goto err_out;
494 }
495
496 /* Wait for PHY register and status bits to become available */
497 usleep_range(256, 1000);
498
499err_out:
500 return ret;
501}
502
503static int encx24j600_hw_reset(struct encx24j600_priv *priv)
504{
505 int ret;
506
507 mutex_lock(&priv->lock);
508 ret = encx24j600_soft_reset(priv);
509 mutex_unlock(&priv->lock);
510
511 return ret;
512}
513
514static void encx24j600_reset_hw_tx(struct encx24j600_priv *priv)
515{
516 encx24j600_set_bits(priv, ECON2, TXRST);
517 encx24j600_clr_bits(priv, ECON2, TXRST);
518}
519
520static void encx24j600_hw_init_tx(struct encx24j600_priv *priv)
521{
522 /* Reset TX */
523 encx24j600_reset_hw_tx(priv);
524
525 /* Clear the TXIF flag if were previously set */
526 encx24j600_clr_bits(priv, EIR, TXIF | TXABTIF);
527
528 /* Write the Tx Buffer pointer */
529 encx24j600_write_reg(priv, EGPWRPT, ENC_TX_BUF_START);
530}
531
532static void encx24j600_hw_init_rx(struct encx24j600_priv *priv)
533{
534 encx24j600_cmd(priv, DISABLERX);
535
536 /* Set up RX packet start address in the SRAM */
537 encx24j600_write_reg(priv, ERXST, ENC_RX_BUF_START);
538
539 /* Preload the RX Data pointer to the beginning of the RX area */
540 encx24j600_write_reg(priv, ERXRDPT, ENC_RX_BUF_START);
541
542 priv->next_packet = ENC_RX_BUF_START;
543
544 /* Set up RX end address in the SRAM */
545 encx24j600_write_reg(priv, ERXTAIL, ENC_SRAM_SIZE - 2);
546
547 /* Reset the user data pointers */
548 encx24j600_write_reg(priv, EUDAST, ENC_SRAM_SIZE);
549 encx24j600_write_reg(priv, EUDAND, ENC_SRAM_SIZE + 1);
550
551 /* Set Max Frame length */
552 encx24j600_write_reg(priv, MAMXFL, MAX_FRAMELEN);
553}
554
555static void encx24j600_dump_config(struct encx24j600_priv *priv,
556 const char *msg)
557{
558 pr_info(DRV_NAME ": %s\n", msg);
559
560 /* CHIP configuration */
561 pr_info(DRV_NAME " ECON1: %04X\n", encx24j600_read_reg(priv, ECON1));
562 pr_info(DRV_NAME " ECON2: %04X\n", encx24j600_read_reg(priv, ECON2));
563 pr_info(DRV_NAME " ERXFCON: %04X\n", encx24j600_read_reg(priv,
564 ERXFCON));
565 pr_info(DRV_NAME " ESTAT: %04X\n", encx24j600_read_reg(priv, ESTAT));
566 pr_info(DRV_NAME " EIR: %04X\n", encx24j600_read_reg(priv, EIR));
567 pr_info(DRV_NAME " EIDLED: %04X\n", encx24j600_read_reg(priv, EIDLED));
568
569 /* MAC layer configuration */
570 pr_info(DRV_NAME " MACON1: %04X\n", encx24j600_read_reg(priv, MACON1));
571 pr_info(DRV_NAME " MACON2: %04X\n", encx24j600_read_reg(priv, MACON2));
572 pr_info(DRV_NAME " MAIPG: %04X\n", encx24j600_read_reg(priv, MAIPG));
573 pr_info(DRV_NAME " MACLCON: %04X\n", encx24j600_read_reg(priv,
574 MACLCON));
575 pr_info(DRV_NAME " MABBIPG: %04X\n", encx24j600_read_reg(priv,
576 MABBIPG));
577
578 /* PHY configuation */
579 pr_info(DRV_NAME " PHCON1: %04X\n", encx24j600_read_phy(priv, PHCON1));
580 pr_info(DRV_NAME " PHCON2: %04X\n", encx24j600_read_phy(priv, PHCON2));
581 pr_info(DRV_NAME " PHANA: %04X\n", encx24j600_read_phy(priv, PHANA));
582 pr_info(DRV_NAME " PHANLPA: %04X\n", encx24j600_read_phy(priv,
583 PHANLPA));
584 pr_info(DRV_NAME " PHANE: %04X\n", encx24j600_read_phy(priv, PHANE));
585 pr_info(DRV_NAME " PHSTAT1: %04X\n", encx24j600_read_phy(priv,
586 PHSTAT1));
587 pr_info(DRV_NAME " PHSTAT2: %04X\n", encx24j600_read_phy(priv,
588 PHSTAT2));
589 pr_info(DRV_NAME " PHSTAT3: %04X\n", encx24j600_read_phy(priv,
590 PHSTAT3));
591}
592
593static void encx24j600_set_rxfilter_mode(struct encx24j600_priv *priv)
594{
595 switch (priv->rxfilter) {
596 case RXFILTER_PROMISC:
597 encx24j600_set_bits(priv, MACON1, PASSALL);
598 encx24j600_write_reg(priv, ERXFCON, UCEN | MCEN | NOTMEEN);
599 break;
600 case RXFILTER_MULTI:
601 encx24j600_clr_bits(priv, MACON1, PASSALL);
602 encx24j600_write_reg(priv, ERXFCON, UCEN | CRCEN | BCEN | MCEN);
603 break;
604 case RXFILTER_NORMAL:
605 default:
606 encx24j600_clr_bits(priv, MACON1, PASSALL);
607 encx24j600_write_reg(priv, ERXFCON, UCEN | CRCEN | BCEN);
608 break;
609 }
610}
611
612static int encx24j600_hw_init(struct encx24j600_priv *priv)
613{
614 int ret = 0;
615 u16 macon2;
616
617 priv->hw_enabled = false;
618
619 /* PHY Leds: link status,
620 * LEDA: Link State + collision events
621 * LEDB: Link State + transmit/receive events
622 */
623 encx24j600_update_reg(priv, EIDLED, 0xff00, 0xcb00);
624
625 /* Loopback disabled */
626 encx24j600_write_reg(priv, MACON1, 0x9);
627
628 /* interpacket gap value */
629 encx24j600_write_reg(priv, MAIPG, 0x0c12);
630
631 /* Write the auto negotiation pattern */
632 encx24j600_write_phy(priv, PHANA, PHANA_DEFAULT);
633
634 encx24j600_update_phcon1(priv);
635 encx24j600_check_link_status(priv);
636
637 macon2 = MACON2_RSV1 | TXCRCEN | PADCFG0 | PADCFG2 | MACON2_DEFER;
638 if ((priv->autoneg == AUTONEG_DISABLE) && priv->full_duplex)
639 macon2 |= FULDPX;
640
641 encx24j600_set_bits(priv, MACON2, macon2);
642
643 priv->rxfilter = RXFILTER_NORMAL;
644 encx24j600_set_rxfilter_mode(priv);
645
646 /* Program the Maximum frame length */
647 encx24j600_write_reg(priv, MAMXFL, MAX_FRAMELEN);
648
649 /* Init Tx pointers */
650 encx24j600_hw_init_tx(priv);
651
652 /* Init Rx pointers */
653 encx24j600_hw_init_rx(priv);
654
655 if (netif_msg_hw(priv))
656 encx24j600_dump_config(priv, "Hw is initialized");
657
658 return ret;
659}
660
661static void encx24j600_hw_enable(struct encx24j600_priv *priv)
662{
663 /* Clear the interrupt flags in case was set */
664 encx24j600_clr_bits(priv, EIR, (PCFULIF | RXABTIF | TXABTIF | TXIF |
665 PKTIF | LINKIF));
666
667 /* Enable the interrupts */
668 encx24j600_write_reg(priv, EIE, (PCFULIE | RXABTIE | TXABTIE | TXIE |
669 PKTIE | LINKIE | INTIE));
670
671 /* Enable RX */
672 encx24j600_cmd(priv, ENABLERX);
673
674 priv->hw_enabled = true;
675}
676
677static void encx24j600_hw_disable(struct encx24j600_priv *priv)
678{
679 /* Disable all interrupts */
680 encx24j600_write_reg(priv, EIE, 0);
681
682 /* Disable RX */
683 encx24j600_cmd(priv, DISABLERX);
684
685 priv->hw_enabled = false;
686}
687
688static int encx24j600_setlink(struct net_device *dev, u8 autoneg, u16 speed,
689 u8 duplex)
690{
691 struct encx24j600_priv *priv = netdev_priv(dev);
692 int ret = 0;
693
694 if (!priv->hw_enabled) {
695 /* link is in low power mode now; duplex setting
696 * will take effect on next encx24j600_hw_init()
697 */
698 if (speed == SPEED_10 || speed == SPEED_100) {
699 priv->autoneg = (autoneg == AUTONEG_ENABLE);
700 priv->full_duplex = (duplex == DUPLEX_FULL);
701 priv->speed = (speed == SPEED_100);
702 } else {
703 netif_warn(priv, link, dev, "unsupported link speed setting\n");
704 /*speeds other than SPEED_10 and SPEED_100 */
705 /*are not supported by chip */
706 ret = -EOPNOTSUPP;
707 }
708 } else {
709 netif_warn(priv, link, dev, "Warning: hw must be disabled to set link mode\n");
710 ret = -EBUSY;
711 }
712 return ret;
713}
714
715static void encx24j600_hw_get_macaddr(struct encx24j600_priv *priv,
716 unsigned char *ethaddr)
717{
718 unsigned short val;
719
720 val = encx24j600_read_reg(priv, MAADR1);
721
722 ethaddr[0] = val & 0x00ff;
723 ethaddr[1] = (val & 0xff00) >> 8;
724
725 val = encx24j600_read_reg(priv, MAADR2);
726
727 ethaddr[2] = val & 0x00ffU;
728 ethaddr[3] = (val & 0xff00U) >> 8;
729
730 val = encx24j600_read_reg(priv, MAADR3);
731
732 ethaddr[4] = val & 0x00ffU;
733 ethaddr[5] = (val & 0xff00U) >> 8;
734}
735
736/* Program the hardware MAC address from dev->dev_addr.*/
737static int encx24j600_set_hw_macaddr(struct net_device *dev)
738{
739 struct encx24j600_priv *priv = netdev_priv(dev);
740
741 if (priv->hw_enabled) {
742 netif_info(priv, drv, dev, "Hardware must be disabled to set Mac address\n");
743 return -EBUSY;
744 }
745
746 mutex_lock(&priv->lock);
747
748 netif_info(priv, drv, dev, "%s: Setting MAC address to %pM\n",
749 dev->name, dev->dev_addr);
750
751 encx24j600_write_reg(priv, MAADR3, (dev->dev_addr[4] |
752 dev->dev_addr[5] << 8));
753 encx24j600_write_reg(priv, MAADR2, (dev->dev_addr[2] |
754 dev->dev_addr[3] << 8));
755 encx24j600_write_reg(priv, MAADR1, (dev->dev_addr[0] |
756 dev->dev_addr[1] << 8));
757
758 mutex_unlock(&priv->lock);
759
760 return 0;
761}
762
763/* Store the new hardware address in dev->dev_addr, and update the MAC.*/
764static int encx24j600_set_mac_address(struct net_device *dev, void *addr)
765{
766 struct sockaddr *address = addr;
767
768 if (netif_running(dev))
769 return -EBUSY;
770 if (!is_valid_ether_addr(address->sa_data))
771 return -EADDRNOTAVAIL;
772
773 memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
774 return encx24j600_set_hw_macaddr(dev);
775}
776
777static int encx24j600_open(struct net_device *dev)
778{
779 struct encx24j600_priv *priv = netdev_priv(dev);
780
781 int ret = request_threaded_irq(priv->ctx.spi->irq, NULL, encx24j600_isr,
782 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
783 DRV_NAME, priv);
784 if (unlikely(ret < 0)) {
785 netdev_err(dev, "request irq %d failed (ret = %d)\n",
786 priv->ctx.spi->irq, ret);
787 return ret;
788 }
789
790 encx24j600_hw_disable(priv);
791 encx24j600_hw_init(priv);
792 encx24j600_hw_enable(priv);
793 netif_start_queue(dev);
794
795 return 0;
796}
797
798static int encx24j600_stop(struct net_device *dev)
799{
800 struct encx24j600_priv *priv = netdev_priv(dev);
801
802 netif_stop_queue(dev);
803 free_irq(priv->ctx.spi->irq, priv);
804 return 0;
805}
806
807static void encx24j600_setrx_proc(struct kthread_work *ws)
808{
809 struct encx24j600_priv *priv =
810 container_of(ws, struct encx24j600_priv, setrx_work);
811
812 mutex_lock(&priv->lock);
813 encx24j600_set_rxfilter_mode(priv);
814 mutex_unlock(&priv->lock);
815}
816
817static void encx24j600_set_multicast_list(struct net_device *dev)
818{
819 struct encx24j600_priv *priv = netdev_priv(dev);
820 int oldfilter = priv->rxfilter;
821
822 if (dev->flags & IFF_PROMISC) {
823 netif_dbg(priv, link, dev, "promiscuous mode\n");
824 priv->rxfilter = RXFILTER_PROMISC;
825 } else if ((dev->flags & IFF_ALLMULTI) || !netdev_mc_empty(dev)) {
826 netif_dbg(priv, link, dev, "%smulticast mode\n",
827 (dev->flags & IFF_ALLMULTI) ? "all-" : "");
828 priv->rxfilter = RXFILTER_MULTI;
829 } else {
830 netif_dbg(priv, link, dev, "normal mode\n");
831 priv->rxfilter = RXFILTER_NORMAL;
832 }
833
834 if (oldfilter != priv->rxfilter)
835 kthread_queue_work(&priv->kworker, &priv->setrx_work);
836}
837
838static void encx24j600_hw_tx(struct encx24j600_priv *priv)
839{
840 struct net_device *dev = priv->ndev;
841
842 netif_info(priv, tx_queued, dev, "TX Packet Len:%d\n",
843 priv->tx_skb->len);
844
845 if (netif_msg_pktdata(priv))
846 dump_packet("TX", priv->tx_skb->len, priv->tx_skb->data);
847
848 if (encx24j600_read_reg(priv, EIR) & TXABTIF)
849 /* Last transmition aborted due to error. Reset TX interface */
850 encx24j600_reset_hw_tx(priv);
851
852 /* Clear the TXIF flag if were previously set */
853 encx24j600_clr_bits(priv, EIR, TXIF);
854
855 /* Set the data pointer to the TX buffer address in the SRAM */
856 encx24j600_write_reg(priv, EGPWRPT, ENC_TX_BUF_START);
857
858 /* Copy the packet into the SRAM */
859 encx24j600_raw_write(priv, WGPDATA, (u8 *)priv->tx_skb->data,
860 priv->tx_skb->len);
861
862 /* Program the Tx buffer start pointer */
863 encx24j600_write_reg(priv, ETXST, ENC_TX_BUF_START);
864
865 /* Program the packet length */
866 encx24j600_write_reg(priv, ETXLEN, priv->tx_skb->len);
867
868 /* Start the transmission */
869 encx24j600_cmd(priv, SETTXRTS);
870}
871
872static void encx24j600_tx_proc(struct kthread_work *ws)
873{
874 struct encx24j600_priv *priv =
875 container_of(ws, struct encx24j600_priv, tx_work);
876
877 mutex_lock(&priv->lock);
878 encx24j600_hw_tx(priv);
879 mutex_unlock(&priv->lock);
880}
881
882static netdev_tx_t encx24j600_tx(struct sk_buff *skb, struct net_device *dev)
883{
884 struct encx24j600_priv *priv = netdev_priv(dev);
885
886 netif_stop_queue(dev);
887
888 /* save the timestamp */
889 netif_trans_update(dev);
890
891 /* Remember the skb for deferred processing */
892 priv->tx_skb = skb;
893
894 kthread_queue_work(&priv->kworker, &priv->tx_work);
895
896 return NETDEV_TX_OK;
897}
898
899/* Deal with a transmit timeout */
900static void encx24j600_tx_timeout(struct net_device *dev)
901{
902 struct encx24j600_priv *priv = netdev_priv(dev);
903
904 netif_err(priv, tx_err, dev, "TX timeout at %ld, latency %ld\n",
905 jiffies, jiffies - dev_trans_start(dev));
906
907 dev->stats.tx_errors++;
908 netif_wake_queue(dev);
909}
910
911static int encx24j600_get_regs_len(struct net_device *dev)
912{
913 return SFR_REG_COUNT;
914}
915
916static void encx24j600_get_regs(struct net_device *dev,
917 struct ethtool_regs *regs, void *p)
918{
919 struct encx24j600_priv *priv = netdev_priv(dev);
920 u16 *buff = p;
921 u8 reg;
922
923 regs->version = 1;
924 mutex_lock(&priv->lock);
925 for (reg = 0; reg < SFR_REG_COUNT; reg += 2) {
926 unsigned int val = 0;
927 /* ignore errors for unreadable registers */
928 regmap_read(priv->ctx.regmap, reg, &val);
929 buff[reg] = val & 0xffff;
930 }
931 mutex_unlock(&priv->lock);
932}
933
934static void encx24j600_get_drvinfo(struct net_device *dev,
935 struct ethtool_drvinfo *info)
936{
937 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
938 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
939 strlcpy(info->bus_info, dev_name(dev->dev.parent),
940 sizeof(info->bus_info));
941}
942
943static int encx24j600_get_link_ksettings(struct net_device *dev,
944 struct ethtool_link_ksettings *cmd)
945{
946 struct encx24j600_priv *priv = netdev_priv(dev);
947 u32 supported;
948
949 supported = SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
950 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
951 SUPPORTED_Autoneg | SUPPORTED_TP;
952
953 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
954 supported);
955
956 cmd->base.speed = priv->speed;
957 cmd->base.duplex = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
958 cmd->base.port = PORT_TP;
959 cmd->base.autoneg = priv->autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE;
960
961 return 0;
962}
963
964static int
965encx24j600_set_link_ksettings(struct net_device *dev,
966 const struct ethtool_link_ksettings *cmd)
967{
968 return encx24j600_setlink(dev, cmd->base.autoneg,
969 cmd->base.speed, cmd->base.duplex);
970}
971
972static u32 encx24j600_get_msglevel(struct net_device *dev)
973{
974 struct encx24j600_priv *priv = netdev_priv(dev);
975
976 return priv->msg_enable;
977}
978
979static void encx24j600_set_msglevel(struct net_device *dev, u32 val)
980{
981 struct encx24j600_priv *priv = netdev_priv(dev);
982
983 priv->msg_enable = val;
984}
985
986static const struct ethtool_ops encx24j600_ethtool_ops = {
987 .get_drvinfo = encx24j600_get_drvinfo,
988 .get_msglevel = encx24j600_get_msglevel,
989 .set_msglevel = encx24j600_set_msglevel,
990 .get_regs_len = encx24j600_get_regs_len,
991 .get_regs = encx24j600_get_regs,
992 .get_link_ksettings = encx24j600_get_link_ksettings,
993 .set_link_ksettings = encx24j600_set_link_ksettings,
994};
995
996static const struct net_device_ops encx24j600_netdev_ops = {
997 .ndo_open = encx24j600_open,
998 .ndo_stop = encx24j600_stop,
999 .ndo_start_xmit = encx24j600_tx,
1000 .ndo_set_rx_mode = encx24j600_set_multicast_list,
1001 .ndo_set_mac_address = encx24j600_set_mac_address,
1002 .ndo_tx_timeout = encx24j600_tx_timeout,
1003 .ndo_validate_addr = eth_validate_addr,
1004};
1005
1006static int encx24j600_spi_probe(struct spi_device *spi)
1007{
1008 int ret;
1009
1010 struct net_device *ndev;
1011 struct encx24j600_priv *priv;
1012 u16 eidled;
1013
1014 ndev = alloc_etherdev(sizeof(struct encx24j600_priv));
1015
1016 if (!ndev) {
1017 ret = -ENOMEM;
1018 goto error_out;
1019 }
1020
1021 priv = netdev_priv(ndev);
1022 spi_set_drvdata(spi, priv);
1023 dev_set_drvdata(&spi->dev, priv);
1024 SET_NETDEV_DEV(ndev, &spi->dev);
1025
1026 priv->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
1027 priv->ndev = ndev;
1028
1029 /* Default configuration PHY configuration */
1030 priv->full_duplex = true;
1031 priv->autoneg = AUTONEG_ENABLE;
1032 priv->speed = SPEED_100;
1033
1034 priv->ctx.spi = spi;
1035 devm_regmap_init_encx24j600(&spi->dev, &priv->ctx);
1036 ndev->irq = spi->irq;
1037 ndev->netdev_ops = &encx24j600_netdev_ops;
1038
1039 mutex_init(&priv->lock);
1040
1041 /* Reset device and check if it is connected */
1042 if (encx24j600_hw_reset(priv)) {
1043 netif_err(priv, probe, ndev,
1044 DRV_NAME ": Chip is not detected\n");
1045 ret = -EIO;
1046 goto out_free;
1047 }
1048
1049 /* Initialize the device HW to the consistent state */
1050 if (encx24j600_hw_init(priv)) {
1051 netif_err(priv, probe, ndev,
1052 DRV_NAME ": HW initialization error\n");
1053 ret = -EIO;
1054 goto out_free;
1055 }
1056
1057 kthread_init_worker(&priv->kworker);
1058 kthread_init_work(&priv->tx_work, encx24j600_tx_proc);
1059 kthread_init_work(&priv->setrx_work, encx24j600_setrx_proc);
1060
1061 priv->kworker_task = kthread_run(kthread_worker_fn, &priv->kworker,
1062 "encx24j600");
1063
1064 if (IS_ERR(priv->kworker_task)) {
1065 ret = PTR_ERR(priv->kworker_task);
1066 goto out_free;
1067 }
1068
1069 /* Get the MAC address from the chip */
1070 encx24j600_hw_get_macaddr(priv, ndev->dev_addr);
1071
1072 ndev->ethtool_ops = &encx24j600_ethtool_ops;
1073
1074 ret = register_netdev(ndev);
1075 if (unlikely(ret)) {
1076 netif_err(priv, probe, ndev, "Error %d initializing card encx24j600 card\n",
1077 ret);
1078 goto out_free;
1079 }
1080
1081 eidled = encx24j600_read_reg(priv, EIDLED);
1082 if (((eidled & DEVID_MASK) >> DEVID_SHIFT) != ENCX24J600_DEV_ID) {
1083 ret = -EINVAL;
1084 goto out_unregister;
1085 }
1086
1087 netif_info(priv, probe, ndev, "Silicon rev ID: 0x%02x\n",
1088 (eidled & REVID_MASK) >> REVID_SHIFT);
1089
1090 netif_info(priv, drv, priv->ndev, "MAC address %pM\n", ndev->dev_addr);
1091
1092 return ret;
1093
1094out_unregister:
1095 unregister_netdev(priv->ndev);
1096out_free:
1097 free_netdev(ndev);
1098
1099error_out:
1100 return ret;
1101}
1102
1103static int encx24j600_spi_remove(struct spi_device *spi)
1104{
1105 struct encx24j600_priv *priv = dev_get_drvdata(&spi->dev);
1106
1107 unregister_netdev(priv->ndev);
1108
1109 free_netdev(priv->ndev);
1110
1111 return 0;
1112}
1113
1114static const struct spi_device_id encx24j600_spi_id_table[] = {
1115 { .name = "encx24j600" },
1116 { /* sentinel */ }
1117};
1118MODULE_DEVICE_TABLE(spi, encx24j600_spi_id_table);
1119
1120static struct spi_driver encx24j600_spi_net_driver = {
1121 .driver = {
1122 .name = DRV_NAME,
1123 .owner = THIS_MODULE,
1124 .bus = &spi_bus_type,
1125 },
1126 .probe = encx24j600_spi_probe,
1127 .remove = encx24j600_spi_remove,
1128 .id_table = encx24j600_spi_id_table,
1129};
1130
1131static int __init encx24j600_init(void)
1132{
1133 return spi_register_driver(&encx24j600_spi_net_driver);
1134}
1135module_init(encx24j600_init);
1136
1137static void encx24j600_exit(void)
1138{
1139 spi_unregister_driver(&encx24j600_spi_net_driver);
1140}
1141module_exit(encx24j600_exit);
1142
1143MODULE_DESCRIPTION(DRV_NAME " ethernet driver");
1144MODULE_AUTHOR("Jon Ringle <jringle@gridpoint.com>");
1145MODULE_LICENSE("GPL");
1146MODULE_ALIAS("spi:" DRV_NAME);