Loading...
1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * rcar_du_drv.c -- R-Car Display Unit DRM driver
4 *
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
6 *
7 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8 */
9
10#include <linux/clk.h>
11#include <linux/io.h>
12#include <linux/mm.h>
13#include <linux/module.h>
14#include <linux/of_device.h>
15#include <linux/platform_device.h>
16#include <linux/pm.h>
17#include <linux/slab.h>
18#include <linux/wait.h>
19
20#include <drm/drm_atomic_helper.h>
21#include <drm/drm_fb_cma_helper.h>
22#include <drm/drm_fb_helper.h>
23#include <drm/drm_drv.h>
24#include <drm/drm_gem_cma_helper.h>
25#include <drm/drm_probe_helper.h>
26
27#include "rcar_du_drv.h"
28#include "rcar_du_kms.h"
29#include "rcar_du_of.h"
30#include "rcar_du_regs.h"
31
32/* -----------------------------------------------------------------------------
33 * Device Information
34 */
35
36static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
37 .gen = 2,
38 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
39 | RCAR_DU_FEATURE_INTERLACED
40 | RCAR_DU_FEATURE_TVM_SYNC,
41 .channels_mask = BIT(1) | BIT(0),
42 .routes = {
43 /*
44 * R8A774[34] has one RGB output and one LVDS output
45 */
46 [RCAR_DU_OUTPUT_DPAD0] = {
47 .possible_crtcs = BIT(1) | BIT(0),
48 .port = 0,
49 },
50 [RCAR_DU_OUTPUT_LVDS0] = {
51 .possible_crtcs = BIT(0),
52 .port = 1,
53 },
54 },
55 .num_lvds = 1,
56};
57
58static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
59 .gen = 2,
60 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
61 | RCAR_DU_FEATURE_INTERLACED
62 | RCAR_DU_FEATURE_TVM_SYNC,
63 .channels_mask = BIT(1) | BIT(0),
64 .routes = {
65 /*
66 * R8A7745 has two RGB outputs
67 */
68 [RCAR_DU_OUTPUT_DPAD0] = {
69 .possible_crtcs = BIT(0),
70 .port = 0,
71 },
72 [RCAR_DU_OUTPUT_DPAD1] = {
73 .possible_crtcs = BIT(1),
74 .port = 1,
75 },
76 },
77};
78
79static const struct rcar_du_device_info rzg1_du_r8a77470_info = {
80 .gen = 2,
81 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
82 | RCAR_DU_FEATURE_INTERLACED
83 | RCAR_DU_FEATURE_TVM_SYNC,
84 .channels_mask = BIT(1) | BIT(0),
85 .routes = {
86 /*
87 * R8A77470 has two RGB outputs, one LVDS output, and
88 * one (currently unsupported) analog video output
89 */
90 [RCAR_DU_OUTPUT_DPAD0] = {
91 .possible_crtcs = BIT(0),
92 .port = 0,
93 },
94 [RCAR_DU_OUTPUT_DPAD1] = {
95 .possible_crtcs = BIT(1),
96 .port = 1,
97 },
98 [RCAR_DU_OUTPUT_LVDS0] = {
99 .possible_crtcs = BIT(0) | BIT(1),
100 .port = 2,
101 },
102 },
103};
104
105static const struct rcar_du_device_info rcar_du_r8a774a1_info = {
106 .gen = 3,
107 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
108 | RCAR_DU_FEATURE_VSP1_SOURCE
109 | RCAR_DU_FEATURE_INTERLACED
110 | RCAR_DU_FEATURE_TVM_SYNC,
111 .channels_mask = BIT(2) | BIT(1) | BIT(0),
112 .routes = {
113 /*
114 * R8A774A1 has one RGB output, one LVDS output and one HDMI
115 * output.
116 */
117 [RCAR_DU_OUTPUT_DPAD0] = {
118 .possible_crtcs = BIT(2),
119 .port = 0,
120 },
121 [RCAR_DU_OUTPUT_HDMI0] = {
122 .possible_crtcs = BIT(1),
123 .port = 1,
124 },
125 [RCAR_DU_OUTPUT_LVDS0] = {
126 .possible_crtcs = BIT(0),
127 .port = 2,
128 },
129 },
130 .num_lvds = 1,
131 .dpll_mask = BIT(1),
132};
133
134static const struct rcar_du_device_info rcar_du_r8a774c0_info = {
135 .gen = 3,
136 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
137 | RCAR_DU_FEATURE_VSP1_SOURCE,
138 .channels_mask = BIT(1) | BIT(0),
139 .routes = {
140 /*
141 * R8A774C0 has one RGB output and two LVDS outputs
142 */
143 [RCAR_DU_OUTPUT_DPAD0] = {
144 .possible_crtcs = BIT(0) | BIT(1),
145 .port = 0,
146 },
147 [RCAR_DU_OUTPUT_LVDS0] = {
148 .possible_crtcs = BIT(0),
149 .port = 1,
150 },
151 [RCAR_DU_OUTPUT_LVDS1] = {
152 .possible_crtcs = BIT(1),
153 .port = 2,
154 },
155 },
156 .num_lvds = 2,
157 .lvds_clk_mask = BIT(1) | BIT(0),
158};
159
160static const struct rcar_du_device_info rcar_du_r8a7779_info = {
161 .gen = 1,
162 .features = RCAR_DU_FEATURE_INTERLACED
163 | RCAR_DU_FEATURE_TVM_SYNC,
164 .channels_mask = BIT(1) | BIT(0),
165 .routes = {
166 /*
167 * R8A7779 has two RGB outputs and one (currently unsupported)
168 * TCON output.
169 */
170 [RCAR_DU_OUTPUT_DPAD0] = {
171 .possible_crtcs = BIT(0),
172 .port = 0,
173 },
174 [RCAR_DU_OUTPUT_DPAD1] = {
175 .possible_crtcs = BIT(1) | BIT(0),
176 .port = 1,
177 },
178 },
179};
180
181static const struct rcar_du_device_info rcar_du_r8a7790_info = {
182 .gen = 2,
183 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
184 | RCAR_DU_FEATURE_INTERLACED
185 | RCAR_DU_FEATURE_TVM_SYNC,
186 .quirks = RCAR_DU_QUIRK_ALIGN_128B,
187 .channels_mask = BIT(2) | BIT(1) | BIT(0),
188 .routes = {
189 /*
190 * R8A7790 has one RGB output, two LVDS outputs and one
191 * (currently unsupported) TCON output.
192 */
193 [RCAR_DU_OUTPUT_DPAD0] = {
194 .possible_crtcs = BIT(2) | BIT(1) | BIT(0),
195 .port = 0,
196 },
197 [RCAR_DU_OUTPUT_LVDS0] = {
198 .possible_crtcs = BIT(0),
199 .port = 1,
200 },
201 [RCAR_DU_OUTPUT_LVDS1] = {
202 .possible_crtcs = BIT(2) | BIT(1),
203 .port = 2,
204 },
205 },
206 .num_lvds = 2,
207};
208
209/* M2-W (r8a7791) and M2-N (r8a7793) are identical */
210static const struct rcar_du_device_info rcar_du_r8a7791_info = {
211 .gen = 2,
212 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
213 | RCAR_DU_FEATURE_INTERLACED
214 | RCAR_DU_FEATURE_TVM_SYNC,
215 .channels_mask = BIT(1) | BIT(0),
216 .routes = {
217 /*
218 * R8A779[13] has one RGB output, one LVDS output and one
219 * (currently unsupported) TCON output.
220 */
221 [RCAR_DU_OUTPUT_DPAD0] = {
222 .possible_crtcs = BIT(1) | BIT(0),
223 .port = 0,
224 },
225 [RCAR_DU_OUTPUT_LVDS0] = {
226 .possible_crtcs = BIT(0),
227 .port = 1,
228 },
229 },
230 .num_lvds = 1,
231};
232
233static const struct rcar_du_device_info rcar_du_r8a7792_info = {
234 .gen = 2,
235 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
236 | RCAR_DU_FEATURE_INTERLACED
237 | RCAR_DU_FEATURE_TVM_SYNC,
238 .channels_mask = BIT(1) | BIT(0),
239 .routes = {
240 /* R8A7792 has two RGB outputs. */
241 [RCAR_DU_OUTPUT_DPAD0] = {
242 .possible_crtcs = BIT(0),
243 .port = 0,
244 },
245 [RCAR_DU_OUTPUT_DPAD1] = {
246 .possible_crtcs = BIT(1),
247 .port = 1,
248 },
249 },
250};
251
252static const struct rcar_du_device_info rcar_du_r8a7794_info = {
253 .gen = 2,
254 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
255 | RCAR_DU_FEATURE_INTERLACED
256 | RCAR_DU_FEATURE_TVM_SYNC,
257 .channels_mask = BIT(1) | BIT(0),
258 .routes = {
259 /*
260 * R8A7794 has two RGB outputs and one (currently unsupported)
261 * TCON output.
262 */
263 [RCAR_DU_OUTPUT_DPAD0] = {
264 .possible_crtcs = BIT(0),
265 .port = 0,
266 },
267 [RCAR_DU_OUTPUT_DPAD1] = {
268 .possible_crtcs = BIT(1),
269 .port = 1,
270 },
271 },
272};
273
274static const struct rcar_du_device_info rcar_du_r8a7795_info = {
275 .gen = 3,
276 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
277 | RCAR_DU_FEATURE_VSP1_SOURCE
278 | RCAR_DU_FEATURE_INTERLACED
279 | RCAR_DU_FEATURE_TVM_SYNC,
280 .channels_mask = BIT(3) | BIT(2) | BIT(1) | BIT(0),
281 .routes = {
282 /*
283 * R8A7795 has one RGB output, two HDMI outputs and one
284 * LVDS output.
285 */
286 [RCAR_DU_OUTPUT_DPAD0] = {
287 .possible_crtcs = BIT(3),
288 .port = 0,
289 },
290 [RCAR_DU_OUTPUT_HDMI0] = {
291 .possible_crtcs = BIT(1),
292 .port = 1,
293 },
294 [RCAR_DU_OUTPUT_HDMI1] = {
295 .possible_crtcs = BIT(2),
296 .port = 2,
297 },
298 [RCAR_DU_OUTPUT_LVDS0] = {
299 .possible_crtcs = BIT(0),
300 .port = 3,
301 },
302 },
303 .num_lvds = 1,
304 .dpll_mask = BIT(2) | BIT(1),
305};
306
307static const struct rcar_du_device_info rcar_du_r8a7796_info = {
308 .gen = 3,
309 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
310 | RCAR_DU_FEATURE_VSP1_SOURCE
311 | RCAR_DU_FEATURE_INTERLACED
312 | RCAR_DU_FEATURE_TVM_SYNC,
313 .channels_mask = BIT(2) | BIT(1) | BIT(0),
314 .routes = {
315 /*
316 * R8A7796 has one RGB output, one LVDS output and one HDMI
317 * output.
318 */
319 [RCAR_DU_OUTPUT_DPAD0] = {
320 .possible_crtcs = BIT(2),
321 .port = 0,
322 },
323 [RCAR_DU_OUTPUT_HDMI0] = {
324 .possible_crtcs = BIT(1),
325 .port = 1,
326 },
327 [RCAR_DU_OUTPUT_LVDS0] = {
328 .possible_crtcs = BIT(0),
329 .port = 2,
330 },
331 },
332 .num_lvds = 1,
333 .dpll_mask = BIT(1),
334};
335
336static const struct rcar_du_device_info rcar_du_r8a77965_info = {
337 .gen = 3,
338 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
339 | RCAR_DU_FEATURE_VSP1_SOURCE
340 | RCAR_DU_FEATURE_INTERLACED
341 | RCAR_DU_FEATURE_TVM_SYNC,
342 .channels_mask = BIT(3) | BIT(1) | BIT(0),
343 .routes = {
344 /*
345 * R8A77965 has one RGB output, one LVDS output and one HDMI
346 * output.
347 */
348 [RCAR_DU_OUTPUT_DPAD0] = {
349 .possible_crtcs = BIT(2),
350 .port = 0,
351 },
352 [RCAR_DU_OUTPUT_HDMI0] = {
353 .possible_crtcs = BIT(1),
354 .port = 1,
355 },
356 [RCAR_DU_OUTPUT_LVDS0] = {
357 .possible_crtcs = BIT(0),
358 .port = 2,
359 },
360 },
361 .num_lvds = 1,
362 .dpll_mask = BIT(1),
363};
364
365static const struct rcar_du_device_info rcar_du_r8a77970_info = {
366 .gen = 3,
367 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
368 | RCAR_DU_FEATURE_VSP1_SOURCE
369 | RCAR_DU_FEATURE_INTERLACED
370 | RCAR_DU_FEATURE_TVM_SYNC,
371 .channels_mask = BIT(0),
372 .routes = {
373 /* R8A77970 has one RGB output and one LVDS output. */
374 [RCAR_DU_OUTPUT_DPAD0] = {
375 .possible_crtcs = BIT(0),
376 .port = 0,
377 },
378 [RCAR_DU_OUTPUT_LVDS0] = {
379 .possible_crtcs = BIT(0),
380 .port = 1,
381 },
382 },
383 .num_lvds = 1,
384};
385
386static const struct rcar_du_device_info rcar_du_r8a7799x_info = {
387 .gen = 3,
388 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
389 | RCAR_DU_FEATURE_VSP1_SOURCE,
390 .channels_mask = BIT(1) | BIT(0),
391 .routes = {
392 /*
393 * R8A77990 and R8A77995 have one RGB output and two LVDS
394 * outputs.
395 */
396 [RCAR_DU_OUTPUT_DPAD0] = {
397 .possible_crtcs = BIT(0) | BIT(1),
398 .port = 0,
399 },
400 [RCAR_DU_OUTPUT_LVDS0] = {
401 .possible_crtcs = BIT(0),
402 .port = 1,
403 },
404 [RCAR_DU_OUTPUT_LVDS1] = {
405 .possible_crtcs = BIT(1),
406 .port = 2,
407 },
408 },
409 .num_lvds = 2,
410 .lvds_clk_mask = BIT(1) | BIT(0),
411};
412
413static const struct of_device_id rcar_du_of_table[] = {
414 { .compatible = "renesas,du-r8a7743", .data = &rzg1_du_r8a7743_info },
415 { .compatible = "renesas,du-r8a7744", .data = &rzg1_du_r8a7743_info },
416 { .compatible = "renesas,du-r8a7745", .data = &rzg1_du_r8a7745_info },
417 { .compatible = "renesas,du-r8a77470", .data = &rzg1_du_r8a77470_info },
418 { .compatible = "renesas,du-r8a774a1", .data = &rcar_du_r8a774a1_info },
419 { .compatible = "renesas,du-r8a774c0", .data = &rcar_du_r8a774c0_info },
420 { .compatible = "renesas,du-r8a7779", .data = &rcar_du_r8a7779_info },
421 { .compatible = "renesas,du-r8a7790", .data = &rcar_du_r8a7790_info },
422 { .compatible = "renesas,du-r8a7791", .data = &rcar_du_r8a7791_info },
423 { .compatible = "renesas,du-r8a7792", .data = &rcar_du_r8a7792_info },
424 { .compatible = "renesas,du-r8a7793", .data = &rcar_du_r8a7791_info },
425 { .compatible = "renesas,du-r8a7794", .data = &rcar_du_r8a7794_info },
426 { .compatible = "renesas,du-r8a7795", .data = &rcar_du_r8a7795_info },
427 { .compatible = "renesas,du-r8a7796", .data = &rcar_du_r8a7796_info },
428 { .compatible = "renesas,du-r8a77965", .data = &rcar_du_r8a77965_info },
429 { .compatible = "renesas,du-r8a77970", .data = &rcar_du_r8a77970_info },
430 { .compatible = "renesas,du-r8a77990", .data = &rcar_du_r8a7799x_info },
431 { .compatible = "renesas,du-r8a77995", .data = &rcar_du_r8a7799x_info },
432 { }
433};
434
435MODULE_DEVICE_TABLE(of, rcar_du_of_table);
436
437/* -----------------------------------------------------------------------------
438 * DRM operations
439 */
440
441DEFINE_DRM_GEM_CMA_FOPS(rcar_du_fops);
442
443static struct drm_driver rcar_du_driver = {
444 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
445 .gem_free_object_unlocked = drm_gem_cma_free_object,
446 .gem_vm_ops = &drm_gem_cma_vm_ops,
447 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
448 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
449 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
450 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
451 .gem_prime_vmap = drm_gem_cma_prime_vmap,
452 .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
453 .gem_prime_mmap = drm_gem_cma_prime_mmap,
454 .dumb_create = rcar_du_dumb_create,
455 .fops = &rcar_du_fops,
456 .name = "rcar-du",
457 .desc = "Renesas R-Car Display Unit",
458 .date = "20130110",
459 .major = 1,
460 .minor = 0,
461};
462
463/* -----------------------------------------------------------------------------
464 * Power management
465 */
466
467#ifdef CONFIG_PM_SLEEP
468static int rcar_du_pm_suspend(struct device *dev)
469{
470 struct rcar_du_device *rcdu = dev_get_drvdata(dev);
471
472 return drm_mode_config_helper_suspend(rcdu->ddev);
473}
474
475static int rcar_du_pm_resume(struct device *dev)
476{
477 struct rcar_du_device *rcdu = dev_get_drvdata(dev);
478
479 return drm_mode_config_helper_resume(rcdu->ddev);
480}
481#endif
482
483static const struct dev_pm_ops rcar_du_pm_ops = {
484 SET_SYSTEM_SLEEP_PM_OPS(rcar_du_pm_suspend, rcar_du_pm_resume)
485};
486
487/* -----------------------------------------------------------------------------
488 * Platform driver
489 */
490
491static int rcar_du_remove(struct platform_device *pdev)
492{
493 struct rcar_du_device *rcdu = platform_get_drvdata(pdev);
494 struct drm_device *ddev = rcdu->ddev;
495
496 drm_dev_unregister(ddev);
497
498 drm_kms_helper_poll_fini(ddev);
499 drm_mode_config_cleanup(ddev);
500
501 drm_dev_put(ddev);
502
503 return 0;
504}
505
506static int rcar_du_probe(struct platform_device *pdev)
507{
508 struct rcar_du_device *rcdu;
509 struct drm_device *ddev;
510 struct resource *mem;
511 int ret;
512
513 /* Allocate and initialize the R-Car device structure. */
514 rcdu = devm_kzalloc(&pdev->dev, sizeof(*rcdu), GFP_KERNEL);
515 if (rcdu == NULL)
516 return -ENOMEM;
517
518 rcdu->dev = &pdev->dev;
519 rcdu->info = of_device_get_match_data(rcdu->dev);
520
521 platform_set_drvdata(pdev, rcdu);
522
523 /* I/O resources */
524 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
525 rcdu->mmio = devm_ioremap_resource(&pdev->dev, mem);
526 if (IS_ERR(rcdu->mmio))
527 return PTR_ERR(rcdu->mmio);
528
529 /* DRM/KMS objects */
530 ddev = drm_dev_alloc(&rcar_du_driver, &pdev->dev);
531 if (IS_ERR(ddev))
532 return PTR_ERR(ddev);
533
534 rcdu->ddev = ddev;
535 ddev->dev_private = rcdu;
536
537 ret = rcar_du_modeset_init(rcdu);
538 if (ret < 0) {
539 if (ret != -EPROBE_DEFER)
540 dev_err(&pdev->dev,
541 "failed to initialize DRM/KMS (%d)\n", ret);
542 goto error;
543 }
544
545 ddev->irq_enabled = 1;
546
547 /*
548 * Register the DRM device with the core and the connectors with
549 * sysfs.
550 */
551 ret = drm_dev_register(ddev, 0);
552 if (ret)
553 goto error;
554
555 DRM_INFO("Device %s probed\n", dev_name(&pdev->dev));
556
557 drm_fbdev_generic_setup(ddev, 32);
558
559 return 0;
560
561error:
562 rcar_du_remove(pdev);
563
564 return ret;
565}
566
567static struct platform_driver rcar_du_platform_driver = {
568 .probe = rcar_du_probe,
569 .remove = rcar_du_remove,
570 .driver = {
571 .name = "rcar-du",
572 .pm = &rcar_du_pm_ops,
573 .of_match_table = rcar_du_of_table,
574 },
575};
576
577static int __init rcar_du_init(void)
578{
579 rcar_du_of_init(rcar_du_of_table);
580
581 return platform_driver_register(&rcar_du_platform_driver);
582}
583module_init(rcar_du_init);
584
585static void __exit rcar_du_exit(void)
586{
587 platform_driver_unregister(&rcar_du_platform_driver);
588}
589module_exit(rcar_du_exit);
590
591MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
592MODULE_DESCRIPTION("Renesas R-Car Display Unit DRM Driver");
593MODULE_LICENSE("GPL");
1/*
2 * rcar_du_drv.c -- R-Car Display Unit DRM driver
3 *
4 * Copyright (C) 2013-2015 Renesas Electronics Corporation
5 *
6 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/clk.h>
15#include <linux/io.h>
16#include <linux/mm.h>
17#include <linux/module.h>
18#include <linux/of_device.h>
19#include <linux/platform_device.h>
20#include <linux/pm.h>
21#include <linux/slab.h>
22#include <linux/wait.h>
23
24#include <drm/drmP.h>
25#include <drm/drm_atomic_helper.h>
26#include <drm/drm_crtc_helper.h>
27#include <drm/drm_fb_cma_helper.h>
28#include <drm/drm_gem_cma_helper.h>
29
30#include "rcar_du_drv.h"
31#include "rcar_du_kms.h"
32#include "rcar_du_of.h"
33#include "rcar_du_regs.h"
34
35/* -----------------------------------------------------------------------------
36 * Device Information
37 */
38
39static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
40 .gen = 2,
41 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
42 | RCAR_DU_FEATURE_EXT_CTRL_REGS,
43 .num_crtcs = 2,
44 .routes = {
45 /*
46 * R8A7743 has one RGB output and one LVDS output
47 */
48 [RCAR_DU_OUTPUT_DPAD0] = {
49 .possible_crtcs = BIT(1) | BIT(0),
50 .port = 0,
51 },
52 [RCAR_DU_OUTPUT_LVDS0] = {
53 .possible_crtcs = BIT(0),
54 .port = 1,
55 },
56 },
57 .num_lvds = 1,
58};
59
60static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
61 .gen = 2,
62 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
63 | RCAR_DU_FEATURE_EXT_CTRL_REGS,
64 .num_crtcs = 2,
65 .routes = {
66 /*
67 * R8A7745 has two RGB outputs
68 */
69 [RCAR_DU_OUTPUT_DPAD0] = {
70 .possible_crtcs = BIT(0),
71 .port = 0,
72 },
73 [RCAR_DU_OUTPUT_DPAD1] = {
74 .possible_crtcs = BIT(1),
75 .port = 1,
76 },
77 },
78};
79
80static const struct rcar_du_device_info rcar_du_r8a7779_info = {
81 .gen = 2,
82 .features = 0,
83 .num_crtcs = 2,
84 .routes = {
85 /*
86 * R8A7779 has two RGB outputs and one (currently unsupported)
87 * TCON output.
88 */
89 [RCAR_DU_OUTPUT_DPAD0] = {
90 .possible_crtcs = BIT(0),
91 .port = 0,
92 },
93 [RCAR_DU_OUTPUT_DPAD1] = {
94 .possible_crtcs = BIT(1) | BIT(0),
95 .port = 1,
96 },
97 },
98};
99
100static const struct rcar_du_device_info rcar_du_r8a7790_info = {
101 .gen = 2,
102 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
103 | RCAR_DU_FEATURE_EXT_CTRL_REGS,
104 .quirks = RCAR_DU_QUIRK_ALIGN_128B,
105 .num_crtcs = 3,
106 .routes = {
107 /*
108 * R8A7790 has one RGB output, two LVDS outputs and one
109 * (currently unsupported) TCON output.
110 */
111 [RCAR_DU_OUTPUT_DPAD0] = {
112 .possible_crtcs = BIT(2) | BIT(1) | BIT(0),
113 .port = 0,
114 },
115 [RCAR_DU_OUTPUT_LVDS0] = {
116 .possible_crtcs = BIT(0),
117 .port = 1,
118 },
119 [RCAR_DU_OUTPUT_LVDS1] = {
120 .possible_crtcs = BIT(2) | BIT(1),
121 .port = 2,
122 },
123 },
124 .num_lvds = 2,
125};
126
127/* M2-W (r8a7791) and M2-N (r8a7793) are identical */
128static const struct rcar_du_device_info rcar_du_r8a7791_info = {
129 .gen = 2,
130 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
131 | RCAR_DU_FEATURE_EXT_CTRL_REGS,
132 .num_crtcs = 2,
133 .routes = {
134 /*
135 * R8A779[13] has one RGB output, one LVDS output and one
136 * (currently unsupported) TCON output.
137 */
138 [RCAR_DU_OUTPUT_DPAD0] = {
139 .possible_crtcs = BIT(1) | BIT(0),
140 .port = 0,
141 },
142 [RCAR_DU_OUTPUT_LVDS0] = {
143 .possible_crtcs = BIT(0),
144 .port = 1,
145 },
146 },
147 .num_lvds = 1,
148};
149
150static const struct rcar_du_device_info rcar_du_r8a7792_info = {
151 .gen = 2,
152 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
153 | RCAR_DU_FEATURE_EXT_CTRL_REGS,
154 .num_crtcs = 2,
155 .routes = {
156 /* R8A7792 has two RGB outputs. */
157 [RCAR_DU_OUTPUT_DPAD0] = {
158 .possible_crtcs = BIT(0),
159 .port = 0,
160 },
161 [RCAR_DU_OUTPUT_DPAD1] = {
162 .possible_crtcs = BIT(1),
163 .port = 1,
164 },
165 },
166};
167
168static const struct rcar_du_device_info rcar_du_r8a7794_info = {
169 .gen = 2,
170 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
171 | RCAR_DU_FEATURE_EXT_CTRL_REGS,
172 .num_crtcs = 2,
173 .routes = {
174 /*
175 * R8A7794 has two RGB outputs and one (currently unsupported)
176 * TCON output.
177 */
178 [RCAR_DU_OUTPUT_DPAD0] = {
179 .possible_crtcs = BIT(0),
180 .port = 0,
181 },
182 [RCAR_DU_OUTPUT_DPAD1] = {
183 .possible_crtcs = BIT(1),
184 .port = 1,
185 },
186 },
187};
188
189static const struct rcar_du_device_info rcar_du_r8a7795_info = {
190 .gen = 3,
191 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
192 | RCAR_DU_FEATURE_EXT_CTRL_REGS
193 | RCAR_DU_FEATURE_VSP1_SOURCE,
194 .num_crtcs = 4,
195 .routes = {
196 /*
197 * R8A7795 has one RGB output, two HDMI outputs and one
198 * LVDS output.
199 */
200 [RCAR_DU_OUTPUT_DPAD0] = {
201 .possible_crtcs = BIT(3),
202 .port = 0,
203 },
204 [RCAR_DU_OUTPUT_HDMI0] = {
205 .possible_crtcs = BIT(1),
206 .port = 1,
207 },
208 [RCAR_DU_OUTPUT_HDMI1] = {
209 .possible_crtcs = BIT(2),
210 .port = 2,
211 },
212 [RCAR_DU_OUTPUT_LVDS0] = {
213 .possible_crtcs = BIT(0),
214 .port = 3,
215 },
216 },
217 .num_lvds = 1,
218 .dpll_ch = BIT(1) | BIT(2),
219};
220
221static const struct rcar_du_device_info rcar_du_r8a7796_info = {
222 .gen = 3,
223 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
224 | RCAR_DU_FEATURE_EXT_CTRL_REGS
225 | RCAR_DU_FEATURE_VSP1_SOURCE,
226 .num_crtcs = 3,
227 .routes = {
228 /*
229 * R8A7796 has one RGB output, one LVDS output and one HDMI
230 * output.
231 */
232 [RCAR_DU_OUTPUT_DPAD0] = {
233 .possible_crtcs = BIT(2),
234 .port = 0,
235 },
236 [RCAR_DU_OUTPUT_HDMI0] = {
237 .possible_crtcs = BIT(1),
238 .port = 1,
239 },
240 [RCAR_DU_OUTPUT_LVDS0] = {
241 .possible_crtcs = BIT(0),
242 .port = 2,
243 },
244 },
245 .num_lvds = 1,
246 .dpll_ch = BIT(1),
247};
248
249static const struct rcar_du_device_info rcar_du_r8a77970_info = {
250 .gen = 3,
251 .features = RCAR_DU_FEATURE_CRTC_IRQ_CLOCK
252 | RCAR_DU_FEATURE_EXT_CTRL_REGS
253 | RCAR_DU_FEATURE_VSP1_SOURCE,
254 .num_crtcs = 1,
255 .routes = {
256 /* R8A77970 has one RGB output and one LVDS output. */
257 [RCAR_DU_OUTPUT_DPAD0] = {
258 .possible_crtcs = BIT(0),
259 .port = 0,
260 },
261 [RCAR_DU_OUTPUT_LVDS0] = {
262 .possible_crtcs = BIT(0),
263 .port = 1,
264 },
265 },
266 .num_lvds = 1,
267};
268
269static const struct of_device_id rcar_du_of_table[] = {
270 { .compatible = "renesas,du-r8a7743", .data = &rzg1_du_r8a7743_info },
271 { .compatible = "renesas,du-r8a7745", .data = &rzg1_du_r8a7745_info },
272 { .compatible = "renesas,du-r8a7779", .data = &rcar_du_r8a7779_info },
273 { .compatible = "renesas,du-r8a7790", .data = &rcar_du_r8a7790_info },
274 { .compatible = "renesas,du-r8a7791", .data = &rcar_du_r8a7791_info },
275 { .compatible = "renesas,du-r8a7792", .data = &rcar_du_r8a7792_info },
276 { .compatible = "renesas,du-r8a7793", .data = &rcar_du_r8a7791_info },
277 { .compatible = "renesas,du-r8a7794", .data = &rcar_du_r8a7794_info },
278 { .compatible = "renesas,du-r8a7795", .data = &rcar_du_r8a7795_info },
279 { .compatible = "renesas,du-r8a7796", .data = &rcar_du_r8a7796_info },
280 { .compatible = "renesas,du-r8a77970", .data = &rcar_du_r8a77970_info },
281 { }
282};
283
284MODULE_DEVICE_TABLE(of, rcar_du_of_table);
285
286/* -----------------------------------------------------------------------------
287 * DRM operations
288 */
289
290static void rcar_du_lastclose(struct drm_device *dev)
291{
292 struct rcar_du_device *rcdu = dev->dev_private;
293
294 drm_fbdev_cma_restore_mode(rcdu->fbdev);
295}
296
297DEFINE_DRM_GEM_CMA_FOPS(rcar_du_fops);
298
299static struct drm_driver rcar_du_driver = {
300 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME
301 | DRIVER_ATOMIC,
302 .lastclose = rcar_du_lastclose,
303 .gem_free_object_unlocked = drm_gem_cma_free_object,
304 .gem_vm_ops = &drm_gem_cma_vm_ops,
305 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
306 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
307 .gem_prime_import = drm_gem_prime_import,
308 .gem_prime_export = drm_gem_prime_export,
309 .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
310 .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
311 .gem_prime_vmap = drm_gem_cma_prime_vmap,
312 .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
313 .gem_prime_mmap = drm_gem_cma_prime_mmap,
314 .dumb_create = rcar_du_dumb_create,
315 .fops = &rcar_du_fops,
316 .name = "rcar-du",
317 .desc = "Renesas R-Car Display Unit",
318 .date = "20130110",
319 .major = 1,
320 .minor = 0,
321};
322
323/* -----------------------------------------------------------------------------
324 * Power management
325 */
326
327#ifdef CONFIG_PM_SLEEP
328static int rcar_du_pm_suspend(struct device *dev)
329{
330 struct rcar_du_device *rcdu = dev_get_drvdata(dev);
331 struct drm_atomic_state *state;
332
333 drm_kms_helper_poll_disable(rcdu->ddev);
334 drm_fbdev_cma_set_suspend_unlocked(rcdu->fbdev, true);
335
336 state = drm_atomic_helper_suspend(rcdu->ddev);
337 if (IS_ERR(state)) {
338 drm_fbdev_cma_set_suspend_unlocked(rcdu->fbdev, false);
339 drm_kms_helper_poll_enable(rcdu->ddev);
340 return PTR_ERR(state);
341 }
342
343 rcdu->suspend_state = state;
344
345 return 0;
346}
347
348static int rcar_du_pm_resume(struct device *dev)
349{
350 struct rcar_du_device *rcdu = dev_get_drvdata(dev);
351
352 drm_atomic_helper_resume(rcdu->ddev, rcdu->suspend_state);
353 drm_fbdev_cma_set_suspend_unlocked(rcdu->fbdev, false);
354 drm_kms_helper_poll_enable(rcdu->ddev);
355
356 return 0;
357}
358#endif
359
360static const struct dev_pm_ops rcar_du_pm_ops = {
361 SET_SYSTEM_SLEEP_PM_OPS(rcar_du_pm_suspend, rcar_du_pm_resume)
362};
363
364/* -----------------------------------------------------------------------------
365 * Platform driver
366 */
367
368static int rcar_du_remove(struct platform_device *pdev)
369{
370 struct rcar_du_device *rcdu = platform_get_drvdata(pdev);
371 struct drm_device *ddev = rcdu->ddev;
372
373 drm_dev_unregister(ddev);
374
375 if (rcdu->fbdev)
376 drm_fbdev_cma_fini(rcdu->fbdev);
377
378 drm_kms_helper_poll_fini(ddev);
379 drm_mode_config_cleanup(ddev);
380
381 drm_dev_unref(ddev);
382
383 return 0;
384}
385
386static int rcar_du_probe(struct platform_device *pdev)
387{
388 struct rcar_du_device *rcdu;
389 struct drm_device *ddev;
390 struct resource *mem;
391 int ret;
392
393 /* Allocate and initialize the R-Car device structure. */
394 rcdu = devm_kzalloc(&pdev->dev, sizeof(*rcdu), GFP_KERNEL);
395 if (rcdu == NULL)
396 return -ENOMEM;
397
398 rcdu->dev = &pdev->dev;
399 rcdu->info = of_device_get_match_data(rcdu->dev);
400
401 platform_set_drvdata(pdev, rcdu);
402
403 /* I/O resources */
404 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
405 rcdu->mmio = devm_ioremap_resource(&pdev->dev, mem);
406 if (IS_ERR(rcdu->mmio))
407 return PTR_ERR(rcdu->mmio);
408
409 /* DRM/KMS objects */
410 ddev = drm_dev_alloc(&rcar_du_driver, &pdev->dev);
411 if (IS_ERR(ddev))
412 return PTR_ERR(ddev);
413
414 rcdu->ddev = ddev;
415 ddev->dev_private = rcdu;
416
417 ret = rcar_du_modeset_init(rcdu);
418 if (ret < 0) {
419 if (ret != -EPROBE_DEFER)
420 dev_err(&pdev->dev,
421 "failed to initialize DRM/KMS (%d)\n", ret);
422 goto error;
423 }
424
425 ddev->irq_enabled = 1;
426
427 /*
428 * Register the DRM device with the core and the connectors with
429 * sysfs.
430 */
431 ret = drm_dev_register(ddev, 0);
432 if (ret)
433 goto error;
434
435 DRM_INFO("Device %s probed\n", dev_name(&pdev->dev));
436
437 return 0;
438
439error:
440 rcar_du_remove(pdev);
441
442 return ret;
443}
444
445static struct platform_driver rcar_du_platform_driver = {
446 .probe = rcar_du_probe,
447 .remove = rcar_du_remove,
448 .driver = {
449 .name = "rcar-du",
450 .pm = &rcar_du_pm_ops,
451 .of_match_table = rcar_du_of_table,
452 },
453};
454
455static int __init rcar_du_init(void)
456{
457 rcar_du_of_init(rcar_du_of_table);
458
459 return platform_driver_register(&rcar_du_platform_driver);
460}
461module_init(rcar_du_init);
462
463static void __exit rcar_du_exit(void)
464{
465 platform_driver_unregister(&rcar_du_platform_driver);
466}
467module_exit(rcar_du_exit);
468
469MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
470MODULE_DESCRIPTION("Renesas R-Car Display Unit DRM Driver");
471MODULE_LICENSE("GPL");