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1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 *
30 * Interface to the hardware Packet Output unit.
31 *
32 * Starting with SDK 1.7.0, the PKO output functions now support
33 * two types of locking. CVMX_PKO_LOCK_ATOMIC_TAG continues to
34 * function similarly to previous SDKs by using POW atomic tags
35 * to preserve ordering and exclusivity. As a new option, you
36 * can now pass CVMX_PKO_LOCK_CMD_QUEUE which uses a ll/sc
37 * memory based locking instead. This locking has the advantage
38 * of not affecting the tag state but doesn't preserve packet
39 * ordering. CVMX_PKO_LOCK_CMD_QUEUE is appropriate in most
40 * generic code while CVMX_PKO_LOCK_CMD_QUEUE should be used
41 * with hand tuned fast path code.
42 *
43 * Some of other SDK differences visible to the command command
44 * queuing:
45 * - PKO indexes are no longer stored in the FAU. A large
46 * percentage of the FAU register block used to be tied up
47 * maintaining PKO queue pointers. These are now stored in a
48 * global named block.
49 * - The PKO <b>use_locking</b> parameter can now have a global
50 * effect. Since all application use the same named block,
51 * queue locking correctly applies across all operating
52 * systems when using CVMX_PKO_LOCK_CMD_QUEUE.
53 * - PKO 3 word commands are now supported. Use
54 * cvmx_pko_send_packet_finish3().
55 *
56 */
57
58#ifndef __CVMX_PKO_H__
59#define __CVMX_PKO_H__
60
61#include <asm/octeon/cvmx-fpa.h>
62#include <asm/octeon/cvmx-pow.h>
63#include <asm/octeon/cvmx-cmd-queue.h>
64#include <asm/octeon/cvmx-pko-defs.h>
65
66/* Adjust the command buffer size by 1 word so that in the case of using only
67 * two word PKO commands no command words stradle buffers. The useful values
68 * for this are 0 and 1. */
69#define CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST (1)
70
71#define CVMX_PKO_MAX_OUTPUT_QUEUES_STATIC 256
72#define CVMX_PKO_MAX_OUTPUT_QUEUES ((OCTEON_IS_MODEL(OCTEON_CN31XX) || \
73 OCTEON_IS_MODEL(OCTEON_CN3010) || OCTEON_IS_MODEL(OCTEON_CN3005) || \
74 OCTEON_IS_MODEL(OCTEON_CN50XX)) ? 32 : \
75 (OCTEON_IS_MODEL(OCTEON_CN58XX) || \
76 OCTEON_IS_MODEL(OCTEON_CN56XX)) ? 256 : 128)
77#define CVMX_PKO_NUM_OUTPUT_PORTS 40
78/* use this for queues that are not used */
79#define CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID 63
80#define CVMX_PKO_QUEUE_STATIC_PRIORITY 9
81#define CVMX_PKO_ILLEGAL_QUEUE 0xFFFF
82#define CVMX_PKO_MAX_QUEUE_DEPTH 0
83
84typedef enum {
85 CVMX_PKO_SUCCESS,
86 CVMX_PKO_INVALID_PORT,
87 CVMX_PKO_INVALID_QUEUE,
88 CVMX_PKO_INVALID_PRIORITY,
89 CVMX_PKO_NO_MEMORY,
90 CVMX_PKO_PORT_ALREADY_SETUP,
91 CVMX_PKO_CMD_QUEUE_INIT_ERROR
92} cvmx_pko_status_t;
93
94/**
95 * This enumeration represents the differnet locking modes supported by PKO.
96 */
97typedef enum {
98 /*
99 * PKO doesn't do any locking. It is the responsibility of the
100 * application to make sure that no other core is accessing
101 * the same queue at the same time
102 */
103 CVMX_PKO_LOCK_NONE = 0,
104 /*
105 * PKO performs an atomic tagswitch to insure exclusive access
106 * to the output queue. This will maintain packet ordering on
107 * output.
108 */
109 CVMX_PKO_LOCK_ATOMIC_TAG = 1,
110 /*
111 * PKO uses the common command queue locks to insure exclusive
112 * access to the output queue. This is a memory based
113 * ll/sc. This is the most portable locking mechanism.
114 */
115 CVMX_PKO_LOCK_CMD_QUEUE = 2,
116} cvmx_pko_lock_t;
117
118typedef struct {
119 uint32_t packets;
120 uint64_t octets;
121 uint64_t doorbell;
122} cvmx_pko_port_status_t;
123
124/**
125 * This structure defines the address to use on a packet enqueue
126 */
127typedef union {
128 uint64_t u64;
129 struct {
130#ifdef __BIG_ENDIAN_BITFIELD
131 /* Must CVMX_IO_SEG */
132 uint64_t mem_space:2;
133 /* Must be zero */
134 uint64_t reserved:13;
135 /* Must be one */
136 uint64_t is_io:1;
137 /* The ID of the device on the non-coherent bus */
138 uint64_t did:8;
139 /* Must be zero */
140 uint64_t reserved2:4;
141 /* Must be zero */
142 uint64_t reserved3:18;
143 /*
144 * The hardware likes to have the output port in
145 * addition to the output queue,
146 */
147 uint64_t port:6;
148 /*
149 * The output queue to send the packet to (0-127 are
150 * legal)
151 */
152 uint64_t queue:9;
153 /* Must be zero */
154 uint64_t reserved4:3;
155#else
156 uint64_t reserved4:3;
157 uint64_t queue:9;
158 uint64_t port:9;
159 uint64_t reserved3:15;
160 uint64_t reserved2:4;
161 uint64_t did:8;
162 uint64_t is_io:1;
163 uint64_t reserved:13;
164 uint64_t mem_space:2;
165#endif
166 } s;
167} cvmx_pko_doorbell_address_t;
168
169/**
170 * Structure of the first packet output command word.
171 */
172typedef union {
173 uint64_t u64;
174 struct {
175#ifdef __BIG_ENDIAN_BITFIELD
176 /*
177 * The size of the reg1 operation - could be 8, 16,
178 * 32, or 64 bits.
179 */
180 uint64_t size1:2;
181 /*
182 * The size of the reg0 operation - could be 8, 16,
183 * 32, or 64 bits.
184 */
185 uint64_t size0:2;
186 /*
187 * If set, subtract 1, if clear, subtract packet
188 * size.
189 */
190 uint64_t subone1:1;
191 /*
192 * The register, subtract will be done if reg1 is
193 * non-zero.
194 */
195 uint64_t reg1:11;
196 /* If set, subtract 1, if clear, subtract packet size */
197 uint64_t subone0:1;
198 /* The register, subtract will be done if reg0 is non-zero */
199 uint64_t reg0:11;
200 /*
201 * When set, interpret segment pointer and segment
202 * bytes in little endian order.
203 */
204 uint64_t le:1;
205 /*
206 * When set, packet data not allocated in L2 cache by
207 * PKO.
208 */
209 uint64_t n2:1;
210 /*
211 * If set and rsp is set, word3 contains a pointer to
212 * a work queue entry.
213 */
214 uint64_t wqp:1;
215 /* If set, the hardware will send a response when done */
216 uint64_t rsp:1;
217 /*
218 * If set, the supplied pkt_ptr is really a pointer to
219 * a list of pkt_ptr's.
220 */
221 uint64_t gather:1;
222 /*
223 * If ipoffp1 is non zero, (ipoffp1-1) is the number
224 * of bytes to IP header, and the hardware will
225 * calculate and insert the UDP/TCP checksum.
226 */
227 uint64_t ipoffp1:7;
228 /*
229 * If set, ignore the I bit (force to zero) from all
230 * pointer structures.
231 */
232 uint64_t ignore_i:1;
233 /*
234 * If clear, the hardware will attempt to free the
235 * buffers containing the packet.
236 */
237 uint64_t dontfree:1;
238 /*
239 * The total number of segs in the packet, if gather
240 * set, also gather list length.
241 */
242 uint64_t segs:6;
243 /* Including L2, but no trailing CRC */
244 uint64_t total_bytes:16;
245#else
246 uint64_t total_bytes:16;
247 uint64_t segs:6;
248 uint64_t dontfree:1;
249 uint64_t ignore_i:1;
250 uint64_t ipoffp1:7;
251 uint64_t gather:1;
252 uint64_t rsp:1;
253 uint64_t wqp:1;
254 uint64_t n2:1;
255 uint64_t le:1;
256 uint64_t reg0:11;
257 uint64_t subone0:1;
258 uint64_t reg1:11;
259 uint64_t subone1:1;
260 uint64_t size0:2;
261 uint64_t size1:2;
262#endif
263 } s;
264} cvmx_pko_command_word0_t;
265
266/* CSR typedefs have been moved to cvmx-csr-*.h */
267
268/**
269 * Definition of internal state for Packet output processing
270 */
271typedef struct {
272 /* ptr to start of buffer, offset kept in FAU reg */
273 uint64_t *start_ptr;
274} cvmx_pko_state_elem_t;
275
276/**
277 * Call before any other calls to initialize the packet
278 * output system.
279 */
280extern void cvmx_pko_initialize_global(void);
281extern int cvmx_pko_initialize_local(void);
282
283/**
284 * Enables the packet output hardware. It must already be
285 * configured.
286 */
287extern void cvmx_pko_enable(void);
288
289/**
290 * Disables the packet output. Does not affect any configuration.
291 */
292extern void cvmx_pko_disable(void);
293
294/**
295 * Shutdown and free resources required by packet output.
296 */
297
298extern void cvmx_pko_shutdown(void);
299
300/**
301 * Configure a output port and the associated queues for use.
302 *
303 * @port: Port to configure.
304 * @base_queue: First queue number to associate with this port.
305 * @num_queues: Number of queues t oassociate with this port
306 * @priority: Array of priority levels for each queue. Values are
307 * allowed to be 1-8. A value of 8 get 8 times the traffic
308 * of a value of 1. There must be num_queues elements in the
309 * array.
310 */
311extern cvmx_pko_status_t cvmx_pko_config_port(uint64_t port,
312 uint64_t base_queue,
313 uint64_t num_queues,
314 const uint64_t priority[]);
315
316/**
317 * Ring the packet output doorbell. This tells the packet
318 * output hardware that "len" command words have been added
319 * to its pending list. This command includes the required
320 * CVMX_SYNCWS before the doorbell ring.
321 *
322 * @port: Port the packet is for
323 * @queue: Queue the packet is for
324 * @len: Length of the command in 64 bit words
325 */
326static inline void cvmx_pko_doorbell(uint64_t port, uint64_t queue,
327 uint64_t len)
328{
329 cvmx_pko_doorbell_address_t ptr;
330
331 ptr.u64 = 0;
332 ptr.s.mem_space = CVMX_IO_SEG;
333 ptr.s.did = CVMX_OCT_DID_PKT_SEND;
334 ptr.s.is_io = 1;
335 ptr.s.port = port;
336 ptr.s.queue = queue;
337 /*
338 * Need to make sure output queue data is in DRAM before
339 * doorbell write.
340 */
341 CVMX_SYNCWS;
342 cvmx_write_io(ptr.u64, len);
343}
344
345/**
346 * Prepare to send a packet. This may initiate a tag switch to
347 * get exclusive access to the output queue structure, and
348 * performs other prep work for the packet send operation.
349 *
350 * cvmx_pko_send_packet_finish() MUST be called after this function is called,
351 * and must be called with the same port/queue/use_locking arguments.
352 *
353 * The use_locking parameter allows the caller to use three
354 * possible locking modes.
355 * - CVMX_PKO_LOCK_NONE
356 * - PKO doesn't do any locking. It is the responsibility
357 * of the application to make sure that no other core
358 * is accessing the same queue at the same time.
359 * - CVMX_PKO_LOCK_ATOMIC_TAG
360 * - PKO performs an atomic tagswitch to insure exclusive
361 * access to the output queue. This will maintain
362 * packet ordering on output.
363 * - CVMX_PKO_LOCK_CMD_QUEUE
364 * - PKO uses the common command queue locks to insure
365 * exclusive access to the output queue. This is a
366 * memory based ll/sc. This is the most portable
367 * locking mechanism.
368 *
369 * NOTE: If atomic locking is used, the POW entry CANNOT be
370 * descheduled, as it does not contain a valid WQE pointer.
371 *
372 * @port: Port to send it on
373 * @queue: Queue to use
374 * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or
375 * CVMX_PKO_LOCK_CMD_QUEUE
376 */
377
378static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue,
379 cvmx_pko_lock_t use_locking)
380{
381 if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG) {
382 /*
383 * Must do a full switch here to handle all cases. We
384 * use a fake WQE pointer, as the POW does not access
385 * this memory. The WQE pointer and group are only
386 * used if this work is descheduled, which is not
387 * supported by the
388 * cvmx_pko_send_packet_prepare/cvmx_pko_send_packet_finish
389 * combination. Note that this is a special case in
390 * which these fake values can be used - this is not a
391 * general technique.
392 */
393 uint32_t tag =
394 CVMX_TAG_SW_BITS_INTERNAL << CVMX_TAG_SW_SHIFT |
395 CVMX_TAG_SUBGROUP_PKO << CVMX_TAG_SUBGROUP_SHIFT |
396 (CVMX_TAG_SUBGROUP_MASK & queue);
397 cvmx_pow_tag_sw_full((cvmx_wqe_t *) cvmx_phys_to_ptr(0x80), tag,
398 CVMX_POW_TAG_TYPE_ATOMIC, 0);
399 }
400}
401
402/**
403 * Complete packet output. cvmx_pko_send_packet_prepare() must be
404 * called exactly once before this, and the same parameters must be
405 * passed to both cvmx_pko_send_packet_prepare() and
406 * cvmx_pko_send_packet_finish().
407 *
408 * @port: Port to send it on
409 * @queue: Queue to use
410 * @pko_command:
411 * PKO HW command word
412 * @packet: Packet to send
413 * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or
414 * CVMX_PKO_LOCK_CMD_QUEUE
415 *
416 * Returns returns CVMX_PKO_SUCCESS on success, or error code on
417 * failure of output
418 */
419static inline cvmx_pko_status_t cvmx_pko_send_packet_finish(
420 uint64_t port,
421 uint64_t queue,
422 cvmx_pko_command_word0_t pko_command,
423 union cvmx_buf_ptr packet,
424 cvmx_pko_lock_t use_locking)
425{
426 cvmx_cmd_queue_result_t result;
427 if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG)
428 cvmx_pow_tag_sw_wait();
429 result = cvmx_cmd_queue_write2(CVMX_CMD_QUEUE_PKO(queue),
430 (use_locking == CVMX_PKO_LOCK_CMD_QUEUE),
431 pko_command.u64, packet.u64);
432 if (likely(result == CVMX_CMD_QUEUE_SUCCESS)) {
433 cvmx_pko_doorbell(port, queue, 2);
434 return CVMX_PKO_SUCCESS;
435 } else if ((result == CVMX_CMD_QUEUE_NO_MEMORY)
436 || (result == CVMX_CMD_QUEUE_FULL)) {
437 return CVMX_PKO_NO_MEMORY;
438 } else {
439 return CVMX_PKO_INVALID_QUEUE;
440 }
441}
442
443/**
444 * Complete packet output. cvmx_pko_send_packet_prepare() must be
445 * called exactly once before this, and the same parameters must be
446 * passed to both cvmx_pko_send_packet_prepare() and
447 * cvmx_pko_send_packet_finish().
448 *
449 * @port: Port to send it on
450 * @queue: Queue to use
451 * @pko_command:
452 * PKO HW command word
453 * @packet: Packet to send
454 * @addr: Plysical address of a work queue entry or physical address
455 * to zero on complete.
456 * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or
457 * CVMX_PKO_LOCK_CMD_QUEUE
458 *
459 * Returns returns CVMX_PKO_SUCCESS on success, or error code on
460 * failure of output
461 */
462static inline cvmx_pko_status_t cvmx_pko_send_packet_finish3(
463 uint64_t port,
464 uint64_t queue,
465 cvmx_pko_command_word0_t pko_command,
466 union cvmx_buf_ptr packet,
467 uint64_t addr,
468 cvmx_pko_lock_t use_locking)
469{
470 cvmx_cmd_queue_result_t result;
471 if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG)
472 cvmx_pow_tag_sw_wait();
473 result = cvmx_cmd_queue_write3(CVMX_CMD_QUEUE_PKO(queue),
474 (use_locking == CVMX_PKO_LOCK_CMD_QUEUE),
475 pko_command.u64, packet.u64, addr);
476 if (likely(result == CVMX_CMD_QUEUE_SUCCESS)) {
477 cvmx_pko_doorbell(port, queue, 3);
478 return CVMX_PKO_SUCCESS;
479 } else if ((result == CVMX_CMD_QUEUE_NO_MEMORY)
480 || (result == CVMX_CMD_QUEUE_FULL)) {
481 return CVMX_PKO_NO_MEMORY;
482 } else {
483 return CVMX_PKO_INVALID_QUEUE;
484 }
485}
486
487/**
488 * Return the pko output queue associated with a port and a specific core.
489 * In normal mode (PKO lockless operation is disabled), the value returned
490 * is the base queue.
491 *
492 * @port: Port number
493 * @core: Core to get queue for
494 *
495 * Returns Core-specific output queue
496 */
497static inline int cvmx_pko_get_base_queue_per_core(int port, int core)
498{
499#ifndef CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0
500#define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 16
501#endif
502#ifndef CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1
503#define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 16
504#endif
505
506 if (port < CVMX_PKO_MAX_PORTS_INTERFACE0)
507 return port * CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + core;
508 else if (port >= 16 && port < 16 + CVMX_PKO_MAX_PORTS_INTERFACE1)
509 return CVMX_PKO_MAX_PORTS_INTERFACE0 *
510 CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + (port -
511 16) *
512 CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + core;
513 else if ((port >= 32) && (port < 36))
514 return CVMX_PKO_MAX_PORTS_INTERFACE0 *
515 CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 +
516 CVMX_PKO_MAX_PORTS_INTERFACE1 *
517 CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + (port -
518 32) *
519 CVMX_PKO_QUEUES_PER_PORT_PCI;
520 else if ((port >= 36) && (port < 40))
521 return CVMX_PKO_MAX_PORTS_INTERFACE0 *
522 CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 +
523 CVMX_PKO_MAX_PORTS_INTERFACE1 *
524 CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 +
525 4 * CVMX_PKO_QUEUES_PER_PORT_PCI + (port -
526 36) *
527 CVMX_PKO_QUEUES_PER_PORT_LOOP;
528 else
529 /* Given the limit on the number of ports we can map to
530 * CVMX_MAX_OUTPUT_QUEUES_STATIC queues (currently 256,
531 * divided among all cores), the remaining unmapped ports
532 * are assigned an illegal queue number */
533 return CVMX_PKO_ILLEGAL_QUEUE;
534}
535
536/**
537 * For a given port number, return the base pko output queue
538 * for the port.
539 *
540 * @port: Port number
541 * Returns Base output queue
542 */
543static inline int cvmx_pko_get_base_queue(int port)
544{
545 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
546 return port;
547
548 return cvmx_pko_get_base_queue_per_core(port, 0);
549}
550
551/**
552 * For a given port number, return the number of pko output queues.
553 *
554 * @port: Port number
555 * Returns Number of output queues
556 */
557static inline int cvmx_pko_get_num_queues(int port)
558{
559 if (port < 16)
560 return CVMX_PKO_QUEUES_PER_PORT_INTERFACE0;
561 else if (port < 32)
562 return CVMX_PKO_QUEUES_PER_PORT_INTERFACE1;
563 else if (port < 36)
564 return CVMX_PKO_QUEUES_PER_PORT_PCI;
565 else if (port < 40)
566 return CVMX_PKO_QUEUES_PER_PORT_LOOP;
567 else
568 return 0;
569}
570
571/**
572 * Get the status counters for a port.
573 *
574 * @port_num: Port number to get statistics for.
575 * @clear: Set to 1 to clear the counters after they are read
576 * @status: Where to put the results.
577 */
578static inline void cvmx_pko_get_port_status(uint64_t port_num, uint64_t clear,
579 cvmx_pko_port_status_t *status)
580{
581 union cvmx_pko_reg_read_idx pko_reg_read_idx;
582 union cvmx_pko_mem_count0 pko_mem_count0;
583 union cvmx_pko_mem_count1 pko_mem_count1;
584
585 pko_reg_read_idx.u64 = 0;
586 pko_reg_read_idx.s.index = port_num;
587 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
588
589 pko_mem_count0.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT0);
590 status->packets = pko_mem_count0.s.count;
591 if (clear) {
592 pko_mem_count0.s.count = port_num;
593 cvmx_write_csr(CVMX_PKO_MEM_COUNT0, pko_mem_count0.u64);
594 }
595
596 pko_mem_count1.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT1);
597 status->octets = pko_mem_count1.s.count;
598 if (clear) {
599 pko_mem_count1.s.count = port_num;
600 cvmx_write_csr(CVMX_PKO_MEM_COUNT1, pko_mem_count1.u64);
601 }
602
603 if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
604 union cvmx_pko_mem_debug9 debug9;
605 pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num);
606 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
607 debug9.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG9);
608 status->doorbell = debug9.cn38xx.doorbell;
609 } else {
610 union cvmx_pko_mem_debug8 debug8;
611 pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num);
612 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
613 debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8);
614 status->doorbell = debug8.cn50xx.doorbell;
615 }
616}
617
618/**
619 * Rate limit a PKO port to a max packets/sec. This function is only
620 * supported on CN57XX, CN56XX, CN55XX, and CN54XX.
621 *
622 * @port: Port to rate limit
623 * @packets_s: Maximum packet/sec
624 * @burst: Maximum number of packets to burst in a row before rate
625 * limiting cuts in.
626 *
627 * Returns Zero on success, negative on failure
628 */
629extern int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst);
630
631/**
632 * Rate limit a PKO port to a max bits/sec. This function is only
633 * supported on CN57XX, CN56XX, CN55XX, and CN54XX.
634 *
635 * @port: Port to rate limit
636 * @bits_s: PKO rate limit in bits/sec
637 * @burst: Maximum number of bits to burst before rate
638 * limiting cuts in.
639 *
640 * Returns Zero on success, negative on failure
641 */
642extern int cvmx_pko_rate_limit_bits(int port, uint64_t bits_s, int burst);
643
644#endif /* __CVMX_PKO_H__ */
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2008 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28/**
29 *
30 * Interface to the hardware Packet Output unit.
31 *
32 * Starting with SDK 1.7.0, the PKO output functions now support
33 * two types of locking. CVMX_PKO_LOCK_ATOMIC_TAG continues to
34 * function similarly to previous SDKs by using POW atomic tags
35 * to preserve ordering and exclusivity. As a new option, you
36 * can now pass CVMX_PKO_LOCK_CMD_QUEUE which uses a ll/sc
37 * memory based locking instead. This locking has the advantage
38 * of not affecting the tag state but doesn't preserve packet
39 * ordering. CVMX_PKO_LOCK_CMD_QUEUE is appropriate in most
40 * generic code while CVMX_PKO_LOCK_CMD_QUEUE should be used
41 * with hand tuned fast path code.
42 *
43 * Some of other SDK differences visible to the command command
44 * queuing:
45 * - PKO indexes are no longer stored in the FAU. A large
46 * percentage of the FAU register block used to be tied up
47 * maintaining PKO queue pointers. These are now stored in a
48 * global named block.
49 * - The PKO <b>use_locking</b> parameter can now have a global
50 * effect. Since all application use the same named block,
51 * queue locking correctly applies across all operating
52 * systems when using CVMX_PKO_LOCK_CMD_QUEUE.
53 * - PKO 3 word commands are now supported. Use
54 * cvmx_pko_send_packet_finish3().
55 *
56 */
57
58#ifndef __CVMX_PKO_H__
59#define __CVMX_PKO_H__
60
61#include <asm/octeon/cvmx-fpa.h>
62#include <asm/octeon/cvmx-pow.h>
63#include <asm/octeon/cvmx-cmd-queue.h>
64#include <asm/octeon/cvmx-pko-defs.h>
65
66/* Adjust the command buffer size by 1 word so that in the case of using only
67 * two word PKO commands no command words stradle buffers. The useful values
68 * for this are 0 and 1. */
69#define CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST (1)
70
71#define CVMX_PKO_MAX_OUTPUT_QUEUES_STATIC 256
72#define CVMX_PKO_MAX_OUTPUT_QUEUES ((OCTEON_IS_MODEL(OCTEON_CN31XX) || \
73 OCTEON_IS_MODEL(OCTEON_CN3010) || OCTEON_IS_MODEL(OCTEON_CN3005) || \
74 OCTEON_IS_MODEL(OCTEON_CN50XX)) ? 32 : \
75 (OCTEON_IS_MODEL(OCTEON_CN58XX) || \
76 OCTEON_IS_MODEL(OCTEON_CN56XX)) ? 256 : 128)
77#define CVMX_PKO_NUM_OUTPUT_PORTS 40
78/* use this for queues that are not used */
79#define CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID 63
80#define CVMX_PKO_QUEUE_STATIC_PRIORITY 9
81#define CVMX_PKO_ILLEGAL_QUEUE 0xFFFF
82#define CVMX_PKO_MAX_QUEUE_DEPTH 0
83
84typedef enum {
85 CVMX_PKO_SUCCESS,
86 CVMX_PKO_INVALID_PORT,
87 CVMX_PKO_INVALID_QUEUE,
88 CVMX_PKO_INVALID_PRIORITY,
89 CVMX_PKO_NO_MEMORY,
90 CVMX_PKO_PORT_ALREADY_SETUP,
91 CVMX_PKO_CMD_QUEUE_INIT_ERROR
92} cvmx_pko_status_t;
93
94/**
95 * This enumeration represents the differnet locking modes supported by PKO.
96 */
97typedef enum {
98 /*
99 * PKO doesn't do any locking. It is the responsibility of the
100 * application to make sure that no other core is accessing
101 * the same queue at the same time
102 */
103 CVMX_PKO_LOCK_NONE = 0,
104 /*
105 * PKO performs an atomic tagswitch to insure exclusive access
106 * to the output queue. This will maintain packet ordering on
107 * output.
108 */
109 CVMX_PKO_LOCK_ATOMIC_TAG = 1,
110 /*
111 * PKO uses the common command queue locks to insure exclusive
112 * access to the output queue. This is a memory based
113 * ll/sc. This is the most portable locking mechanism.
114 */
115 CVMX_PKO_LOCK_CMD_QUEUE = 2,
116} cvmx_pko_lock_t;
117
118typedef struct {
119 uint32_t packets;
120 uint64_t octets;
121 uint64_t doorbell;
122} cvmx_pko_port_status_t;
123
124/**
125 * This structure defines the address to use on a packet enqueue
126 */
127typedef union {
128 uint64_t u64;
129 struct {
130#ifdef __BIG_ENDIAN_BITFIELD
131 /* Must CVMX_IO_SEG */
132 uint64_t mem_space:2;
133 /* Must be zero */
134 uint64_t reserved:13;
135 /* Must be one */
136 uint64_t is_io:1;
137 /* The ID of the device on the non-coherent bus */
138 uint64_t did:8;
139 /* Must be zero */
140 uint64_t reserved2:4;
141 /* Must be zero */
142 uint64_t reserved3:18;
143 /*
144 * The hardware likes to have the output port in
145 * addition to the output queue,
146 */
147 uint64_t port:6;
148 /*
149 * The output queue to send the packet to (0-127 are
150 * legal)
151 */
152 uint64_t queue:9;
153 /* Must be zero */
154 uint64_t reserved4:3;
155#else
156 uint64_t reserved4:3;
157 uint64_t queue:9;
158 uint64_t port:9;
159 uint64_t reserved3:15;
160 uint64_t reserved2:4;
161 uint64_t did:8;
162 uint64_t is_io:1;
163 uint64_t reserved:13;
164 uint64_t mem_space:2;
165#endif
166 } s;
167} cvmx_pko_doorbell_address_t;
168
169/**
170 * Structure of the first packet output command word.
171 */
172typedef union {
173 uint64_t u64;
174 struct {
175#ifdef __BIG_ENDIAN_BITFIELD
176 /*
177 * The size of the reg1 operation - could be 8, 16,
178 * 32, or 64 bits.
179 */
180 uint64_t size1:2;
181 /*
182 * The size of the reg0 operation - could be 8, 16,
183 * 32, or 64 bits.
184 */
185 uint64_t size0:2;
186 /*
187 * If set, subtract 1, if clear, subtract packet
188 * size.
189 */
190 uint64_t subone1:1;
191 /*
192 * The register, subtract will be done if reg1 is
193 * non-zero.
194 */
195 uint64_t reg1:11;
196 /* If set, subtract 1, if clear, subtract packet size */
197 uint64_t subone0:1;
198 /* The register, subtract will be done if reg0 is non-zero */
199 uint64_t reg0:11;
200 /*
201 * When set, interpret segment pointer and segment
202 * bytes in little endian order.
203 */
204 uint64_t le:1;
205 /*
206 * When set, packet data not allocated in L2 cache by
207 * PKO.
208 */
209 uint64_t n2:1;
210 /*
211 * If set and rsp is set, word3 contains a pointer to
212 * a work queue entry.
213 */
214 uint64_t wqp:1;
215 /* If set, the hardware will send a response when done */
216 uint64_t rsp:1;
217 /*
218 * If set, the supplied pkt_ptr is really a pointer to
219 * a list of pkt_ptr's.
220 */
221 uint64_t gather:1;
222 /*
223 * If ipoffp1 is non zero, (ipoffp1-1) is the number
224 * of bytes to IP header, and the hardware will
225 * calculate and insert the UDP/TCP checksum.
226 */
227 uint64_t ipoffp1:7;
228 /*
229 * If set, ignore the I bit (force to zero) from all
230 * pointer structures.
231 */
232 uint64_t ignore_i:1;
233 /*
234 * If clear, the hardware will attempt to free the
235 * buffers containing the packet.
236 */
237 uint64_t dontfree:1;
238 /*
239 * The total number of segs in the packet, if gather
240 * set, also gather list length.
241 */
242 uint64_t segs:6;
243 /* Including L2, but no trailing CRC */
244 uint64_t total_bytes:16;
245#else
246 uint64_t total_bytes:16;
247 uint64_t segs:6;
248 uint64_t dontfree:1;
249 uint64_t ignore_i:1;
250 uint64_t ipoffp1:7;
251 uint64_t gather:1;
252 uint64_t rsp:1;
253 uint64_t wqp:1;
254 uint64_t n2:1;
255 uint64_t le:1;
256 uint64_t reg0:11;
257 uint64_t subone0:1;
258 uint64_t reg1:11;
259 uint64_t subone1:1;
260 uint64_t size0:2;
261 uint64_t size1:2;
262#endif
263 } s;
264} cvmx_pko_command_word0_t;
265
266/* CSR typedefs have been moved to cvmx-csr-*.h */
267
268/**
269 * Definition of internal state for Packet output processing
270 */
271typedef struct {
272 /* ptr to start of buffer, offset kept in FAU reg */
273 uint64_t *start_ptr;
274} cvmx_pko_state_elem_t;
275
276/**
277 * Call before any other calls to initialize the packet
278 * output system.
279 */
280extern void cvmx_pko_initialize_global(void);
281extern int cvmx_pko_initialize_local(void);
282
283/**
284 * Enables the packet output hardware. It must already be
285 * configured.
286 */
287extern void cvmx_pko_enable(void);
288
289/**
290 * Disables the packet output. Does not affect any configuration.
291 */
292extern void cvmx_pko_disable(void);
293
294/**
295 * Shutdown and free resources required by packet output.
296 */
297
298extern void cvmx_pko_shutdown(void);
299
300/**
301 * Configure a output port and the associated queues for use.
302 *
303 * @port: Port to configure.
304 * @base_queue: First queue number to associate with this port.
305 * @num_queues: Number of queues t oassociate with this port
306 * @priority: Array of priority levels for each queue. Values are
307 * allowed to be 1-8. A value of 8 get 8 times the traffic
308 * of a value of 1. There must be num_queues elements in the
309 * array.
310 */
311extern cvmx_pko_status_t cvmx_pko_config_port(uint64_t port,
312 uint64_t base_queue,
313 uint64_t num_queues,
314 const uint64_t priority[]);
315
316/**
317 * Ring the packet output doorbell. This tells the packet
318 * output hardware that "len" command words have been added
319 * to its pending list. This command includes the required
320 * CVMX_SYNCWS before the doorbell ring.
321 *
322 * @port: Port the packet is for
323 * @queue: Queue the packet is for
324 * @len: Length of the command in 64 bit words
325 */
326static inline void cvmx_pko_doorbell(uint64_t port, uint64_t queue,
327 uint64_t len)
328{
329 cvmx_pko_doorbell_address_t ptr;
330
331 ptr.u64 = 0;
332 ptr.s.mem_space = CVMX_IO_SEG;
333 ptr.s.did = CVMX_OCT_DID_PKT_SEND;
334 ptr.s.is_io = 1;
335 ptr.s.port = port;
336 ptr.s.queue = queue;
337 /*
338 * Need to make sure output queue data is in DRAM before
339 * doorbell write.
340 */
341 CVMX_SYNCWS;
342 cvmx_write_io(ptr.u64, len);
343}
344
345/**
346 * Prepare to send a packet. This may initiate a tag switch to
347 * get exclusive access to the output queue structure, and
348 * performs other prep work for the packet send operation.
349 *
350 * cvmx_pko_send_packet_finish() MUST be called after this function is called,
351 * and must be called with the same port/queue/use_locking arguments.
352 *
353 * The use_locking parameter allows the caller to use three
354 * possible locking modes.
355 * - CVMX_PKO_LOCK_NONE
356 * - PKO doesn't do any locking. It is the responsibility
357 * of the application to make sure that no other core
358 * is accessing the same queue at the same time.
359 * - CVMX_PKO_LOCK_ATOMIC_TAG
360 * - PKO performs an atomic tagswitch to insure exclusive
361 * access to the output queue. This will maintain
362 * packet ordering on output.
363 * - CVMX_PKO_LOCK_CMD_QUEUE
364 * - PKO uses the common command queue locks to insure
365 * exclusive access to the output queue. This is a
366 * memory based ll/sc. This is the most portable
367 * locking mechanism.
368 *
369 * NOTE: If atomic locking is used, the POW entry CANNOT be
370 * descheduled, as it does not contain a valid WQE pointer.
371 *
372 * @port: Port to send it on
373 * @queue: Queue to use
374 * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or
375 * CVMX_PKO_LOCK_CMD_QUEUE
376 */
377
378static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue,
379 cvmx_pko_lock_t use_locking)
380{
381 if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG) {
382 /*
383 * Must do a full switch here to handle all cases. We
384 * use a fake WQE pointer, as the POW does not access
385 * this memory. The WQE pointer and group are only
386 * used if this work is descheduled, which is not
387 * supported by the
388 * cvmx_pko_send_packet_prepare/cvmx_pko_send_packet_finish
389 * combination. Note that this is a special case in
390 * which these fake values can be used - this is not a
391 * general technique.
392 */
393 uint32_t tag =
394 CVMX_TAG_SW_BITS_INTERNAL << CVMX_TAG_SW_SHIFT |
395 CVMX_TAG_SUBGROUP_PKO << CVMX_TAG_SUBGROUP_SHIFT |
396 (CVMX_TAG_SUBGROUP_MASK & queue);
397 cvmx_pow_tag_sw_full((cvmx_wqe_t *) cvmx_phys_to_ptr(0x80), tag,
398 CVMX_POW_TAG_TYPE_ATOMIC, 0);
399 }
400}
401
402/**
403 * Complete packet output. cvmx_pko_send_packet_prepare() must be
404 * called exactly once before this, and the same parameters must be
405 * passed to both cvmx_pko_send_packet_prepare() and
406 * cvmx_pko_send_packet_finish().
407 *
408 * @port: Port to send it on
409 * @queue: Queue to use
410 * @pko_command:
411 * PKO HW command word
412 * @packet: Packet to send
413 * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or
414 * CVMX_PKO_LOCK_CMD_QUEUE
415 *
416 * Returns returns CVMX_PKO_SUCCESS on success, or error code on
417 * failure of output
418 */
419static inline cvmx_pko_status_t cvmx_pko_send_packet_finish(
420 uint64_t port,
421 uint64_t queue,
422 cvmx_pko_command_word0_t pko_command,
423 union cvmx_buf_ptr packet,
424 cvmx_pko_lock_t use_locking)
425{
426 cvmx_cmd_queue_result_t result;
427 if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG)
428 cvmx_pow_tag_sw_wait();
429 result = cvmx_cmd_queue_write2(CVMX_CMD_QUEUE_PKO(queue),
430 (use_locking == CVMX_PKO_LOCK_CMD_QUEUE),
431 pko_command.u64, packet.u64);
432 if (likely(result == CVMX_CMD_QUEUE_SUCCESS)) {
433 cvmx_pko_doorbell(port, queue, 2);
434 return CVMX_PKO_SUCCESS;
435 } else if ((result == CVMX_CMD_QUEUE_NO_MEMORY)
436 || (result == CVMX_CMD_QUEUE_FULL)) {
437 return CVMX_PKO_NO_MEMORY;
438 } else {
439 return CVMX_PKO_INVALID_QUEUE;
440 }
441}
442
443/**
444 * Complete packet output. cvmx_pko_send_packet_prepare() must be
445 * called exactly once before this, and the same parameters must be
446 * passed to both cvmx_pko_send_packet_prepare() and
447 * cvmx_pko_send_packet_finish().
448 *
449 * @port: Port to send it on
450 * @queue: Queue to use
451 * @pko_command:
452 * PKO HW command word
453 * @packet: Packet to send
454 * @addr: Plysical address of a work queue entry or physical address
455 * to zero on complete.
456 * @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or
457 * CVMX_PKO_LOCK_CMD_QUEUE
458 *
459 * Returns returns CVMX_PKO_SUCCESS on success, or error code on
460 * failure of output
461 */
462static inline cvmx_pko_status_t cvmx_pko_send_packet_finish3(
463 uint64_t port,
464 uint64_t queue,
465 cvmx_pko_command_word0_t pko_command,
466 union cvmx_buf_ptr packet,
467 uint64_t addr,
468 cvmx_pko_lock_t use_locking)
469{
470 cvmx_cmd_queue_result_t result;
471 if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG)
472 cvmx_pow_tag_sw_wait();
473 result = cvmx_cmd_queue_write3(CVMX_CMD_QUEUE_PKO(queue),
474 (use_locking == CVMX_PKO_LOCK_CMD_QUEUE),
475 pko_command.u64, packet.u64, addr);
476 if (likely(result == CVMX_CMD_QUEUE_SUCCESS)) {
477 cvmx_pko_doorbell(port, queue, 3);
478 return CVMX_PKO_SUCCESS;
479 } else if ((result == CVMX_CMD_QUEUE_NO_MEMORY)
480 || (result == CVMX_CMD_QUEUE_FULL)) {
481 return CVMX_PKO_NO_MEMORY;
482 } else {
483 return CVMX_PKO_INVALID_QUEUE;
484 }
485}
486
487/**
488 * Return the pko output queue associated with a port and a specific core.
489 * In normal mode (PKO lockless operation is disabled), the value returned
490 * is the base queue.
491 *
492 * @port: Port number
493 * @core: Core to get queue for
494 *
495 * Returns Core-specific output queue
496 */
497static inline int cvmx_pko_get_base_queue_per_core(int port, int core)
498{
499#ifndef CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0
500#define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 16
501#endif
502#ifndef CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1
503#define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 16
504#endif
505
506 if (port < CVMX_PKO_MAX_PORTS_INTERFACE0)
507 return port * CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + core;
508 else if (port >= 16 && port < 16 + CVMX_PKO_MAX_PORTS_INTERFACE1)
509 return CVMX_PKO_MAX_PORTS_INTERFACE0 *
510 CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + (port -
511 16) *
512 CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + core;
513 else if ((port >= 32) && (port < 36))
514 return CVMX_PKO_MAX_PORTS_INTERFACE0 *
515 CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 +
516 CVMX_PKO_MAX_PORTS_INTERFACE1 *
517 CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + (port -
518 32) *
519 CVMX_PKO_QUEUES_PER_PORT_PCI;
520 else if ((port >= 36) && (port < 40))
521 return CVMX_PKO_MAX_PORTS_INTERFACE0 *
522 CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 +
523 CVMX_PKO_MAX_PORTS_INTERFACE1 *
524 CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 +
525 4 * CVMX_PKO_QUEUES_PER_PORT_PCI + (port -
526 36) *
527 CVMX_PKO_QUEUES_PER_PORT_LOOP;
528 else
529 /* Given the limit on the number of ports we can map to
530 * CVMX_MAX_OUTPUT_QUEUES_STATIC queues (currently 256,
531 * divided among all cores), the remaining unmapped ports
532 * are assigned an illegal queue number */
533 return CVMX_PKO_ILLEGAL_QUEUE;
534}
535
536/**
537 * For a given port number, return the base pko output queue
538 * for the port.
539 *
540 * @port: Port number
541 * Returns Base output queue
542 */
543static inline int cvmx_pko_get_base_queue(int port)
544{
545 if (OCTEON_IS_MODEL(OCTEON_CN68XX))
546 return port;
547
548 return cvmx_pko_get_base_queue_per_core(port, 0);
549}
550
551/**
552 * For a given port number, return the number of pko output queues.
553 *
554 * @port: Port number
555 * Returns Number of output queues
556 */
557static inline int cvmx_pko_get_num_queues(int port)
558{
559 if (port < 16)
560 return CVMX_PKO_QUEUES_PER_PORT_INTERFACE0;
561 else if (port < 32)
562 return CVMX_PKO_QUEUES_PER_PORT_INTERFACE1;
563 else if (port < 36)
564 return CVMX_PKO_QUEUES_PER_PORT_PCI;
565 else if (port < 40)
566 return CVMX_PKO_QUEUES_PER_PORT_LOOP;
567 else
568 return 0;
569}
570
571/**
572 * Get the status counters for a port.
573 *
574 * @port_num: Port number to get statistics for.
575 * @clear: Set to 1 to clear the counters after they are read
576 * @status: Where to put the results.
577 */
578static inline void cvmx_pko_get_port_status(uint64_t port_num, uint64_t clear,
579 cvmx_pko_port_status_t *status)
580{
581 union cvmx_pko_reg_read_idx pko_reg_read_idx;
582 union cvmx_pko_mem_count0 pko_mem_count0;
583 union cvmx_pko_mem_count1 pko_mem_count1;
584
585 pko_reg_read_idx.u64 = 0;
586 pko_reg_read_idx.s.index = port_num;
587 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
588
589 pko_mem_count0.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT0);
590 status->packets = pko_mem_count0.s.count;
591 if (clear) {
592 pko_mem_count0.s.count = port_num;
593 cvmx_write_csr(CVMX_PKO_MEM_COUNT0, pko_mem_count0.u64);
594 }
595
596 pko_mem_count1.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT1);
597 status->octets = pko_mem_count1.s.count;
598 if (clear) {
599 pko_mem_count1.s.count = port_num;
600 cvmx_write_csr(CVMX_PKO_MEM_COUNT1, pko_mem_count1.u64);
601 }
602
603 if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
604 union cvmx_pko_mem_debug9 debug9;
605 pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num);
606 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
607 debug9.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG9);
608 status->doorbell = debug9.cn38xx.doorbell;
609 } else {
610 union cvmx_pko_mem_debug8 debug8;
611 pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num);
612 cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
613 debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8);
614 status->doorbell = debug8.cn58xx.doorbell;
615 }
616}
617
618/**
619 * Rate limit a PKO port to a max packets/sec. This function is only
620 * supported on CN57XX, CN56XX, CN55XX, and CN54XX.
621 *
622 * @port: Port to rate limit
623 * @packets_s: Maximum packet/sec
624 * @burst: Maximum number of packets to burst in a row before rate
625 * limiting cuts in.
626 *
627 * Returns Zero on success, negative on failure
628 */
629extern int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst);
630
631/**
632 * Rate limit a PKO port to a max bits/sec. This function is only
633 * supported on CN57XX, CN56XX, CN55XX, and CN54XX.
634 *
635 * @port: Port to rate limit
636 * @bits_s: PKO rate limit in bits/sec
637 * @burst: Maximum number of bits to burst before rate
638 * limiting cuts in.
639 *
640 * Returns Zero on success, negative on failure
641 */
642extern int cvmx_pko_rate_limit_bits(int port, uint64_t bits_s, int burst);
643
644#endif /* __CVMX_PKO_H__ */