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1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Copyright (C) 2002 MontaVista Software Inc.
4 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
5 */
6#ifndef _ASM_FPU_H
7#define _ASM_FPU_H
8
9#include <linux/sched.h>
10#include <linux/sched/task_stack.h>
11#include <linux/ptrace.h>
12#include <linux/thread_info.h>
13#include <linux/bitops.h>
14
15#include <asm/mipsregs.h>
16#include <asm/cpu.h>
17#include <asm/cpu-features.h>
18#include <asm/fpu_emulator.h>
19#include <asm/hazards.h>
20#include <asm/ptrace.h>
21#include <asm/processor.h>
22#include <asm/current.h>
23#include <asm/msa.h>
24
25#ifdef CONFIG_MIPS_MT_FPAFF
26#include <asm/mips_mt.h>
27#endif
28
29/*
30 * This enum specifies a mode in which we want the FPU to operate, for cores
31 * which implement the Status.FR bit. Note that the bottom bit of the value
32 * purposefully matches the desired value of the Status.FR bit.
33 */
34enum fpu_mode {
35 FPU_32BIT = 0, /* FR = 0 */
36 FPU_64BIT, /* FR = 1, FRE = 0 */
37 FPU_AS_IS,
38 FPU_HYBRID, /* FR = 1, FRE = 1 */
39
40#define FPU_FR_MASK 0x1
41};
42
43#ifdef CONFIG_MIPS_FP_SUPPORT
44
45extern void _save_fp(struct task_struct *);
46extern void _restore_fp(struct task_struct *);
47
48#define __disable_fpu() \
49do { \
50 clear_c0_status(ST0_CU1); \
51 disable_fpu_hazard(); \
52} while (0)
53
54static inline int __enable_fpu(enum fpu_mode mode)
55{
56 int fr;
57
58 switch (mode) {
59 case FPU_AS_IS:
60 /* just enable the FPU in its current mode */
61 set_c0_status(ST0_CU1);
62 enable_fpu_hazard();
63 return 0;
64
65 case FPU_HYBRID:
66 if (!cpu_has_fre)
67 return SIGFPE;
68
69 /* set FRE */
70 set_c0_config5(MIPS_CONF5_FRE);
71 goto fr_common;
72
73 case FPU_64BIT:
74#if !(defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) \
75 || defined(CONFIG_64BIT))
76 /* we only have a 32-bit FPU */
77 return SIGFPE;
78#endif
79 /* fall through */
80 case FPU_32BIT:
81 if (cpu_has_fre) {
82 /* clear FRE */
83 clear_c0_config5(MIPS_CONF5_FRE);
84 }
85fr_common:
86 /* set CU1 & change FR appropriately */
87 fr = (int)mode & FPU_FR_MASK;
88 change_c0_status(ST0_CU1 | ST0_FR, ST0_CU1 | (fr ? ST0_FR : 0));
89 enable_fpu_hazard();
90
91 /* check FR has the desired value */
92 if (!!(read_c0_status() & ST0_FR) == !!fr)
93 return 0;
94
95 /* unsupported FR value */
96 __disable_fpu();
97 return SIGFPE;
98
99 default:
100 BUG();
101 }
102
103 return SIGFPE;
104}
105
106#define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU)
107
108static inline int __is_fpu_owner(void)
109{
110 return test_thread_flag(TIF_USEDFPU);
111}
112
113static inline int is_fpu_owner(void)
114{
115 return cpu_has_fpu && __is_fpu_owner();
116}
117
118static inline int __own_fpu(void)
119{
120 enum fpu_mode mode;
121 int ret;
122
123 if (test_thread_flag(TIF_HYBRID_FPREGS))
124 mode = FPU_HYBRID;
125 else
126 mode = !test_thread_flag(TIF_32BIT_FPREGS);
127
128 ret = __enable_fpu(mode);
129 if (ret)
130 return ret;
131
132 KSTK_STATUS(current) |= ST0_CU1;
133 if (mode == FPU_64BIT || mode == FPU_HYBRID)
134 KSTK_STATUS(current) |= ST0_FR;
135 else /* mode == FPU_32BIT */
136 KSTK_STATUS(current) &= ~ST0_FR;
137
138 set_thread_flag(TIF_USEDFPU);
139 return 0;
140}
141
142static inline int own_fpu_inatomic(int restore)
143{
144 int ret = 0;
145
146 if (cpu_has_fpu && !__is_fpu_owner()) {
147 ret = __own_fpu();
148 if (restore && !ret)
149 _restore_fp(current);
150 }
151 return ret;
152}
153
154static inline int own_fpu(int restore)
155{
156 int ret;
157
158 preempt_disable();
159 ret = own_fpu_inatomic(restore);
160 preempt_enable();
161 return ret;
162}
163
164static inline void lose_fpu_inatomic(int save, struct task_struct *tsk)
165{
166 if (is_msa_enabled()) {
167 if (save) {
168 save_msa(tsk);
169 tsk->thread.fpu.fcr31 =
170 read_32bit_cp1_register(CP1_STATUS);
171 }
172 disable_msa();
173 clear_tsk_thread_flag(tsk, TIF_USEDMSA);
174 __disable_fpu();
175 } else if (is_fpu_owner()) {
176 if (save)
177 _save_fp(tsk);
178 __disable_fpu();
179 } else {
180 /* FPU should not have been left enabled with no owner */
181 WARN(read_c0_status() & ST0_CU1,
182 "Orphaned FPU left enabled");
183 }
184 KSTK_STATUS(tsk) &= ~ST0_CU1;
185 clear_tsk_thread_flag(tsk, TIF_USEDFPU);
186}
187
188static inline void lose_fpu(int save)
189{
190 preempt_disable();
191 lose_fpu_inatomic(save, current);
192 preempt_enable();
193}
194
195/**
196 * init_fp_ctx() - Initialize task FP context
197 * @target: The task whose FP context should be initialized.
198 *
199 * Initializes the FP context of the target task to sane default values if that
200 * target task does not already have valid FP context. Once the context has
201 * been initialized, the task will be marked as having used FP & thus having
202 * valid FP context.
203 *
204 * Returns: true if context is initialized, else false.
205 */
206static inline bool init_fp_ctx(struct task_struct *target)
207{
208 /* If FP has been used then the target already has context */
209 if (tsk_used_math(target))
210 return false;
211
212 /* Begin with data registers set to all 1s... */
213 memset(&target->thread.fpu.fpr, ~0, sizeof(target->thread.fpu.fpr));
214
215 /* FCSR has been preset by `mips_set_personality_nan'. */
216
217 /*
218 * Record that the target has "used" math, such that the context
219 * just initialised, and any modifications made by the caller,
220 * aren't discarded.
221 */
222 set_stopped_child_used_math(target);
223
224 return true;
225}
226
227static inline void save_fp(struct task_struct *tsk)
228{
229 if (cpu_has_fpu)
230 _save_fp(tsk);
231}
232
233static inline void restore_fp(struct task_struct *tsk)
234{
235 if (cpu_has_fpu)
236 _restore_fp(tsk);
237}
238
239static inline union fpureg *get_fpu_regs(struct task_struct *tsk)
240{
241 if (tsk == current) {
242 preempt_disable();
243 if (is_fpu_owner())
244 _save_fp(current);
245 preempt_enable();
246 }
247
248 return tsk->thread.fpu.fpr;
249}
250
251#else /* !CONFIG_MIPS_FP_SUPPORT */
252
253/*
254 * When FP support is disabled we provide only a minimal set of stub functions
255 * to avoid callers needing to care too much about CONFIG_MIPS_FP_SUPPORT.
256 */
257
258static inline int __enable_fpu(enum fpu_mode mode)
259{
260 return SIGILL;
261}
262
263static inline void __disable_fpu(void)
264{
265 /* no-op */
266}
267
268
269static inline int is_fpu_owner(void)
270{
271 return 0;
272}
273
274static inline void clear_fpu_owner(void)
275{
276 /* no-op */
277}
278
279static inline int own_fpu_inatomic(int restore)
280{
281 return SIGILL;
282}
283
284static inline int own_fpu(int restore)
285{
286 return SIGILL;
287}
288
289static inline void lose_fpu_inatomic(int save, struct task_struct *tsk)
290{
291 /* no-op */
292}
293
294static inline void lose_fpu(int save)
295{
296 /* no-op */
297}
298
299static inline bool init_fp_ctx(struct task_struct *target)
300{
301 return false;
302}
303
304/*
305 * The following functions should only be called in paths where we know that FP
306 * support is enabled, typically a path where own_fpu() or __enable_fpu() have
307 * returned successfully. When CONFIG_MIPS_FP_SUPPORT=n it is known at compile
308 * time that this should never happen, so calls to these functions should be
309 * optimized away & never actually be emitted.
310 */
311
312extern void save_fp(struct task_struct *tsk)
313 __compiletime_error("save_fp() should not be called when CONFIG_MIPS_FP_SUPPORT=n");
314
315extern void _save_fp(struct task_struct *)
316 __compiletime_error("_save_fp() should not be called when CONFIG_MIPS_FP_SUPPORT=n");
317
318extern void restore_fp(struct task_struct *tsk)
319 __compiletime_error("restore_fp() should not be called when CONFIG_MIPS_FP_SUPPORT=n");
320
321extern void _restore_fp(struct task_struct *)
322 __compiletime_error("_restore_fp() should not be called when CONFIG_MIPS_FP_SUPPORT=n");
323
324extern union fpureg *get_fpu_regs(struct task_struct *tsk)
325 __compiletime_error("get_fpu_regs() should not be called when CONFIG_MIPS_FP_SUPPORT=n");
326
327#endif /* !CONFIG_MIPS_FP_SUPPORT */
328#endif /* _ASM_FPU_H */
1/*
2 * Copyright (C) 2002 MontaVista Software Inc.
3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
9 */
10#ifndef _ASM_FPU_H
11#define _ASM_FPU_H
12
13#include <linux/sched.h>
14#include <linux/sched/task_stack.h>
15#include <linux/ptrace.h>
16#include <linux/thread_info.h>
17#include <linux/bitops.h>
18
19#include <asm/mipsregs.h>
20#include <asm/cpu.h>
21#include <asm/cpu-features.h>
22#include <asm/fpu_emulator.h>
23#include <asm/hazards.h>
24#include <asm/ptrace.h>
25#include <asm/processor.h>
26#include <asm/current.h>
27#include <asm/msa.h>
28
29#ifdef CONFIG_MIPS_MT_FPAFF
30#include <asm/mips_mt.h>
31#endif
32
33struct sigcontext;
34struct sigcontext32;
35
36extern void _init_fpu(unsigned int);
37extern void _save_fp(struct task_struct *);
38extern void _restore_fp(struct task_struct *);
39
40/*
41 * This enum specifies a mode in which we want the FPU to operate, for cores
42 * which implement the Status.FR bit. Note that the bottom bit of the value
43 * purposefully matches the desired value of the Status.FR bit.
44 */
45enum fpu_mode {
46 FPU_32BIT = 0, /* FR = 0 */
47 FPU_64BIT, /* FR = 1, FRE = 0 */
48 FPU_AS_IS,
49 FPU_HYBRID, /* FR = 1, FRE = 1 */
50
51#define FPU_FR_MASK 0x1
52};
53
54#define __disable_fpu() \
55do { \
56 clear_c0_status(ST0_CU1); \
57 disable_fpu_hazard(); \
58} while (0)
59
60static inline int __enable_fpu(enum fpu_mode mode)
61{
62 int fr;
63
64 switch (mode) {
65 case FPU_AS_IS:
66 /* just enable the FPU in its current mode */
67 set_c0_status(ST0_CU1);
68 enable_fpu_hazard();
69 return 0;
70
71 case FPU_HYBRID:
72 if (!cpu_has_fre)
73 return SIGFPE;
74
75 /* set FRE */
76 set_c0_config5(MIPS_CONF5_FRE);
77 goto fr_common;
78
79 case FPU_64BIT:
80#if !(defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR6) \
81 || defined(CONFIG_64BIT))
82 /* we only have a 32-bit FPU */
83 return SIGFPE;
84#endif
85 /* fall through */
86 case FPU_32BIT:
87 if (cpu_has_fre) {
88 /* clear FRE */
89 clear_c0_config5(MIPS_CONF5_FRE);
90 }
91fr_common:
92 /* set CU1 & change FR appropriately */
93 fr = (int)mode & FPU_FR_MASK;
94 change_c0_status(ST0_CU1 | ST0_FR, ST0_CU1 | (fr ? ST0_FR : 0));
95 enable_fpu_hazard();
96
97 /* check FR has the desired value */
98 if (!!(read_c0_status() & ST0_FR) == !!fr)
99 return 0;
100
101 /* unsupported FR value */
102 __disable_fpu();
103 return SIGFPE;
104
105 default:
106 BUG();
107 }
108
109 return SIGFPE;
110}
111
112#define clear_fpu_owner() clear_thread_flag(TIF_USEDFPU)
113
114static inline int __is_fpu_owner(void)
115{
116 return test_thread_flag(TIF_USEDFPU);
117}
118
119static inline int is_fpu_owner(void)
120{
121 return cpu_has_fpu && __is_fpu_owner();
122}
123
124static inline int __own_fpu(void)
125{
126 enum fpu_mode mode;
127 int ret;
128
129 if (test_thread_flag(TIF_HYBRID_FPREGS))
130 mode = FPU_HYBRID;
131 else
132 mode = !test_thread_flag(TIF_32BIT_FPREGS);
133
134 ret = __enable_fpu(mode);
135 if (ret)
136 return ret;
137
138 KSTK_STATUS(current) |= ST0_CU1;
139 if (mode == FPU_64BIT || mode == FPU_HYBRID)
140 KSTK_STATUS(current) |= ST0_FR;
141 else /* mode == FPU_32BIT */
142 KSTK_STATUS(current) &= ~ST0_FR;
143
144 set_thread_flag(TIF_USEDFPU);
145 return 0;
146}
147
148static inline int own_fpu_inatomic(int restore)
149{
150 int ret = 0;
151
152 if (cpu_has_fpu && !__is_fpu_owner()) {
153 ret = __own_fpu();
154 if (restore && !ret)
155 _restore_fp(current);
156 }
157 return ret;
158}
159
160static inline int own_fpu(int restore)
161{
162 int ret;
163
164 preempt_disable();
165 ret = own_fpu_inatomic(restore);
166 preempt_enable();
167 return ret;
168}
169
170static inline void lose_fpu_inatomic(int save, struct task_struct *tsk)
171{
172 if (is_msa_enabled()) {
173 if (save) {
174 save_msa(tsk);
175 tsk->thread.fpu.fcr31 =
176 read_32bit_cp1_register(CP1_STATUS);
177 }
178 disable_msa();
179 clear_tsk_thread_flag(tsk, TIF_USEDMSA);
180 __disable_fpu();
181 } else if (is_fpu_owner()) {
182 if (save)
183 _save_fp(tsk);
184 __disable_fpu();
185 } else {
186 /* FPU should not have been left enabled with no owner */
187 WARN(read_c0_status() & ST0_CU1,
188 "Orphaned FPU left enabled");
189 }
190 KSTK_STATUS(tsk) &= ~ST0_CU1;
191 clear_tsk_thread_flag(tsk, TIF_USEDFPU);
192}
193
194static inline void lose_fpu(int save)
195{
196 preempt_disable();
197 lose_fpu_inatomic(save, current);
198 preempt_enable();
199}
200
201static inline int init_fpu(void)
202{
203 unsigned int fcr31 = current->thread.fpu.fcr31;
204 int ret = 0;
205
206 if (cpu_has_fpu) {
207 unsigned int config5;
208
209 ret = __own_fpu();
210 if (ret)
211 return ret;
212
213 if (!cpu_has_fre) {
214 _init_fpu(fcr31);
215
216 return 0;
217 }
218
219 /*
220 * Ensure FRE is clear whilst running _init_fpu, since
221 * single precision FP instructions are used. If FRE
222 * was set then we'll just end up initialising all 32
223 * 64b registers.
224 */
225 config5 = clear_c0_config5(MIPS_CONF5_FRE);
226 enable_fpu_hazard();
227
228 _init_fpu(fcr31);
229
230 /* Restore FRE */
231 write_c0_config5(config5);
232 enable_fpu_hazard();
233 } else
234 fpu_emulator_init_fpu();
235
236 return ret;
237}
238
239static inline void save_fp(struct task_struct *tsk)
240{
241 if (cpu_has_fpu)
242 _save_fp(tsk);
243}
244
245static inline void restore_fp(struct task_struct *tsk)
246{
247 if (cpu_has_fpu)
248 _restore_fp(tsk);
249}
250
251static inline union fpureg *get_fpu_regs(struct task_struct *tsk)
252{
253 if (tsk == current) {
254 preempt_disable();
255 if (is_fpu_owner())
256 _save_fp(current);
257 preempt_enable();
258 }
259
260 return tsk->thread.fpu.fpr;
261}
262
263#endif /* _ASM_FPU_H */