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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * ARM Ltd. Versatile Express
4 *
5 * Motherboard Express uATX
6 * V2M-P1
7 *
8 * HBI-0190D
9 *
10 * RS1 memory map ("ARM Cortex-A Series memory map" in the board's
11 * Technical Reference Manual)
12 *
13 * WARNING! The hardware described in this file is independent from the
14 * original variant (vexpress-v2m.dtsi), but there is a strong
15 * correspondence between the two configurations.
16 *
17 * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
18 * CHANGES TO vexpress-v2m.dtsi!
19 */
20
21/ {
22 smb@8000000 {
23 motherboard {
24 model = "V2M-P1";
25 arm,hbi = <0x190>;
26 arm,vexpress,site = <0>;
27 arm,v2m-memory-map = "rs1";
28 compatible = "arm,vexpress,v2m-p1", "simple-bus";
29 #address-cells = <2>; /* SMB chipselect number and offset */
30 #size-cells = <1>;
31 #interrupt-cells = <1>;
32 ranges;
33
34 nor_flash: flash@0,00000000 {
35 compatible = "arm,vexpress-flash", "cfi-flash";
36 reg = <0 0x00000000 0x04000000>,
37 <4 0x00000000 0x04000000>;
38 bank-width = <4>;
39 partitions {
40 compatible = "arm,arm-firmware-suite";
41 };
42 };
43
44 psram@1,00000000 {
45 compatible = "arm,vexpress-psram", "mtd-ram";
46 reg = <1 0x00000000 0x02000000>;
47 bank-width = <4>;
48 };
49
50 ethernet@2,02000000 {
51 compatible = "smsc,lan9118", "smsc,lan9115";
52 reg = <2 0x02000000 0x10000>;
53 interrupts = <15>;
54 phy-mode = "mii";
55 reg-io-width = <4>;
56 smsc,irq-active-high;
57 smsc,irq-push-pull;
58 vdd33a-supply = <&v2m_fixed_3v3>;
59 vddvario-supply = <&v2m_fixed_3v3>;
60 };
61
62 usb@2,03000000 {
63 compatible = "nxp,usb-isp1761";
64 reg = <2 0x03000000 0x20000>;
65 interrupts = <16>;
66 port1-otg;
67 };
68
69 iofpga@3,00000000 {
70 compatible = "simple-bus";
71 #address-cells = <1>;
72 #size-cells = <1>;
73 ranges = <0 3 0 0x200000>;
74
75 v2m_sysreg: sysreg@10000 {
76 compatible = "arm,vexpress-sysreg";
77 reg = <0x010000 0x1000>;
78 #address-cells = <1>;
79 #size-cells = <1>;
80 ranges = <0 0x10000 0x1000>;
81
82 v2m_led_gpios: gpio@8 {
83 compatible = "arm,vexpress-sysreg,sys_led";
84 reg = <0x008 4>;
85 gpio-controller;
86 #gpio-cells = <2>;
87 };
88
89 v2m_mmc_gpios: gpio@48 {
90 compatible = "arm,vexpress-sysreg,sys_mci";
91 reg = <0x048 4>;
92 gpio-controller;
93 #gpio-cells = <2>;
94 };
95
96 v2m_flash_gpios: gpio@4c {
97 compatible = "arm,vexpress-sysreg,sys_flash";
98 reg = <0x04c 4>;
99 gpio-controller;
100 #gpio-cells = <2>;
101 };
102 };
103
104 v2m_sysctl: sysctl@20000 {
105 compatible = "arm,sp810", "arm,primecell";
106 reg = <0x020000 0x1000>;
107 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
108 clock-names = "refclk", "timclk", "apb_pclk";
109 #clock-cells = <1>;
110 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
111 assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
112 assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
113 };
114
115 /* PCI-E I2C bus */
116 v2m_i2c_pcie: i2c@30000 {
117 compatible = "arm,versatile-i2c";
118 reg = <0x030000 0x1000>;
119
120 #address-cells = <1>;
121 #size-cells = <0>;
122
123 pcie-switch@60 {
124 compatible = "idt,89hpes32h8";
125 reg = <0x60>;
126 };
127 };
128
129 aaci@40000 {
130 compatible = "arm,pl041", "arm,primecell";
131 reg = <0x040000 0x1000>;
132 interrupts = <11>;
133 clocks = <&smbclk>;
134 clock-names = "apb_pclk";
135 };
136
137 mmci@50000 {
138 compatible = "arm,pl180", "arm,primecell";
139 reg = <0x050000 0x1000>;
140 interrupts = <9>, <10>;
141 cd-gpios = <&v2m_mmc_gpios 0 0>;
142 wp-gpios = <&v2m_mmc_gpios 1 0>;
143 max-frequency = <12000000>;
144 vmmc-supply = <&v2m_fixed_3v3>;
145 clocks = <&v2m_clk24mhz>, <&smbclk>;
146 clock-names = "mclk", "apb_pclk";
147 };
148
149 kmi@60000 {
150 compatible = "arm,pl050", "arm,primecell";
151 reg = <0x060000 0x1000>;
152 interrupts = <12>;
153 clocks = <&v2m_clk24mhz>, <&smbclk>;
154 clock-names = "KMIREFCLK", "apb_pclk";
155 };
156
157 kmi@70000 {
158 compatible = "arm,pl050", "arm,primecell";
159 reg = <0x070000 0x1000>;
160 interrupts = <13>;
161 clocks = <&v2m_clk24mhz>, <&smbclk>;
162 clock-names = "KMIREFCLK", "apb_pclk";
163 };
164
165 v2m_serial0: uart@90000 {
166 compatible = "arm,pl011", "arm,primecell";
167 reg = <0x090000 0x1000>;
168 interrupts = <5>;
169 clocks = <&v2m_oscclk2>, <&smbclk>;
170 clock-names = "uartclk", "apb_pclk";
171 };
172
173 v2m_serial1: uart@a0000 {
174 compatible = "arm,pl011", "arm,primecell";
175 reg = <0x0a0000 0x1000>;
176 interrupts = <6>;
177 clocks = <&v2m_oscclk2>, <&smbclk>;
178 clock-names = "uartclk", "apb_pclk";
179 };
180
181 v2m_serial2: uart@b0000 {
182 compatible = "arm,pl011", "arm,primecell";
183 reg = <0x0b0000 0x1000>;
184 interrupts = <7>;
185 clocks = <&v2m_oscclk2>, <&smbclk>;
186 clock-names = "uartclk", "apb_pclk";
187 };
188
189 v2m_serial3: uart@c0000 {
190 compatible = "arm,pl011", "arm,primecell";
191 reg = <0x0c0000 0x1000>;
192 interrupts = <8>;
193 clocks = <&v2m_oscclk2>, <&smbclk>;
194 clock-names = "uartclk", "apb_pclk";
195 };
196
197 wdt@f0000 {
198 compatible = "arm,sp805", "arm,primecell";
199 reg = <0x0f0000 0x1000>;
200 interrupts = <0>;
201 clocks = <&v2m_refclk32khz>, <&smbclk>;
202 clock-names = "wdogclk", "apb_pclk";
203 };
204
205 v2m_timer01: timer@110000 {
206 compatible = "arm,sp804", "arm,primecell";
207 reg = <0x110000 0x1000>;
208 interrupts = <2>;
209 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
210 clock-names = "timclken1", "timclken2", "apb_pclk";
211 };
212
213 v2m_timer23: timer@120000 {
214 compatible = "arm,sp804", "arm,primecell";
215 reg = <0x120000 0x1000>;
216 interrupts = <3>;
217 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
218 clock-names = "timclken1", "timclken2", "apb_pclk";
219 };
220
221 /* DVI I2C bus */
222 v2m_i2c_dvi: i2c@160000 {
223 compatible = "arm,versatile-i2c";
224 reg = <0x160000 0x1000>;
225 #address-cells = <1>;
226 #size-cells = <0>;
227
228 dvi-transmitter@39 {
229 compatible = "sil,sii9022-tpi", "sil,sii9022";
230 reg = <0x39>;
231
232 ports {
233 #address-cells = <1>;
234 #size-cells = <0>;
235
236 port@0 {
237 reg = <0>;
238 dvi_bridge_in: endpoint {
239 remote-endpoint = <&clcd_pads>;
240 };
241 };
242 };
243 };
244
245 dvi-transmitter@60 {
246 compatible = "sil,sii9022-cpi", "sil,sii9022";
247 reg = <0x60>;
248 };
249 };
250
251 rtc@170000 {
252 compatible = "arm,pl031", "arm,primecell";
253 reg = <0x170000 0x1000>;
254 interrupts = <4>;
255 clocks = <&smbclk>;
256 clock-names = "apb_pclk";
257 };
258
259 compact-flash@1a0000 {
260 compatible = "arm,vexpress-cf", "ata-generic";
261 reg = <0x1a0000 0x100
262 0x1a0100 0xf00>;
263 reg-shift = <2>;
264 };
265
266 clcd@1f0000 {
267 compatible = "arm,pl111", "arm,primecell";
268 reg = <0x1f0000 0x1000>;
269 interrupt-names = "combined";
270 interrupts = <14>;
271 clocks = <&v2m_oscclk1>, <&smbclk>;
272 clock-names = "clcdclk", "apb_pclk";
273 /* 800x600 16bpp @36MHz works fine */
274 max-memory-bandwidth = <54000000>;
275 memory-region = <&vram>;
276
277 port {
278 clcd_pads: endpoint {
279 remote-endpoint = <&dvi_bridge_in>;
280 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
281 };
282 };
283 };
284 };
285
286 v2m_fixed_3v3: fixed-regulator-0 {
287 compatible = "regulator-fixed";
288 regulator-name = "3V3";
289 regulator-min-microvolt = <3300000>;
290 regulator-max-microvolt = <3300000>;
291 regulator-always-on;
292 };
293
294 v2m_clk24mhz: clk24mhz {
295 compatible = "fixed-clock";
296 #clock-cells = <0>;
297 clock-frequency = <24000000>;
298 clock-output-names = "v2m:clk24mhz";
299 };
300
301 v2m_refclk1mhz: refclk1mhz {
302 compatible = "fixed-clock";
303 #clock-cells = <0>;
304 clock-frequency = <1000000>;
305 clock-output-names = "v2m:refclk1mhz";
306 };
307
308 v2m_refclk32khz: refclk32khz {
309 compatible = "fixed-clock";
310 #clock-cells = <0>;
311 clock-frequency = <32768>;
312 clock-output-names = "v2m:refclk32khz";
313 };
314
315 leds {
316 compatible = "gpio-leds";
317
318 user1 {
319 label = "v2m:green:user1";
320 gpios = <&v2m_led_gpios 0 0>;
321 linux,default-trigger = "heartbeat";
322 };
323
324 user2 {
325 label = "v2m:green:user2";
326 gpios = <&v2m_led_gpios 1 0>;
327 linux,default-trigger = "mmc0";
328 };
329
330 user3 {
331 label = "v2m:green:user3";
332 gpios = <&v2m_led_gpios 2 0>;
333 linux,default-trigger = "cpu0";
334 };
335
336 user4 {
337 label = "v2m:green:user4";
338 gpios = <&v2m_led_gpios 3 0>;
339 linux,default-trigger = "cpu1";
340 };
341
342 user5 {
343 label = "v2m:green:user5";
344 gpios = <&v2m_led_gpios 4 0>;
345 linux,default-trigger = "cpu2";
346 };
347
348 user6 {
349 label = "v2m:green:user6";
350 gpios = <&v2m_led_gpios 5 0>;
351 linux,default-trigger = "cpu3";
352 };
353
354 user7 {
355 label = "v2m:green:user7";
356 gpios = <&v2m_led_gpios 6 0>;
357 linux,default-trigger = "cpu4";
358 };
359
360 user8 {
361 label = "v2m:green:user8";
362 gpios = <&v2m_led_gpios 7 0>;
363 linux,default-trigger = "cpu5";
364 };
365 };
366
367 mcc {
368 compatible = "arm,vexpress,config-bus";
369 arm,vexpress,config-bridge = <&v2m_sysreg>;
370
371 oscclk0 {
372 /* MCC static memory clock */
373 compatible = "arm,vexpress-osc";
374 arm,vexpress-sysreg,func = <1 0>;
375 freq-range = <25000000 60000000>;
376 #clock-cells = <0>;
377 clock-output-names = "v2m:oscclk0";
378 };
379
380 v2m_oscclk1: oscclk1 {
381 /* CLCD clock */
382 compatible = "arm,vexpress-osc";
383 arm,vexpress-sysreg,func = <1 1>;
384 freq-range = <23750000 65000000>;
385 #clock-cells = <0>;
386 clock-output-names = "v2m:oscclk1";
387 };
388
389 v2m_oscclk2: oscclk2 {
390 /* IO FPGA peripheral clock */
391 compatible = "arm,vexpress-osc";
392 arm,vexpress-sysreg,func = <1 2>;
393 freq-range = <24000000 24000000>;
394 #clock-cells = <0>;
395 clock-output-names = "v2m:oscclk2";
396 };
397
398 volt-vio {
399 /* Logic level voltage */
400 compatible = "arm,vexpress-volt";
401 arm,vexpress-sysreg,func = <2 0>;
402 regulator-name = "VIO";
403 regulator-always-on;
404 label = "VIO";
405 };
406
407 temp-mcc {
408 /* MCC internal operating temperature */
409 compatible = "arm,vexpress-temp";
410 arm,vexpress-sysreg,func = <4 0>;
411 label = "MCC";
412 };
413
414 reset {
415 compatible = "arm,vexpress-reset";
416 arm,vexpress-sysreg,func = <5 0>;
417 };
418
419 muxfpga {
420 compatible = "arm,vexpress-muxfpga";
421 arm,vexpress-sysreg,func = <7 0>;
422 };
423
424 shutdown {
425 compatible = "arm,vexpress-shutdown";
426 arm,vexpress-sysreg,func = <8 0>;
427 };
428
429 reboot {
430 compatible = "arm,vexpress-reboot";
431 arm,vexpress-sysreg,func = <9 0>;
432 };
433
434 dvimode {
435 compatible = "arm,vexpress-dvimode";
436 arm,vexpress-sysreg,func = <11 0>;
437 };
438 };
439 };
440 };
441};
1/*
2 * ARM Ltd. Versatile Express
3 *
4 * Motherboard Express uATX
5 * V2M-P1
6 *
7 * HBI-0190D
8 *
9 * RS1 memory map ("ARM Cortex-A Series memory map" in the board's
10 * Technical Reference Manual)
11 *
12 * WARNING! The hardware described in this file is independent from the
13 * original variant (vexpress-v2m.dtsi), but there is a strong
14 * correspondence between the two configurations.
15 *
16 * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
17 * CHANGES TO vexpress-v2m.dtsi!
18 */
19
20 motherboard {
21 model = "V2M-P1";
22 arm,hbi = <0x190>;
23 arm,vexpress,site = <0>;
24 arm,v2m-memory-map = "rs1";
25 compatible = "arm,vexpress,v2m-p1", "simple-bus";
26 #address-cells = <2>; /* SMB chipselect number and offset */
27 #size-cells = <1>;
28 #interrupt-cells = <1>;
29 ranges;
30
31 flash@0,00000000 {
32 compatible = "arm,vexpress-flash", "cfi-flash";
33 reg = <0 0x00000000 0x04000000>,
34 <4 0x00000000 0x04000000>;
35 bank-width = <4>;
36 };
37
38 psram@1,00000000 {
39 compatible = "arm,vexpress-psram", "mtd-ram";
40 reg = <1 0x00000000 0x02000000>;
41 bank-width = <4>;
42 };
43
44 v2m_video_ram: vram@2,00000000 {
45 compatible = "arm,vexpress-vram";
46 reg = <2 0x00000000 0x00800000>;
47 };
48
49 ethernet@2,02000000 {
50 compatible = "smsc,lan9118", "smsc,lan9115";
51 reg = <2 0x02000000 0x10000>;
52 interrupts = <15>;
53 phy-mode = "mii";
54 reg-io-width = <4>;
55 smsc,irq-active-high;
56 smsc,irq-push-pull;
57 vdd33a-supply = <&v2m_fixed_3v3>;
58 vddvario-supply = <&v2m_fixed_3v3>;
59 };
60
61 usb@2,03000000 {
62 compatible = "nxp,usb-isp1761";
63 reg = <2 0x03000000 0x20000>;
64 interrupts = <16>;
65 port1-otg;
66 };
67
68 iofpga@3,00000000 {
69 compatible = "simple-bus";
70 #address-cells = <1>;
71 #size-cells = <1>;
72 ranges = <0 3 0 0x200000>;
73
74 v2m_sysreg: sysreg@10000 {
75 compatible = "arm,vexpress-sysreg";
76 reg = <0x010000 0x1000>;
77
78 v2m_led_gpios: sys_led {
79 compatible = "arm,vexpress-sysreg,sys_led";
80 gpio-controller;
81 #gpio-cells = <2>;
82 };
83
84 v2m_mmc_gpios: sys_mci {
85 compatible = "arm,vexpress-sysreg,sys_mci";
86 gpio-controller;
87 #gpio-cells = <2>;
88 };
89
90 v2m_flash_gpios: sys_flash {
91 compatible = "arm,vexpress-sysreg,sys_flash";
92 gpio-controller;
93 #gpio-cells = <2>;
94 };
95 };
96
97 v2m_sysctl: sysctl@20000 {
98 compatible = "arm,sp810", "arm,primecell";
99 reg = <0x020000 0x1000>;
100 clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
101 clock-names = "refclk", "timclk", "apb_pclk";
102 #clock-cells = <1>;
103 clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
104 assigned-clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_sysctl 3>, <&v2m_sysctl 3>;
105 assigned-clock-parents = <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>, <&v2m_refclk1mhz>;
106 };
107
108 /* PCI-E I2C bus */
109 v2m_i2c_pcie: i2c@30000 {
110 compatible = "arm,versatile-i2c";
111 reg = <0x030000 0x1000>;
112
113 #address-cells = <1>;
114 #size-cells = <0>;
115
116 pcie-switch@60 {
117 compatible = "idt,89hpes32h8";
118 reg = <0x60>;
119 };
120 };
121
122 aaci@40000 {
123 compatible = "arm,pl041", "arm,primecell";
124 reg = <0x040000 0x1000>;
125 interrupts = <11>;
126 clocks = <&smbclk>;
127 clock-names = "apb_pclk";
128 };
129
130 mmci@50000 {
131 compatible = "arm,pl180", "arm,primecell";
132 reg = <0x050000 0x1000>;
133 interrupts = <9 10>;
134 cd-gpios = <&v2m_mmc_gpios 0 0>;
135 wp-gpios = <&v2m_mmc_gpios 1 0>;
136 max-frequency = <12000000>;
137 vmmc-supply = <&v2m_fixed_3v3>;
138 clocks = <&v2m_clk24mhz>, <&smbclk>;
139 clock-names = "mclk", "apb_pclk";
140 };
141
142 kmi@60000 {
143 compatible = "arm,pl050", "arm,primecell";
144 reg = <0x060000 0x1000>;
145 interrupts = <12>;
146 clocks = <&v2m_clk24mhz>, <&smbclk>;
147 clock-names = "KMIREFCLK", "apb_pclk";
148 };
149
150 kmi@70000 {
151 compatible = "arm,pl050", "arm,primecell";
152 reg = <0x070000 0x1000>;
153 interrupts = <13>;
154 clocks = <&v2m_clk24mhz>, <&smbclk>;
155 clock-names = "KMIREFCLK", "apb_pclk";
156 };
157
158 v2m_serial0: uart@90000 {
159 compatible = "arm,pl011", "arm,primecell";
160 reg = <0x090000 0x1000>;
161 interrupts = <5>;
162 clocks = <&v2m_oscclk2>, <&smbclk>;
163 clock-names = "uartclk", "apb_pclk";
164 };
165
166 v2m_serial1: uart@a0000 {
167 compatible = "arm,pl011", "arm,primecell";
168 reg = <0x0a0000 0x1000>;
169 interrupts = <6>;
170 clocks = <&v2m_oscclk2>, <&smbclk>;
171 clock-names = "uartclk", "apb_pclk";
172 };
173
174 v2m_serial2: uart@b0000 {
175 compatible = "arm,pl011", "arm,primecell";
176 reg = <0x0b0000 0x1000>;
177 interrupts = <7>;
178 clocks = <&v2m_oscclk2>, <&smbclk>;
179 clock-names = "uartclk", "apb_pclk";
180 };
181
182 v2m_serial3: uart@c0000 {
183 compatible = "arm,pl011", "arm,primecell";
184 reg = <0x0c0000 0x1000>;
185 interrupts = <8>;
186 clocks = <&v2m_oscclk2>, <&smbclk>;
187 clock-names = "uartclk", "apb_pclk";
188 };
189
190 wdt@f0000 {
191 compatible = "arm,sp805", "arm,primecell";
192 reg = <0x0f0000 0x1000>;
193 interrupts = <0>;
194 clocks = <&v2m_refclk32khz>, <&smbclk>;
195 clock-names = "wdogclk", "apb_pclk";
196 };
197
198 v2m_timer01: timer@110000 {
199 compatible = "arm,sp804", "arm,primecell";
200 reg = <0x110000 0x1000>;
201 interrupts = <2>;
202 clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
203 clock-names = "timclken1", "timclken2", "apb_pclk";
204 };
205
206 v2m_timer23: timer@120000 {
207 compatible = "arm,sp804", "arm,primecell";
208 reg = <0x120000 0x1000>;
209 interrupts = <3>;
210 clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
211 clock-names = "timclken1", "timclken2", "apb_pclk";
212 };
213
214 /* DVI I2C bus */
215 v2m_i2c_dvi: i2c@160000 {
216 compatible = "arm,versatile-i2c";
217 reg = <0x160000 0x1000>;
218
219 #address-cells = <1>;
220 #size-cells = <0>;
221
222 dvi-transmitter@39 {
223 compatible = "sil,sii9022-tpi", "sil,sii9022";
224 reg = <0x39>;
225 };
226
227 dvi-transmitter@60 {
228 compatible = "sil,sii9022-cpi", "sil,sii9022";
229 reg = <0x60>;
230 };
231 };
232
233 rtc@170000 {
234 compatible = "arm,pl031", "arm,primecell";
235 reg = <0x170000 0x1000>;
236 interrupts = <4>;
237 clocks = <&smbclk>;
238 clock-names = "apb_pclk";
239 };
240
241 compact-flash@1a0000 {
242 compatible = "arm,vexpress-cf", "ata-generic";
243 reg = <0x1a0000 0x100
244 0x1a0100 0xf00>;
245 reg-shift = <2>;
246 };
247
248 clcd@1f0000 {
249 compatible = "arm,pl111", "arm,primecell";
250 reg = <0x1f0000 0x1000>;
251 interrupt-names = "combined";
252 interrupts = <14>;
253 clocks = <&v2m_oscclk1>, <&smbclk>;
254 clock-names = "clcdclk", "apb_pclk";
255 memory-region = <&v2m_video_ram>;
256 max-memory-bandwidth = <50350000>; /* 16bpp @ 25.175MHz */
257
258 port {
259 v2m_clcd_pads: endpoint {
260 remote-endpoint = <&v2m_clcd_panel>;
261 arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
262 };
263 };
264
265 panel {
266 compatible = "panel-dpi";
267
268 port {
269 v2m_clcd_panel: endpoint {
270 remote-endpoint = <&v2m_clcd_pads>;
271 };
272 };
273
274 panel-timing {
275 clock-frequency = <25175000>;
276 hactive = <640>;
277 hback-porch = <40>;
278 hfront-porch = <24>;
279 hsync-len = <96>;
280 vactive = <480>;
281 vback-porch = <32>;
282 vfront-porch = <11>;
283 vsync-len = <2>;
284 };
285 };
286 };
287 };
288
289 v2m_fixed_3v3: fixed-regulator-0 {
290 compatible = "regulator-fixed";
291 regulator-name = "3V3";
292 regulator-min-microvolt = <3300000>;
293 regulator-max-microvolt = <3300000>;
294 regulator-always-on;
295 };
296
297 v2m_clk24mhz: clk24mhz {
298 compatible = "fixed-clock";
299 #clock-cells = <0>;
300 clock-frequency = <24000000>;
301 clock-output-names = "v2m:clk24mhz";
302 };
303
304 v2m_refclk1mhz: refclk1mhz {
305 compatible = "fixed-clock";
306 #clock-cells = <0>;
307 clock-frequency = <1000000>;
308 clock-output-names = "v2m:refclk1mhz";
309 };
310
311 v2m_refclk32khz: refclk32khz {
312 compatible = "fixed-clock";
313 #clock-cells = <0>;
314 clock-frequency = <32768>;
315 clock-output-names = "v2m:refclk32khz";
316 };
317
318 leds {
319 compatible = "gpio-leds";
320
321 user1 {
322 label = "v2m:green:user1";
323 gpios = <&v2m_led_gpios 0 0>;
324 linux,default-trigger = "heartbeat";
325 };
326
327 user2 {
328 label = "v2m:green:user2";
329 gpios = <&v2m_led_gpios 1 0>;
330 linux,default-trigger = "mmc0";
331 };
332
333 user3 {
334 label = "v2m:green:user3";
335 gpios = <&v2m_led_gpios 2 0>;
336 linux,default-trigger = "cpu0";
337 };
338
339 user4 {
340 label = "v2m:green:user4";
341 gpios = <&v2m_led_gpios 3 0>;
342 linux,default-trigger = "cpu1";
343 };
344
345 user5 {
346 label = "v2m:green:user5";
347 gpios = <&v2m_led_gpios 4 0>;
348 linux,default-trigger = "cpu2";
349 };
350
351 user6 {
352 label = "v2m:green:user6";
353 gpios = <&v2m_led_gpios 5 0>;
354 linux,default-trigger = "cpu3";
355 };
356
357 user7 {
358 label = "v2m:green:user7";
359 gpios = <&v2m_led_gpios 6 0>;
360 linux,default-trigger = "cpu4";
361 };
362
363 user8 {
364 label = "v2m:green:user8";
365 gpios = <&v2m_led_gpios 7 0>;
366 linux,default-trigger = "cpu5";
367 };
368 };
369
370 mcc {
371 compatible = "arm,vexpress,config-bus";
372 arm,vexpress,config-bridge = <&v2m_sysreg>;
373
374 oscclk0 {
375 /* MCC static memory clock */
376 compatible = "arm,vexpress-osc";
377 arm,vexpress-sysreg,func = <1 0>;
378 freq-range = <25000000 60000000>;
379 #clock-cells = <0>;
380 clock-output-names = "v2m:oscclk0";
381 };
382
383 v2m_oscclk1: oscclk1 {
384 /* CLCD clock */
385 compatible = "arm,vexpress-osc";
386 arm,vexpress-sysreg,func = <1 1>;
387 freq-range = <23750000 65000000>;
388 #clock-cells = <0>;
389 clock-output-names = "v2m:oscclk1";
390 };
391
392 v2m_oscclk2: oscclk2 {
393 /* IO FPGA peripheral clock */
394 compatible = "arm,vexpress-osc";
395 arm,vexpress-sysreg,func = <1 2>;
396 freq-range = <24000000 24000000>;
397 #clock-cells = <0>;
398 clock-output-names = "v2m:oscclk2";
399 };
400
401 volt-vio {
402 /* Logic level voltage */
403 compatible = "arm,vexpress-volt";
404 arm,vexpress-sysreg,func = <2 0>;
405 regulator-name = "VIO";
406 regulator-always-on;
407 label = "VIO";
408 };
409
410 temp-mcc {
411 /* MCC internal operating temperature */
412 compatible = "arm,vexpress-temp";
413 arm,vexpress-sysreg,func = <4 0>;
414 label = "MCC";
415 };
416
417 reset {
418 compatible = "arm,vexpress-reset";
419 arm,vexpress-sysreg,func = <5 0>;
420 };
421
422 muxfpga {
423 compatible = "arm,vexpress-muxfpga";
424 arm,vexpress-sysreg,func = <7 0>;
425 };
426
427 shutdown {
428 compatible = "arm,vexpress-shutdown";
429 arm,vexpress-sysreg,func = <8 0>;
430 };
431
432 reboot {
433 compatible = "arm,vexpress-reboot";
434 arm,vexpress-sysreg,func = <9 0>;
435 };
436
437 dvimode {
438 compatible = "arm,vexpress-dvimode";
439 arm,vexpress-sysreg,func = <11 0>;
440 };
441 };
442 };