Loading...
1// SPDX-License-Identifier: GPL-2.0
2//
3// Copyright (C) 2015 Freescale Semiconductor, Inc.
4
5/ {
6 chosen {
7 stdout-path = &uart1;
8 };
9
10 memory@80000000 {
11 device_type = "memory";
12 reg = <0x80000000 0x20000000>;
13 };
14
15 backlight_display: backlight-display {
16 compatible = "pwm-backlight";
17 pwms = <&pwm1 0 5000000>;
18 brightness-levels = <0 4 8 16 32 64 128 255>;
19 default-brightness-level = <6>;
20 status = "okay";
21 };
22
23
24 reg_sd1_vmmc: regulator-sd1-vmmc {
25 compatible = "regulator-fixed";
26 regulator-name = "VSD_3V3";
27 regulator-min-microvolt = <3300000>;
28 regulator-max-microvolt = <3300000>;
29 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
30 enable-active-high;
31 };
32
33 reg_can_3v3: regulator-can-3v3 {
34 compatible = "regulator-fixed";
35 regulator-name = "can-3v3";
36 regulator-min-microvolt = <3300000>;
37 regulator-max-microvolt = <3300000>;
38 gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
39 };
40
41 sound {
42 compatible = "simple-audio-card";
43 simple-audio-card,name = "mx6ul-wm8960";
44 simple-audio-card,format = "i2s";
45 simple-audio-card,bitclock-master = <&dailink_master>;
46 simple-audio-card,frame-master = <&dailink_master>;
47 simple-audio-card,widgets =
48 "Microphone", "Mic Jack",
49 "Line", "Line In",
50 "Line", "Line Out",
51 "Speaker", "Speaker",
52 "Headphone", "Headphone Jack";
53 simple-audio-card,routing =
54 "Headphone Jack", "HP_L",
55 "Headphone Jack", "HP_R",
56 "Speaker", "SPK_LP",
57 "Speaker", "SPK_LN",
58 "Speaker", "SPK_RP",
59 "Speaker", "SPK_RN",
60 "LINPUT1", "Mic Jack",
61 "LINPUT3", "Mic Jack",
62 "RINPUT1", "Mic Jack",
63 "RINPUT2", "Mic Jack";
64
65 simple-audio-card,cpu {
66 sound-dai = <&sai2>;
67 };
68
69 dailink_master: simple-audio-card,codec {
70 sound-dai = <&codec>;
71 clocks = <&clks IMX6UL_CLK_SAI2>;
72 };
73 };
74
75 spi4 {
76 compatible = "spi-gpio";
77 pinctrl-names = "default";
78 pinctrl-0 = <&pinctrl_spi4>;
79 status = "okay";
80 gpio-sck = <&gpio5 11 0>;
81 gpio-mosi = <&gpio5 10 0>;
82 cs-gpios = <&gpio5 7 0>;
83 num-chipselects = <1>;
84 #address-cells = <1>;
85 #size-cells = <0>;
86
87 gpio_spi: gpio@0 {
88 compatible = "fairchild,74hc595";
89 gpio-controller;
90 #gpio-cells = <2>;
91 reg = <0>;
92 registers-number = <1>;
93 spi-max-frequency = <100000>;
94 };
95 };
96
97 panel {
98 compatible = "innolux,at043tn24";
99 backlight = <&backlight_display>;
100
101 port {
102 panel_in: endpoint {
103 remote-endpoint = <&display_out>;
104 };
105 };
106 };
107};
108
109&clks {
110 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
111 assigned-clock-rates = <786432000>;
112};
113
114&i2c2 {
115 clock-frequency = <100000>;
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_i2c2>;
118 status = "okay";
119
120 codec: wm8960@1a {
121 #sound-dai-cells = <0>;
122 compatible = "wlf,wm8960";
123 reg = <0x1a>;
124 wlf,shared-lrclk;
125 };
126};
127
128&fec1 {
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_enet1>;
131 phy-mode = "rmii";
132 phy-handle = <ðphy0>;
133 status = "okay";
134};
135
136&fec2 {
137 pinctrl-names = "default";
138 pinctrl-0 = <&pinctrl_enet2>;
139 phy-mode = "rmii";
140 phy-handle = <ðphy1>;
141 status = "okay";
142
143 mdio {
144 #address-cells = <1>;
145 #size-cells = <0>;
146
147 ethphy0: ethernet-phy@2 {
148 reg = <2>;
149 micrel,led-mode = <1>;
150 clocks = <&clks IMX6UL_CLK_ENET_REF>;
151 clock-names = "rmii-ref";
152 };
153
154 ethphy1: ethernet-phy@1 {
155 reg = <1>;
156 micrel,led-mode = <1>;
157 clocks = <&clks IMX6UL_CLK_ENET2_REF>;
158 clock-names = "rmii-ref";
159 };
160 };
161};
162
163&can1 {
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_flexcan1>;
166 xceiver-supply = <®_can_3v3>;
167 status = "okay";
168};
169
170&can2 {
171 pinctrl-names = "default";
172 pinctrl-0 = <&pinctrl_flexcan2>;
173 xceiver-supply = <®_can_3v3>;
174 status = "okay";
175};
176
177&i2c1 {
178 clock-frequency = <100000>;
179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_i2c1>;
181 status = "okay";
182
183 mag3110@e {
184 compatible = "fsl,mag3110";
185 reg = <0x0e>;
186 };
187};
188
189&lcdif {
190 assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>;
191 assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>;
192 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_lcdif_dat
194 &pinctrl_lcdif_ctrl>;
195 status = "okay";
196
197 port {
198 display_out: endpoint {
199 remote-endpoint = <&panel_in>;
200 };
201 };
202};
203
204&pwm1 {
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_pwm1>;
207 status = "okay";
208};
209
210&qspi {
211 pinctrl-names = "default";
212 pinctrl-0 = <&pinctrl_qspi>;
213 status = "okay";
214
215 flash0: n25q256a@0 {
216 #address-cells = <1>;
217 #size-cells = <1>;
218 compatible = "micron,n25q256a";
219 spi-max-frequency = <29000000>;
220 spi-rx-bus-width = <4>;
221 spi-tx-bus-width = <4>;
222 reg = <0>;
223 };
224};
225
226&sai2 {
227 pinctrl-names = "default";
228 pinctrl-0 = <&pinctrl_sai2>;
229 assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
230 <&clks IMX6UL_CLK_SAI2>;
231 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
232 assigned-clock-rates = <0>, <12288000>;
233 fsl,sai-mclk-direction-output;
234 status = "okay";
235};
236
237&snvs_poweroff {
238 status = "okay";
239};
240
241&snvs_pwrkey {
242 status = "okay";
243};
244
245&tsc {
246 pinctrl-names = "default";
247 pinctrl-0 = <&pinctrl_tsc>;
248 xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
249 measure-delay-time = <0xffff>;
250 pre-charge-time = <0xfff>;
251 status = "okay";
252};
253
254&uart1 {
255 pinctrl-names = "default";
256 pinctrl-0 = <&pinctrl_uart1>;
257 status = "okay";
258};
259
260&uart2 {
261 pinctrl-names = "default";
262 pinctrl-0 = <&pinctrl_uart2>;
263 uart-has-rtscts;
264 status = "okay";
265};
266
267&usbotg1 {
268 dr_mode = "otg";
269 status = "okay";
270};
271
272&usbotg2 {
273 dr_mode = "host";
274 disable-over-current;
275 status = "okay";
276};
277
278&usbphy1 {
279 fsl,tx-d-cal = <106>;
280};
281
282&usbphy2 {
283 fsl,tx-d-cal = <106>;
284};
285
286&usdhc1 {
287 pinctrl-names = "default", "state_100mhz", "state_200mhz";
288 pinctrl-0 = <&pinctrl_usdhc1>;
289 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
290 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
291 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
292 keep-power-in-suspend;
293 wakeup-source;
294 vmmc-supply = <®_sd1_vmmc>;
295 status = "okay";
296};
297
298&usdhc2 {
299 pinctrl-names = "default";
300 pinctrl-0 = <&pinctrl_usdhc2>;
301 no-1-8-v;
302 keep-power-in-suspend;
303 wakeup-source;
304 status = "okay";
305};
306
307&wdog1 {
308 pinctrl-names = "default";
309 pinctrl-0 = <&pinctrl_wdog>;
310 fsl,ext-reset-output;
311};
312
313&iomuxc {
314 pinctrl-names = "default";
315
316 pinctrl_csi1: csi1grp {
317 fsl,pins = <
318 MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088
319 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088
320 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088
321 MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088
322 MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088
323 MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088
324 MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088
325 MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088
326 MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088
327 MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088
328 MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088
329 MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088
330 >;
331 };
332
333 pinctrl_enet1: enet1grp {
334 fsl,pins = <
335 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
336 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
337 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
338 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
339 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
340 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
341 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
342 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
343 >;
344 };
345
346 pinctrl_enet2: enet2grp {
347 fsl,pins = <
348 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
349 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
350 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
351 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
352 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
353 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
354 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
355 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
356 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
357 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
358 >;
359 };
360
361 pinctrl_flexcan1: flexcan1grp{
362 fsl,pins = <
363 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
364 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
365 >;
366 };
367
368 pinctrl_flexcan2: flexcan2grp{
369 fsl,pins = <
370 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
371 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
372 >;
373 };
374
375 pinctrl_i2c1: i2c1grp {
376 fsl,pins = <
377 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
378 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
379 >;
380 };
381
382 pinctrl_i2c2: i2c2grp {
383 fsl,pins = <
384 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
385 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
386 >;
387 };
388
389 pinctrl_lcdif_dat: lcdifdatgrp {
390 fsl,pins = <
391 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
392 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
393 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
394 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
395 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
396 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
397 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
398 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
399 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
400 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
401 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
402 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
403 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
404 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
405 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
406 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
407 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
408 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
409 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
410 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
411 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
412 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
413 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
414 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
415 >;
416 };
417
418 pinctrl_lcdif_ctrl: lcdifctrlgrp {
419 fsl,pins = <
420 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
421 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
422 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
423 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
424 /* used for lcd reset */
425 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
426 >;
427 };
428
429 pinctrl_qspi: qspigrp {
430 fsl,pins = <
431 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
432 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
433 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
434 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
435 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
436 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
437 >;
438 };
439
440 pinctrl_sai2: sai2grp {
441 fsl,pins = <
442 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
443 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
444 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
445 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
446 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
447 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059
448 >;
449 };
450
451 pinctrl_pwm1: pwm1grp {
452 fsl,pins = <
453 MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
454 >;
455 };
456
457 pinctrl_sim2: sim2grp {
458 fsl,pins = <
459 MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808
460 MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31
461 MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808
462 MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808
463 MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809
464 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008
465 >;
466 };
467
468 pinctrl_spi4: spi4grp {
469 fsl,pins = <
470 MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1
471 MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1
472 MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1
473 MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000
474 >;
475 };
476
477 pinctrl_tsc: tscgrp {
478 fsl,pins = <
479 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
480 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
481 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
482 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
483 >;
484 };
485
486 pinctrl_uart1: uart1grp {
487 fsl,pins = <
488 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
489 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
490 >;
491 };
492
493 pinctrl_uart2: uart2grp {
494 fsl,pins = <
495 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
496 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
497 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
498 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
499 >;
500 };
501
502 pinctrl_usdhc1: usdhc1grp {
503 fsl,pins = <
504 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
505 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
506 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
507 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
508 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
509 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
510 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
511 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
512 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
513 >;
514 };
515
516 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
517 fsl,pins = <
518 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
519 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
520 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
521 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
522 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
523 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
524
525 >;
526 };
527
528 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
529 fsl,pins = <
530 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
531 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
532 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
533 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
534 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
535 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
536 >;
537 };
538
539 pinctrl_usdhc2: usdhc2grp {
540 fsl,pins = <
541 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
542 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
543 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
544 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
545 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
546 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
547 >;
548 };
549
550 pinctrl_wdog: wdoggrp {
551 fsl,pins = <
552 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
553 >;
554 };
555};
1/*
2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/ {
10 chosen {
11 stdout-path = &uart1;
12 };
13
14 memory@80000000 {
15 reg = <0x80000000 0x20000000>;
16 };
17
18 backlight_display: backlight-display {
19 compatible = "pwm-backlight";
20 pwms = <&pwm1 0 5000000>;
21 brightness-levels = <0 4 8 16 32 64 128 255>;
22 default-brightness-level = <6>;
23 status = "okay";
24 };
25
26
27 reg_sd1_vmmc: regulator-sd1-vmmc {
28 compatible = "regulator-fixed";
29 regulator-name = "VSD_3V3";
30 regulator-min-microvolt = <3300000>;
31 regulator-max-microvolt = <3300000>;
32 gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
33 enable-active-high;
34 };
35
36 sound {
37 compatible = "simple-audio-card";
38 simple-audio-card,name = "mx6ul-wm8960";
39 simple-audio-card,format = "i2s";
40 simple-audio-card,bitclock-master = <&dailink_master>;
41 simple-audio-card,frame-master = <&dailink_master>;
42 simple-audio-card,widgets =
43 "Microphone", "Mic Jack",
44 "Line", "Line In",
45 "Line", "Line Out",
46 "Speaker", "Speaker",
47 "Headphone", "Headphone Jack";
48 simple-audio-card,routing =
49 "Headphone Jack", "HP_L",
50 "Headphone Jack", "HP_R",
51 "Speaker", "SPK_LP",
52 "Speaker", "SPK_LN",
53 "Speaker", "SPK_RP",
54 "Speaker", "SPK_RN",
55 "LINPUT1", "Mic Jack",
56 "LINPUT3", "Mic Jack",
57 "RINPUT1", "Mic Jack",
58 "RINPUT2", "Mic Jack";
59
60 simple-audio-card,cpu {
61 sound-dai = <&sai2>;
62 };
63
64 dailink_master: simple-audio-card,codec {
65 sound-dai = <&codec>;
66 clocks = <&clks IMX6UL_CLK_SAI2>;
67 };
68 };
69
70 panel {
71 compatible = "innolux,at043tn24";
72 backlight = <&backlight_display>;
73
74 port {
75 panel_in: endpoint {
76 remote-endpoint = <&display_out>;
77 };
78 };
79 };
80};
81
82&clks {
83 assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
84 assigned-clock-rates = <786432000>;
85};
86
87&i2c2 {
88 clock_frequency = <100000>;
89 pinctrl-names = "default";
90 pinctrl-0 = <&pinctrl_i2c2>;
91 status = "okay";
92
93 codec: wm8960@1a {
94 #sound-dai-cells = <0>;
95 compatible = "wlf,wm8960";
96 reg = <0x1a>;
97 wlf,shared-lrclk;
98 };
99};
100
101&fec1 {
102 pinctrl-names = "default";
103 pinctrl-0 = <&pinctrl_enet1>;
104 phy-mode = "rmii";
105 phy-handle = <ðphy0>;
106 status = "okay";
107};
108
109&fec2 {
110 pinctrl-names = "default";
111 pinctrl-0 = <&pinctrl_enet2>;
112 phy-mode = "rmii";
113 phy-handle = <ðphy1>;
114 status = "okay";
115
116 mdio {
117 #address-cells = <1>;
118 #size-cells = <0>;
119
120 ethphy0: ethernet-phy@2 {
121 reg = <2>;
122 micrel,led-mode = <1>;
123 clocks = <&clks IMX6UL_CLK_ENET_REF>;
124 clock-names = "rmii-ref";
125 };
126
127 ethphy1: ethernet-phy@1 {
128 reg = <1>;
129 micrel,led-mode = <1>;
130 clocks = <&clks IMX6UL_CLK_ENET2_REF>;
131 clock-names = "rmii-ref";
132 };
133 };
134};
135
136&i2c1 {
137 clock-frequency = <100000>;
138 pinctrl-names = "default";
139 pinctrl-0 = <&pinctrl_i2c1>;
140 status = "okay";
141
142 mag3110@e {
143 compatible = "fsl,mag3110";
144 reg = <0x0e>;
145 };
146};
147
148&lcdif {
149 assigned-clocks = <&clks IMX6UL_CLK_LCDIF_PRE_SEL>;
150 assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>;
151 pinctrl-names = "default";
152 pinctrl-0 = <&pinctrl_lcdif_dat
153 &pinctrl_lcdif_ctrl>;
154 status = "okay";
155
156 port {
157 display_out: endpoint {
158 remote-endpoint = <&panel_in>;
159 };
160 };
161};
162
163&pwm1 {
164 pinctrl-names = "default";
165 pinctrl-0 = <&pinctrl_pwm1>;
166 status = "okay";
167};
168
169&qspi {
170 pinctrl-names = "default";
171 pinctrl-0 = <&pinctrl_qspi>;
172 status = "okay";
173
174 flash0: n25q256a@0 {
175 #address-cells = <1>;
176 #size-cells = <1>;
177 compatible = "micron,n25q256a";
178 spi-max-frequency = <29000000>;
179 reg = <0>;
180 };
181};
182
183&sai2 {
184 pinctrl-names = "default";
185 pinctrl-0 = <&pinctrl_sai2>;
186 assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
187 <&clks IMX6UL_CLK_SAI2>;
188 assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
189 assigned-clock-rates = <0>, <12288000>;
190 fsl,sai-mclk-direction-output;
191 status = "okay";
192};
193
194&snvs_poweroff {
195 status = "okay";
196};
197
198&tsc {
199 pinctrl-names = "default";
200 pinctrl-0 = <&pinctrl_tsc>;
201 xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
202 measure-delay-time = <0xffff>;
203 pre-charge-time = <0xfff>;
204 status = "okay";
205};
206
207&uart1 {
208 pinctrl-names = "default";
209 pinctrl-0 = <&pinctrl_uart1>;
210 status = "okay";
211};
212
213&uart2 {
214 pinctrl-names = "default";
215 pinctrl-0 = <&pinctrl_uart2>;
216 uart-has-rtscts;
217 status = "okay";
218};
219
220&usbotg1 {
221 dr_mode = "otg";
222 status = "okay";
223};
224
225&usbotg2 {
226 dr_mode = "host";
227 disable-over-current;
228 status = "okay";
229};
230
231&usbphy1 {
232 fsl,tx-d-cal = <106>;
233};
234
235&usbphy2 {
236 fsl,tx-d-cal = <106>;
237};
238
239&usdhc1 {
240 pinctrl-names = "default", "state_100mhz", "state_200mhz";
241 pinctrl-0 = <&pinctrl_usdhc1>;
242 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
243 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
244 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
245 keep-power-in-suspend;
246 wakeup-source;
247 vmmc-supply = <®_sd1_vmmc>;
248 status = "okay";
249};
250
251&usdhc2 {
252 pinctrl-names = "default";
253 pinctrl-0 = <&pinctrl_usdhc2>;
254 no-1-8-v;
255 keep-power-in-suspend;
256 wakeup-source;
257 status = "okay";
258};
259
260&wdog1 {
261 pinctrl-names = "default";
262 pinctrl-0 = <&pinctrl_wdog>;
263 fsl,ext-reset-output;
264};
265
266&iomuxc {
267 pinctrl-names = "default";
268
269 pinctrl_csi1: csi1grp {
270 fsl,pins = <
271 MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088
272 MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088
273 MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088
274 MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088
275 MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088
276 MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088
277 MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088
278 MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088
279 MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088
280 MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088
281 MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088
282 MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088
283 >;
284 };
285
286 pinctrl_enet1: enet1grp {
287 fsl,pins = <
288 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
289 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
290 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
291 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
292 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
293 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
294 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
295 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
296 >;
297 };
298
299 pinctrl_enet2: enet2grp {
300 fsl,pins = <
301 MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
302 MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
303 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
304 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
305 MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
306 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
307 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
308 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
309 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
310 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
311 >;
312 };
313
314 pinctrl_flexcan1: flexcan1grp{
315 fsl,pins = <
316 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
317 MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
318 >;
319 };
320
321 pinctrl_flexcan2: flexcan2grp{
322 fsl,pins = <
323 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
324 MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
325 >;
326 };
327
328 pinctrl_i2c1: i2c1grp {
329 fsl,pins = <
330 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
331 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
332 >;
333 };
334
335 pinctrl_i2c2: i2c2grp {
336 fsl,pins = <
337 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
338 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
339 >;
340 };
341
342 pinctrl_lcdif_dat: lcdifdatgrp {
343 fsl,pins = <
344 MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
345 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
346 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
347 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
348 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
349 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
350 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
351 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
352 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
353 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
354 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
355 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
356 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
357 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
358 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
359 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
360 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
361 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
362 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
363 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
364 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
365 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
366 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
367 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
368 >;
369 };
370
371 pinctrl_lcdif_ctrl: lcdifctrlgrp {
372 fsl,pins = <
373 MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
374 MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
375 MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
376 MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
377 /* used for lcd reset */
378 MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
379 >;
380 };
381
382 pinctrl_qspi: qspigrp {
383 fsl,pins = <
384 MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
385 MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
386 MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
387 MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
388 MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
389 MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
390 >;
391 };
392
393 pinctrl_sai2: sai2grp {
394 fsl,pins = <
395 MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
396 MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
397 MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
398 MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
399 MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
400 MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059
401 >;
402 };
403
404 pinctrl_pwm1: pwm1grp {
405 fsl,pins = <
406 MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
407 >;
408 };
409
410 pinctrl_sim2: sim2grp {
411 fsl,pins = <
412 MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808
413 MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31
414 MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808
415 MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808
416 MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809
417 MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008
418 >;
419 };
420
421 pinctrl_tsc: tscgrp {
422 fsl,pins = <
423 MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
424 MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
425 MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
426 MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
427 >;
428 };
429
430 pinctrl_uart1: uart1grp {
431 fsl,pins = <
432 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
433 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
434 >;
435 };
436
437 pinctrl_uart2: uart2grp {
438 fsl,pins = <
439 MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
440 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
441 MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
442 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
443 >;
444 };
445
446 pinctrl_usdhc1: usdhc1grp {
447 fsl,pins = <
448 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
449 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
450 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
451 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
452 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
453 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
454 MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
455 MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
456 MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
457 >;
458 };
459
460 pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
461 fsl,pins = <
462 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
463 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
464 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
465 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
466 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
467 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
468
469 >;
470 };
471
472 pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
473 fsl,pins = <
474 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
475 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
476 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
477 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
478 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
479 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
480 >;
481 };
482
483 pinctrl_usdhc2: usdhc2grp {
484 fsl,pins = <
485 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
486 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
487 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
488 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
489 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
490 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
491 >;
492 };
493
494 pinctrl_wdog: wdoggrp {
495 fsl,pins = <
496 MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
497 >;
498 };
499};