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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2013 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7
8/ {
9 /* these are used by bootloader for disabling nodes */
10 aliases {
11 led0 = &led0;
12 led1 = &led1;
13 led2 = &led2;
14 nand = &gpmi;
15 ssi0 = &ssi1;
16 usb0 = &usbh1;
17 usb1 = &usbotg;
18 };
19
20 chosen {
21 bootargs = "console=ttymxc1,115200";
22 };
23
24 backlight {
25 compatible = "pwm-backlight";
26 pwms = <&pwm4 0 5000000>;
27 brightness-levels = <0 4 8 16 32 64 128 255>;
28 default-brightness-level = <7>;
29 };
30
31 leds {
32 compatible = "gpio-leds";
33 pinctrl-names = "default";
34 pinctrl-0 = <&pinctrl_gpio_leds>;
35
36 led0: user1 {
37 label = "user1";
38 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
39 default-state = "on";
40 linux,default-trigger = "heartbeat";
41 };
42
43 led1: user2 {
44 label = "user2";
45 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
46 default-state = "off";
47 };
48
49 led2: user3 {
50 label = "user3";
51 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
52 default-state = "off";
53 };
54 };
55
56 memory@10000000 {
57 device_type = "memory";
58 reg = <0x10000000 0x40000000>;
59 };
60
61 pps {
62 compatible = "pps-gpio";
63 pinctrl-names = "default";
64 pinctrl-0 = <&pinctrl_pps>;
65 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
66 status = "okay";
67 };
68
69 reg_1p0v: regulator-1p0v {
70 compatible = "regulator-fixed";
71 regulator-name = "1P0V";
72 regulator-min-microvolt = <1000000>;
73 regulator-max-microvolt = <1000000>;
74 regulator-always-on;
75 };
76
77 reg_3p3v: regulator-3p3v {
78 compatible = "regulator-fixed";
79 regulator-name = "3P3V";
80 regulator-min-microvolt = <3300000>;
81 regulator-max-microvolt = <3300000>;
82 regulator-always-on;
83 };
84
85 reg_usb_h1_vbus: regulator-usb-h1-vbus {
86 compatible = "regulator-fixed";
87 regulator-name = "usb_h1_vbus";
88 regulator-min-microvolt = <5000000>;
89 regulator-max-microvolt = <5000000>;
90 regulator-always-on;
91 };
92
93 reg_usb_otg_vbus: regulator-usb-otg-vbus {
94 compatible = "regulator-fixed";
95 regulator-name = "usb_otg_vbus";
96 regulator-min-microvolt = <5000000>;
97 regulator-max-microvolt = <5000000>;
98 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
99 enable-active-high;
100 };
101
102 sound {
103 compatible = "fsl,imx6q-ventana-sgtl5000",
104 "fsl,imx-audio-sgtl5000";
105 model = "sgtl5000-audio";
106 ssi-controller = <&ssi1>;
107 audio-codec = <&codec>;
108 audio-routing =
109 "MIC_IN", "Mic Jack",
110 "Mic Jack", "Mic Bias",
111 "Headphone Jack", "HP_OUT";
112 mux-int-port = <1>;
113 mux-ext-port = <4>;
114 };
115};
116
117&audmux {
118 pinctrl-names = "default";
119 pinctrl-0 = <&pinctrl_audmux>;
120 status = "okay";
121};
122
123&can1 {
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_flexcan1>;
126 status = "okay";
127};
128
129&clks {
130 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
131 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
132 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
133 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
134};
135
136&fec {
137 pinctrl-names = "default";
138 pinctrl-0 = <&pinctrl_enet>;
139 phy-mode = "rgmii-id";
140 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
141 status = "okay";
142};
143
144&gpmi {
145 pinctrl-names = "default";
146 pinctrl-0 = <&pinctrl_gpmi_nand>;
147 status = "okay";
148};
149
150&hdmi {
151 ddc-i2c-bus = <&i2c3>;
152 status = "okay";
153};
154
155&i2c1 {
156 clock-frequency = <100000>;
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_i2c1>;
159 status = "okay";
160
161 eeprom1: eeprom@50 {
162 compatible = "atmel,24c02";
163 reg = <0x50>;
164 pagesize = <16>;
165 };
166
167 eeprom2: eeprom@51 {
168 compatible = "atmel,24c02";
169 reg = <0x51>;
170 pagesize = <16>;
171 };
172
173 eeprom3: eeprom@52 {
174 compatible = "atmel,24c02";
175 reg = <0x52>;
176 pagesize = <16>;
177 };
178
179 eeprom4: eeprom@53 {
180 compatible = "atmel,24c02";
181 reg = <0x53>;
182 pagesize = <16>;
183 };
184
185 gpio: pca9555@23 {
186 compatible = "nxp,pca9555";
187 reg = <0x23>;
188 gpio-controller;
189 #gpio-cells = <2>;
190 };
191
192 rtc: ds1672@68 {
193 compatible = "dallas,ds1672";
194 reg = <0x68>;
195 };
196};
197
198&i2c2 {
199 clock-frequency = <100000>;
200 pinctrl-names = "default";
201 pinctrl-0 = <&pinctrl_i2c2>;
202 status = "okay";
203
204 ltc3676: pmic@3c {
205 compatible = "lltc,ltc3676";
206 reg = <0x3c>;
207 interrupt-parent = <&gpio1>;
208 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
209
210 regulators {
211 /* VDD_SOC (1+R1/R2 = 1.635) */
212 reg_vdd_soc: sw1 {
213 regulator-name = "vddsoc";
214 regulator-min-microvolt = <674400>;
215 regulator-max-microvolt = <1308000>;
216 lltc,fb-voltage-divider = <127000 200000>;
217 regulator-ramp-delay = <7000>;
218 regulator-boot-on;
219 regulator-always-on;
220 };
221
222 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
223 reg_1p8v: sw2 {
224 regulator-name = "vdd1p8";
225 regulator-min-microvolt = <1033310>;
226 regulator-max-microvolt = <2004000>;
227 lltc,fb-voltage-divider = <301000 200000>;
228 regulator-ramp-delay = <7000>;
229 regulator-boot-on;
230 regulator-always-on;
231 };
232
233 /* VDD_ARM (1+R1/R2 = 1.635) */
234 reg_vdd_arm: sw3 {
235 regulator-name = "vddarm";
236 regulator-min-microvolt = <674400>;
237 regulator-max-microvolt = <1308000>;
238 lltc,fb-voltage-divider = <127000 200000>;
239 regulator-ramp-delay = <7000>;
240 regulator-boot-on;
241 regulator-always-on;
242 };
243
244 /* VDD_DDR (1+R1/R2 = 2.105) */
245 reg_vdd_ddr: sw4 {
246 regulator-name = "vddddr";
247 regulator-min-microvolt = <868310>;
248 regulator-max-microvolt = <1684000>;
249 lltc,fb-voltage-divider = <221000 200000>;
250 regulator-ramp-delay = <7000>;
251 regulator-boot-on;
252 regulator-always-on;
253 };
254
255 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
256 reg_2p5v: ldo2 {
257 regulator-name = "vdd2p5";
258 regulator-min-microvolt = <2490375>;
259 regulator-max-microvolt = <2490375>;
260 lltc,fb-voltage-divider = <487000 200000>;
261 regulator-boot-on;
262 regulator-always-on;
263 };
264
265 /* VDD_AUD_1P8: Audio codec */
266 reg_aud_1p8v: ldo3 {
267 regulator-name = "vdd1p8a";
268 regulator-min-microvolt = <1800000>;
269 regulator-max-microvolt = <1800000>;
270 regulator-boot-on;
271 };
272
273 /* VDD_HIGH (1+R1/R2 = 4.17) */
274 reg_3p0v: ldo4 {
275 regulator-name = "vdd3p0";
276 regulator-min-microvolt = <3023250>;
277 regulator-max-microvolt = <3023250>;
278 lltc,fb-voltage-divider = <634000 200000>;
279 regulator-boot-on;
280 regulator-always-on;
281 };
282 };
283 };
284};
285
286&i2c3 {
287 clock-frequency = <100000>;
288 pinctrl-names = "default";
289 pinctrl-0 = <&pinctrl_i2c3>;
290 status = "okay";
291
292 codec: sgtl5000@a {
293 compatible = "fsl,sgtl5000";
294 reg = <0x0a>;
295 clocks = <&clks IMX6QDL_CLK_CKO>;
296 VDDA-supply = <®_1p8v>;
297 VDDIO-supply = <®_3p3v>;
298 };
299
300 touchscreen: egalax_ts@4 {
301 compatible = "eeti,egalax_ts";
302 reg = <0x04>;
303 interrupt-parent = <&gpio1>;
304 interrupts = <11 2>;
305 wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
306 };
307};
308
309&ldb {
310 status = "okay";
311
312 lvds-channel@0 {
313 fsl,data-mapping = "spwg";
314 fsl,data-width = <18>;
315 status = "okay";
316
317 display-timings {
318 native-mode = <&timing0>;
319 timing0: hsd100pxn1 {
320 clock-frequency = <65000000>;
321 hactive = <1024>;
322 vactive = <768>;
323 hback-porch = <220>;
324 hfront-porch = <40>;
325 vback-porch = <21>;
326 vfront-porch = <7>;
327 hsync-len = <60>;
328 vsync-len = <10>;
329 };
330 };
331 };
332};
333
334&pcie {
335 pinctrl-names = "default";
336 pinctrl-0 = <&pinctrl_pcie>;
337 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
338 status = "okay";
339};
340
341&pwm2 {
342 pinctrl-names = "default";
343 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
344 status = "disabled";
345};
346
347&pwm3 {
348 pinctrl-names = "default";
349 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
350 status = "disabled";
351};
352
353&pwm4 {
354 pinctrl-names = "default";
355 pinctrl-0 = <&pinctrl_pwm4>;
356 status = "okay";
357};
358
359&ssi1 {
360 status = "okay";
361};
362
363&uart1 {
364 pinctrl-names = "default";
365 pinctrl-0 = <&pinctrl_uart1>;
366 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
367 status = "okay";
368};
369
370&uart2 {
371 pinctrl-names = "default";
372 pinctrl-0 = <&pinctrl_uart2>;
373 status = "okay";
374};
375
376&uart5 {
377 pinctrl-names = "default";
378 pinctrl-0 = <&pinctrl_uart5>;
379 status = "okay";
380};
381
382&usbotg {
383 vbus-supply = <®_usb_otg_vbus>;
384 pinctrl-names = "default";
385 pinctrl-0 = <&pinctrl_usbotg>;
386 disable-over-current;
387 status = "okay";
388};
389
390&usbh1 {
391 vbus-supply = <®_usb_h1_vbus>;
392 status = "okay";
393};
394
395&usdhc3 {
396 pinctrl-names = "default", "state_100mhz", "state_200mhz";
397 pinctrl-0 = <&pinctrl_usdhc3>;
398 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
399 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
400 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
401 vmmc-supply = <®_3p3v>;
402 no-1-8-v; /* firmware will remove if board revision supports */
403 status = "okay";
404};
405
406&wdog1 {
407 pinctrl-names = "default";
408 pinctrl-0 = <&pinctrl_wdog>;
409 fsl,ext-reset-output;
410};
411
412&iomuxc {
413 pinctrl_audmux: audmuxgrp {
414 fsl,pins = <
415 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
416 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
417 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
418 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
419 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
420 >;
421 };
422
423 pinctrl_enet: enetgrp {
424 fsl,pins = <
425 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
426 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
427 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
428 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
429 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
430 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
431 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
432 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
433 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
434 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
435 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
436 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
437 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
438 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
439 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
440 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
441 >;
442 };
443
444 pinctrl_flexcan1: flexcan1grp {
445 fsl,pins = <
446 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
447 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
448 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
449 >;
450 };
451
452 pinctrl_gpio_leds: gpioledsgrp {
453 fsl,pins = <
454 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
455 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
456 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
457 >;
458 };
459
460 pinctrl_gpmi_nand: gpminandgrp {
461 fsl,pins = <
462 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
463 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
464 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
465 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
466 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
467 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
468 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
469 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
470 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
471 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
472 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
473 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
474 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
475 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
476 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
477 >;
478 };
479
480 pinctrl_i2c1: i2c1grp {
481 fsl,pins = <
482 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
483 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
484 >;
485 };
486
487 pinctrl_i2c2: i2c2grp {
488 fsl,pins = <
489 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
490 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
491 >;
492 };
493
494 pinctrl_i2c3: i2c3grp {
495 fsl,pins = <
496 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
497 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
498 >;
499 };
500
501 pinctrl_pcie: pciegrp {
502 fsl,pins = <
503 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
504 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
505 >;
506 };
507
508 pinctrl_pmic: pmicgrp {
509 fsl,pins = <
510 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
511 >;
512 };
513
514 pinctrl_pps: ppsgrp {
515 fsl,pins = <
516 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
517 >;
518 };
519
520 pinctrl_pwm2: pwm2grp {
521 fsl,pins = <
522 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
523 >;
524 };
525
526 pinctrl_pwm3: pwm3grp {
527 fsl,pins = <
528 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
529 >;
530 };
531
532 pinctrl_pwm4: pwm4grp {
533 fsl,pins = <
534 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
535 >;
536 };
537
538 pinctrl_uart1: uart1grp {
539 fsl,pins = <
540 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
541 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
542 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
543 >;
544 };
545
546 pinctrl_uart2: uart2grp {
547 fsl,pins = <
548 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
549 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
550 >;
551 };
552
553 pinctrl_uart5: uart5grp {
554 fsl,pins = <
555 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
556 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
557 >;
558 };
559
560 pinctrl_usbotg: usbotggrp {
561 fsl,pins = <
562 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
563 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
564 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
565 >;
566 };
567
568 pinctrl_usdhc3: usdhc3grp {
569 fsl,pins = <
570 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
571 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
572 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
573 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
574 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
575 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
576 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
577 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
578 >;
579 };
580
581 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
582 fsl,pins = <
583 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
584 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
585 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
586 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
587 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
588 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
589 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
590 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
591 >;
592 };
593
594 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
595 fsl,pins = <
596 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
597 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
598 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
599 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
600 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
601 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
602 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
603 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
604 >;
605 };
606
607 pinctrl_wdog: wdoggrp {
608 fsl,pins = <
609 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
610 >;
611 };
612};
1/*
2 * Copyright 2013 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <dt-bindings/gpio/gpio.h>
13
14/ {
15 /* these are used by bootloader for disabling nodes */
16 aliases {
17 led0 = &led0;
18 led1 = &led1;
19 led2 = &led2;
20 nand = &gpmi;
21 ssi0 = &ssi1;
22 usb0 = &usbh1;
23 usb1 = &usbotg;
24 };
25
26 chosen {
27 bootargs = "console=ttymxc1,115200";
28 };
29
30 backlight {
31 compatible = "pwm-backlight";
32 pwms = <&pwm4 0 5000000>;
33 brightness-levels = <0 4 8 16 32 64 128 255>;
34 default-brightness-level = <7>;
35 };
36
37 leds {
38 compatible = "gpio-leds";
39 pinctrl-names = "default";
40 pinctrl-0 = <&pinctrl_gpio_leds>;
41
42 led0: user1 {
43 label = "user1";
44 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
45 default-state = "on";
46 linux,default-trigger = "heartbeat";
47 };
48
49 led1: user2 {
50 label = "user2";
51 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
52 default-state = "off";
53 };
54
55 led2: user3 {
56 label = "user3";
57 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
58 default-state = "off";
59 };
60 };
61
62 memory@10000000 {
63 reg = <0x10000000 0x40000000>;
64 };
65
66 pps {
67 compatible = "pps-gpio";
68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_pps>;
70 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
71 status = "okay";
72 };
73
74 reg_1p0v: regulator-1p0v {
75 compatible = "regulator-fixed";
76 regulator-name = "1P0V";
77 regulator-min-microvolt = <1000000>;
78 regulator-max-microvolt = <1000000>;
79 regulator-always-on;
80 };
81
82 reg_3p3v: regulator-3p3v {
83 compatible = "regulator-fixed";
84 regulator-name = "3P3V";
85 regulator-min-microvolt = <3300000>;
86 regulator-max-microvolt = <3300000>;
87 regulator-always-on;
88 };
89
90 reg_usb_h1_vbus: regulator-usb-h1-vbus {
91 compatible = "regulator-fixed";
92 regulator-name = "usb_h1_vbus";
93 regulator-min-microvolt = <5000000>;
94 regulator-max-microvolt = <5000000>;
95 regulator-always-on;
96 };
97
98 reg_usb_otg_vbus: regulator-usb-otg-vbus {
99 compatible = "regulator-fixed";
100 regulator-name = "usb_otg_vbus";
101 regulator-min-microvolt = <5000000>;
102 regulator-max-microvolt = <5000000>;
103 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
104 enable-active-high;
105 };
106
107 sound {
108 compatible = "fsl,imx6q-ventana-sgtl5000",
109 "fsl,imx-audio-sgtl5000";
110 model = "sgtl5000-audio";
111 ssi-controller = <&ssi1>;
112 audio-codec = <&codec>;
113 audio-routing =
114 "MIC_IN", "Mic Jack",
115 "Mic Jack", "Mic Bias",
116 "Headphone Jack", "HP_OUT";
117 mux-int-port = <1>;
118 mux-ext-port = <4>;
119 };
120};
121
122&audmux {
123 pinctrl-names = "default";
124 pinctrl-0 = <&pinctrl_audmux>;
125 status = "okay";
126};
127
128&can1 {
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_flexcan1>;
131 status = "okay";
132};
133
134&clks {
135 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
136 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
137 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
138 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
139};
140
141&fec {
142 pinctrl-names = "default";
143 pinctrl-0 = <&pinctrl_enet>;
144 phy-mode = "rgmii-id";
145 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
146 status = "okay";
147};
148
149&gpmi {
150 pinctrl-names = "default";
151 pinctrl-0 = <&pinctrl_gpmi_nand>;
152 status = "okay";
153};
154
155&hdmi {
156 ddc-i2c-bus = <&i2c3>;
157 status = "okay";
158};
159
160&i2c1 {
161 clock-frequency = <100000>;
162 pinctrl-names = "default";
163 pinctrl-0 = <&pinctrl_i2c1>;
164 status = "okay";
165
166 eeprom1: eeprom@50 {
167 compatible = "atmel,24c02";
168 reg = <0x50>;
169 pagesize = <16>;
170 };
171
172 eeprom2: eeprom@51 {
173 compatible = "atmel,24c02";
174 reg = <0x51>;
175 pagesize = <16>;
176 };
177
178 eeprom3: eeprom@52 {
179 compatible = "atmel,24c02";
180 reg = <0x52>;
181 pagesize = <16>;
182 };
183
184 eeprom4: eeprom@53 {
185 compatible = "atmel,24c02";
186 reg = <0x53>;
187 pagesize = <16>;
188 };
189
190 gpio: pca9555@23 {
191 compatible = "nxp,pca9555";
192 reg = <0x23>;
193 gpio-controller;
194 #gpio-cells = <2>;
195 };
196
197 rtc: ds1672@68 {
198 compatible = "dallas,ds1672";
199 reg = <0x68>;
200 };
201};
202
203&i2c2 {
204 clock-frequency = <100000>;
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_i2c2>;
207 status = "okay";
208
209 ltc3676: pmic@3c {
210 compatible = "lltc,ltc3676";
211 reg = <0x3c>;
212 interrupt-parent = <&gpio1>;
213 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
214
215 regulators {
216 /* VDD_SOC (1+R1/R2 = 1.635) */
217 reg_vdd_soc: sw1 {
218 regulator-name = "vddsoc";
219 regulator-min-microvolt = <674400>;
220 regulator-max-microvolt = <1308000>;
221 lltc,fb-voltage-divider = <127000 200000>;
222 regulator-ramp-delay = <7000>;
223 regulator-boot-on;
224 regulator-always-on;
225 };
226
227 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
228 reg_1p8v: sw2 {
229 regulator-name = "vdd1p8";
230 regulator-min-microvolt = <1033310>;
231 regulator-max-microvolt = <2004000>;
232 lltc,fb-voltage-divider = <301000 200000>;
233 regulator-ramp-delay = <7000>;
234 regulator-boot-on;
235 regulator-always-on;
236 };
237
238 /* VDD_ARM (1+R1/R2 = 1.635) */
239 reg_vdd_arm: sw3 {
240 regulator-name = "vddarm";
241 regulator-min-microvolt = <674400>;
242 regulator-max-microvolt = <1308000>;
243 lltc,fb-voltage-divider = <127000 200000>;
244 regulator-ramp-delay = <7000>;
245 regulator-boot-on;
246 regulator-always-on;
247 };
248
249 /* VDD_DDR (1+R1/R2 = 2.105) */
250 reg_vdd_ddr: sw4 {
251 regulator-name = "vddddr";
252 regulator-min-microvolt = <868310>;
253 regulator-max-microvolt = <1684000>;
254 lltc,fb-voltage-divider = <221000 200000>;
255 regulator-ramp-delay = <7000>;
256 regulator-boot-on;
257 regulator-always-on;
258 };
259
260 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
261 reg_2p5v: ldo2 {
262 regulator-name = "vdd2p5";
263 regulator-min-microvolt = <2490375>;
264 regulator-max-microvolt = <2490375>;
265 lltc,fb-voltage-divider = <487000 200000>;
266 regulator-boot-on;
267 regulator-always-on;
268 };
269
270 /* VDD_AUD_1P8: Audio codec */
271 reg_aud_1p8v: ldo3 {
272 regulator-name = "vdd1p8a";
273 regulator-min-microvolt = <1800000>;
274 regulator-max-microvolt = <1800000>;
275 regulator-boot-on;
276 };
277
278 /* VDD_HIGH (1+R1/R2 = 4.17) */
279 reg_3p0v: ldo4 {
280 regulator-name = "vdd3p0";
281 regulator-min-microvolt = <3023250>;
282 regulator-max-microvolt = <3023250>;
283 lltc,fb-voltage-divider = <634000 200000>;
284 regulator-boot-on;
285 regulator-always-on;
286 };
287 };
288 };
289};
290
291&i2c3 {
292 clock-frequency = <100000>;
293 pinctrl-names = "default";
294 pinctrl-0 = <&pinctrl_i2c3>;
295 status = "okay";
296
297 codec: sgtl5000@a {
298 compatible = "fsl,sgtl5000";
299 reg = <0x0a>;
300 clocks = <&clks IMX6QDL_CLK_CKO>;
301 VDDA-supply = <®_1p8v>;
302 VDDIO-supply = <®_3p3v>;
303 };
304
305 touchscreen: egalax_ts@4 {
306 compatible = "eeti,egalax_ts";
307 reg = <0x04>;
308 interrupt-parent = <&gpio1>;
309 interrupts = <11 2>;
310 wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
311 };
312};
313
314&ldb {
315 status = "okay";
316
317 lvds-channel@0 {
318 fsl,data-mapping = "spwg";
319 fsl,data-width = <18>;
320 status = "okay";
321
322 display-timings {
323 native-mode = <&timing0>;
324 timing0: hsd100pxn1 {
325 clock-frequency = <65000000>;
326 hactive = <1024>;
327 vactive = <768>;
328 hback-porch = <220>;
329 hfront-porch = <40>;
330 vback-porch = <21>;
331 vfront-porch = <7>;
332 hsync-len = <60>;
333 vsync-len = <10>;
334 };
335 };
336 };
337};
338
339&pcie {
340 pinctrl-names = "default";
341 pinctrl-0 = <&pinctrl_pcie>;
342 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
343 status = "okay";
344};
345
346&pwm2 {
347 pinctrl-names = "default";
348 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
349 status = "disabled";
350};
351
352&pwm3 {
353 pinctrl-names = "default";
354 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
355 status = "disabled";
356};
357
358&pwm4 {
359 pinctrl-names = "default";
360 pinctrl-0 = <&pinctrl_pwm4>;
361 status = "okay";
362};
363
364&ssi1 {
365 status = "okay";
366};
367
368&uart1 {
369 pinctrl-names = "default";
370 pinctrl-0 = <&pinctrl_uart1>;
371 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
372 status = "okay";
373};
374
375&uart2 {
376 pinctrl-names = "default";
377 pinctrl-0 = <&pinctrl_uart2>;
378 status = "okay";
379};
380
381&uart5 {
382 pinctrl-names = "default";
383 pinctrl-0 = <&pinctrl_uart5>;
384 status = "okay";
385};
386
387&usbotg {
388 vbus-supply = <®_usb_otg_vbus>;
389 pinctrl-names = "default";
390 pinctrl-0 = <&pinctrl_usbotg>;
391 disable-over-current;
392 status = "okay";
393};
394
395&usbh1 {
396 vbus-supply = <®_usb_h1_vbus>;
397 status = "okay";
398};
399
400&usdhc3 {
401 pinctrl-names = "default", "state_100mhz", "state_200mhz";
402 pinctrl-0 = <&pinctrl_usdhc3>;
403 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
404 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
405 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
406 vmmc-supply = <®_3p3v>;
407 no-1-8-v; /* firmware will remove if board revision supports */
408 status = "okay";
409};
410
411&wdog1 {
412 pinctrl-names = "default";
413 pinctrl-0 = <&pinctrl_wdog>;
414 fsl,ext-reset-output;
415};
416
417&iomuxc {
418 pinctrl_audmux: audmuxgrp {
419 fsl,pins = <
420 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
421 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
422 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
423 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
424 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
425 >;
426 };
427
428 pinctrl_enet: enetgrp {
429 fsl,pins = <
430 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
431 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
432 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
433 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
434 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
435 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
436 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
437 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
438 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
439 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
440 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
441 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
442 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
443 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
444 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
445 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
446 >;
447 };
448
449 pinctrl_flexcan1: flexcan1grp {
450 fsl,pins = <
451 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
452 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
453 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
454 >;
455 };
456
457 pinctrl_gpio_leds: gpioledsgrp {
458 fsl,pins = <
459 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
460 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
461 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
462 >;
463 };
464
465 pinctrl_gpmi_nand: gpminandgrp {
466 fsl,pins = <
467 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
468 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
469 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
470 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
471 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
472 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
473 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
474 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
475 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
476 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
477 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
478 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
479 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
480 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
481 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
482 >;
483 };
484
485 pinctrl_i2c1: i2c1grp {
486 fsl,pins = <
487 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
488 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
489 >;
490 };
491
492 pinctrl_i2c2: i2c2grp {
493 fsl,pins = <
494 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
495 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
496 >;
497 };
498
499 pinctrl_i2c3: i2c3grp {
500 fsl,pins = <
501 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
502 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
503 >;
504 };
505
506 pinctrl_pcie: pciegrp {
507 fsl,pins = <
508 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
509 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
510 >;
511 };
512
513 pinctrl_pmic: pmicgrp {
514 fsl,pins = <
515 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
516 >;
517 };
518
519 pinctrl_pps: ppsgrp {
520 fsl,pins = <
521 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
522 >;
523 };
524
525 pinctrl_pwm2: pwm2grp {
526 fsl,pins = <
527 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
528 >;
529 };
530
531 pinctrl_pwm3: pwm3grp {
532 fsl,pins = <
533 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
534 >;
535 };
536
537 pinctrl_pwm4: pwm4grp {
538 fsl,pins = <
539 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
540 >;
541 };
542
543 pinctrl_uart1: uart1grp {
544 fsl,pins = <
545 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
546 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
547 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
548 >;
549 };
550
551 pinctrl_uart2: uart2grp {
552 fsl,pins = <
553 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
554 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
555 >;
556 };
557
558 pinctrl_uart5: uart5grp {
559 fsl,pins = <
560 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
561 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
562 >;
563 };
564
565 pinctrl_usbotg: usbotggrp {
566 fsl,pins = <
567 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
568 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
569 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */
570 >;
571 };
572
573 pinctrl_usdhc3: usdhc3grp {
574 fsl,pins = <
575 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
576 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
577 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
578 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
579 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
580 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
581 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
582 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
583 >;
584 };
585
586 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
587 fsl,pins = <
588 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
589 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
590 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
591 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
592 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
593 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
594 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
595 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
596 >;
597 };
598
599 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
600 fsl,pins = <
601 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
602 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
603 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
604 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
605 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
606 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
607 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
608 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
609 >;
610 };
611
612 pinctrl_wdog: wdoggrp {
613 fsl,pins = <
614 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
615 >;
616 };
617};