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1/*
2 * Copyright © 2008-2010 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Zou Nan hai <nanhai.zou@intel.com>
26 * Xiang Hai hao<haihao.xiang@intel.com>
27 *
28 */
29
30#include <linux/log2.h>
31
32#include <drm/drmP.h>
33#include <drm/i915_drm.h>
34
35#include "i915_drv.h"
36#include "i915_gem_render_state.h"
37#include "i915_trace.h"
38#include "intel_drv.h"
39
40/* Rough estimate of the typical request size, performing a flush,
41 * set-context and then emitting the batch.
42 */
43#define LEGACY_REQUEST_SIZE 200
44
45static unsigned int __intel_ring_space(unsigned int head,
46 unsigned int tail,
47 unsigned int size)
48{
49 /*
50 * "If the Ring Buffer Head Pointer and the Tail Pointer are on the
51 * same cacheline, the Head Pointer must not be greater than the Tail
52 * Pointer."
53 */
54 GEM_BUG_ON(!is_power_of_2(size));
55 return (head - tail - CACHELINE_BYTES) & (size - 1);
56}
57
58unsigned int intel_ring_update_space(struct intel_ring *ring)
59{
60 unsigned int space;
61
62 space = __intel_ring_space(ring->head, ring->emit, ring->size);
63
64 ring->space = space;
65 return space;
66}
67
68static int
69gen2_render_ring_flush(struct i915_request *rq, u32 mode)
70{
71 u32 cmd, *cs;
72
73 cmd = MI_FLUSH;
74
75 if (mode & EMIT_INVALIDATE)
76 cmd |= MI_READ_FLUSH;
77
78 cs = intel_ring_begin(rq, 2);
79 if (IS_ERR(cs))
80 return PTR_ERR(cs);
81
82 *cs++ = cmd;
83 *cs++ = MI_NOOP;
84 intel_ring_advance(rq, cs);
85
86 return 0;
87}
88
89static int
90gen4_render_ring_flush(struct i915_request *rq, u32 mode)
91{
92 u32 cmd, *cs;
93
94 /*
95 * read/write caches:
96 *
97 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
98 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
99 * also flushed at 2d versus 3d pipeline switches.
100 *
101 * read-only caches:
102 *
103 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
104 * MI_READ_FLUSH is set, and is always flushed on 965.
105 *
106 * I915_GEM_DOMAIN_COMMAND may not exist?
107 *
108 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
109 * invalidated when MI_EXE_FLUSH is set.
110 *
111 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
112 * invalidated with every MI_FLUSH.
113 *
114 * TLBs:
115 *
116 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
117 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
118 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
119 * are flushed at any MI_FLUSH.
120 */
121
122 cmd = MI_FLUSH;
123 if (mode & EMIT_INVALIDATE) {
124 cmd |= MI_EXE_FLUSH;
125 if (IS_G4X(rq->i915) || IS_GEN5(rq->i915))
126 cmd |= MI_INVALIDATE_ISP;
127 }
128
129 cs = intel_ring_begin(rq, 2);
130 if (IS_ERR(cs))
131 return PTR_ERR(cs);
132
133 *cs++ = cmd;
134 *cs++ = MI_NOOP;
135 intel_ring_advance(rq, cs);
136
137 return 0;
138}
139
140/*
141 * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
142 * implementing two workarounds on gen6. From section 1.4.7.1
143 * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
144 *
145 * [DevSNB-C+{W/A}] Before any depth stall flush (including those
146 * produced by non-pipelined state commands), software needs to first
147 * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
148 * 0.
149 *
150 * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
151 * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
152 *
153 * And the workaround for these two requires this workaround first:
154 *
155 * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
156 * BEFORE the pipe-control with a post-sync op and no write-cache
157 * flushes.
158 *
159 * And this last workaround is tricky because of the requirements on
160 * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
161 * volume 2 part 1:
162 *
163 * "1 of the following must also be set:
164 * - Render Target Cache Flush Enable ([12] of DW1)
165 * - Depth Cache Flush Enable ([0] of DW1)
166 * - Stall at Pixel Scoreboard ([1] of DW1)
167 * - Depth Stall ([13] of DW1)
168 * - Post-Sync Operation ([13] of DW1)
169 * - Notify Enable ([8] of DW1)"
170 *
171 * The cache flushes require the workaround flush that triggered this
172 * one, so we can't use it. Depth stall would trigger the same.
173 * Post-sync nonzero is what triggered this second workaround, so we
174 * can't use that one either. Notify enable is IRQs, which aren't
175 * really our business. That leaves only stall at scoreboard.
176 */
177static int
178intel_emit_post_sync_nonzero_flush(struct i915_request *rq)
179{
180 u32 scratch_addr =
181 i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES;
182 u32 *cs;
183
184 cs = intel_ring_begin(rq, 6);
185 if (IS_ERR(cs))
186 return PTR_ERR(cs);
187
188 *cs++ = GFX_OP_PIPE_CONTROL(5);
189 *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD;
190 *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;
191 *cs++ = 0; /* low dword */
192 *cs++ = 0; /* high dword */
193 *cs++ = MI_NOOP;
194 intel_ring_advance(rq, cs);
195
196 cs = intel_ring_begin(rq, 6);
197 if (IS_ERR(cs))
198 return PTR_ERR(cs);
199
200 *cs++ = GFX_OP_PIPE_CONTROL(5);
201 *cs++ = PIPE_CONTROL_QW_WRITE;
202 *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;
203 *cs++ = 0;
204 *cs++ = 0;
205 *cs++ = MI_NOOP;
206 intel_ring_advance(rq, cs);
207
208 return 0;
209}
210
211static int
212gen6_render_ring_flush(struct i915_request *rq, u32 mode)
213{
214 u32 scratch_addr =
215 i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES;
216 u32 *cs, flags = 0;
217 int ret;
218
219 /* Force SNB workarounds for PIPE_CONTROL flushes */
220 ret = intel_emit_post_sync_nonzero_flush(rq);
221 if (ret)
222 return ret;
223
224 /* Just flush everything. Experiments have shown that reducing the
225 * number of bits based on the write domains has little performance
226 * impact.
227 */
228 if (mode & EMIT_FLUSH) {
229 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
230 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
231 /*
232 * Ensure that any following seqno writes only happen
233 * when the render cache is indeed flushed.
234 */
235 flags |= PIPE_CONTROL_CS_STALL;
236 }
237 if (mode & EMIT_INVALIDATE) {
238 flags |= PIPE_CONTROL_TLB_INVALIDATE;
239 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
240 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
241 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
242 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
243 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
244 /*
245 * TLB invalidate requires a post-sync write.
246 */
247 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
248 }
249
250 cs = intel_ring_begin(rq, 4);
251 if (IS_ERR(cs))
252 return PTR_ERR(cs);
253
254 *cs++ = GFX_OP_PIPE_CONTROL(4);
255 *cs++ = flags;
256 *cs++ = scratch_addr | PIPE_CONTROL_GLOBAL_GTT;
257 *cs++ = 0;
258 intel_ring_advance(rq, cs);
259
260 return 0;
261}
262
263static int
264gen7_render_ring_cs_stall_wa(struct i915_request *rq)
265{
266 u32 *cs;
267
268 cs = intel_ring_begin(rq, 4);
269 if (IS_ERR(cs))
270 return PTR_ERR(cs);
271
272 *cs++ = GFX_OP_PIPE_CONTROL(4);
273 *cs++ = PIPE_CONTROL_CS_STALL | PIPE_CONTROL_STALL_AT_SCOREBOARD;
274 *cs++ = 0;
275 *cs++ = 0;
276 intel_ring_advance(rq, cs);
277
278 return 0;
279}
280
281static int
282gen7_render_ring_flush(struct i915_request *rq, u32 mode)
283{
284 u32 scratch_addr =
285 i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES;
286 u32 *cs, flags = 0;
287
288 /*
289 * Ensure that any following seqno writes only happen when the render
290 * cache is indeed flushed.
291 *
292 * Workaround: 4th PIPE_CONTROL command (except the ones with only
293 * read-cache invalidate bits set) must have the CS_STALL bit set. We
294 * don't try to be clever and just set it unconditionally.
295 */
296 flags |= PIPE_CONTROL_CS_STALL;
297
298 /* Just flush everything. Experiments have shown that reducing the
299 * number of bits based on the write domains has little performance
300 * impact.
301 */
302 if (mode & EMIT_FLUSH) {
303 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
304 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
305 flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
306 flags |= PIPE_CONTROL_FLUSH_ENABLE;
307 }
308 if (mode & EMIT_INVALIDATE) {
309 flags |= PIPE_CONTROL_TLB_INVALIDATE;
310 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
311 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
312 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
313 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
314 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
315 flags |= PIPE_CONTROL_MEDIA_STATE_CLEAR;
316 /*
317 * TLB invalidate requires a post-sync write.
318 */
319 flags |= PIPE_CONTROL_QW_WRITE;
320 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
321
322 flags |= PIPE_CONTROL_STALL_AT_SCOREBOARD;
323
324 /* Workaround: we must issue a pipe_control with CS-stall bit
325 * set before a pipe_control command that has the state cache
326 * invalidate bit set. */
327 gen7_render_ring_cs_stall_wa(rq);
328 }
329
330 cs = intel_ring_begin(rq, 4);
331 if (IS_ERR(cs))
332 return PTR_ERR(cs);
333
334 *cs++ = GFX_OP_PIPE_CONTROL(4);
335 *cs++ = flags;
336 *cs++ = scratch_addr;
337 *cs++ = 0;
338 intel_ring_advance(rq, cs);
339
340 return 0;
341}
342
343static void ring_setup_phys_status_page(struct intel_engine_cs *engine)
344{
345 struct drm_i915_private *dev_priv = engine->i915;
346 u32 addr;
347
348 addr = dev_priv->status_page_dmah->busaddr;
349 if (INTEL_GEN(dev_priv) >= 4)
350 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
351 I915_WRITE(HWS_PGA, addr);
352}
353
354static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
355{
356 struct drm_i915_private *dev_priv = engine->i915;
357 i915_reg_t mmio;
358
359 /* The ring status page addresses are no longer next to the rest of
360 * the ring registers as of gen7.
361 */
362 if (IS_GEN7(dev_priv)) {
363 switch (engine->id) {
364 /*
365 * No more rings exist on Gen7. Default case is only to shut up
366 * gcc switch check warning.
367 */
368 default:
369 GEM_BUG_ON(engine->id);
370 case RCS:
371 mmio = RENDER_HWS_PGA_GEN7;
372 break;
373 case BCS:
374 mmio = BLT_HWS_PGA_GEN7;
375 break;
376 case VCS:
377 mmio = BSD_HWS_PGA_GEN7;
378 break;
379 case VECS:
380 mmio = VEBOX_HWS_PGA_GEN7;
381 break;
382 }
383 } else if (IS_GEN6(dev_priv)) {
384 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
385 } else {
386 mmio = RING_HWS_PGA(engine->mmio_base);
387 }
388
389 if (INTEL_GEN(dev_priv) >= 6)
390 I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
391
392 I915_WRITE(mmio, engine->status_page.ggtt_offset);
393 POSTING_READ(mmio);
394
395 /* Flush the TLB for this page */
396 if (IS_GEN(dev_priv, 6, 7)) {
397 i915_reg_t reg = RING_INSTPM(engine->mmio_base);
398
399 /* ring should be idle before issuing a sync flush*/
400 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0);
401
402 I915_WRITE(reg,
403 _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
404 INSTPM_SYNC_FLUSH));
405 if (intel_wait_for_register(dev_priv,
406 reg, INSTPM_SYNC_FLUSH, 0,
407 1000))
408 DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
409 engine->name);
410 }
411}
412
413static bool stop_ring(struct intel_engine_cs *engine)
414{
415 struct drm_i915_private *dev_priv = engine->i915;
416
417 if (INTEL_GEN(dev_priv) > 2) {
418 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING));
419 if (intel_wait_for_register(dev_priv,
420 RING_MI_MODE(engine->mmio_base),
421 MODE_IDLE,
422 MODE_IDLE,
423 1000)) {
424 DRM_ERROR("%s : timed out trying to stop ring\n",
425 engine->name);
426 /* Sometimes we observe that the idle flag is not
427 * set even though the ring is empty. So double
428 * check before giving up.
429 */
430 if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine))
431 return false;
432 }
433 }
434
435 I915_WRITE_HEAD(engine, I915_READ_TAIL(engine));
436
437 I915_WRITE_HEAD(engine, 0);
438 I915_WRITE_TAIL(engine, 0);
439
440 /* The ring must be empty before it is disabled */
441 I915_WRITE_CTL(engine, 0);
442
443 return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0;
444}
445
446static int init_ring_common(struct intel_engine_cs *engine)
447{
448 struct drm_i915_private *dev_priv = engine->i915;
449 struct intel_ring *ring = engine->buffer;
450 int ret = 0;
451
452 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
453
454 if (!stop_ring(engine)) {
455 /* G45 ring initialization often fails to reset head to zero */
456 DRM_DEBUG_DRIVER("%s head not reset to zero "
457 "ctl %08x head %08x tail %08x start %08x\n",
458 engine->name,
459 I915_READ_CTL(engine),
460 I915_READ_HEAD(engine),
461 I915_READ_TAIL(engine),
462 I915_READ_START(engine));
463
464 if (!stop_ring(engine)) {
465 DRM_ERROR("failed to set %s head to zero "
466 "ctl %08x head %08x tail %08x start %08x\n",
467 engine->name,
468 I915_READ_CTL(engine),
469 I915_READ_HEAD(engine),
470 I915_READ_TAIL(engine),
471 I915_READ_START(engine));
472 ret = -EIO;
473 goto out;
474 }
475 }
476
477 if (HWS_NEEDS_PHYSICAL(dev_priv))
478 ring_setup_phys_status_page(engine);
479 else
480 intel_ring_setup_status_page(engine);
481
482 intel_engine_reset_breadcrumbs(engine);
483
484 /* Enforce ordering by reading HEAD register back */
485 I915_READ_HEAD(engine);
486
487 /* Initialize the ring. This must happen _after_ we've cleared the ring
488 * registers with the above sequence (the readback of the HEAD registers
489 * also enforces ordering), otherwise the hw might lose the new ring
490 * register values. */
491 I915_WRITE_START(engine, i915_ggtt_offset(ring->vma));
492
493 /* WaClearRingBufHeadRegAtInit:ctg,elk */
494 if (I915_READ_HEAD(engine))
495 DRM_DEBUG_DRIVER("%s initialization failed [head=%08x], fudging\n",
496 engine->name, I915_READ_HEAD(engine));
497
498 intel_ring_update_space(ring);
499 I915_WRITE_HEAD(engine, ring->head);
500 I915_WRITE_TAIL(engine, ring->tail);
501 (void)I915_READ_TAIL(engine);
502
503 I915_WRITE_CTL(engine, RING_CTL_SIZE(ring->size) | RING_VALID);
504
505 /* If the head is still not zero, the ring is dead */
506 if (intel_wait_for_register(dev_priv, RING_CTL(engine->mmio_base),
507 RING_VALID, RING_VALID,
508 50)) {
509 DRM_ERROR("%s initialization failed "
510 "ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n",
511 engine->name,
512 I915_READ_CTL(engine),
513 I915_READ_CTL(engine) & RING_VALID,
514 I915_READ_HEAD(engine), ring->head,
515 I915_READ_TAIL(engine), ring->tail,
516 I915_READ_START(engine),
517 i915_ggtt_offset(ring->vma));
518 ret = -EIO;
519 goto out;
520 }
521
522 intel_engine_init_hangcheck(engine);
523
524 if (INTEL_GEN(dev_priv) > 2)
525 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING));
526
527out:
528 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
529
530 return ret;
531}
532
533static void reset_ring_common(struct intel_engine_cs *engine,
534 struct i915_request *request)
535{
536 /*
537 * RC6 must be prevented until the reset is complete and the engine
538 * reinitialised. If it occurs in the middle of this sequence, the
539 * state written to/loaded from the power context is ill-defined (e.g.
540 * the PP_BASE_DIR may be lost).
541 */
542 assert_forcewakes_active(engine->i915, FORCEWAKE_ALL);
543
544 /*
545 * Try to restore the logical GPU state to match the continuation
546 * of the request queue. If we skip the context/PD restore, then
547 * the next request may try to execute assuming that its context
548 * is valid and loaded on the GPU and so may try to access invalid
549 * memory, prompting repeated GPU hangs.
550 *
551 * If the request was guilty, we still restore the logical state
552 * in case the next request requires it (e.g. the aliasing ppgtt),
553 * but skip over the hung batch.
554 *
555 * If the request was innocent, we try to replay the request with
556 * the restored context.
557 */
558 if (request) {
559 struct drm_i915_private *dev_priv = request->i915;
560 struct intel_context *ce = &request->ctx->engine[engine->id];
561 struct i915_hw_ppgtt *ppgtt;
562
563 if (ce->state) {
564 I915_WRITE(CCID,
565 i915_ggtt_offset(ce->state) |
566 BIT(8) /* must be set! */ |
567 CCID_EXTENDED_STATE_SAVE |
568 CCID_EXTENDED_STATE_RESTORE |
569 CCID_EN);
570 }
571
572 ppgtt = request->ctx->ppgtt ?: engine->i915->mm.aliasing_ppgtt;
573 if (ppgtt) {
574 u32 pd_offset = ppgtt->pd.base.ggtt_offset << 10;
575
576 I915_WRITE(RING_PP_DIR_DCLV(engine), PP_DIR_DCLV_2G);
577 I915_WRITE(RING_PP_DIR_BASE(engine), pd_offset);
578
579 /* Wait for the PD reload to complete */
580 if (intel_wait_for_register(dev_priv,
581 RING_PP_DIR_BASE(engine),
582 BIT(0), 0,
583 10))
584 DRM_ERROR("Wait for reload of ppgtt page-directory timed out\n");
585
586 ppgtt->pd_dirty_rings &= ~intel_engine_flag(engine);
587 }
588
589 /* If the rq hung, jump to its breadcrumb and skip the batch */
590 if (request->fence.error == -EIO)
591 request->ring->head = request->postfix;
592 } else {
593 engine->legacy_active_context = NULL;
594 engine->legacy_active_ppgtt = NULL;
595 }
596}
597
598static int intel_rcs_ctx_init(struct i915_request *rq)
599{
600 int ret;
601
602 ret = intel_ring_workarounds_emit(rq);
603 if (ret != 0)
604 return ret;
605
606 ret = i915_gem_render_state_emit(rq);
607 if (ret)
608 return ret;
609
610 return 0;
611}
612
613static int init_render_ring(struct intel_engine_cs *engine)
614{
615 struct drm_i915_private *dev_priv = engine->i915;
616 int ret = init_ring_common(engine);
617 if (ret)
618 return ret;
619
620 /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
621 if (IS_GEN(dev_priv, 4, 6))
622 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
623
624 /* We need to disable the AsyncFlip performance optimisations in order
625 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
626 * programmed to '1' on all products.
627 *
628 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
629 */
630 if (IS_GEN(dev_priv, 6, 7))
631 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
632
633 /* Required for the hardware to program scanline values for waiting */
634 /* WaEnableFlushTlbInvalidationMode:snb */
635 if (IS_GEN6(dev_priv))
636 I915_WRITE(GFX_MODE,
637 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
638
639 /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
640 if (IS_GEN7(dev_priv))
641 I915_WRITE(GFX_MODE_GEN7,
642 _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
643 _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
644
645 if (IS_GEN6(dev_priv)) {
646 /* From the Sandybridge PRM, volume 1 part 3, page 24:
647 * "If this bit is set, STCunit will have LRA as replacement
648 * policy. [...] This bit must be reset. LRA replacement
649 * policy is not supported."
650 */
651 I915_WRITE(CACHE_MODE_0,
652 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
653 }
654
655 if (IS_GEN(dev_priv, 6, 7))
656 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
657
658 if (INTEL_GEN(dev_priv) >= 6)
659 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
660
661 return init_workarounds_ring(engine);
662}
663
664static u32 *gen6_signal(struct i915_request *rq, u32 *cs)
665{
666 struct drm_i915_private *dev_priv = rq->i915;
667 struct intel_engine_cs *engine;
668 enum intel_engine_id id;
669 int num_rings = 0;
670
671 for_each_engine(engine, dev_priv, id) {
672 i915_reg_t mbox_reg;
673
674 if (!(BIT(engine->hw_id) & GEN6_SEMAPHORES_MASK))
675 continue;
676
677 mbox_reg = rq->engine->semaphore.mbox.signal[engine->hw_id];
678 if (i915_mmio_reg_valid(mbox_reg)) {
679 *cs++ = MI_LOAD_REGISTER_IMM(1);
680 *cs++ = i915_mmio_reg_offset(mbox_reg);
681 *cs++ = rq->global_seqno;
682 num_rings++;
683 }
684 }
685 if (num_rings & 1)
686 *cs++ = MI_NOOP;
687
688 return cs;
689}
690
691static void cancel_requests(struct intel_engine_cs *engine)
692{
693 struct i915_request *request;
694 unsigned long flags;
695
696 spin_lock_irqsave(&engine->timeline->lock, flags);
697
698 /* Mark all submitted requests as skipped. */
699 list_for_each_entry(request, &engine->timeline->requests, link) {
700 GEM_BUG_ON(!request->global_seqno);
701 if (!i915_request_completed(request))
702 dma_fence_set_error(&request->fence, -EIO);
703 }
704 /* Remaining _unready_ requests will be nop'ed when submitted */
705
706 spin_unlock_irqrestore(&engine->timeline->lock, flags);
707}
708
709static void i9xx_submit_request(struct i915_request *request)
710{
711 struct drm_i915_private *dev_priv = request->i915;
712
713 i915_request_submit(request);
714
715 I915_WRITE_TAIL(request->engine,
716 intel_ring_set_tail(request->ring, request->tail));
717}
718
719static void i9xx_emit_breadcrumb(struct i915_request *rq, u32 *cs)
720{
721 *cs++ = MI_STORE_DWORD_INDEX;
722 *cs++ = I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT;
723 *cs++ = rq->global_seqno;
724 *cs++ = MI_USER_INTERRUPT;
725
726 rq->tail = intel_ring_offset(rq, cs);
727 assert_ring_tail_valid(rq->ring, rq->tail);
728}
729
730static const int i9xx_emit_breadcrumb_sz = 4;
731
732static void gen6_sema_emit_breadcrumb(struct i915_request *rq, u32 *cs)
733{
734 return i9xx_emit_breadcrumb(rq, rq->engine->semaphore.signal(rq, cs));
735}
736
737static int
738gen6_ring_sync_to(struct i915_request *rq, struct i915_request *signal)
739{
740 u32 dw1 = MI_SEMAPHORE_MBOX |
741 MI_SEMAPHORE_COMPARE |
742 MI_SEMAPHORE_REGISTER;
743 u32 wait_mbox = signal->engine->semaphore.mbox.wait[rq->engine->hw_id];
744 u32 *cs;
745
746 WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID);
747
748 cs = intel_ring_begin(rq, 4);
749 if (IS_ERR(cs))
750 return PTR_ERR(cs);
751
752 *cs++ = dw1 | wait_mbox;
753 /* Throughout all of the GEM code, seqno passed implies our current
754 * seqno is >= the last seqno executed. However for hardware the
755 * comparison is strictly greater than.
756 */
757 *cs++ = signal->global_seqno - 1;
758 *cs++ = 0;
759 *cs++ = MI_NOOP;
760 intel_ring_advance(rq, cs);
761
762 return 0;
763}
764
765static void
766gen5_seqno_barrier(struct intel_engine_cs *engine)
767{
768 /* MI_STORE are internally buffered by the GPU and not flushed
769 * either by MI_FLUSH or SyncFlush or any other combination of
770 * MI commands.
771 *
772 * "Only the submission of the store operation is guaranteed.
773 * The write result will be complete (coherent) some time later
774 * (this is practically a finite period but there is no guaranteed
775 * latency)."
776 *
777 * Empirically, we observe that we need a delay of at least 75us to
778 * be sure that the seqno write is visible by the CPU.
779 */
780 usleep_range(125, 250);
781}
782
783static void
784gen6_seqno_barrier(struct intel_engine_cs *engine)
785{
786 struct drm_i915_private *dev_priv = engine->i915;
787
788 /* Workaround to force correct ordering between irq and seqno writes on
789 * ivb (and maybe also on snb) by reading from a CS register (like
790 * ACTHD) before reading the status page.
791 *
792 * Note that this effectively stalls the read by the time it takes to
793 * do a memory transaction, which more or less ensures that the write
794 * from the GPU has sufficient time to invalidate the CPU cacheline.
795 * Alternatively we could delay the interrupt from the CS ring to give
796 * the write time to land, but that would incur a delay after every
797 * batch i.e. much more frequent than a delay when waiting for the
798 * interrupt (with the same net latency).
799 *
800 * Also note that to prevent whole machine hangs on gen7, we have to
801 * take the spinlock to guard against concurrent cacheline access.
802 */
803 spin_lock_irq(&dev_priv->uncore.lock);
804 POSTING_READ_FW(RING_ACTHD(engine->mmio_base));
805 spin_unlock_irq(&dev_priv->uncore.lock);
806}
807
808static void
809gen5_irq_enable(struct intel_engine_cs *engine)
810{
811 gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask);
812}
813
814static void
815gen5_irq_disable(struct intel_engine_cs *engine)
816{
817 gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask);
818}
819
820static void
821i9xx_irq_enable(struct intel_engine_cs *engine)
822{
823 struct drm_i915_private *dev_priv = engine->i915;
824
825 dev_priv->irq_mask &= ~engine->irq_enable_mask;
826 I915_WRITE(IMR, dev_priv->irq_mask);
827 POSTING_READ_FW(RING_IMR(engine->mmio_base));
828}
829
830static void
831i9xx_irq_disable(struct intel_engine_cs *engine)
832{
833 struct drm_i915_private *dev_priv = engine->i915;
834
835 dev_priv->irq_mask |= engine->irq_enable_mask;
836 I915_WRITE(IMR, dev_priv->irq_mask);
837}
838
839static void
840i8xx_irq_enable(struct intel_engine_cs *engine)
841{
842 struct drm_i915_private *dev_priv = engine->i915;
843
844 dev_priv->irq_mask &= ~engine->irq_enable_mask;
845 I915_WRITE16(IMR, dev_priv->irq_mask);
846 POSTING_READ16(RING_IMR(engine->mmio_base));
847}
848
849static void
850i8xx_irq_disable(struct intel_engine_cs *engine)
851{
852 struct drm_i915_private *dev_priv = engine->i915;
853
854 dev_priv->irq_mask |= engine->irq_enable_mask;
855 I915_WRITE16(IMR, dev_priv->irq_mask);
856}
857
858static int
859bsd_ring_flush(struct i915_request *rq, u32 mode)
860{
861 u32 *cs;
862
863 cs = intel_ring_begin(rq, 2);
864 if (IS_ERR(cs))
865 return PTR_ERR(cs);
866
867 *cs++ = MI_FLUSH;
868 *cs++ = MI_NOOP;
869 intel_ring_advance(rq, cs);
870 return 0;
871}
872
873static void
874gen6_irq_enable(struct intel_engine_cs *engine)
875{
876 struct drm_i915_private *dev_priv = engine->i915;
877
878 I915_WRITE_IMR(engine,
879 ~(engine->irq_enable_mask |
880 engine->irq_keep_mask));
881 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask);
882}
883
884static void
885gen6_irq_disable(struct intel_engine_cs *engine)
886{
887 struct drm_i915_private *dev_priv = engine->i915;
888
889 I915_WRITE_IMR(engine, ~engine->irq_keep_mask);
890 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask);
891}
892
893static void
894hsw_vebox_irq_enable(struct intel_engine_cs *engine)
895{
896 struct drm_i915_private *dev_priv = engine->i915;
897
898 I915_WRITE_IMR(engine, ~engine->irq_enable_mask);
899 gen6_unmask_pm_irq(dev_priv, engine->irq_enable_mask);
900}
901
902static void
903hsw_vebox_irq_disable(struct intel_engine_cs *engine)
904{
905 struct drm_i915_private *dev_priv = engine->i915;
906
907 I915_WRITE_IMR(engine, ~0);
908 gen6_mask_pm_irq(dev_priv, engine->irq_enable_mask);
909}
910
911static int
912i965_emit_bb_start(struct i915_request *rq,
913 u64 offset, u32 length,
914 unsigned int dispatch_flags)
915{
916 u32 *cs;
917
918 cs = intel_ring_begin(rq, 2);
919 if (IS_ERR(cs))
920 return PTR_ERR(cs);
921
922 *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT | (dispatch_flags &
923 I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965);
924 *cs++ = offset;
925 intel_ring_advance(rq, cs);
926
927 return 0;
928}
929
930/* Just userspace ABI convention to limit the wa batch bo to a resonable size */
931#define I830_BATCH_LIMIT (256*1024)
932#define I830_TLB_ENTRIES (2)
933#define I830_WA_SIZE max(I830_TLB_ENTRIES*4096, I830_BATCH_LIMIT)
934static int
935i830_emit_bb_start(struct i915_request *rq,
936 u64 offset, u32 len,
937 unsigned int dispatch_flags)
938{
939 u32 *cs, cs_offset = i915_ggtt_offset(rq->engine->scratch);
940
941 cs = intel_ring_begin(rq, 6);
942 if (IS_ERR(cs))
943 return PTR_ERR(cs);
944
945 /* Evict the invalid PTE TLBs */
946 *cs++ = COLOR_BLT_CMD | BLT_WRITE_RGBA;
947 *cs++ = BLT_DEPTH_32 | BLT_ROP_COLOR_COPY | 4096;
948 *cs++ = I830_TLB_ENTRIES << 16 | 4; /* load each page */
949 *cs++ = cs_offset;
950 *cs++ = 0xdeadbeef;
951 *cs++ = MI_NOOP;
952 intel_ring_advance(rq, cs);
953
954 if ((dispatch_flags & I915_DISPATCH_PINNED) == 0) {
955 if (len > I830_BATCH_LIMIT)
956 return -ENOSPC;
957
958 cs = intel_ring_begin(rq, 6 + 2);
959 if (IS_ERR(cs))
960 return PTR_ERR(cs);
961
962 /* Blit the batch (which has now all relocs applied) to the
963 * stable batch scratch bo area (so that the CS never
964 * stumbles over its tlb invalidation bug) ...
965 */
966 *cs++ = SRC_COPY_BLT_CMD | BLT_WRITE_RGBA;
967 *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | 4096;
968 *cs++ = DIV_ROUND_UP(len, 4096) << 16 | 4096;
969 *cs++ = cs_offset;
970 *cs++ = 4096;
971 *cs++ = offset;
972
973 *cs++ = MI_FLUSH;
974 *cs++ = MI_NOOP;
975 intel_ring_advance(rq, cs);
976
977 /* ... and execute it. */
978 offset = cs_offset;
979 }
980
981 cs = intel_ring_begin(rq, 2);
982 if (IS_ERR(cs))
983 return PTR_ERR(cs);
984
985 *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
986 *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 :
987 MI_BATCH_NON_SECURE);
988 intel_ring_advance(rq, cs);
989
990 return 0;
991}
992
993static int
994i915_emit_bb_start(struct i915_request *rq,
995 u64 offset, u32 len,
996 unsigned int dispatch_flags)
997{
998 u32 *cs;
999
1000 cs = intel_ring_begin(rq, 2);
1001 if (IS_ERR(cs))
1002 return PTR_ERR(cs);
1003
1004 *cs++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
1005 *cs++ = offset | (dispatch_flags & I915_DISPATCH_SECURE ? 0 :
1006 MI_BATCH_NON_SECURE);
1007 intel_ring_advance(rq, cs);
1008
1009 return 0;
1010}
1011
1012
1013
1014int intel_ring_pin(struct intel_ring *ring,
1015 struct drm_i915_private *i915,
1016 unsigned int offset_bias)
1017{
1018 enum i915_map_type map = HAS_LLC(i915) ? I915_MAP_WB : I915_MAP_WC;
1019 struct i915_vma *vma = ring->vma;
1020 unsigned int flags;
1021 void *addr;
1022 int ret;
1023
1024 GEM_BUG_ON(ring->vaddr);
1025
1026
1027 flags = PIN_GLOBAL;
1028 if (offset_bias)
1029 flags |= PIN_OFFSET_BIAS | offset_bias;
1030 if (vma->obj->stolen)
1031 flags |= PIN_MAPPABLE;
1032
1033 if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
1034 if (flags & PIN_MAPPABLE || map == I915_MAP_WC)
1035 ret = i915_gem_object_set_to_gtt_domain(vma->obj, true);
1036 else
1037 ret = i915_gem_object_set_to_cpu_domain(vma->obj, true);
1038 if (unlikely(ret))
1039 return ret;
1040 }
1041
1042 ret = i915_vma_pin(vma, 0, PAGE_SIZE, flags);
1043 if (unlikely(ret))
1044 return ret;
1045
1046 if (i915_vma_is_map_and_fenceable(vma))
1047 addr = (void __force *)i915_vma_pin_iomap(vma);
1048 else
1049 addr = i915_gem_object_pin_map(vma->obj, map);
1050 if (IS_ERR(addr))
1051 goto err;
1052
1053 vma->obj->pin_global++;
1054
1055 ring->vaddr = addr;
1056 return 0;
1057
1058err:
1059 i915_vma_unpin(vma);
1060 return PTR_ERR(addr);
1061}
1062
1063void intel_ring_reset(struct intel_ring *ring, u32 tail)
1064{
1065 GEM_BUG_ON(!list_empty(&ring->request_list));
1066 ring->tail = tail;
1067 ring->head = tail;
1068 ring->emit = tail;
1069 intel_ring_update_space(ring);
1070}
1071
1072void intel_ring_unpin(struct intel_ring *ring)
1073{
1074 GEM_BUG_ON(!ring->vma);
1075 GEM_BUG_ON(!ring->vaddr);
1076
1077 /* Discard any unused bytes beyond that submitted to hw. */
1078 intel_ring_reset(ring, ring->tail);
1079
1080 if (i915_vma_is_map_and_fenceable(ring->vma))
1081 i915_vma_unpin_iomap(ring->vma);
1082 else
1083 i915_gem_object_unpin_map(ring->vma->obj);
1084 ring->vaddr = NULL;
1085
1086 ring->vma->obj->pin_global--;
1087 i915_vma_unpin(ring->vma);
1088}
1089
1090static struct i915_vma *
1091intel_ring_create_vma(struct drm_i915_private *dev_priv, int size)
1092{
1093 struct drm_i915_gem_object *obj;
1094 struct i915_vma *vma;
1095
1096 obj = i915_gem_object_create_stolen(dev_priv, size);
1097 if (!obj)
1098 obj = i915_gem_object_create_internal(dev_priv, size);
1099 if (IS_ERR(obj))
1100 return ERR_CAST(obj);
1101
1102 /* mark ring buffers as read-only from GPU side by default */
1103 obj->gt_ro = 1;
1104
1105 vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL);
1106 if (IS_ERR(vma))
1107 goto err;
1108
1109 return vma;
1110
1111err:
1112 i915_gem_object_put(obj);
1113 return vma;
1114}
1115
1116struct intel_ring *
1117intel_engine_create_ring(struct intel_engine_cs *engine, int size)
1118{
1119 struct intel_ring *ring;
1120 struct i915_vma *vma;
1121
1122 GEM_BUG_ON(!is_power_of_2(size));
1123 GEM_BUG_ON(RING_CTL_SIZE(size) & ~RING_NR_PAGES);
1124
1125 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
1126 if (!ring)
1127 return ERR_PTR(-ENOMEM);
1128
1129 INIT_LIST_HEAD(&ring->request_list);
1130
1131 ring->size = size;
1132 /* Workaround an erratum on the i830 which causes a hang if
1133 * the TAIL pointer points to within the last 2 cachelines
1134 * of the buffer.
1135 */
1136 ring->effective_size = size;
1137 if (IS_I830(engine->i915) || IS_I845G(engine->i915))
1138 ring->effective_size -= 2 * CACHELINE_BYTES;
1139
1140 intel_ring_update_space(ring);
1141
1142 vma = intel_ring_create_vma(engine->i915, size);
1143 if (IS_ERR(vma)) {
1144 kfree(ring);
1145 return ERR_CAST(vma);
1146 }
1147 ring->vma = vma;
1148
1149 return ring;
1150}
1151
1152void
1153intel_ring_free(struct intel_ring *ring)
1154{
1155 struct drm_i915_gem_object *obj = ring->vma->obj;
1156
1157 i915_vma_close(ring->vma);
1158 __i915_gem_object_release_unless_active(obj);
1159
1160 kfree(ring);
1161}
1162
1163static int context_pin(struct i915_gem_context *ctx)
1164{
1165 struct i915_vma *vma = ctx->engine[RCS].state;
1166 int ret;
1167
1168 /*
1169 * Clear this page out of any CPU caches for coherent swap-in/out.
1170 * We only want to do this on the first bind so that we do not stall
1171 * on an active context (which by nature is already on the GPU).
1172 */
1173 if (!(vma->flags & I915_VMA_GLOBAL_BIND)) {
1174 ret = i915_gem_object_set_to_gtt_domain(vma->obj, true);
1175 if (ret)
1176 return ret;
1177 }
1178
1179 return i915_vma_pin(vma, 0, I915_GTT_MIN_ALIGNMENT,
1180 PIN_GLOBAL | PIN_HIGH);
1181}
1182
1183static struct i915_vma *
1184alloc_context_vma(struct intel_engine_cs *engine)
1185{
1186 struct drm_i915_private *i915 = engine->i915;
1187 struct drm_i915_gem_object *obj;
1188 struct i915_vma *vma;
1189 int err;
1190
1191 obj = i915_gem_object_create(i915, engine->context_size);
1192 if (IS_ERR(obj))
1193 return ERR_CAST(obj);
1194
1195 if (engine->default_state) {
1196 void *defaults, *vaddr;
1197
1198 vaddr = i915_gem_object_pin_map(obj, I915_MAP_WB);
1199 if (IS_ERR(vaddr)) {
1200 err = PTR_ERR(vaddr);
1201 goto err_obj;
1202 }
1203
1204 defaults = i915_gem_object_pin_map(engine->default_state,
1205 I915_MAP_WB);
1206 if (IS_ERR(defaults)) {
1207 err = PTR_ERR(defaults);
1208 goto err_map;
1209 }
1210
1211 memcpy(vaddr, defaults, engine->context_size);
1212
1213 i915_gem_object_unpin_map(engine->default_state);
1214 i915_gem_object_unpin_map(obj);
1215 }
1216
1217 /*
1218 * Try to make the context utilize L3 as well as LLC.
1219 *
1220 * On VLV we don't have L3 controls in the PTEs so we
1221 * shouldn't touch the cache level, especially as that
1222 * would make the object snooped which might have a
1223 * negative performance impact.
1224 *
1225 * Snooping is required on non-llc platforms in execlist
1226 * mode, but since all GGTT accesses use PAT entry 0 we
1227 * get snooping anyway regardless of cache_level.
1228 *
1229 * This is only applicable for Ivy Bridge devices since
1230 * later platforms don't have L3 control bits in the PTE.
1231 */
1232 if (IS_IVYBRIDGE(i915)) {
1233 /* Ignore any error, regard it as a simple optimisation */
1234 i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
1235 }
1236
1237 vma = i915_vma_instance(obj, &i915->ggtt.base, NULL);
1238 if (IS_ERR(vma)) {
1239 err = PTR_ERR(vma);
1240 goto err_obj;
1241 }
1242
1243 return vma;
1244
1245err_map:
1246 i915_gem_object_unpin_map(obj);
1247err_obj:
1248 i915_gem_object_put(obj);
1249 return ERR_PTR(err);
1250}
1251
1252static struct intel_ring *
1253intel_ring_context_pin(struct intel_engine_cs *engine,
1254 struct i915_gem_context *ctx)
1255{
1256 struct intel_context *ce = &ctx->engine[engine->id];
1257 int ret;
1258
1259 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
1260
1261 if (likely(ce->pin_count++))
1262 goto out;
1263 GEM_BUG_ON(!ce->pin_count); /* no overflow please! */
1264
1265 if (!ce->state && engine->context_size) {
1266 struct i915_vma *vma;
1267
1268 vma = alloc_context_vma(engine);
1269 if (IS_ERR(vma)) {
1270 ret = PTR_ERR(vma);
1271 goto err;
1272 }
1273
1274 ce->state = vma;
1275 }
1276
1277 if (ce->state) {
1278 ret = context_pin(ctx);
1279 if (ret)
1280 goto err;
1281
1282 ce->state->obj->pin_global++;
1283 }
1284
1285 i915_gem_context_get(ctx);
1286
1287out:
1288 /* One ringbuffer to rule them all */
1289 return engine->buffer;
1290
1291err:
1292 ce->pin_count = 0;
1293 return ERR_PTR(ret);
1294}
1295
1296static void intel_ring_context_unpin(struct intel_engine_cs *engine,
1297 struct i915_gem_context *ctx)
1298{
1299 struct intel_context *ce = &ctx->engine[engine->id];
1300
1301 lockdep_assert_held(&ctx->i915->drm.struct_mutex);
1302 GEM_BUG_ON(ce->pin_count == 0);
1303
1304 if (--ce->pin_count)
1305 return;
1306
1307 if (ce->state) {
1308 ce->state->obj->pin_global--;
1309 i915_vma_unpin(ce->state);
1310 }
1311
1312 i915_gem_context_put(ctx);
1313}
1314
1315static int intel_init_ring_buffer(struct intel_engine_cs *engine)
1316{
1317 struct intel_ring *ring;
1318 int err;
1319
1320 intel_engine_setup_common(engine);
1321
1322 err = intel_engine_init_common(engine);
1323 if (err)
1324 goto err;
1325
1326 ring = intel_engine_create_ring(engine, 32 * PAGE_SIZE);
1327 if (IS_ERR(ring)) {
1328 err = PTR_ERR(ring);
1329 goto err;
1330 }
1331
1332 /* Ring wraparound at offset 0 sometimes hangs. No idea why. */
1333 err = intel_ring_pin(ring, engine->i915, I915_GTT_PAGE_SIZE);
1334 if (err)
1335 goto err_ring;
1336
1337 GEM_BUG_ON(engine->buffer);
1338 engine->buffer = ring;
1339
1340 return 0;
1341
1342err_ring:
1343 intel_ring_free(ring);
1344err:
1345 intel_engine_cleanup_common(engine);
1346 return err;
1347}
1348
1349void intel_engine_cleanup(struct intel_engine_cs *engine)
1350{
1351 struct drm_i915_private *dev_priv = engine->i915;
1352
1353 WARN_ON(INTEL_GEN(dev_priv) > 2 &&
1354 (I915_READ_MODE(engine) & MODE_IDLE) == 0);
1355
1356 intel_ring_unpin(engine->buffer);
1357 intel_ring_free(engine->buffer);
1358
1359 if (engine->cleanup)
1360 engine->cleanup(engine);
1361
1362 intel_engine_cleanup_common(engine);
1363
1364 dev_priv->engine[engine->id] = NULL;
1365 kfree(engine);
1366}
1367
1368void intel_legacy_submission_resume(struct drm_i915_private *dev_priv)
1369{
1370 struct intel_engine_cs *engine;
1371 enum intel_engine_id id;
1372
1373 /* Restart from the beginning of the rings for convenience */
1374 for_each_engine(engine, dev_priv, id)
1375 intel_ring_reset(engine->buffer, 0);
1376}
1377
1378static inline int mi_set_context(struct i915_request *rq, u32 flags)
1379{
1380 struct drm_i915_private *i915 = rq->i915;
1381 struct intel_engine_cs *engine = rq->engine;
1382 enum intel_engine_id id;
1383 const int num_rings =
1384 /* Use an extended w/a on gen7 if signalling from other rings */
1385 (HAS_LEGACY_SEMAPHORES(i915) && IS_GEN7(i915)) ?
1386 INTEL_INFO(i915)->num_rings - 1 :
1387 0;
1388 int len;
1389 u32 *cs;
1390
1391 flags |= MI_MM_SPACE_GTT;
1392 if (IS_HASWELL(i915))
1393 /* These flags are for resource streamer on HSW+ */
1394 flags |= HSW_MI_RS_SAVE_STATE_EN | HSW_MI_RS_RESTORE_STATE_EN;
1395 else
1396 flags |= MI_SAVE_EXT_STATE_EN | MI_RESTORE_EXT_STATE_EN;
1397
1398 len = 4;
1399 if (IS_GEN7(i915))
1400 len += 2 + (num_rings ? 4*num_rings + 6 : 0);
1401
1402 cs = intel_ring_begin(rq, len);
1403 if (IS_ERR(cs))
1404 return PTR_ERR(cs);
1405
1406 /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw,bdw,chv */
1407 if (IS_GEN7(i915)) {
1408 *cs++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1409 if (num_rings) {
1410 struct intel_engine_cs *signaller;
1411
1412 *cs++ = MI_LOAD_REGISTER_IMM(num_rings);
1413 for_each_engine(signaller, i915, id) {
1414 if (signaller == engine)
1415 continue;
1416
1417 *cs++ = i915_mmio_reg_offset(
1418 RING_PSMI_CTL(signaller->mmio_base));
1419 *cs++ = _MASKED_BIT_ENABLE(
1420 GEN6_PSMI_SLEEP_MSG_DISABLE);
1421 }
1422 }
1423 }
1424
1425 *cs++ = MI_NOOP;
1426 *cs++ = MI_SET_CONTEXT;
1427 *cs++ = i915_ggtt_offset(rq->ctx->engine[RCS].state) | flags;
1428 /*
1429 * w/a: MI_SET_CONTEXT must always be followed by MI_NOOP
1430 * WaMiSetContext_Hang:snb,ivb,vlv
1431 */
1432 *cs++ = MI_NOOP;
1433
1434 if (IS_GEN7(i915)) {
1435 if (num_rings) {
1436 struct intel_engine_cs *signaller;
1437 i915_reg_t last_reg = {}; /* keep gcc quiet */
1438
1439 *cs++ = MI_LOAD_REGISTER_IMM(num_rings);
1440 for_each_engine(signaller, i915, id) {
1441 if (signaller == engine)
1442 continue;
1443
1444 last_reg = RING_PSMI_CTL(signaller->mmio_base);
1445 *cs++ = i915_mmio_reg_offset(last_reg);
1446 *cs++ = _MASKED_BIT_DISABLE(
1447 GEN6_PSMI_SLEEP_MSG_DISABLE);
1448 }
1449
1450 /* Insert a delay before the next switch! */
1451 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
1452 *cs++ = i915_mmio_reg_offset(last_reg);
1453 *cs++ = i915_ggtt_offset(engine->scratch);
1454 *cs++ = MI_NOOP;
1455 }
1456 *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1457 }
1458
1459 intel_ring_advance(rq, cs);
1460
1461 return 0;
1462}
1463
1464static int remap_l3(struct i915_request *rq, int slice)
1465{
1466 u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice];
1467 int i;
1468
1469 if (!remap_info)
1470 return 0;
1471
1472 cs = intel_ring_begin(rq, GEN7_L3LOG_SIZE/4 * 2 + 2);
1473 if (IS_ERR(cs))
1474 return PTR_ERR(cs);
1475
1476 /*
1477 * Note: We do not worry about the concurrent register cacheline hang
1478 * here because no other code should access these registers other than
1479 * at initialization time.
1480 */
1481 *cs++ = MI_LOAD_REGISTER_IMM(GEN7_L3LOG_SIZE/4);
1482 for (i = 0; i < GEN7_L3LOG_SIZE/4; i++) {
1483 *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i));
1484 *cs++ = remap_info[i];
1485 }
1486 *cs++ = MI_NOOP;
1487 intel_ring_advance(rq, cs);
1488
1489 return 0;
1490}
1491
1492static int switch_context(struct i915_request *rq)
1493{
1494 struct intel_engine_cs *engine = rq->engine;
1495 struct i915_gem_context *to_ctx = rq->ctx;
1496 struct i915_hw_ppgtt *to_mm =
1497 to_ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt;
1498 struct i915_gem_context *from_ctx = engine->legacy_active_context;
1499 struct i915_hw_ppgtt *from_mm = engine->legacy_active_ppgtt;
1500 u32 hw_flags = 0;
1501 int ret, i;
1502
1503 lockdep_assert_held(&rq->i915->drm.struct_mutex);
1504 GEM_BUG_ON(HAS_EXECLISTS(rq->i915));
1505
1506 if (to_mm != from_mm ||
1507 (to_mm && intel_engine_flag(engine) & to_mm->pd_dirty_rings)) {
1508 trace_switch_mm(engine, to_ctx);
1509 ret = to_mm->switch_mm(to_mm, rq);
1510 if (ret)
1511 goto err;
1512
1513 to_mm->pd_dirty_rings &= ~intel_engine_flag(engine);
1514 engine->legacy_active_ppgtt = to_mm;
1515 hw_flags = MI_FORCE_RESTORE;
1516 }
1517
1518 if (to_ctx->engine[engine->id].state &&
1519 (to_ctx != from_ctx || hw_flags & MI_FORCE_RESTORE)) {
1520 GEM_BUG_ON(engine->id != RCS);
1521
1522 /*
1523 * The kernel context(s) is treated as pure scratch and is not
1524 * expected to retain any state (as we sacrifice it during
1525 * suspend and on resume it may be corrupted). This is ok,
1526 * as nothing actually executes using the kernel context; it
1527 * is purely used for flushing user contexts.
1528 */
1529 if (i915_gem_context_is_kernel(to_ctx))
1530 hw_flags = MI_RESTORE_INHIBIT;
1531
1532 ret = mi_set_context(rq, hw_flags);
1533 if (ret)
1534 goto err_mm;
1535
1536 engine->legacy_active_context = to_ctx;
1537 }
1538
1539 if (to_ctx->remap_slice) {
1540 for (i = 0; i < MAX_L3_SLICES; i++) {
1541 if (!(to_ctx->remap_slice & BIT(i)))
1542 continue;
1543
1544 ret = remap_l3(rq, i);
1545 if (ret)
1546 goto err_ctx;
1547 }
1548
1549 to_ctx->remap_slice = 0;
1550 }
1551
1552 return 0;
1553
1554err_ctx:
1555 engine->legacy_active_context = from_ctx;
1556err_mm:
1557 engine->legacy_active_ppgtt = from_mm;
1558err:
1559 return ret;
1560}
1561
1562static int ring_request_alloc(struct i915_request *request)
1563{
1564 int ret;
1565
1566 GEM_BUG_ON(!request->ctx->engine[request->engine->id].pin_count);
1567
1568 /* Flush enough space to reduce the likelihood of waiting after
1569 * we start building the request - in which case we will just
1570 * have to repeat work.
1571 */
1572 request->reserved_space += LEGACY_REQUEST_SIZE;
1573
1574 ret = intel_ring_wait_for_space(request->ring, request->reserved_space);
1575 if (ret)
1576 return ret;
1577
1578 ret = switch_context(request);
1579 if (ret)
1580 return ret;
1581
1582 request->reserved_space -= LEGACY_REQUEST_SIZE;
1583 return 0;
1584}
1585
1586static noinline int wait_for_space(struct intel_ring *ring, unsigned int bytes)
1587{
1588 struct i915_request *target;
1589 long timeout;
1590
1591 lockdep_assert_held(&ring->vma->vm->i915->drm.struct_mutex);
1592
1593 if (intel_ring_update_space(ring) >= bytes)
1594 return 0;
1595
1596 list_for_each_entry(target, &ring->request_list, ring_link) {
1597 /* Would completion of this request free enough space? */
1598 if (bytes <= __intel_ring_space(target->postfix,
1599 ring->emit, ring->size))
1600 break;
1601 }
1602
1603 if (WARN_ON(&target->ring_link == &ring->request_list))
1604 return -ENOSPC;
1605
1606 timeout = i915_request_wait(target,
1607 I915_WAIT_INTERRUPTIBLE | I915_WAIT_LOCKED,
1608 MAX_SCHEDULE_TIMEOUT);
1609 if (timeout < 0)
1610 return timeout;
1611
1612 i915_request_retire_upto(target);
1613
1614 intel_ring_update_space(ring);
1615 GEM_BUG_ON(ring->space < bytes);
1616 return 0;
1617}
1618
1619int intel_ring_wait_for_space(struct intel_ring *ring, unsigned int bytes)
1620{
1621 GEM_BUG_ON(bytes > ring->effective_size);
1622 if (unlikely(bytes > ring->effective_size - ring->emit))
1623 bytes += ring->size - ring->emit;
1624
1625 if (unlikely(bytes > ring->space)) {
1626 int ret = wait_for_space(ring, bytes);
1627 if (unlikely(ret))
1628 return ret;
1629 }
1630
1631 GEM_BUG_ON(ring->space < bytes);
1632 return 0;
1633}
1634
1635u32 *intel_ring_begin(struct i915_request *rq, unsigned int num_dwords)
1636{
1637 struct intel_ring *ring = rq->ring;
1638 const unsigned int remain_usable = ring->effective_size - ring->emit;
1639 const unsigned int bytes = num_dwords * sizeof(u32);
1640 unsigned int need_wrap = 0;
1641 unsigned int total_bytes;
1642 u32 *cs;
1643
1644 /* Packets must be qword aligned. */
1645 GEM_BUG_ON(num_dwords & 1);
1646
1647 total_bytes = bytes + rq->reserved_space;
1648 GEM_BUG_ON(total_bytes > ring->effective_size);
1649
1650 if (unlikely(total_bytes > remain_usable)) {
1651 const int remain_actual = ring->size - ring->emit;
1652
1653 if (bytes > remain_usable) {
1654 /*
1655 * Not enough space for the basic request. So need to
1656 * flush out the remainder and then wait for
1657 * base + reserved.
1658 */
1659 total_bytes += remain_actual;
1660 need_wrap = remain_actual | 1;
1661 } else {
1662 /*
1663 * The base request will fit but the reserved space
1664 * falls off the end. So we don't need an immediate
1665 * wrap and only need to effectively wait for the
1666 * reserved size from the start of ringbuffer.
1667 */
1668 total_bytes = rq->reserved_space + remain_actual;
1669 }
1670 }
1671
1672 if (unlikely(total_bytes > ring->space)) {
1673 int ret;
1674
1675 /*
1676 * Space is reserved in the ringbuffer for finalising the
1677 * request, as that cannot be allowed to fail. During request
1678 * finalisation, reserved_space is set to 0 to stop the
1679 * overallocation and the assumption is that then we never need
1680 * to wait (which has the risk of failing with EINTR).
1681 *
1682 * See also i915_request_alloc() and i915_request_add().
1683 */
1684 GEM_BUG_ON(!rq->reserved_space);
1685
1686 ret = wait_for_space(ring, total_bytes);
1687 if (unlikely(ret))
1688 return ERR_PTR(ret);
1689 }
1690
1691 if (unlikely(need_wrap)) {
1692 need_wrap &= ~1;
1693 GEM_BUG_ON(need_wrap > ring->space);
1694 GEM_BUG_ON(ring->emit + need_wrap > ring->size);
1695
1696 /* Fill the tail with MI_NOOP */
1697 memset(ring->vaddr + ring->emit, 0, need_wrap);
1698 ring->emit = 0;
1699 ring->space -= need_wrap;
1700 }
1701
1702 GEM_BUG_ON(ring->emit > ring->size - bytes);
1703 GEM_BUG_ON(ring->space < bytes);
1704 cs = ring->vaddr + ring->emit;
1705 GEM_DEBUG_EXEC(memset(cs, POISON_INUSE, bytes));
1706 ring->emit += bytes;
1707 ring->space -= bytes;
1708
1709 return cs;
1710}
1711
1712/* Align the ring tail to a cacheline boundary */
1713int intel_ring_cacheline_align(struct i915_request *rq)
1714{
1715 int num_dwords = (rq->ring->emit & (CACHELINE_BYTES - 1)) / sizeof(u32);
1716 u32 *cs;
1717
1718 if (num_dwords == 0)
1719 return 0;
1720
1721 num_dwords = CACHELINE_BYTES / sizeof(u32) - num_dwords;
1722 cs = intel_ring_begin(rq, num_dwords);
1723 if (IS_ERR(cs))
1724 return PTR_ERR(cs);
1725
1726 while (num_dwords--)
1727 *cs++ = MI_NOOP;
1728
1729 intel_ring_advance(rq, cs);
1730
1731 return 0;
1732}
1733
1734static void gen6_bsd_submit_request(struct i915_request *request)
1735{
1736 struct drm_i915_private *dev_priv = request->i915;
1737
1738 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1739
1740 /* Every tail move must follow the sequence below */
1741
1742 /* Disable notification that the ring is IDLE. The GT
1743 * will then assume that it is busy and bring it out of rc6.
1744 */
1745 I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,
1746 _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1747
1748 /* Clear the context id. Here be magic! */
1749 I915_WRITE64_FW(GEN6_BSD_RNCID, 0x0);
1750
1751 /* Wait for the ring not to be idle, i.e. for it to wake up. */
1752 if (__intel_wait_for_register_fw(dev_priv,
1753 GEN6_BSD_SLEEP_PSMI_CONTROL,
1754 GEN6_BSD_SLEEP_INDICATOR,
1755 0,
1756 1000, 0, NULL))
1757 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1758
1759 /* Now that the ring is fully powered up, update the tail */
1760 i9xx_submit_request(request);
1761
1762 /* Let the ring send IDLE messages to the GT again,
1763 * and so let it sleep to conserve power when idle.
1764 */
1765 I915_WRITE_FW(GEN6_BSD_SLEEP_PSMI_CONTROL,
1766 _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1767
1768 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1769}
1770
1771static int gen6_bsd_ring_flush(struct i915_request *rq, u32 mode)
1772{
1773 u32 cmd, *cs;
1774
1775 cs = intel_ring_begin(rq, 4);
1776 if (IS_ERR(cs))
1777 return PTR_ERR(cs);
1778
1779 cmd = MI_FLUSH_DW;
1780
1781 /* We always require a command barrier so that subsequent
1782 * commands, such as breadcrumb interrupts, are strictly ordered
1783 * wrt the contents of the write cache being flushed to memory
1784 * (and thus being coherent from the CPU).
1785 */
1786 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1787
1788 /*
1789 * Bspec vol 1c.5 - video engine command streamer:
1790 * "If ENABLED, all TLBs will be invalidated once the flush
1791 * operation is complete. This bit is only valid when the
1792 * Post-Sync Operation field is a value of 1h or 3h."
1793 */
1794 if (mode & EMIT_INVALIDATE)
1795 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1796
1797 *cs++ = cmd;
1798 *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
1799 *cs++ = 0;
1800 *cs++ = MI_NOOP;
1801 intel_ring_advance(rq, cs);
1802 return 0;
1803}
1804
1805static int
1806hsw_emit_bb_start(struct i915_request *rq,
1807 u64 offset, u32 len,
1808 unsigned int dispatch_flags)
1809{
1810 u32 *cs;
1811
1812 cs = intel_ring_begin(rq, 2);
1813 if (IS_ERR(cs))
1814 return PTR_ERR(cs);
1815
1816 *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ?
1817 0 : MI_BATCH_PPGTT_HSW | MI_BATCH_NON_SECURE_HSW) |
1818 (dispatch_flags & I915_DISPATCH_RS ?
1819 MI_BATCH_RESOURCE_STREAMER : 0);
1820 /* bit0-7 is the length on GEN6+ */
1821 *cs++ = offset;
1822 intel_ring_advance(rq, cs);
1823
1824 return 0;
1825}
1826
1827static int
1828gen6_emit_bb_start(struct i915_request *rq,
1829 u64 offset, u32 len,
1830 unsigned int dispatch_flags)
1831{
1832 u32 *cs;
1833
1834 cs = intel_ring_begin(rq, 2);
1835 if (IS_ERR(cs))
1836 return PTR_ERR(cs);
1837
1838 *cs++ = MI_BATCH_BUFFER_START | (dispatch_flags & I915_DISPATCH_SECURE ?
1839 0 : MI_BATCH_NON_SECURE_I965);
1840 /* bit0-7 is the length on GEN6+ */
1841 *cs++ = offset;
1842 intel_ring_advance(rq, cs);
1843
1844 return 0;
1845}
1846
1847/* Blitter support (SandyBridge+) */
1848
1849static int gen6_ring_flush(struct i915_request *rq, u32 mode)
1850{
1851 u32 cmd, *cs;
1852
1853 cs = intel_ring_begin(rq, 4);
1854 if (IS_ERR(cs))
1855 return PTR_ERR(cs);
1856
1857 cmd = MI_FLUSH_DW;
1858
1859 /* We always require a command barrier so that subsequent
1860 * commands, such as breadcrumb interrupts, are strictly ordered
1861 * wrt the contents of the write cache being flushed to memory
1862 * (and thus being coherent from the CPU).
1863 */
1864 cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1865
1866 /*
1867 * Bspec vol 1c.3 - blitter engine command streamer:
1868 * "If ENABLED, all TLBs will be invalidated once the flush
1869 * operation is complete. This bit is only valid when the
1870 * Post-Sync Operation field is a value of 1h or 3h."
1871 */
1872 if (mode & EMIT_INVALIDATE)
1873 cmd |= MI_INVALIDATE_TLB;
1874 *cs++ = cmd;
1875 *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT;
1876 *cs++ = 0;
1877 *cs++ = MI_NOOP;
1878 intel_ring_advance(rq, cs);
1879
1880 return 0;
1881}
1882
1883static void intel_ring_init_semaphores(struct drm_i915_private *dev_priv,
1884 struct intel_engine_cs *engine)
1885{
1886 int i;
1887
1888 if (!HAS_LEGACY_SEMAPHORES(dev_priv))
1889 return;
1890
1891 GEM_BUG_ON(INTEL_GEN(dev_priv) < 6);
1892 engine->semaphore.sync_to = gen6_ring_sync_to;
1893 engine->semaphore.signal = gen6_signal;
1894
1895 /*
1896 * The current semaphore is only applied on pre-gen8
1897 * platform. And there is no VCS2 ring on the pre-gen8
1898 * platform. So the semaphore between RCS and VCS2 is
1899 * initialized as INVALID.
1900 */
1901 for (i = 0; i < GEN6_NUM_SEMAPHORES; i++) {
1902 static const struct {
1903 u32 wait_mbox;
1904 i915_reg_t mbox_reg;
1905 } sem_data[GEN6_NUM_SEMAPHORES][GEN6_NUM_SEMAPHORES] = {
1906 [RCS_HW] = {
1907 [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RV, .mbox_reg = GEN6_VRSYNC },
1908 [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RB, .mbox_reg = GEN6_BRSYNC },
1909 [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_RVE, .mbox_reg = GEN6_VERSYNC },
1910 },
1911 [VCS_HW] = {
1912 [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VR, .mbox_reg = GEN6_RVSYNC },
1913 [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VB, .mbox_reg = GEN6_BVSYNC },
1914 [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VVE, .mbox_reg = GEN6_VEVSYNC },
1915 },
1916 [BCS_HW] = {
1917 [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BR, .mbox_reg = GEN6_RBSYNC },
1918 [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BV, .mbox_reg = GEN6_VBSYNC },
1919 [VECS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_BVE, .mbox_reg = GEN6_VEBSYNC },
1920 },
1921 [VECS_HW] = {
1922 [RCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VER, .mbox_reg = GEN6_RVESYNC },
1923 [VCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEV, .mbox_reg = GEN6_VVESYNC },
1924 [BCS_HW] = { .wait_mbox = MI_SEMAPHORE_SYNC_VEB, .mbox_reg = GEN6_BVESYNC },
1925 },
1926 };
1927 u32 wait_mbox;
1928 i915_reg_t mbox_reg;
1929
1930 if (i == engine->hw_id) {
1931 wait_mbox = MI_SEMAPHORE_SYNC_INVALID;
1932 mbox_reg = GEN6_NOSYNC;
1933 } else {
1934 wait_mbox = sem_data[engine->hw_id][i].wait_mbox;
1935 mbox_reg = sem_data[engine->hw_id][i].mbox_reg;
1936 }
1937
1938 engine->semaphore.mbox.wait[i] = wait_mbox;
1939 engine->semaphore.mbox.signal[i] = mbox_reg;
1940 }
1941}
1942
1943static void intel_ring_init_irq(struct drm_i915_private *dev_priv,
1944 struct intel_engine_cs *engine)
1945{
1946 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << engine->irq_shift;
1947
1948 if (INTEL_GEN(dev_priv) >= 6) {
1949 engine->irq_enable = gen6_irq_enable;
1950 engine->irq_disable = gen6_irq_disable;
1951 engine->irq_seqno_barrier = gen6_seqno_barrier;
1952 } else if (INTEL_GEN(dev_priv) >= 5) {
1953 engine->irq_enable = gen5_irq_enable;
1954 engine->irq_disable = gen5_irq_disable;
1955 engine->irq_seqno_barrier = gen5_seqno_barrier;
1956 } else if (INTEL_GEN(dev_priv) >= 3) {
1957 engine->irq_enable = i9xx_irq_enable;
1958 engine->irq_disable = i9xx_irq_disable;
1959 } else {
1960 engine->irq_enable = i8xx_irq_enable;
1961 engine->irq_disable = i8xx_irq_disable;
1962 }
1963}
1964
1965static void i9xx_set_default_submission(struct intel_engine_cs *engine)
1966{
1967 engine->submit_request = i9xx_submit_request;
1968 engine->cancel_requests = cancel_requests;
1969
1970 engine->park = NULL;
1971 engine->unpark = NULL;
1972}
1973
1974static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine)
1975{
1976 i9xx_set_default_submission(engine);
1977 engine->submit_request = gen6_bsd_submit_request;
1978}
1979
1980static void intel_ring_default_vfuncs(struct drm_i915_private *dev_priv,
1981 struct intel_engine_cs *engine)
1982{
1983 /* gen8+ are only supported with execlists */
1984 GEM_BUG_ON(INTEL_GEN(dev_priv) >= 8);
1985
1986 intel_ring_init_irq(dev_priv, engine);
1987 intel_ring_init_semaphores(dev_priv, engine);
1988
1989 engine->init_hw = init_ring_common;
1990 engine->reset_hw = reset_ring_common;
1991
1992 engine->context_pin = intel_ring_context_pin;
1993 engine->context_unpin = intel_ring_context_unpin;
1994
1995 engine->request_alloc = ring_request_alloc;
1996
1997 engine->emit_breadcrumb = i9xx_emit_breadcrumb;
1998 engine->emit_breadcrumb_sz = i9xx_emit_breadcrumb_sz;
1999 if (HAS_LEGACY_SEMAPHORES(dev_priv)) {
2000 int num_rings;
2001
2002 engine->emit_breadcrumb = gen6_sema_emit_breadcrumb;
2003
2004 num_rings = INTEL_INFO(dev_priv)->num_rings - 1;
2005 engine->emit_breadcrumb_sz += num_rings * 3;
2006 if (num_rings & 1)
2007 engine->emit_breadcrumb_sz++;
2008 }
2009
2010 engine->set_default_submission = i9xx_set_default_submission;
2011
2012 if (INTEL_GEN(dev_priv) >= 6)
2013 engine->emit_bb_start = gen6_emit_bb_start;
2014 else if (INTEL_GEN(dev_priv) >= 4)
2015 engine->emit_bb_start = i965_emit_bb_start;
2016 else if (IS_I830(dev_priv) || IS_I845G(dev_priv))
2017 engine->emit_bb_start = i830_emit_bb_start;
2018 else
2019 engine->emit_bb_start = i915_emit_bb_start;
2020}
2021
2022int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
2023{
2024 struct drm_i915_private *dev_priv = engine->i915;
2025 int ret;
2026
2027 intel_ring_default_vfuncs(dev_priv, engine);
2028
2029 if (HAS_L3_DPF(dev_priv))
2030 engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
2031
2032 if (INTEL_GEN(dev_priv) >= 6) {
2033 engine->init_context = intel_rcs_ctx_init;
2034 engine->emit_flush = gen7_render_ring_flush;
2035 if (IS_GEN6(dev_priv))
2036 engine->emit_flush = gen6_render_ring_flush;
2037 } else if (IS_GEN5(dev_priv)) {
2038 engine->emit_flush = gen4_render_ring_flush;
2039 } else {
2040 if (INTEL_GEN(dev_priv) < 4)
2041 engine->emit_flush = gen2_render_ring_flush;
2042 else
2043 engine->emit_flush = gen4_render_ring_flush;
2044 engine->irq_enable_mask = I915_USER_INTERRUPT;
2045 }
2046
2047 if (IS_HASWELL(dev_priv))
2048 engine->emit_bb_start = hsw_emit_bb_start;
2049
2050 engine->init_hw = init_render_ring;
2051
2052 ret = intel_init_ring_buffer(engine);
2053 if (ret)
2054 return ret;
2055
2056 if (INTEL_GEN(dev_priv) >= 6) {
2057 ret = intel_engine_create_scratch(engine, PAGE_SIZE);
2058 if (ret)
2059 return ret;
2060 } else if (HAS_BROKEN_CS_TLB(dev_priv)) {
2061 ret = intel_engine_create_scratch(engine, I830_WA_SIZE);
2062 if (ret)
2063 return ret;
2064 }
2065
2066 return 0;
2067}
2068
2069int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine)
2070{
2071 struct drm_i915_private *dev_priv = engine->i915;
2072
2073 intel_ring_default_vfuncs(dev_priv, engine);
2074
2075 if (INTEL_GEN(dev_priv) >= 6) {
2076 /* gen6 bsd needs a special wa for tail updates */
2077 if (IS_GEN6(dev_priv))
2078 engine->set_default_submission = gen6_bsd_set_default_submission;
2079 engine->emit_flush = gen6_bsd_ring_flush;
2080 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT;
2081 } else {
2082 engine->mmio_base = BSD_RING_BASE;
2083 engine->emit_flush = bsd_ring_flush;
2084 if (IS_GEN5(dev_priv))
2085 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
2086 else
2087 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT;
2088 }
2089
2090 return intel_init_ring_buffer(engine);
2091}
2092
2093int intel_init_blt_ring_buffer(struct intel_engine_cs *engine)
2094{
2095 struct drm_i915_private *dev_priv = engine->i915;
2096
2097 intel_ring_default_vfuncs(dev_priv, engine);
2098
2099 engine->emit_flush = gen6_ring_flush;
2100 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT;
2101
2102 return intel_init_ring_buffer(engine);
2103}
2104
2105int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine)
2106{
2107 struct drm_i915_private *dev_priv = engine->i915;
2108
2109 intel_ring_default_vfuncs(dev_priv, engine);
2110
2111 engine->emit_flush = gen6_ring_flush;
2112 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT;
2113 engine->irq_enable = hsw_vebox_irq_enable;
2114 engine->irq_disable = hsw_vebox_irq_disable;
2115
2116 return intel_init_ring_buffer(engine);
2117}