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1/*
2 * Copyright 2012-14 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef DC_STREAM_H_
27#define DC_STREAM_H_
28
29#include "dc_types.h"
30#include "grph_object_defs.h"
31
32/*******************************************************************************
33 * Stream Interfaces
34 ******************************************************************************/
35struct timing_sync_info {
36 int group_id;
37 int group_size;
38 bool master;
39};
40
41struct dc_stream_status {
42 int primary_otg_inst;
43 int stream_enc_inst;
44 int plane_count;
45 int audio_inst;
46 struct timing_sync_info timing_sync_info;
47 struct dc_plane_state *plane_states[MAX_SURFACE_NUM];
48};
49
50// TODO: References to this needs to be removed..
51struct freesync_context {
52 bool dummy;
53};
54
55#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
56enum hubp_dmdata_mode {
57 DMDATA_SW_MODE,
58 DMDATA_HW_MODE
59};
60
61struct dc_dmdata_attributes {
62 /* Specifies whether dynamic meta data will be updated by software
63 * or has to be fetched by hardware (DMA mode)
64 */
65 enum hubp_dmdata_mode dmdata_mode;
66 /* Specifies if current dynamic meta data is to be used only for the current frame */
67 bool dmdata_repeat;
68 /* Specifies the size of Dynamic Metadata surface in byte. Size of 0 means no Dynamic metadata is fetched */
69 uint32_t dmdata_size;
70 /* Specifies if a new dynamic meta data should be fetched for an upcoming frame */
71 bool dmdata_updated;
72 /* If hardware mode is used, the base address where DMDATA surface is located */
73 PHYSICAL_ADDRESS_LOC address;
74 /* Specifies whether QOS level will be provided by TTU or it will come from DMDATA_QOS_LEVEL */
75 bool dmdata_qos_mode;
76 /* If qos_mode = 1, this is the QOS value to be used: */
77 uint32_t dmdata_qos_level;
78 /* Specifies the value in unit of REFCLK cycles to be added to the
79 * current time to produce the Amortized deadline for Dynamic Metadata chunk request
80 */
81 uint32_t dmdata_dl_delta;
82 /* An unbounded array of uint32s, represents software dmdata to be loaded */
83 uint32_t *dmdata_sw_data;
84};
85#endif
86
87#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
88struct dc_writeback_info {
89 bool wb_enabled;
90 int dwb_pipe_inst;
91 struct dc_dwb_params dwb_params;
92 struct mcif_buf_params mcif_buf_params;
93};
94
95struct dc_writeback_update {
96 unsigned int num_wb_info;
97 struct dc_writeback_info writeback_info[MAX_DWB_PIPES];
98};
99#endif
100
101enum vertical_interrupt_ref_point {
102 START_V_UPDATE = 0,
103 START_V_SYNC,
104 INVALID_POINT
105
106 //For now, only v_update interrupt is used.
107 //START_V_BLANK,
108 //START_V_ACTIVE
109};
110
111struct periodic_interrupt_config {
112 enum vertical_interrupt_ref_point ref_point;
113 int lines_offset;
114};
115
116
117struct dc_stream_state {
118 // sink is deprecated, new code should not reference
119 // this pointer
120 struct dc_sink *sink;
121
122 struct dc_link *link;
123 struct dc_panel_patch sink_patches;
124 union display_content_support content_support;
125 struct dc_crtc_timing timing;
126 struct dc_crtc_timing_adjust adjust;
127 struct dc_info_packet vrr_infopacket;
128 struct dc_info_packet vsc_infopacket;
129 struct dc_info_packet vsp_infopacket;
130
131 struct rect src; /* composition area */
132 struct rect dst; /* stream addressable area */
133
134 // TODO: References to this needs to be removed..
135 struct freesync_context freesync_ctx;
136
137 struct audio_info audio_info;
138
139 struct dc_info_packet hdr_static_metadata;
140 PHYSICAL_ADDRESS_LOC dmdata_address;
141 bool use_dynamic_meta;
142
143 struct dc_transfer_func *out_transfer_func;
144 struct colorspace_transform gamut_remap_matrix;
145 struct dc_csc_transform csc_color_matrix;
146
147 enum dc_color_space output_color_space;
148 enum dc_dither_option dither_option;
149
150 enum view_3d_format view_format;
151
152 bool ignore_msa_timing_param;
153 bool converter_disable_audio;
154 uint8_t qs_bit;
155 uint8_t qy_bit;
156
157 /* TODO: custom INFO packets */
158 /* TODO: ABM info (DMCU) */
159 /* PSR info */
160 unsigned char psr_version;
161 /* TODO: CEA VIC */
162
163 /* DMCU info */
164 unsigned int abm_level;
165
166 struct periodic_interrupt_config periodic_interrupt0;
167 struct periodic_interrupt_config periodic_interrupt1;
168
169 /* from core_stream struct */
170 struct dc_context *ctx;
171
172 /* used by DCP and FMT */
173 struct bit_depth_reduction_params bit_depth_params;
174 struct clamping_and_pixel_encoding_params clamping;
175
176 int phy_pix_clk;
177 enum signal_type signal;
178 bool dpms_off;
179
180 void *dm_stream_context;
181
182 struct dc_cursor_attributes cursor_attributes;
183 struct dc_cursor_position cursor_position;
184 uint32_t sdr_white_level; // for boosting (SDR) cursor in HDR mode
185
186 /* from stream struct */
187 struct kref refcount;
188
189 struct crtc_trigger_info triggered_crtc_reset;
190
191#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
192 /* writeback */
193 unsigned int num_wb_info;
194 struct dc_writeback_info writeback_info[MAX_DWB_PIPES];
195#endif
196 /* Computed state bits */
197 bool mode_changed : 1;
198
199 /* Output from DC when stream state is committed or altered
200 * DC may only access these values during:
201 * dc_commit_state, dc_commit_state_no_check, dc_commit_streams
202 * values may not change outside of those calls
203 */
204 struct {
205 // For interrupt management, some hardware instance
206 // offsets need to be exposed to DM
207 uint8_t otg_offset;
208 } out;
209
210 bool apply_edp_fast_boot_optimization;
211 bool apply_seamless_boot_optimization;
212
213 uint32_t stream_id;
214#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
215 bool is_dsc_enabled;
216#endif
217};
218
219struct dc_stream_update {
220 struct rect src;
221 struct rect dst;
222 struct dc_transfer_func *out_transfer_func;
223 struct dc_info_packet *hdr_static_metadata;
224 unsigned int *abm_level;
225
226 struct periodic_interrupt_config *periodic_interrupt0;
227 struct periodic_interrupt_config *periodic_interrupt1;
228
229 struct dc_info_packet *vrr_infopacket;
230 struct dc_info_packet *vsc_infopacket;
231 struct dc_info_packet *vsp_infopacket;
232
233 bool *dpms_off;
234
235 struct colorspace_transform *gamut_remap;
236 enum dc_color_space *output_color_space;
237 enum dc_dither_option *dither_option;
238
239 struct dc_csc_transform *output_csc_transform;
240
241#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
242 struct dc_writeback_update *wb_update;
243#endif
244#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT)
245 struct dc_dsc_config *dsc_config;
246#endif
247};
248
249bool dc_is_stream_unchanged(
250 struct dc_stream_state *old_stream, struct dc_stream_state *stream);
251bool dc_is_stream_scaling_unchanged(
252 struct dc_stream_state *old_stream, struct dc_stream_state *stream);
253
254/*
255 * Set up surface attributes and associate to a stream
256 * The surfaces parameter is an absolute set of all surface active for the stream.
257 * If no surfaces are provided, the stream will be blanked; no memory read.
258 * Any flip related attribute changes must be done through this interface.
259 *
260 * After this call:
261 * Surfaces attributes are programmed and configured to be composed into stream.
262 * This does not trigger a flip. No surface address is programmed.
263 */
264
265void dc_commit_updates_for_stream(struct dc *dc,
266 struct dc_surface_update *srf_updates,
267 int surface_count,
268 struct dc_stream_state *stream,
269 struct dc_stream_update *stream_update,
270 struct dc_state *state);
271/*
272 * Log the current stream state.
273 */
274void dc_stream_log(const struct dc *dc, const struct dc_stream_state *stream);
275
276uint8_t dc_get_current_stream_count(struct dc *dc);
277struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i);
278
279/*
280 * Return the current frame counter.
281 */
282uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream);
283
284/*
285 * Send dp sdp message.
286 */
287bool dc_stream_send_dp_sdp(const struct dc_stream_state *stream,
288 const uint8_t *custom_sdp_message,
289 unsigned int sdp_message_size);
290
291/* TODO: Return parsed values rather than direct register read
292 * This has a dependency on the caller (amdgpu_display_get_crtc_scanoutpos)
293 * being refactored properly to be dce-specific
294 */
295bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
296 uint32_t *v_blank_start,
297 uint32_t *v_blank_end,
298 uint32_t *h_position,
299 uint32_t *v_position);
300
301enum dc_status dc_add_stream_to_ctx(
302 struct dc *dc,
303 struct dc_state *new_ctx,
304 struct dc_stream_state *stream);
305
306enum dc_status dc_remove_stream_from_ctx(
307 struct dc *dc,
308 struct dc_state *new_ctx,
309 struct dc_stream_state *stream);
310
311
312bool dc_add_plane_to_context(
313 const struct dc *dc,
314 struct dc_stream_state *stream,
315 struct dc_plane_state *plane_state,
316 struct dc_state *context);
317
318bool dc_remove_plane_from_context(
319 const struct dc *dc,
320 struct dc_stream_state *stream,
321 struct dc_plane_state *plane_state,
322 struct dc_state *context);
323
324bool dc_rem_all_planes_for_stream(
325 const struct dc *dc,
326 struct dc_stream_state *stream,
327 struct dc_state *context);
328
329bool dc_add_all_planes_for_stream(
330 const struct dc *dc,
331 struct dc_stream_state *stream,
332 struct dc_plane_state * const *plane_states,
333 int plane_count,
334 struct dc_state *context);
335
336#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
337bool dc_stream_add_writeback(struct dc *dc,
338 struct dc_stream_state *stream,
339 struct dc_writeback_info *wb_info);
340bool dc_stream_remove_writeback(struct dc *dc,
341 struct dc_stream_state *stream,
342 uint32_t dwb_pipe_inst);
343bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream);
344bool dc_stream_set_dynamic_metadata(struct dc *dc,
345 struct dc_stream_state *stream,
346 struct dc_dmdata_attributes *dmdata_attr);
347#endif
348
349enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream);
350
351/*
352 * Set up streams and links associated to drive sinks
353 * The streams parameter is an absolute set of all active streams.
354 *
355 * After this call:
356 * Phy, Encoder, Timing Generator are programmed and enabled.
357 * New streams are enabled with blank stream; no memory read.
358 */
359/*
360 * Enable stereo when commit_streams is not required,
361 * for example, frame alternate.
362 */
363bool dc_enable_stereo(
364 struct dc *dc,
365 struct dc_state *context,
366 struct dc_stream_state *streams[],
367 uint8_t stream_count);
368
369
370enum surface_update_type dc_check_update_surfaces_for_stream(
371 struct dc *dc,
372 struct dc_surface_update *updates,
373 int surface_count,
374 struct dc_stream_update *stream_update,
375 const struct dc_stream_status *stream_status);
376
377/**
378 * Create a new default stream for the requested sink
379 */
380struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink);
381
382struct dc_stream_state *dc_copy_stream(const struct dc_stream_state *stream);
383
384void update_stream_signal(struct dc_stream_state *stream, struct dc_sink *sink);
385
386void dc_stream_retain(struct dc_stream_state *dc_stream);
387void dc_stream_release(struct dc_stream_state *dc_stream);
388
389struct dc_stream_status *dc_stream_get_status_from_state(
390 struct dc_state *state,
391 struct dc_stream_state *stream);
392struct dc_stream_status *dc_stream_get_status(
393 struct dc_stream_state *dc_stream);
394
395/*******************************************************************************
396 * Cursor interfaces - To manages the cursor within a stream
397 ******************************************************************************/
398/* TODO: Deprecated once we switch to dc_set_cursor_position */
399bool dc_stream_set_cursor_attributes(
400 struct dc_stream_state *stream,
401 const struct dc_cursor_attributes *attributes);
402
403bool dc_stream_set_cursor_position(
404 struct dc_stream_state *stream,
405 const struct dc_cursor_position *position);
406
407
408bool dc_stream_adjust_vmin_vmax(struct dc *dc,
409 struct dc_stream_state *stream,
410 struct dc_crtc_timing_adjust *adjust);
411
412bool dc_stream_get_crtc_position(struct dc *dc,
413 struct dc_stream_state **stream,
414 int num_streams,
415 unsigned int *v_pos,
416 unsigned int *nom_v_pos);
417
418bool dc_stream_configure_crc(struct dc *dc,
419 struct dc_stream_state *stream,
420 bool enable,
421 bool continuous);
422
423bool dc_stream_get_crc(struct dc *dc,
424 struct dc_stream_state *stream,
425 uint32_t *r_cr,
426 uint32_t *g_y,
427 uint32_t *b_cb);
428
429void dc_stream_set_static_screen_events(struct dc *dc,
430 struct dc_stream_state **stream,
431 int num_streams,
432 const struct dc_static_screen_events *events);
433
434void dc_stream_set_dither_option(struct dc_stream_state *stream,
435 enum dc_dither_option option);
436
437bool dc_stream_set_gamut_remap(struct dc *dc,
438 const struct dc_stream_state *stream);
439
440bool dc_stream_program_csc_matrix(struct dc *dc,
441 struct dc_stream_state *stream);
442
443bool dc_stream_get_crtc_position(struct dc *dc,
444 struct dc_stream_state **stream,
445 int num_streams,
446 unsigned int *v_pos,
447 unsigned int *nom_v_pos);
448
449#endif /* DC_STREAM_H_ */
1/*
2 * Copyright 2012-14 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26#ifndef DC_STREAM_H_
27#define DC_STREAM_H_
28
29#include "dc_types.h"
30#include "grph_object_defs.h"
31
32/*******************************************************************************
33 * Stream Interfaces
34 ******************************************************************************/
35
36struct dc_stream_status {
37 int primary_otg_inst;
38 int stream_enc_inst;
39 int plane_count;
40 struct dc_plane_state *plane_states[MAX_SURFACE_NUM];
41
42 /*
43 * link this stream passes through
44 */
45 struct dc_link *link;
46};
47
48struct dc_stream_state {
49 struct dc_sink *sink;
50 struct dc_crtc_timing timing;
51 struct dc_crtc_timing_adjust timing_adjust;
52 struct vrr_params vrr_params;
53
54 struct rect src; /* composition area */
55 struct rect dst; /* stream addressable area */
56
57 struct audio_info audio_info;
58
59 struct freesync_context freesync_ctx;
60
61 struct dc_hdr_static_metadata hdr_static_metadata;
62 struct dc_transfer_func *out_transfer_func;
63 struct colorspace_transform gamut_remap_matrix;
64 struct csc_transform csc_color_matrix;
65
66 enum dc_color_space output_color_space;
67 enum dc_dither_option dither_option;
68
69 enum view_3d_format view_format;
70 enum color_transfer_func output_tf;
71
72 bool ignore_msa_timing_param;
73 /* TODO: custom INFO packets */
74 /* TODO: ABM info (DMCU) */
75 /* PSR info */
76 unsigned char psr_version;
77 /* TODO: CEA VIC */
78
79 /* DMCU info */
80 unsigned int abm_level;
81 unsigned int bl_pwm_level;
82
83 /* from core_stream struct */
84 struct dc_context *ctx;
85
86 /* used by DCP and FMT */
87 struct bit_depth_reduction_params bit_depth_params;
88 struct clamping_and_pixel_encoding_params clamping;
89
90 int phy_pix_clk;
91 enum signal_type signal;
92 bool dpms_off;
93
94 struct dc_stream_status status;
95
96 struct dc_cursor_attributes cursor_attributes;
97 struct dc_cursor_position cursor_position;
98
99 /* from stream struct */
100 struct kref refcount;
101
102 struct crtc_trigger_info triggered_crtc_reset;
103
104 /* Computed state bits */
105 bool mode_changed : 1;
106
107};
108
109struct dc_stream_update {
110 struct rect src;
111 struct rect dst;
112 struct dc_transfer_func *out_transfer_func;
113 struct dc_hdr_static_metadata *hdr_static_metadata;
114 enum color_transfer_func color_output_tf;
115 unsigned int *abm_level;
116};
117
118bool dc_is_stream_unchanged(
119 struct dc_stream_state *old_stream, struct dc_stream_state *stream);
120bool dc_is_stream_scaling_unchanged(
121 struct dc_stream_state *old_stream, struct dc_stream_state *stream);
122
123/*
124 * Set up surface attributes and associate to a stream
125 * The surfaces parameter is an absolute set of all surface active for the stream.
126 * If no surfaces are provided, the stream will be blanked; no memory read.
127 * Any flip related attribute changes must be done through this interface.
128 *
129 * After this call:
130 * Surfaces attributes are programmed and configured to be composed into stream.
131 * This does not trigger a flip. No surface address is programmed.
132 */
133
134bool dc_commit_planes_to_stream(
135 struct dc *dc,
136 struct dc_plane_state **plane_states,
137 uint8_t new_plane_count,
138 struct dc_stream_state *dc_stream,
139 struct dc_state *state);
140
141void dc_commit_updates_for_stream(struct dc *dc,
142 struct dc_surface_update *srf_updates,
143 int surface_count,
144 struct dc_stream_state *stream,
145 struct dc_stream_update *stream_update,
146 struct dc_plane_state **plane_states,
147 struct dc_state *state);
148/*
149 * Log the current stream state.
150 */
151void dc_stream_log(
152 const struct dc_stream_state *stream,
153 struct dal_logger *dc_logger,
154 enum dc_log_type log_type);
155
156uint8_t dc_get_current_stream_count(struct dc *dc);
157struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i);
158
159/*
160 * Return the current frame counter.
161 */
162uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream);
163
164/* TODO: Return parsed values rather than direct register read
165 * This has a dependency on the caller (amdgpu_display_get_crtc_scanoutpos)
166 * being refactored properly to be dce-specific
167 */
168bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
169 uint32_t *v_blank_start,
170 uint32_t *v_blank_end,
171 uint32_t *h_position,
172 uint32_t *v_position);
173
174enum dc_status dc_add_stream_to_ctx(
175 struct dc *dc,
176 struct dc_state *new_ctx,
177 struct dc_stream_state *stream);
178
179enum dc_status dc_remove_stream_from_ctx(
180 struct dc *dc,
181 struct dc_state *new_ctx,
182 struct dc_stream_state *stream);
183
184
185bool dc_add_plane_to_context(
186 const struct dc *dc,
187 struct dc_stream_state *stream,
188 struct dc_plane_state *plane_state,
189 struct dc_state *context);
190
191bool dc_remove_plane_from_context(
192 const struct dc *dc,
193 struct dc_stream_state *stream,
194 struct dc_plane_state *plane_state,
195 struct dc_state *context);
196
197bool dc_rem_all_planes_for_stream(
198 const struct dc *dc,
199 struct dc_stream_state *stream,
200 struct dc_state *context);
201
202bool dc_add_all_planes_for_stream(
203 const struct dc *dc,
204 struct dc_stream_state *stream,
205 struct dc_plane_state * const *plane_states,
206 int plane_count,
207 struct dc_state *context);
208
209enum dc_status dc_validate_stream(struct dc *dc, struct dc_stream_state *stream);
210
211/*
212 * This function takes a stream and checks if it is guaranteed to be supported.
213 * Guaranteed means that MAX_COFUNC similar streams are supported.
214 *
215 * After this call:
216 * No hardware is programmed for call. Only validation is done.
217 */
218
219/*
220 * Set up streams and links associated to drive sinks
221 * The streams parameter is an absolute set of all active streams.
222 *
223 * After this call:
224 * Phy, Encoder, Timing Generator are programmed and enabled.
225 * New streams are enabled with blank stream; no memory read.
226 */
227/*
228 * Enable stereo when commit_streams is not required,
229 * for example, frame alternate.
230 */
231bool dc_enable_stereo(
232 struct dc *dc,
233 struct dc_state *context,
234 struct dc_stream_state *streams[],
235 uint8_t stream_count);
236
237
238enum surface_update_type dc_check_update_surfaces_for_stream(
239 struct dc *dc,
240 struct dc_surface_update *updates,
241 int surface_count,
242 struct dc_stream_update *stream_update,
243 const struct dc_stream_status *stream_status);
244
245/**
246 * Create a new default stream for the requested sink
247 */
248struct dc_stream_state *dc_create_stream_for_sink(struct dc_sink *dc_sink);
249
250void update_stream_signal(struct dc_stream_state *stream);
251
252void dc_stream_retain(struct dc_stream_state *dc_stream);
253void dc_stream_release(struct dc_stream_state *dc_stream);
254
255struct dc_stream_status *dc_stream_get_status(
256 struct dc_stream_state *dc_stream);
257
258/*******************************************************************************
259 * Cursor interfaces - To manages the cursor within a stream
260 ******************************************************************************/
261/* TODO: Deprecated once we switch to dc_set_cursor_position */
262bool dc_stream_set_cursor_attributes(
263 struct dc_stream_state *stream,
264 const struct dc_cursor_attributes *attributes);
265
266bool dc_stream_set_cursor_position(
267 struct dc_stream_state *stream,
268 const struct dc_cursor_position *position);
269
270bool dc_stream_adjust_vmin_vmax(struct dc *dc,
271 struct dc_stream_state **stream,
272 int num_streams,
273 int vmin,
274 int vmax);
275
276bool dc_stream_get_crtc_position(struct dc *dc,
277 struct dc_stream_state **stream,
278 int num_streams,
279 unsigned int *v_pos,
280 unsigned int *nom_v_pos);
281
282bool dc_stream_configure_crc(struct dc *dc,
283 struct dc_stream_state *stream,
284 bool enable,
285 bool continuous);
286
287bool dc_stream_get_crc(struct dc *dc,
288 struct dc_stream_state *stream,
289 uint32_t *r_cr,
290 uint32_t *g_y,
291 uint32_t *b_cb);
292
293void dc_stream_set_static_screen_events(struct dc *dc,
294 struct dc_stream_state **stream,
295 int num_streams,
296 const struct dc_static_screen_events *events);
297
298void dc_stream_set_dither_option(struct dc_stream_state *stream,
299 enum dc_dither_option option);
300
301
302bool dc_stream_adjust_vmin_vmax(struct dc *dc,
303 struct dc_stream_state **stream,
304 int num_streams,
305 int vmin,
306 int vmax);
307
308bool dc_stream_get_crtc_position(struct dc *dc,
309 struct dc_stream_state **stream,
310 int num_streams,
311 unsigned int *v_pos,
312 unsigned int *nom_v_pos);
313
314void dc_stream_set_static_screen_events(struct dc *dc,
315 struct dc_stream_state **stream,
316 int num_streams,
317 const struct dc_static_screen_events *events);
318
319#endif /* DC_STREAM_H_ */