1/* SPDX-License-Identifier: GPL-2.0-only */
 2/*
 3 * Ralink MT7621 specific CPU feature overrides
 4 *
 5 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
 6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
 7 * Copyright (C) 2015 Felix Fietkau <nbd@openwrt.org>
 8 *
 9 * This file was derived from: include/asm-mips/cpu-features.h
10 *	Copyright (C) 2003, 2004 Ralf Baechle
11 *	Copyright (C) 2004 Maciej W. Rozycki
 
 
 
 
 
12 */
13#ifndef _MT7621_CPU_FEATURE_OVERRIDES_H
14#define _MT7621_CPU_FEATURE_OVERRIDES_H
15
16#define cpu_has_tlb		1
17#define cpu_has_4kex		1
18#define cpu_has_3k_cache	0
19#define cpu_has_4k_cache	1
20#define cpu_has_tx39_cache	0
21#define cpu_has_sb1_cache	0
22#define cpu_has_fpu		0
23#define cpu_has_32fpr		0
24#define cpu_has_counter		1
25#define cpu_has_watch		1
26#define cpu_has_divec		1
27
28#define cpu_has_prefetch	1
29#define cpu_has_ejtag		1
30#define cpu_has_llsc		1
31
32#define cpu_has_mips16		1
33#define cpu_has_mdmx		0
34#define cpu_has_mips3d		0
35#define cpu_has_smartmips	0
36
37#define cpu_has_mips32r1	1
38#define cpu_has_mips32r2	1
39#define cpu_has_mips64r1	0
40#define cpu_has_mips64r2	0
41
42#define cpu_has_dsp		1
43#define cpu_has_dsp2		0
44#define cpu_has_mipsmt		1
45
46#define cpu_has_64bits		0
47#define cpu_has_64bit_zero_reg	0
48#define cpu_has_64bit_gp_regs	0
49#define cpu_has_64bit_addresses	0
50
51#define cpu_dcache_line_size()	32
52#define cpu_icache_line_size()	32
53
54#define cpu_has_dc_aliases	0
55#define cpu_has_vtag_icache	0
56
57#define cpu_has_rixi		0
58#define cpu_has_tlbinv		0
59#define cpu_has_userlocal	1
60
61#endif /* _MT7621_CPU_FEATURE_OVERRIDES_H */

 
 1/*
 2 * Ralink MT7621 specific CPU feature overrides
 3 *
 4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
 5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
 6 * Copyright (C) 2015 Felix Fietkau <nbd@openwrt.org>
 7 *
 8 * This file was derived from: include/asm-mips/cpu-features.h
 9 *	Copyright (C) 2003, 2004 Ralf Baechle
10 *	Copyright (C) 2004 Maciej W. Rozycki
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License version 2 as published
14 * by the Free Software Foundation.
15 *
16 */
17#ifndef _MT7621_CPU_FEATURE_OVERRIDES_H
18#define _MT7621_CPU_FEATURE_OVERRIDES_H
19
20#define cpu_has_tlb		1
21#define cpu_has_4kex		1
22#define cpu_has_3k_cache	0
23#define cpu_has_4k_cache	1
24#define cpu_has_tx39_cache	0
25#define cpu_has_sb1_cache	0
26#define cpu_has_fpu		0
27#define cpu_has_32fpr		0
28#define cpu_has_counter		1
29#define cpu_has_watch		1
30#define cpu_has_divec		1
31
32#define cpu_has_prefetch	1
33#define cpu_has_ejtag		1
34#define cpu_has_llsc		1
35
36#define cpu_has_mips16		1
37#define cpu_has_mdmx		0
38#define cpu_has_mips3d		0
39#define cpu_has_smartmips	0
40
41#define cpu_has_mips32r1	1
42#define cpu_has_mips32r2	1
43#define cpu_has_mips64r1	0
44#define cpu_has_mips64r2	0
45
46#define cpu_has_dsp		1
47#define cpu_has_dsp2		0
48#define cpu_has_mipsmt		1
49
50#define cpu_has_64bits		0
51#define cpu_has_64bit_zero_reg	0
52#define cpu_has_64bit_gp_regs	0
53#define cpu_has_64bit_addresses	0
54
55#define cpu_dcache_line_size()	32
56#define cpu_icache_line_size()	32
57
58#define cpu_has_dc_aliases	0
59#define cpu_has_vtag_icache	0
60
61#define cpu_has_rixi		0
62#define cpu_has_tlbinv		0
63#define cpu_has_userlocal	1
64
65#endif /* _MT7621_CPU_FEATURE_OVERRIDES_H */