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1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2
3#include <dt-bindings/gpio/gpio.h>
4#include <dt-bindings/interrupt-controller/irq.h>
5#include <dt-bindings/interrupt-controller/arm-gic.h>
6#include <dt-bindings/clock/rv1108-cru.h>
7#include <dt-bindings/pinctrl/rockchip.h>
8#include <dt-bindings/thermal/thermal.h>
9/ {
10 #address-cells = <1>;
11 #size-cells = <1>;
12
13 compatible = "rockchip,rv1108";
14
15 interrupt-parent = <&gic>;
16
17 aliases {
18 i2c0 = &i2c0;
19 i2c1 = &i2c1;
20 i2c2 = &i2c2;
21 i2c3 = &i2c3;
22 serial0 = &uart0;
23 serial1 = &uart1;
24 serial2 = &uart2;
25 };
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 cpu0: cpu@f00 {
32 device_type = "cpu";
33 compatible = "arm,cortex-a7";
34 reg = <0xf00>;
35 clock-latency = <40000>;
36 clocks = <&cru ARMCLK>;
37 #cooling-cells = <2>; /* min followed by max */
38 dynamic-power-coefficient = <75>;
39 operating-points-v2 = <&cpu_opp_table>;
40 };
41 };
42
43 cpu_opp_table: opp_table {
44 compatible = "operating-points-v2";
45
46 opp-408000000 {
47 opp-hz = /bits/ 64 <408000000>;
48 opp-microvolt = <975000>;
49 clock-latency-ns = <40000>;
50 };
51 opp-600000000 {
52 opp-hz = /bits/ 64 <600000000>;
53 opp-microvolt = <975000>;
54 clock-latency-ns = <40000>;
55 };
56 opp-816000000 {
57 opp-hz = /bits/ 64 <816000000>;
58 opp-microvolt = <1025000>;
59 clock-latency-ns = <40000>;
60 };
61 opp-1008000000 {
62 opp-hz = /bits/ 64 <1008000000>;
63 opp-microvolt = <1150000>;
64 clock-latency-ns = <40000>;
65 };
66 };
67
68 arm-pmu {
69 compatible = "arm,cortex-a7-pmu";
70 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
71 };
72
73 timer {
74 compatible = "arm,armv7-timer";
75 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
76 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
77 arm,cpu-registers-not-fw-configured;
78 clock-frequency = <24000000>;
79 };
80
81 xin24m: oscillator {
82 compatible = "fixed-clock";
83 clock-frequency = <24000000>;
84 clock-output-names = "xin24m";
85 #clock-cells = <0>;
86 };
87
88 amba {
89 compatible = "simple-bus";
90 #address-cells = <1>;
91 #size-cells = <1>;
92 ranges;
93
94 pdma: pdma@102a0000 {
95 compatible = "arm,pl330", "arm,primecell";
96 reg = <0x102a0000 0x4000>;
97 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
98 #dma-cells = <1>;
99 arm,pl330-broken-no-flushp;
100 clocks = <&cru ACLK_DMAC>;
101 clock-names = "apb_pclk";
102 };
103 };
104
105 bus_intmem@10080000 {
106 compatible = "mmio-sram";
107 reg = <0x10080000 0x2000>;
108 #address-cells = <1>;
109 #size-cells = <1>;
110 ranges = <0 0x10080000 0x2000>;
111 };
112
113 uart2: serial@10210000 {
114 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
115 reg = <0x10210000 0x100>;
116 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
117 reg-shift = <2>;
118 reg-io-width = <4>;
119 clock-frequency = <24000000>;
120 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
121 clock-names = "baudclk", "apb_pclk";
122 dmas = <&pdma 6>, <&pdma 7>;
123 #dma-cells = <2>;
124 pinctrl-names = "default";
125 pinctrl-0 = <&uart2m0_xfer>;
126 status = "disabled";
127 };
128
129 uart1: serial@10220000 {
130 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
131 reg = <0x10220000 0x100>;
132 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
133 reg-shift = <2>;
134 reg-io-width = <4>;
135 clock-frequency = <24000000>;
136 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
137 clock-names = "baudclk", "apb_pclk";
138 dmas = <&pdma 4>, <&pdma 5>;
139 #dma-cells = <2>;
140 pinctrl-names = "default";
141 pinctrl-0 = <&uart1_xfer>;
142 status = "disabled";
143 };
144
145 uart0: serial@10230000 {
146 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
147 reg = <0x10230000 0x100>;
148 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
149 reg-shift = <2>;
150 reg-io-width = <4>;
151 clock-frequency = <24000000>;
152 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
153 clock-names = "baudclk", "apb_pclk";
154 dmas = <&pdma 2>, <&pdma 3>;
155 #dma-cells = <2>;
156 pinctrl-names = "default";
157 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
158 status = "disabled";
159 };
160
161 i2c1: i2c@10240000 {
162 compatible = "rockchip,rv1108-i2c";
163 reg = <0x10240000 0x1000>;
164 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
165 #address-cells = <1>;
166 #size-cells = <0>;
167 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
168 clock-names = "i2c", "pclk";
169 pinctrl-names = "default";
170 pinctrl-0 = <&i2c1_xfer>;
171 rockchip,grf = <&grf>;
172 status = "disabled";
173 };
174
175 i2c2: i2c@10250000 {
176 compatible = "rockchip,rv1108-i2c";
177 reg = <0x10250000 0x1000>;
178 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
179 #address-cells = <1>;
180 #size-cells = <0>;
181 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
182 clock-names = "i2c", "pclk";
183 pinctrl-names = "default";
184 pinctrl-0 = <&i2c2m1_xfer>;
185 rockchip,grf = <&grf>;
186 status = "disabled";
187 };
188
189 i2c3: i2c@10260000 {
190 compatible = "rockchip,rv1108-i2c";
191 reg = <0x10260000 0x1000>;
192 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
193 #address-cells = <1>;
194 #size-cells = <0>;
195 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
196 clock-names = "i2c", "pclk";
197 pinctrl-names = "default";
198 pinctrl-0 = <&i2c3_xfer>;
199 rockchip,grf = <&grf>;
200 status = "disabled";
201 };
202
203 spi: spi@10270000 {
204 compatible = "rockchip,rv1108-spi";
205 reg = <0x10270000 0x1000>;
206 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
208 clock-names = "spiclk", "apb_pclk";
209 dmas = <&pdma 8>, <&pdma 9>;
210 dma-names = "tx", "rx";
211 #dma-cells = <2>;
212 #address-cells = <1>;
213 #size-cells = <0>;
214 status = "disabled";
215 };
216
217 pwm4: pwm@10280000 {
218 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
219 reg = <0x10280000 0x10>;
220 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
221 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
222 clock-names = "pwm", "pclk";
223 pinctrl-names = "default";
224 pinctrl-0 = <&pwm4_pin>;
225 #pwm-cells = <3>;
226 status = "disabled";
227 };
228
229 pwm5: pwm@10280010 {
230 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
231 reg = <0x10280010 0x10>;
232 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
234 clock-names = "pwm", "pclk";
235 pinctrl-names = "default";
236 pinctrl-0 = <&pwm5_pin>;
237 #pwm-cells = <3>;
238 status = "disabled";
239 };
240
241 pwm6: pwm@10280020 {
242 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
243 reg = <0x10280020 0x10>;
244 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
246 clock-names = "pwm", "pclk";
247 pinctrl-names = "default";
248 pinctrl-0 = <&pwm6_pin>;
249 #pwm-cells = <3>;
250 status = "disabled";
251 };
252
253 pwm7: pwm@10280030 {
254 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
255 reg = <0x10280030 0x10>;
256 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
257 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
258 clock-names = "pwm", "pclk";
259 pinctrl-names = "default";
260 pinctrl-0 = <&pwm7_pin>;
261 #pwm-cells = <3>;
262 status = "disabled";
263 };
264
265 grf: syscon@10300000 {
266 compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
267 reg = <0x10300000 0x1000>;
268 #address-cells = <1>;
269 #size-cells = <1>;
270
271 u2phy: usb2-phy@100 {
272 compatible = "rockchip,rv1108-usb2phy";
273 reg = <0x100 0x0c>;
274 clocks = <&cru SCLK_USBPHY>;
275 clock-names = "phyclk";
276 #clock-cells = <0>;
277 clock-output-names = "usbphy";
278 rockchip,usbgrf = <&usbgrf>;
279 status = "disabled";
280
281 u2phy_otg: otg-port {
282 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
283 interrupt-names = "otg-mux";
284 #phy-cells = <0>;
285 status = "disabled";
286 };
287
288 u2phy_host: host-port {
289 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
290 interrupt-names = "linestate";
291 #phy-cells = <0>;
292 status = "disabled";
293 };
294 };
295 };
296
297 timer: timer@10350000 {
298 compatible = "rockchip,rv1108-timer", "rockchip,rk3288-timer";
299 reg = <0x10350000 0x20>;
300 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
301 clocks = <&xin24m>, <&cru PCLK_TIMER>;
302 clock-names = "timer", "pclk";
303 };
304
305 watchdog: wdt@10360000 {
306 compatible = "snps,dw-wdt";
307 reg = <0x10360000 0x100>;
308 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&cru PCLK_WDT>;
310 clock-names = "pclk_wdt";
311 status = "disabled";
312 };
313
314 thermal-zones {
315 soc_thermal: soc-thermal {
316 polling-delay-passive = <20>;
317 polling-delay = <1000>;
318 sustainable-power = <50>;
319 thermal-sensors = <&tsadc 0>;
320
321 trips {
322 threshold: trip-point0 {
323 temperature = <70000>;
324 hysteresis = <2000>;
325 type = "passive";
326 };
327 target: trip-point1 {
328 temperature = <85000>;
329 hysteresis = <2000>;
330 type = "passive";
331 };
332 soc_crit: soc-crit {
333 temperature = <95000>;
334 hysteresis = <2000>;
335 type = "critical";
336 };
337 };
338
339 cooling-maps {
340 map0 {
341 trip = <&target>;
342 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
343 contribution = <4096>;
344 };
345 };
346 };
347 };
348
349 tsadc: tsadc@10370000 {
350 compatible = "rockchip,rv1108-tsadc";
351 reg = <0x10370000 0x100>;
352 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
353 assigned-clocks = <&cru SCLK_TSADC>;
354 assigned-clock-rates = <750000>;
355 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
356 clock-names = "tsadc", "apb_pclk";
357 pinctrl-names = "init", "default", "sleep";
358 pinctrl-0 = <&otp_gpio>;
359 pinctrl-1 = <&otp_out>;
360 pinctrl-2 = <&otp_gpio>;
361 resets = <&cru SRST_TSADC>;
362 reset-names = "tsadc-apb";
363 rockchip,hw-tshut-temp = <120000>;
364 #thermal-sensor-cells = <1>;
365 status = "disabled";
366 };
367
368 adc: adc@1038c000 {
369 compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
370 reg = <0x1038c000 0x100>;
371 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
372 #io-channel-cells = <1>;
373 clock-frequency = <1000000>;
374 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
375 clock-names = "saradc", "apb_pclk";
376 status = "disabled";
377 };
378
379 i2c0: i2c@20000000 {
380 compatible = "rockchip,rv1108-i2c";
381 reg = <0x20000000 0x1000>;
382 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
383 #address-cells = <1>;
384 #size-cells = <0>;
385 clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>;
386 clock-names = "i2c", "pclk";
387 pinctrl-names = "default";
388 pinctrl-0 = <&i2c0_xfer>;
389 rockchip,grf = <&grf>;
390 status = "disabled";
391 };
392
393 pwm0: pwm@20040000 {
394 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
395 reg = <0x20040000 0x10>;
396 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
397 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
398 clock-names = "pwm", "pclk";
399 pinctrl-names = "default";
400 pinctrl-0 = <&pwm0_pin>;
401 #pwm-cells = <3>;
402 status = "disabled";
403 };
404
405 pwm1: pwm@20040010 {
406 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
407 reg = <0x20040010 0x10>;
408 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
409 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
410 clock-names = "pwm", "pclk";
411 pinctrl-names = "default";
412 pinctrl-0 = <&pwm1_pin>;
413 #pwm-cells = <3>;
414 status = "disabled";
415 };
416
417 pwm2: pwm@20040020 {
418 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
419 reg = <0x20040020 0x10>;
420 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
422 clock-names = "pwm", "pclk";
423 pinctrl-names = "default";
424 pinctrl-0 = <&pwm2_pin>;
425 #pwm-cells = <3>;
426 status = "disabled";
427 };
428
429 pwm3: pwm@20040030 {
430 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
431 reg = <0x20040030 0x10>;
432 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
433 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
434 clock-names = "pwm", "pclk";
435 pinctrl-names = "default";
436 pinctrl-0 = <&pwm3_pin>;
437 #pwm-cells = <3>;
438 status = "disabled";
439 };
440
441 pmugrf: syscon@20060000 {
442 compatible = "rockchip,rv1108-pmugrf", "syscon";
443 reg = <0x20060000 0x1000>;
444 };
445
446 usbgrf: syscon@202a0000 {
447 compatible = "rockchip,rv1108-usbgrf", "syscon";
448 reg = <0x202a0000 0x1000>;
449 };
450
451 cru: clock-controller@20200000 {
452 compatible = "rockchip,rv1108-cru";
453 reg = <0x20200000 0x1000>;
454 rockchip,grf = <&grf>;
455 #clock-cells = <1>;
456 #reset-cells = <1>;
457 };
458
459 emmc: dwmmc@30110000 {
460 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
461 reg = <0x30110000 0x4000>;
462 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
464 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
465 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
466 fifo-depth = <0x100>;
467 max-frequency = <150000000>;
468 status = "disabled";
469 };
470
471 sdio: dwmmc@30120000 {
472 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
473 reg = <0x30120000 0x4000>;
474 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
475 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
476 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
477 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
478 fifo-depth = <0x100>;
479 max-frequency = <150000000>;
480 status = "disabled";
481 };
482
483 sdmmc: dwmmc@30130000 {
484 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
485 reg = <0x30130000 0x4000>;
486 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
487 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
488 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
489 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
490 fifo-depth = <0x100>;
491 max-frequency = <100000000>;
492 pinctrl-names = "default";
493 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
494 status = "disabled";
495 };
496
497 usb_host_ehci: usb@30140000 {
498 compatible = "generic-ehci";
499 reg = <0x30140000 0x20000>;
500 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
501 clocks = <&cru HCLK_HOST0>, <&u2phy>;
502 clock-names = "usbhost", "utmi";
503 phys = <&u2phy_host>;
504 phy-names = "usb";
505 status = "disabled";
506 };
507
508 usb_host_ohci: usb@30160000 {
509 compatible = "generic-ohci";
510 reg = <0x30160000 0x20000>;
511 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
512 clocks = <&cru HCLK_HOST0>, <&u2phy>;
513 clock-names = "usbhost", "utmi";
514 phys = <&u2phy_host>;
515 phy-names = "usb";
516 status = "disabled";
517 };
518
519 usb_otg: usb@30180000 {
520 compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
521 "snps,dwc2";
522 reg = <0x30180000 0x40000>;
523 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
524 clocks = <&cru HCLK_OTG>;
525 clock-names = "otg";
526 dr_mode = "otg";
527 g-np-tx-fifo-size = <16>;
528 g-rx-fifo-size = <280>;
529 g-tx-fifo-size = <256 128 128 64 32 16>;
530 g-use-dma;
531 phys = <&u2phy_otg>;
532 phy-names = "usb2-phy";
533 status = "disabled";
534 };
535
536 gmac: eth@30200000 {
537 compatible = "rockchip,rv1108-gmac";
538 reg = <0x30200000 0x10000>;
539 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
540 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
541 interrupt-names = "macirq", "eth_wake_irq";
542 clocks = <&cru SCLK_MAC>,
543 <&cru SCLK_MAC_RX>, <&cru SCLK_MAC_RX>,
544 <&cru SCLK_MAC_REF>, <&cru SCLK_MAC_REFOUT>,
545 <&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
546 clock-names = "stmmaceth",
547 "mac_clk_rx", "mac_clk_tx",
548 "clk_mac_ref", "clk_mac_refout",
549 "aclk_mac", "pclk_mac";
550 /* rv1108 only supports an rmii interface */
551 phy-mode = "rmii";
552 pinctrl-names = "default";
553 pinctrl-0 = <&rmii_pins>;
554 rockchip,grf = <&grf>;
555 status = "disabled";
556 };
557
558 gic: interrupt-controller@32010000 {
559 compatible = "arm,gic-400";
560 interrupt-controller;
561 #interrupt-cells = <3>;
562 #address-cells = <0>;
563
564 reg = <0x32011000 0x1000>,
565 <0x32012000 0x2000>,
566 <0x32014000 0x2000>,
567 <0x32016000 0x2000>;
568 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
569 };
570
571 pinctrl: pinctrl {
572 compatible = "rockchip,rv1108-pinctrl";
573 rockchip,grf = <&grf>;
574 rockchip,pmu = <&pmugrf>;
575 #address-cells = <1>;
576 #size-cells = <1>;
577 ranges;
578
579 gpio0: gpio0@20030000 {
580 compatible = "rockchip,gpio-bank";
581 reg = <0x20030000 0x100>;
582 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
583 clocks = <&cru PCLK_GPIO0_PMU>;
584
585 gpio-controller;
586 #gpio-cells = <2>;
587
588 interrupt-controller;
589 #interrupt-cells = <2>;
590 };
591
592 gpio1: gpio1@10310000 {
593 compatible = "rockchip,gpio-bank";
594 reg = <0x10310000 0x100>;
595 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
596 clocks = <&cru PCLK_GPIO1>;
597
598 gpio-controller;
599 #gpio-cells = <2>;
600
601 interrupt-controller;
602 #interrupt-cells = <2>;
603 };
604
605 gpio2: gpio2@10320000 {
606 compatible = "rockchip,gpio-bank";
607 reg = <0x10320000 0x100>;
608 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
609 clocks = <&cru PCLK_GPIO2>;
610
611 gpio-controller;
612 #gpio-cells = <2>;
613
614 interrupt-controller;
615 #interrupt-cells = <2>;
616 };
617
618 gpio3: gpio3@10330000 {
619 compatible = "rockchip,gpio-bank";
620 reg = <0x10330000 0x100>;
621 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
622 clocks = <&cru PCLK_GPIO3>;
623
624 gpio-controller;
625 #gpio-cells = <2>;
626
627 interrupt-controller;
628 #interrupt-cells = <2>;
629 };
630
631 pcfg_pull_up: pcfg-pull-up {
632 bias-pull-up;
633 };
634
635 pcfg_pull_down: pcfg-pull-down {
636 bias-pull-down;
637 };
638
639 pcfg_pull_none: pcfg-pull-none {
640 bias-disable;
641 };
642
643 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
644 drive-strength = <8>;
645 };
646
647 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
648 drive-strength = <12>;
649 };
650
651 pcfg_pull_none_smt: pcfg-pull-none-smt {
652 bias-disable;
653 input-schmitt-enable;
654 };
655
656 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
657 bias-pull-up;
658 drive-strength = <8>;
659 };
660
661 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
662 drive-strength = <4>;
663 };
664
665 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
666 bias-pull-up;
667 drive-strength = <4>;
668 };
669
670 pcfg_output_high: pcfg-output-high {
671 output-high;
672 };
673
674 pcfg_output_low: pcfg-output-low {
675 output-low;
676 };
677
678 pcfg_input_high: pcfg-input-high {
679 bias-pull-up;
680 input-enable;
681 };
682
683 emmc {
684 emmc_bus8: emmc-bus8 {
685 rockchip,pins = <2 RK_PA0 2 &pcfg_pull_up_drv_8ma>,
686 <2 RK_PA1 2 &pcfg_pull_up_drv_8ma>,
687 <2 RK_PA2 2 &pcfg_pull_up_drv_8ma>,
688 <2 RK_PA3 2 &pcfg_pull_up_drv_8ma>,
689 <2 RK_PA4 2 &pcfg_pull_up_drv_8ma>,
690 <2 RK_PA5 2 &pcfg_pull_up_drv_8ma>,
691 <2 RK_PA6 2 &pcfg_pull_up_drv_8ma>,
692 <2 RK_PA7 2 &pcfg_pull_up_drv_8ma>;
693 };
694
695 emmc_clk: emmc-clk {
696 rockchip,pins = <2 RK_PB6 1 &pcfg_pull_none_drv_8ma>;
697 };
698
699 emmc_cmd: emmc-cmd {
700 rockchip,pins = <2 RK_PB4 2 &pcfg_pull_up_drv_8ma>;
701 };
702 };
703
704 gmac {
705 rmii_pins: rmii-pins {
706 rockchip,pins = <1 RK_PC5 2 &pcfg_pull_none>,
707 <1 RK_PC3 2 &pcfg_pull_none>,
708 <1 RK_PC4 2 &pcfg_pull_none>,
709 <1 RK_PB2 3 &pcfg_pull_none_drv_12ma>,
710 <1 RK_PB3 3 &pcfg_pull_none_drv_12ma>,
711 <1 RK_PB4 3 &pcfg_pull_none_drv_12ma>,
712 <1 RK_PB5 3 &pcfg_pull_none>,
713 <1 RK_PB6 3 &pcfg_pull_none>,
714 <1 RK_PB7 3 &pcfg_pull_none>,
715 <1 RK_PC2 3 &pcfg_pull_none>;
716 };
717 };
718
719 i2c0 {
720 i2c0_xfer: i2c0-xfer {
721 rockchip,pins = <0 RK_PB1 1 &pcfg_pull_none_smt>,
722 <0 RK_PB2 1 &pcfg_pull_none_smt>;
723 };
724 };
725
726 i2c1 {
727 i2c1_xfer: i2c1-xfer {
728 rockchip,pins = <2 RK_PD3 1 &pcfg_pull_up>,
729 <2 RK_PD4 1 &pcfg_pull_up>;
730 };
731 };
732
733 i2c2m1 {
734 i2c2m1_xfer: i2c2m1-xfer {
735 rockchip,pins = <0 RK_PC2 2 &pcfg_pull_none>,
736 <0 RK_PC6 3 &pcfg_pull_none>;
737 };
738
739 i2c2m1_gpio: i2c2m1-gpio {
740 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
741 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
742 };
743 };
744
745 i2c2m05v {
746 i2c2m05v_xfer: i2c2m05v-xfer {
747 rockchip,pins = <1 RK_PD5 2 &pcfg_pull_none>,
748 <1 RK_PD4 2 &pcfg_pull_none>;
749 };
750
751 i2c2m05v_gpio: i2c2m05v-gpio {
752 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
753 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
754 };
755 };
756
757 i2c3 {
758 i2c3_xfer: i2c3-xfer {
759 rockchip,pins = <0 RK_PB6 1 &pcfg_pull_none>,
760 <0 RK_PC4 2 &pcfg_pull_none>;
761 };
762 };
763
764 pwm0 {
765 pwm0_pin: pwm0-pin {
766 rockchip,pins = <0 RK_PC5 1 &pcfg_pull_none>;
767 };
768 };
769
770 pwm1 {
771 pwm1_pin: pwm1-pin {
772 rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>;
773 };
774 };
775
776 pwm2 {
777 pwm2_pin: pwm2-pin {
778 rockchip,pins = <0 RK_PC6 1 &pcfg_pull_none>;
779 };
780 };
781
782 pwm3 {
783 pwm3_pin: pwm3-pin {
784 rockchip,pins = <0 RK_PC0 1 &pcfg_pull_none>;
785 };
786 };
787
788 pwm4 {
789 pwm4_pin: pwm4-pin {
790 rockchip,pins = <1 RK_PC1 3 &pcfg_pull_none>;
791 };
792 };
793
794 pwm5 {
795 pwm5_pin: pwm5-pin {
796 rockchip,pins = <1 RK_PA7 2 &pcfg_pull_none>;
797 };
798 };
799
800 pwm6 {
801 pwm6_pin: pwm6-pin {
802 rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>;
803 };
804 };
805
806 pwm7 {
807 pwm7_pin: pwm7-pin {
808 rockchip,pins = <1 RK_PB1 2 &pcfg_pull_none>;
809 };
810 };
811
812 sdmmc {
813 sdmmc_clk: sdmmc-clk {
814 rockchip,pins = <3 RK_PC4 1 &pcfg_pull_none_drv_4ma>;
815 };
816
817 sdmmc_cmd: sdmmc-cmd {
818 rockchip,pins = <3 RK_PC5 1 &pcfg_pull_up_drv_4ma>;
819 };
820
821 sdmmc_cd: sdmmc-cd {
822 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_up_drv_4ma>;
823 };
824
825 sdmmc_bus1: sdmmc-bus1 {
826 rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>;
827 };
828
829 sdmmc_bus4: sdmmc-bus4 {
830 rockchip,pins = <3 RK_PC3 1 &pcfg_pull_up_drv_4ma>,
831 <3 RK_PC2 1 &pcfg_pull_up_drv_4ma>,
832 <3 RK_PC1 1 &pcfg_pull_up_drv_4ma>,
833 <3 RK_PC0 1 &pcfg_pull_up_drv_4ma>;
834 };
835 };
836
837 spim0 {
838 spim0_clk: spim0-clk {
839 rockchip,pins = <1 RK_PD0 2 &pcfg_pull_up>;
840 };
841
842 spim0_cs0: spim0-cs0 {
843 rockchip,pins = <1 RK_PD1 2 &pcfg_pull_up>;
844 };
845
846 spim0_tx: spim0-tx {
847 rockchip,pins = <1 RK_PD3 2 &pcfg_pull_up>;
848 };
849
850 spim0_rx: spim0-rx {
851 rockchip,pins = <1 RK_PD2 2 &pcfg_pull_up>;
852 };
853 };
854
855 spim1 {
856 spim1_clk: spim1-clk {
857 rockchip,pins = <0 RK_PA3 1 &pcfg_pull_up>;
858 };
859
860 spim1_cs0: spim1-cs0 {
861 rockchip,pins = <0 RK_PA4 1 &pcfg_pull_up>;
862 };
863
864 spim1_rx: spim1-rx {
865 rockchip,pins = <0 RK_PB0 1 &pcfg_pull_up>;
866 };
867
868 spim1_tx: spim1-tx {
869 rockchip,pins = <0 RK_PA7 1 &pcfg_pull_up>;
870 };
871 };
872
873 tsadc {
874 otp_out: otp-out {
875 rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>;
876 };
877
878 otp_gpio: otp-gpio {
879 rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
880 };
881 };
882
883 uart0 {
884 uart0_xfer: uart0-xfer {
885 rockchip,pins = <3 RK_PA6 1 &pcfg_pull_up>,
886 <3 RK_PA5 1 &pcfg_pull_none>;
887 };
888
889 uart0_cts: uart0-cts {
890 rockchip,pins = <3 RK_PA4 1 &pcfg_pull_none>;
891 };
892
893 uart0_rts: uart0-rts {
894 rockchip,pins = <3 RK_PA3 1 &pcfg_pull_none>;
895 };
896
897 uart0_rts_gpio: uart0-rts-gpio {
898 rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
899 };
900 };
901
902 uart1 {
903 uart1_xfer: uart1-xfer {
904 rockchip,pins = <1 RK_PD3 1 &pcfg_pull_up>,
905 <1 RK_PD2 1 &pcfg_pull_none>;
906 };
907
908 uart1_cts: uart1-cts {
909 rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
910 };
911
912 uart1_rts: uart1-rts {
913 rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
914 };
915 };
916
917 uart2m0 {
918 uart2m0_xfer: uart2m0-xfer {
919 rockchip,pins = <2 RK_PD2 1 &pcfg_pull_up>,
920 <2 RK_PD1 1 &pcfg_pull_none>;
921 };
922 };
923
924 uart2m1 {
925 uart2m1_xfer: uart2m1-xfer {
926 rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up>,
927 <3 RK_PC2 2 &pcfg_pull_none>;
928 };
929 };
930
931 uart2_5v {
932 uart2_5v_cts: uart2_5v-cts {
933 rockchip,pins = <1 RK_PD4 1 &pcfg_pull_none>;
934 };
935
936 uart2_5v_rts: uart2_5v-rts {
937 rockchip,pins = <1 RK_PD5 1 &pcfg_pull_none>;
938 };
939 };
940 };
941};
1/*
2 * This file is dual-licensed: you can use it either under the terms
3 * of the GPL or the X11 license, at your option. Note that this dual
4 * licensing only applies to this file, and not this project as a
5 * whole.
6 *
7 * a) This file is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or (at your option) any later version.
11 *
12 * This file is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * Or, alternatively,
18 *
19 * b) Permission is hereby granted, free of charge, to any person
20 * obtaining a copy of this software and associated documentation
21 * files (the "Software"), to deal in the Software without
22 * restriction, including without limitation the rights to use,
23 * copy, modify, merge, publish, distribute, sublicense, and/or
24 * sell copies of the Software, and to permit persons to whom the
25 * Software is furnished to do so, subject to the following
26 * conditions:
27 *
28 * The above copyright notice and this permission notice shall be
29 * included in all copies or substantial portions of the Software.
30 *
31 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
33 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
35 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
36 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
37 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
38 * OTHER DEALINGS IN THE SOFTWARE.
39 */
40
41#include <dt-bindings/gpio/gpio.h>
42#include <dt-bindings/interrupt-controller/irq.h>
43#include <dt-bindings/interrupt-controller/arm-gic.h>
44#include <dt-bindings/clock/rv1108-cru.h>
45#include <dt-bindings/pinctrl/rockchip.h>
46#include <dt-bindings/thermal/thermal.h>
47/ {
48 #address-cells = <1>;
49 #size-cells = <1>;
50
51 compatible = "rockchip,rv1108";
52
53 interrupt-parent = <&gic>;
54
55 aliases {
56 i2c0 = &i2c0;
57 i2c1 = &i2c1;
58 i2c2 = &i2c2;
59 i2c3 = &i2c3;
60 serial0 = &uart0;
61 serial1 = &uart1;
62 serial2 = &uart2;
63 };
64
65 cpus {
66 #address-cells = <1>;
67 #size-cells = <0>;
68
69 cpu0: cpu@f00 {
70 device_type = "cpu";
71 compatible = "arm,cortex-a7";
72 reg = <0xf00>;
73 clocks = <&cru ARMCLK>;
74 #cooling-cells = <2>; /* min followed by max */
75 dynamic-power-coefficient = <75>;
76 operating-points-v2 = <&cpu_opp_table>;
77 };
78 };
79
80 cpu_opp_table: opp_table {
81 compatible = "operating-points-v2";
82
83 opp-408000000 {
84 opp-hz = /bits/ 64 <408000000>;
85 opp-microvolt = <975000>;
86 clock-latency-ns = <40000>;
87 };
88 opp-600000000 {
89 opp-hz = /bits/ 64 <600000000>;
90 opp-microvolt = <975000>;
91 clock-latency-ns = <40000>;
92 };
93 opp-816000000 {
94 opp-hz = /bits/ 64 <816000000>;
95 opp-microvolt = <1025000>;
96 clock-latency-ns = <40000>;
97 };
98 opp-1008000000 {
99 opp-hz = /bits/ 64 <1008000000>;
100 opp-microvolt = <1150000>;
101 clock-latency-ns = <40000>;
102 };
103 };
104
105 arm-pmu {
106 compatible = "arm,cortex-a7-pmu";
107 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
108 };
109
110 timer {
111 compatible = "arm,armv7-timer";
112 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>,
113 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
114 clock-frequency = <24000000>;
115 };
116
117 xin24m: oscillator {
118 compatible = "fixed-clock";
119 clock-frequency = <24000000>;
120 clock-output-names = "xin24m";
121 #clock-cells = <0>;
122 };
123
124 amba {
125 compatible = "simple-bus";
126 #address-cells = <1>;
127 #size-cells = <1>;
128 ranges;
129
130 pdma: pdma@102a0000 {
131 compatible = "arm,pl330", "arm,primecell";
132 reg = <0x102a0000 0x4000>;
133 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
134 #dma-cells = <1>;
135 arm,pl330-broken-no-flushp;
136 clocks = <&cru ACLK_DMAC>;
137 clock-names = "apb_pclk";
138 };
139 };
140
141 bus_intmem@10080000 {
142 compatible = "mmio-sram";
143 reg = <0x10080000 0x2000>;
144 #address-cells = <1>;
145 #size-cells = <1>;
146 ranges = <0 0x10080000 0x2000>;
147 };
148
149 uart2: serial@10210000 {
150 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
151 reg = <0x10210000 0x100>;
152 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
153 reg-shift = <2>;
154 reg-io-width = <4>;
155 clock-frequency = <24000000>;
156 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
157 clock-names = "baudclk", "apb_pclk";
158 pinctrl-names = "default";
159 pinctrl-0 = <&uart2m0_xfer>;
160 status = "disabled";
161 };
162
163 uart1: serial@10220000 {
164 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
165 reg = <0x10220000 0x100>;
166 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
167 reg-shift = <2>;
168 reg-io-width = <4>;
169 clock-frequency = <24000000>;
170 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
171 clock-names = "baudclk", "apb_pclk";
172 pinctrl-names = "default";
173 pinctrl-0 = <&uart1_xfer>;
174 status = "disabled";
175 };
176
177 uart0: serial@10230000 {
178 compatible = "rockchip,rv1108-uart", "snps,dw-apb-uart";
179 reg = <0x10230000 0x100>;
180 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
181 reg-shift = <2>;
182 reg-io-width = <4>;
183 clock-frequency = <24000000>;
184 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
185 clock-names = "baudclk", "apb_pclk";
186 pinctrl-names = "default";
187 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
188 status = "disabled";
189 };
190
191 i2c1: i2c@10240000 {
192 compatible = "rockchip,rv1108-i2c";
193 reg = <0x10240000 0x1000>;
194 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
195 #address-cells = <1>;
196 #size-cells = <0>;
197 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
198 clock-names = "i2c", "pclk";
199 pinctrl-names = "default";
200 pinctrl-0 = <&i2c1_xfer>;
201 rockchip,grf = <&grf>;
202 status = "disabled";
203 };
204
205 i2c2: i2c@10250000 {
206 compatible = "rockchip,rv1108-i2c";
207 reg = <0x10250000 0x1000>;
208 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
209 #address-cells = <1>;
210 #size-cells = <0>;
211 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
212 clock-names = "i2c", "pclk";
213 pinctrl-names = "default";
214 pinctrl-0 = <&i2c2m1_xfer>;
215 rockchip,grf = <&grf>;
216 status = "disabled";
217 };
218
219 i2c3: i2c@10260000 {
220 compatible = "rockchip,rv1108-i2c";
221 reg = <0x10260000 0x1000>;
222 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
223 #address-cells = <1>;
224 #size-cells = <0>;
225 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
226 clock-names = "i2c", "pclk";
227 pinctrl-names = "default";
228 pinctrl-0 = <&i2c3_xfer>;
229 rockchip,grf = <&grf>;
230 status = "disabled";
231 };
232
233 spi: spi@10270000 {
234 compatible = "rockchip,rv1108-spi";
235 reg = <0x10270000 0x1000>;
236 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
238 clock-names = "spiclk", "apb_pclk";
239 dmas = <&pdma 8>, <&pdma 9>;
240 #dma-cells = <2>;
241 #address-cells = <1>;
242 #size-cells = <0>;
243 status = "disabled";
244 };
245
246 pwm4: pwm@10280000 {
247 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
248 reg = <0x10280000 0x10>;
249 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
250 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
251 clock-names = "pwm", "pclk";
252 pinctrl-names = "default";
253 pinctrl-0 = <&pwm4_pin>;
254 #pwm-cells = <3>;
255 status = "disabled";
256 };
257
258 pwm5: pwm@10280010 {
259 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
260 reg = <0x10280010 0x10>;
261 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
262 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
263 clock-names = "pwm", "pclk";
264 pinctrl-names = "default";
265 pinctrl-0 = <&pwm5_pin>;
266 #pwm-cells = <3>;
267 status = "disabled";
268 };
269
270 pwm6: pwm@10280020 {
271 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
272 reg = <0x10280020 0x10>;
273 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
274 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
275 clock-names = "pwm", "pclk";
276 pinctrl-names = "default";
277 pinctrl-0 = <&pwm6_pin>;
278 #pwm-cells = <3>;
279 status = "disabled";
280 };
281
282 pwm7: pwm@10280030 {
283 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
284 reg = <0x10280030 0x10>;
285 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
287 clock-names = "pwm", "pclk";
288 pinctrl-names = "default";
289 pinctrl-0 = <&pwm7_pin>;
290 #pwm-cells = <3>;
291 status = "disabled";
292 };
293
294 grf: syscon@10300000 {
295 compatible = "rockchip,rv1108-grf", "syscon", "simple-mfd";
296 reg = <0x10300000 0x1000>;
297 #address-cells = <1>;
298 #size-cells = <1>;
299
300 u2phy: usb2-phy@100 {
301 compatible = "rockchip,rv1108-usb2phy";
302 reg = <0x100 0x0c>;
303 clocks = <&cru SCLK_USBPHY>;
304 clock-names = "phyclk";
305 #clock-cells = <0>;
306 clock-output-names = "usbphy";
307 rockchip,usbgrf = <&usbgrf>;
308 status = "disabled";
309
310 u2phy_otg: otg-port {
311 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
312 interrupt-names = "otg-mux";
313 #phy-cells = <0>;
314 status = "disabled";
315 };
316
317 u2phy_host: host-port {
318 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
319 interrupt-names = "linestate";
320 #phy-cells = <0>;
321 status = "disabled";
322 };
323 };
324 };
325
326 watchdog: wdt@10360000 {
327 compatible = "snps,dw-wdt";
328 reg = <0x10360000 0x100>;
329 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&cru PCLK_WDT>;
331 clock-names = "pclk_wdt";
332 status = "disabled";
333 };
334
335 thermal-zones {
336 soc_thermal: soc-thermal {
337 polling-delay-passive = <20>;
338 polling-delay = <1000>;
339 sustainable-power = <50>;
340 thermal-sensors = <&tsadc 0>;
341
342 trips {
343 threshold: trip-point0 {
344 temperature = <70000>;
345 hysteresis = <2000>;
346 type = "passive";
347 };
348 target: trip-point1 {
349 temperature = <85000>;
350 hysteresis = <2000>;
351 type = "passive";
352 };
353 soc_crit: soc-crit {
354 temperature = <95000>;
355 hysteresis = <2000>;
356 type = "critical";
357 };
358 };
359
360 cooling-maps {
361 map0 {
362 trip = <&target>;
363 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
364 contribution = <4096>;
365 };
366 };
367 };
368 };
369
370 tsadc: tsadc@10370000 {
371 compatible = "rockchip,rv1108-tsadc";
372 reg = <0x10370000 0x100>;
373 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
374 assigned-clocks = <&cru SCLK_TSADC>;
375 assigned-clock-rates = <750000>;
376 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
377 clock-names = "tsadc", "apb_pclk";
378 pinctrl-names = "init", "default", "sleep";
379 pinctrl-0 = <&otp_gpio>;
380 pinctrl-1 = <&otp_out>;
381 pinctrl-2 = <&otp_gpio>;
382 resets = <&cru SRST_TSADC>;
383 reset-names = "tsadc-apb";
384 rockchip,hw-tshut-temp = <120000>;
385 #thermal-sensor-cells = <1>;
386 status = "disabled";
387 };
388
389 adc: adc@1038c000 {
390 compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
391 reg = <0x1038c000 0x100>;
392 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
393 #io-channel-cells = <1>;
394 clock-frequency = <1000000>;
395 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
396 clock-names = "saradc", "apb_pclk";
397 status = "disabled";
398 };
399
400 i2c0: i2c@20000000 {
401 compatible = "rockchip,rv1108-i2c";
402 reg = <0x20000000 0x1000>;
403 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
404 #address-cells = <1>;
405 #size-cells = <0>;
406 clocks = <&cru SCLK_I2C0_PMU>, <&cru PCLK_I2C0_PMU>;
407 clock-names = "i2c", "pclk";
408 pinctrl-names = "default";
409 pinctrl-0 = <&i2c0_xfer>;
410 rockchip,grf = <&grf>;
411 status = "disabled";
412 };
413
414 pwm0: pwm@20040000 {
415 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
416 reg = <0x20040000 0x10>;
417 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
418 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
419 clock-names = "pwm", "pclk";
420 pinctrl-names = "default";
421 pinctrl-0 = <&pwm0_pin>;
422 #pwm-cells = <3>;
423 status = "disabled";
424 };
425
426 pwm1: pwm@20040010 {
427 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
428 reg = <0x20040010 0x10>;
429 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
431 clock-names = "pwm", "pclk";
432 pinctrl-names = "default";
433 pinctrl-0 = <&pwm1_pin>;
434 #pwm-cells = <3>;
435 status = "disabled";
436 };
437
438 pwm2: pwm@20040020 {
439 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
440 reg = <0x20040020 0x10>;
441 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
442 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
443 clock-names = "pwm", "pclk";
444 pinctrl-names = "default";
445 pinctrl-0 = <&pwm2_pin>;
446 #pwm-cells = <3>;
447 status = "disabled";
448 };
449
450 pwm3: pwm@20040030 {
451 compatible = "rockchip,rv1108-pwm", "rockchip,rk3288-pwm";
452 reg = <0x20040030 0x10>;
453 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
454 clocks = <&cru SCLK_PWM0_PMU>, <&cru PCLK_PWM0_PMU>;
455 clock-names = "pwm", "pclk";
456 pinctrl-names = "default";
457 pinctrl-0 = <&pwm3_pin>;
458 #pwm-cells = <3>;
459 status = "disabled";
460 };
461
462 pmugrf: syscon@20060000 {
463 compatible = "rockchip,rv1108-pmugrf", "syscon";
464 reg = <0x20060000 0x1000>;
465 };
466
467 usbgrf: syscon@202a0000 {
468 compatible = "rockchip,rv1108-usbgrf", "syscon";
469 reg = <0x202a0000 0x1000>;
470 };
471
472 cru: clock-controller@20200000 {
473 compatible = "rockchip,rv1108-cru";
474 reg = <0x20200000 0x1000>;
475 rockchip,grf = <&grf>;
476 #clock-cells = <1>;
477 #reset-cells = <1>;
478 };
479
480 emmc: dwmmc@30110000 {
481 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
482 reg = <0x30110000 0x4000>;
483 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
484 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
485 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
486 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
487 fifo-depth = <0x100>;
488 max-frequency = <150000000>;
489 status = "disabled";
490 };
491
492 sdio: dwmmc@30120000 {
493 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
494 reg = <0x30120000 0x4000>;
495 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
497 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
498 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
499 fifo-depth = <0x100>;
500 max-frequency = <150000000>;
501 status = "disabled";
502 };
503
504 sdmmc: dwmmc@30130000 {
505 compatible = "rockchip,rv1108-dw-mshc", "rockchip,rk3288-dw-mshc";
506 reg = <0x30130000 0x4000>;
507 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
509 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
510 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
511 fifo-depth = <0x100>;
512 max-frequency = <100000000>;
513 pinctrl-names = "default";
514 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd &sdmmc_bus4>;
515 status = "disabled";
516 };
517
518 usb_host_ehci: usb@30140000 {
519 compatible = "generic-ehci";
520 reg = <0x30140000 0x20000>;
521 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
522 clocks = <&cru HCLK_HOST0>, <&u2phy>;
523 clock-names = "usbhost", "utmi";
524 phys = <&u2phy_host>;
525 phy-names = "usb";
526 status = "disabled";
527 };
528
529 usb_host_ohci: usb@30160000 {
530 compatible = "generic-ohci";
531 reg = <0x30160000 0x20000>;
532 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
533 clocks = <&cru HCLK_HOST0>, <&u2phy>;
534 clock-names = "usbhost", "utmi";
535 phys = <&u2phy_host>;
536 phy-names = "usb";
537 status = "disabled";
538 };
539
540 usb_otg: usb@30180000 {
541 compatible = "rockchip,rv1108-usb", "rockchip,rk3066-usb",
542 "snps,dwc2";
543 reg = <0x30180000 0x40000>;
544 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
545 clocks = <&cru HCLK_OTG>;
546 clock-names = "otg";
547 dr_mode = "otg";
548 g-np-tx-fifo-size = <16>;
549 g-rx-fifo-size = <280>;
550 g-tx-fifo-size = <256 128 128 64 32 16>;
551 g-use-dma;
552 phys = <&u2phy_otg>;
553 phy-names = "usb2-phy";
554 status = "disabled";
555 };
556
557 gic: interrupt-controller@32010000 {
558 compatible = "arm,gic-400";
559 interrupt-controller;
560 #interrupt-cells = <3>;
561 #address-cells = <0>;
562
563 reg = <0x32011000 0x1000>,
564 <0x32012000 0x2000>,
565 <0x32014000 0x2000>,
566 <0x32016000 0x2000>;
567 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
568 };
569
570 pinctrl: pinctrl {
571 compatible = "rockchip,rv1108-pinctrl";
572 rockchip,grf = <&grf>;
573 rockchip,pmu = <&pmugrf>;
574 #address-cells = <1>;
575 #size-cells = <1>;
576 ranges;
577
578 gpio0: gpio0@20030000 {
579 compatible = "rockchip,gpio-bank";
580 reg = <0x20030000 0x100>;
581 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
582 clocks = <&xin24m>;
583
584 gpio-controller;
585 #gpio-cells = <2>;
586
587 interrupt-controller;
588 #interrupt-cells = <2>;
589 };
590
591 gpio1: gpio1@10310000 {
592 compatible = "rockchip,gpio-bank";
593 reg = <0x10310000 0x100>;
594 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
595 clocks = <&xin24m>;
596
597 gpio-controller;
598 #gpio-cells = <2>;
599
600 interrupt-controller;
601 #interrupt-cells = <2>;
602 };
603
604 gpio2: gpio2@10320000 {
605 compatible = "rockchip,gpio-bank";
606 reg = <0x10320000 0x100>;
607 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
608 clocks = <&xin24m>;
609
610 gpio-controller;
611 #gpio-cells = <2>;
612
613 interrupt-controller;
614 #interrupt-cells = <2>;
615 };
616
617 gpio3: gpio3@10330000 {
618 compatible = "rockchip,gpio-bank";
619 reg = <0x10330000 0x100>;
620 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
621 clocks = <&xin24m>;
622
623 gpio-controller;
624 #gpio-cells = <2>;
625
626 interrupt-controller;
627 #interrupt-cells = <2>;
628 };
629
630 pcfg_pull_up: pcfg-pull-up {
631 bias-pull-up;
632 };
633
634 pcfg_pull_down: pcfg-pull-down {
635 bias-pull-down;
636 };
637
638 pcfg_pull_none: pcfg-pull-none {
639 bias-disable;
640 };
641
642 pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
643 drive-strength = <8>;
644 };
645
646 pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
647 drive-strength = <12>;
648 };
649
650 pcfg_pull_none_smt: pcfg-pull-none-smt {
651 bias-disable;
652 input-schmitt-enable;
653 };
654
655 pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
656 bias-pull-up;
657 drive-strength = <8>;
658 };
659
660 pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
661 drive-strength = <4>;
662 };
663
664 pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
665 bias-pull-up;
666 drive-strength = <4>;
667 };
668
669 pcfg_output_high: pcfg-output-high {
670 output-high;
671 };
672
673 pcfg_output_low: pcfg-output-low {
674 output-low;
675 };
676
677 pcfg_input_high: pcfg-input-high {
678 bias-pull-up;
679 input-enable;
680 };
681
682 i2c0 {
683 i2c0_xfer: i2c0-xfer {
684 rockchip,pins = <0 RK_PB1 RK_FUNC_1 &pcfg_pull_none_smt>,
685 <0 RK_PB2 RK_FUNC_1 &pcfg_pull_none_smt>;
686 };
687 };
688
689 i2c1 {
690 i2c1_xfer: i2c1-xfer {
691 rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
692 <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
693 };
694 };
695
696 i2c2m1 {
697 i2c2m1_xfer: i2c2m1-xfer {
698 rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
699 <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>;
700 };
701
702 i2c2m1_gpio: i2c2m1-gpio {
703 rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
704 <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
705 };
706 };
707
708 i2c2m05v {
709 i2c2m05v_xfer: i2c2m05v-xfer {
710 rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
711 <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>;
712 };
713
714 i2c2m05v_gpio: i2c2m05v-gpio {
715 rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
716 <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
717 };
718 };
719
720 i2c3 {
721 i2c3_xfer: i2c3-xfer {
722 rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
723 <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
724 };
725 };
726
727 pwm0 {
728 pwm0_pin: pwm0-pin {
729 rockchip,pins = <0 RK_PC5 RK_FUNC_1 &pcfg_pull_none>;
730 };
731 };
732
733 pwm1 {
734 pwm1_pin: pwm1-pin {
735 rockchip,pins = <0 RK_PC4 RK_FUNC_1 &pcfg_pull_none>;
736 };
737 };
738
739 pwm2 {
740 pwm2_pin: pwm2-pin {
741 rockchip,pins = <0 RK_PC6 RK_FUNC_1 &pcfg_pull_none>;
742 };
743 };
744
745 pwm3 {
746 pwm3_pin: pwm3-pin {
747 rockchip,pins = <0 RK_PC0 RK_FUNC_1 &pcfg_pull_none>;
748 };
749 };
750
751 pwm4 {
752 pwm4_pin: pwm4-pin {
753 rockchip,pins = <1 RK_PC1 RK_FUNC_3 &pcfg_pull_none>;
754 };
755 };
756
757 pwm5 {
758 pwm5_pin: pwm5-pin {
759 rockchip,pins = <1 RK_PA7 RK_FUNC_2 &pcfg_pull_none>;
760 };
761 };
762
763 pwm6 {
764 pwm6_pin: pwm6-pin {
765 rockchip,pins = <1 RK_PB0 RK_FUNC_2 &pcfg_pull_none>;
766 };
767 };
768
769 pwm7 {
770 pwm7_pin: pwm7-pin {
771 rockchip,pins = <1 RK_PB1 RK_FUNC_2 &pcfg_pull_none>;
772 };
773 };
774
775 sdmmc {
776 sdmmc_clk: sdmmc-clk {
777 rockchip,pins = <3 RK_PC4 RK_FUNC_1 &pcfg_pull_none_drv_4ma>;
778 };
779
780 sdmmc_cmd: sdmmc-cmd {
781 rockchip,pins = <3 RK_PC5 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
782 };
783
784 sdmmc_cd: sdmmc-cd {
785 rockchip,pins = <0 RK_PA1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
786 };
787
788 sdmmc_bus1: sdmmc-bus1 {
789 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
790 };
791
792 sdmmc_bus4: sdmmc-bus4 {
793 rockchip,pins = <3 RK_PC3 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
794 <3 RK_PC2 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
795 <3 RK_PC1 RK_FUNC_1 &pcfg_pull_up_drv_4ma>,
796 <3 RK_PC0 RK_FUNC_1 &pcfg_pull_up_drv_4ma>;
797 };
798 };
799
800 tsadc {
801 otp_out: otp-out {
802 rockchip,pins = <0 RK_PB7 RK_FUNC_1 &pcfg_pull_none>;
803 };
804
805 otp_gpio: otp-gpio {
806 rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
807 };
808 };
809
810 uart0 {
811 uart0_xfer: uart0-xfer {
812 rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>,
813 <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
814 };
815
816 uart0_cts: uart0-cts {
817 rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
818 };
819
820 uart0_rts: uart0-rts {
821 rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
822 };
823
824 uart0_rts_gpio: uart0-rts-gpio {
825 rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
826 };
827 };
828
829 uart1 {
830 uart1_xfer: uart1-xfer {
831 rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
832 <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
833 };
834
835 uart1_cts: uart1-cts {
836 rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
837 };
838
839 uart1_rts: uart1-rts {
840 rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
841 };
842 };
843
844 uart2m0 {
845 uart2m0_xfer: uart2m0-xfer {
846 rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>,
847 <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
848 };
849 };
850
851 uart2m1 {
852 uart2m1_xfer: uart2m1-xfer {
853 rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>,
854 <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
855 };
856 };
857
858 uart2_5v {
859 uart2_5v_cts: uart2_5v-cts {
860 rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
861 };
862
863 uart2_5v_rts: uart2_5v-rts {
864 rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
865 };
866 };
867 };
868};