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1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Google Veyron Jaq Rev 1+ board device tree source
4 *
5 * Copyright 2015 Google, Inc
6 */
7
8/dts-v1/;
9
10#include "rk3288-veyron-chromebook.dtsi"
11#include "cros-ec-sbs.dtsi"
12
13/ {
14 model = "Google Jaq";
15 compatible = "google,veyron-jaq-rev5", "google,veyron-jaq-rev4",
16 "google,veyron-jaq-rev3", "google,veyron-jaq-rev2",
17 "google,veyron-jaq-rev1", "google,veyron-jaq",
18 "google,veyron", "rockchip,rk3288";
19};
20
21&backlight {
22 /* Jaq panel PWM must be >= 3%, so start non-zero brightness at 8 */
23 brightness-levels = <
24 0
25 8 9 10 11 12 13 14 15
26 16 17 18 19 20 21 22 23
27 24 25 26 27 28 29 30 31
28 32 33 34 35 36 37 38 39
29 40 41 42 43 44 45 46 47
30 48 49 50 51 52 53 54 55
31 56 57 58 59 60 61 62 63
32 64 65 66 67 68 69 70 71
33 72 73 74 75 76 77 78 79
34 80 81 82 83 84 85 86 87
35 88 89 90 91 92 93 94 95
36 96 97 98 99 100 101 102 103
37 104 105 106 107 108 109 110 111
38 112 113 114 115 116 117 118 119
39 120 121 122 123 124 125 126 127
40 128 129 130 131 132 133 134 135
41 136 137 138 139 140 141 142 143
42 144 145 146 147 148 149 150 151
43 152 153 154 155 156 157 158 159
44 160 161 162 163 164 165 166 167
45 168 169 170 171 172 173 174 175
46 176 177 178 179 180 181 182 183
47 184 185 186 187 188 189 190 191
48 192 193 194 195 196 197 198 199
49 200 201 202 203 204 205 206 207
50 208 209 210 211 212 213 214 215
51 216 217 218 219 220 221 222 223
52 224 225 226 227 228 229 230 231
53 232 233 234 235 236 237 238 239
54 240 241 242 243 244 245 246 247
55 248 249 250 251 252 253 254 255>;
56};
57
58&rk808 {
59 pinctrl-names = "default";
60 pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
61 dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>,
62 <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;
63
64 regulators {
65 mic_vcc: LDO_REG2 {
66 regulator-name = "mic_vcc";
67 regulator-always-on;
68 regulator-boot-on;
69 regulator-min-microvolt = <1800000>;
70 regulator-max-microvolt = <1800000>;
71 regulator-state-mem {
72 regulator-off-in-suspend;
73 };
74 };
75 };
76};
77
78&sdmmc {
79 disable-wp;
80 pinctrl-names = "default";
81 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
82 &sdmmc_bus4>;
83};
84
85&vcc_5v {
86 enable-active-high;
87 gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
88 pinctrl-names = "default";
89 pinctrl-0 = <&drv_5v>;
90};
91
92&vcc50_hdmi {
93 enable-active-high;
94 gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
95 pinctrl-names = "default";
96 pinctrl-0 = <&vcc50_hdmi_en>;
97};
98
99&gpio0 {
100 gpio-line-names = "PMIC_SLEEP_AP",
101 "DDRIO_PWROFF",
102 "DDRIO_RETEN",
103 "TS3A227E_INT_L",
104 "PMIC_INT_L",
105 "PWR_KEY_L",
106 "AP_LID_INT_L",
107 "EC_IN_RW",
108
109 "AC_PRESENT_AP",
110 /*
111 * RECOVERY_SW_L is Chrome OS ABI. Schematics call
112 * it REC_MODE_L.
113 */
114 "RECOVERY_SW_L",
115 "OTP_OUT",
116 "HOST1_PWR_EN",
117 "USBOTG_PWREN_H",
118 "AP_WARM_RESET_H",
119 "nFALUT2",
120 "I2C0_SDA_PMIC",
121
122 "I2C0_SCL_PMIC",
123 "SUSPEND_L",
124 "USB_INT";
125};
126
127&gpio2 {
128 gpio-line-names = "CONFIG0",
129 "CONFIG1",
130 "CONFIG2",
131 "",
132 "",
133 "",
134 "",
135 "CONFIG3",
136
137 "",
138 "EMMC_RST_L",
139 "",
140 "",
141 "BL_PWR_EN",
142 "AVDD_1V8_DISP_EN";
143};
144
145&gpio3 {
146 gpio-line-names = "FLASH0_D0",
147 "FLASH0_D1",
148 "FLASH0_D2",
149 "FLASH0_D3",
150 "FLASH0_D4",
151 "FLASH0_D5",
152 "FLASH0_D6",
153 "FLASH0_D7",
154
155 "",
156 "",
157 "",
158 "",
159 "",
160 "",
161 "",
162 "",
163
164 "FLASH0_CS2/EMMC_CMD",
165 "",
166 "FLASH0_DQS/EMMC_CLKO";
167};
168
169&gpio4 {
170 gpio-line-names = "",
171 "",
172 "",
173 "",
174 "",
175 "",
176 "",
177 "",
178
179 "",
180 "",
181 "",
182 "",
183 "",
184 "",
185 "",
186 "",
187
188 "UART0_RXD",
189 "UART0_TXD",
190 "UART0_CTS",
191 "UART0_RTS",
192 "SDIO0_D0",
193 "SDIO0_D1",
194 "SDIO0_D2",
195 "SDIO0_D3",
196
197 "SDIO0_CMD",
198 "SDIO0_CLK",
199 "BT_DEV_WAKE", /* Maybe missing from mighty? */
200 "",
201 "WIFI_ENABLE_H",
202 "BT_ENABLE_L",
203 "WIFI_HOST_WAKE",
204 "BT_HOST_WAKE";
205};
206
207&gpio5 {
208 gpio-line-names = "",
209 "",
210 "",
211 "",
212 "",
213 "",
214 "",
215 "",
216
217 "",
218 "",
219 "",
220 "",
221 "SPI0_CLK",
222 "SPI0_CS0",
223 "SPI0_TXD",
224 "SPI0_RXD",
225
226 "",
227 "",
228 "",
229 "VCC50_HDMI_EN";
230};
231
232&gpio6 {
233 gpio-line-names = "I2S0_SCLK",
234 "I2S0_LRCK_RX",
235 "I2S0_LRCK_TX",
236 "I2S0_SDI",
237 "I2S0_SDO0",
238 "HP_DET_H",
239 "ALS_INT",
240 "INT_CODEC",
241
242 "I2S0_CLK",
243 "I2C2_SDA",
244 "I2C2_SCL",
245 "MICDET",
246 "",
247 "",
248 "",
249 "",
250
251 "SDMMC_D0",
252 "SDMMC_D1",
253 "SDMMC_D2",
254 "SDMMC_D3",
255 "SDMMC_CLK",
256 "SDMMC_CMD";
257};
258
259&gpio7 {
260 gpio-line-names = "LCDC_BL",
261 "PWM_LOG",
262 "BL_EN",
263 "TRACKPAD_INT",
264 "TPM_INT_H",
265 "SDMMC_DET_L",
266 /*
267 * AP_FLASH_WP_L is Chrome OS ABI. Schematics call
268 * it FW_WP_AP.
269 */
270 "AP_FLASH_WP_L",
271 "EC_INT",
272
273 "CPU_NMI",
274 "DVSOK",
275 "SDMMC_WP", /* mighty only */
276 "EDP_HPD",
277 "DVS1",
278 "nFALUT1", /* nFAULT1 on jaq */
279 "LCD_EN",
280 "DVS2",
281
282 "VCC5V_GOOD_H",
283 "I2C4_SDA_TP",
284 "I2C4_SCL_TP",
285 "I2C5_SDA_HDMI",
286 "I2C5_SCL_HDMI",
287 "5V_DRV",
288 "UART2_RXD",
289 "UART2_TXD";
290};
291
292&gpio8 {
293 gpio-line-names = "RAM_ID0",
294 "RAM_ID1",
295 "RAM_ID2",
296 "RAM_ID3",
297 "I2C1_SDA_TPM",
298 "I2C1_SCL_TPM",
299 "SPI2_CLK",
300 "SPI2_CS0",
301
302 "SPI2_RXD",
303 "SPI2_TXD";
304};
305
306&pinctrl {
307 buck-5v {
308 drv_5v: drv-5v {
309 rockchip,pins = <7 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
310 };
311 };
312
313 hdmi {
314 vcc50_hdmi_en: vcc50-hdmi-en {
315 rockchip,pins = <5 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
316 };
317 };
318
319 pmic {
320 dvs_1: dvs-1 {
321 rockchip,pins = <7 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
322 };
323
324 dvs_2: dvs-2 {
325 rockchip,pins = <7 RK_PB7 RK_FUNC_GPIO &pcfg_pull_down>;
326 };
327 };
328};
1/*
2 * Google Veyron Jaq Rev 1+ board device tree source
3 *
4 * Copyright 2015 Google, Inc
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45/dts-v1/;
46
47#include "rk3288-veyron-chromebook.dtsi"
48#include "cros-ec-sbs.dtsi"
49
50/ {
51 model = "Google Jaq";
52 compatible = "google,veyron-jaq-rev5", "google,veyron-jaq-rev4",
53 "google,veyron-jaq-rev3", "google,veyron-jaq-rev2",
54 "google,veyron-jaq-rev1", "google,veyron-jaq",
55 "google,veyron", "rockchip,rk3288";
56
57 panel_regulator: panel-regulator {
58 compatible = "regulator-fixed";
59 enable-active-high;
60 gpio = <&gpio7 RK_PB6 GPIO_ACTIVE_HIGH>;
61 pinctrl-names = "default";
62 pinctrl-0 = <&lcd_enable_h>;
63 regulator-name = "panel_regulator";
64 startup-delay-us = <100000>;
65 vin-supply = <&vcc33_sys>;
66 };
67
68 vcc18_lcd: vcc18-lcd {
69 compatible = "regulator-fixed";
70 enable-active-high;
71 gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
72 pinctrl-names = "default";
73 pinctrl-0 = <&avdd_1v8_disp_en>;
74 regulator-name = "vcc18_lcd";
75 regulator-always-on;
76 regulator-boot-on;
77 vin-supply = <&vcc18_wl>;
78 };
79
80 backlight_regulator: backlight-regulator {
81 compatible = "regulator-fixed";
82 enable-active-high;
83 gpio = <&gpio2 RK_PB4 GPIO_ACTIVE_HIGH>;
84 pinctrl-names = "default";
85 pinctrl-0 = <&bl_pwr_en>;
86 regulator-name = "backlight_regulator";
87 vin-supply = <&vcc33_sys>;
88 startup-delay-us = <15000>;
89 };
90};
91
92&backlight {
93 /* Jaq panel PWM must be >= 3%, so start non-zero brightness at 8 */
94 brightness-levels = <
95 0
96 8 9 10 11 12 13 14 15
97 16 17 18 19 20 21 22 23
98 24 25 26 27 28 29 30 31
99 32 33 34 35 36 37 38 39
100 40 41 42 43 44 45 46 47
101 48 49 50 51 52 53 54 55
102 56 57 58 59 60 61 62 63
103 64 65 66 67 68 69 70 71
104 72 73 74 75 76 77 78 79
105 80 81 82 83 84 85 86 87
106 88 89 90 91 92 93 94 95
107 96 97 98 99 100 101 102 103
108 104 105 106 107 108 109 110 111
109 112 113 114 115 116 117 118 119
110 120 121 122 123 124 125 126 127
111 128 129 130 131 132 133 134 135
112 136 137 138 139 140 141 142 143
113 144 145 146 147 148 149 150 151
114 152 153 154 155 156 157 158 159
115 160 161 162 163 164 165 166 167
116 168 169 170 171 172 173 174 175
117 176 177 178 179 180 181 182 183
118 184 185 186 187 188 189 190 191
119 192 193 194 195 196 197 198 199
120 200 201 202 203 204 205 206 207
121 208 209 210 211 212 213 214 215
122 216 217 218 219 220 221 222 223
123 224 225 226 227 228 229 230 231
124 232 233 234 235 236 237 238 239
125 240 241 242 243 244 245 246 247
126 248 249 250 251 252 253 254 255>;
127 power-supply = <&backlight_regulator>;
128};
129
130&panel {
131 power-supply = <&panel_regulator>;
132};
133
134&rk808 {
135 pinctrl-names = "default";
136 pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
137 dvs-gpios = <&gpio7 RK_PB4 GPIO_ACTIVE_HIGH>,
138 <&gpio7 RK_PB7 GPIO_ACTIVE_HIGH>;
139
140 regulators {
141 mic_vcc: LDO_REG2 {
142 regulator-name = "mic_vcc";
143 regulator-always-on;
144 regulator-boot-on;
145 regulator-min-microvolt = <1800000>;
146 regulator-max-microvolt = <1800000>;
147 regulator-state-mem {
148 regulator-off-in-suspend;
149 };
150 };
151 };
152};
153
154&sdmmc {
155 disable-wp;
156 pinctrl-names = "default";
157 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_cd_disabled &sdmmc_cd_gpio
158 &sdmmc_bus4>;
159};
160
161&vcc_5v {
162 enable-active-high;
163 gpio = <&gpio7 RK_PC5 GPIO_ACTIVE_HIGH>;
164 pinctrl-names = "default";
165 pinctrl-0 = <&drv_5v>;
166};
167
168&vcc50_hdmi {
169 enable-active-high;
170 gpio = <&gpio5 RK_PC3 GPIO_ACTIVE_HIGH>;
171 pinctrl-names = "default";
172 pinctrl-0 = <&vcc50_hdmi_en>;
173};
174
175&pinctrl {
176 backlight {
177 bl_pwr_en: bl_pwr_en {
178 rockchip,pins = <2 12 RK_FUNC_GPIO &pcfg_pull_none>;
179 };
180 };
181
182 buck-5v {
183 drv_5v: drv-5v {
184 rockchip,pins = <7 21 RK_FUNC_GPIO &pcfg_pull_none>;
185 };
186 };
187
188 hdmi {
189 vcc50_hdmi_en: vcc50-hdmi-en {
190 rockchip,pins = <5 19 RK_FUNC_GPIO &pcfg_pull_none>;
191 };
192 };
193
194 lcd {
195 lcd_enable_h: lcd-en {
196 rockchip,pins = <7 14 RK_FUNC_GPIO &pcfg_pull_none>;
197 };
198
199 avdd_1v8_disp_en: avdd-1v8-disp-en {
200 rockchip,pins = <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
201 };
202 };
203
204 pmic {
205 dvs_1: dvs-1 {
206 rockchip,pins = <7 12 RK_FUNC_GPIO &pcfg_pull_down>;
207 };
208
209 dvs_2: dvs-2 {
210 rockchip,pins = <7 15 RK_FUNC_GPIO &pcfg_pull_down>;
211 };
212 };
213};