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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * PCI support in ACPI
4 *
5 * Copyright (C) 2005 David Shaohua Li <shaohua.li@intel.com>
6 * Copyright (C) 2004 Tom Long Nguyen <tom.l.nguyen@intel.com>
7 * Copyright (C) 2004 Intel Corp.
8 */
9
10#include <linux/delay.h>
11#include <linux/init.h>
12#include <linux/irqdomain.h>
13#include <linux/pci.h>
14#include <linux/msi.h>
15#include <linux/pci_hotplug.h>
16#include <linux/module.h>
17#include <linux/pci-acpi.h>
18#include <linux/pm_runtime.h>
19#include <linux/pm_qos.h>
20#include "pci.h"
21
22/*
23 * The GUID is defined in the PCI Firmware Specification available here:
24 * https://www.pcisig.com/members/downloads/pcifw_r3_1_13Dec10.pdf
25 */
26const guid_t pci_acpi_dsm_guid =
27 GUID_INIT(0xe5c937d0, 0x3553, 0x4d7a,
28 0x91, 0x17, 0xea, 0x4d, 0x19, 0xc3, 0x43, 0x4d);
29
30#if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
31static int acpi_get_rc_addr(struct acpi_device *adev, struct resource *res)
32{
33 struct device *dev = &adev->dev;
34 struct resource_entry *entry;
35 struct list_head list;
36 unsigned long flags;
37 int ret;
38
39 INIT_LIST_HEAD(&list);
40 flags = IORESOURCE_MEM;
41 ret = acpi_dev_get_resources(adev, &list,
42 acpi_dev_filter_resource_type_cb,
43 (void *) flags);
44 if (ret < 0) {
45 dev_err(dev, "failed to parse _CRS method, error code %d\n",
46 ret);
47 return ret;
48 }
49
50 if (ret == 0) {
51 dev_err(dev, "no IO and memory resources present in _CRS\n");
52 return -EINVAL;
53 }
54
55 entry = list_first_entry(&list, struct resource_entry, node);
56 *res = *entry->res;
57 acpi_dev_free_resource_list(&list);
58 return 0;
59}
60
61static acpi_status acpi_match_rc(acpi_handle handle, u32 lvl, void *context,
62 void **retval)
63{
64 u16 *segment = context;
65 unsigned long long uid;
66 acpi_status status;
67
68 status = acpi_evaluate_integer(handle, "_UID", NULL, &uid);
69 if (ACPI_FAILURE(status) || uid != *segment)
70 return AE_CTRL_DEPTH;
71
72 *(acpi_handle *)retval = handle;
73 return AE_CTRL_TERMINATE;
74}
75
76int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
77 struct resource *res)
78{
79 struct acpi_device *adev;
80 acpi_status status;
81 acpi_handle handle;
82 int ret;
83
84 status = acpi_get_devices(hid, acpi_match_rc, &segment, &handle);
85 if (ACPI_FAILURE(status)) {
86 dev_err(dev, "can't find _HID %s device to locate resources\n",
87 hid);
88 return -ENODEV;
89 }
90
91 ret = acpi_bus_get_device(handle, &adev);
92 if (ret)
93 return ret;
94
95 ret = acpi_get_rc_addr(adev, res);
96 if (ret) {
97 dev_err(dev, "can't get resource from %s\n",
98 dev_name(&adev->dev));
99 return ret;
100 }
101
102 return 0;
103}
104#endif
105
106phys_addr_t acpi_pci_root_get_mcfg_addr(acpi_handle handle)
107{
108 acpi_status status = AE_NOT_EXIST;
109 unsigned long long mcfg_addr;
110
111 if (handle)
112 status = acpi_evaluate_integer(handle, METHOD_NAME__CBA,
113 NULL, &mcfg_addr);
114 if (ACPI_FAILURE(status))
115 return 0;
116
117 return (phys_addr_t)mcfg_addr;
118}
119
120/* _HPX PCI Setting Record (Type 0); same as _HPP */
121struct hpx_type0 {
122 u32 revision; /* Not present in _HPP */
123 u8 cache_line_size; /* Not applicable to PCIe */
124 u8 latency_timer; /* Not applicable to PCIe */
125 u8 enable_serr;
126 u8 enable_perr;
127};
128
129static struct hpx_type0 pci_default_type0 = {
130 .revision = 1,
131 .cache_line_size = 8,
132 .latency_timer = 0x40,
133 .enable_serr = 0,
134 .enable_perr = 0,
135};
136
137static void program_hpx_type0(struct pci_dev *dev, struct hpx_type0 *hpx)
138{
139 u16 pci_cmd, pci_bctl;
140
141 if (!hpx)
142 hpx = &pci_default_type0;
143
144 if (hpx->revision > 1) {
145 pci_warn(dev, "PCI settings rev %d not supported; using defaults\n",
146 hpx->revision);
147 hpx = &pci_default_type0;
148 }
149
150 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpx->cache_line_size);
151 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpx->latency_timer);
152 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
153 if (hpx->enable_serr)
154 pci_cmd |= PCI_COMMAND_SERR;
155 if (hpx->enable_perr)
156 pci_cmd |= PCI_COMMAND_PARITY;
157 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
158
159 /* Program bridge control value */
160 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
161 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
162 hpx->latency_timer);
163 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
164 if (hpx->enable_perr)
165 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
166 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
167 }
168}
169
170static acpi_status decode_type0_hpx_record(union acpi_object *record,
171 struct hpx_type0 *hpx0)
172{
173 int i;
174 union acpi_object *fields = record->package.elements;
175 u32 revision = fields[1].integer.value;
176
177 switch (revision) {
178 case 1:
179 if (record->package.count != 6)
180 return AE_ERROR;
181 for (i = 2; i < 6; i++)
182 if (fields[i].type != ACPI_TYPE_INTEGER)
183 return AE_ERROR;
184 hpx0->revision = revision;
185 hpx0->cache_line_size = fields[2].integer.value;
186 hpx0->latency_timer = fields[3].integer.value;
187 hpx0->enable_serr = fields[4].integer.value;
188 hpx0->enable_perr = fields[5].integer.value;
189 break;
190 default:
191 pr_warn("%s: Type 0 Revision %d record not supported\n",
192 __func__, revision);
193 return AE_ERROR;
194 }
195 return AE_OK;
196}
197
198/* _HPX PCI-X Setting Record (Type 1) */
199struct hpx_type1 {
200 u32 revision;
201 u8 max_mem_read;
202 u8 avg_max_split;
203 u16 tot_max_split;
204};
205
206static void program_hpx_type1(struct pci_dev *dev, struct hpx_type1 *hpx)
207{
208 int pos;
209
210 if (!hpx)
211 return;
212
213 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
214 if (!pos)
215 return;
216
217 pci_warn(dev, "PCI-X settings not supported\n");
218}
219
220static acpi_status decode_type1_hpx_record(union acpi_object *record,
221 struct hpx_type1 *hpx1)
222{
223 int i;
224 union acpi_object *fields = record->package.elements;
225 u32 revision = fields[1].integer.value;
226
227 switch (revision) {
228 case 1:
229 if (record->package.count != 5)
230 return AE_ERROR;
231 for (i = 2; i < 5; i++)
232 if (fields[i].type != ACPI_TYPE_INTEGER)
233 return AE_ERROR;
234 hpx1->revision = revision;
235 hpx1->max_mem_read = fields[2].integer.value;
236 hpx1->avg_max_split = fields[3].integer.value;
237 hpx1->tot_max_split = fields[4].integer.value;
238 break;
239 default:
240 pr_warn("%s: Type 1 Revision %d record not supported\n",
241 __func__, revision);
242 return AE_ERROR;
243 }
244 return AE_OK;
245}
246
247static bool pcie_root_rcb_set(struct pci_dev *dev)
248{
249 struct pci_dev *rp = pcie_find_root_port(dev);
250 u16 lnkctl;
251
252 if (!rp)
253 return false;
254
255 pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &lnkctl);
256 if (lnkctl & PCI_EXP_LNKCTL_RCB)
257 return true;
258
259 return false;
260}
261
262/* _HPX PCI Express Setting Record (Type 2) */
263struct hpx_type2 {
264 u32 revision;
265 u32 unc_err_mask_and;
266 u32 unc_err_mask_or;
267 u32 unc_err_sever_and;
268 u32 unc_err_sever_or;
269 u32 cor_err_mask_and;
270 u32 cor_err_mask_or;
271 u32 adv_err_cap_and;
272 u32 adv_err_cap_or;
273 u16 pci_exp_devctl_and;
274 u16 pci_exp_devctl_or;
275 u16 pci_exp_lnkctl_and;
276 u16 pci_exp_lnkctl_or;
277 u32 sec_unc_err_sever_and;
278 u32 sec_unc_err_sever_or;
279 u32 sec_unc_err_mask_and;
280 u32 sec_unc_err_mask_or;
281};
282
283static void program_hpx_type2(struct pci_dev *dev, struct hpx_type2 *hpx)
284{
285 int pos;
286 u32 reg32;
287
288 if (!hpx)
289 return;
290
291 if (!pci_is_pcie(dev))
292 return;
293
294 if (hpx->revision > 1) {
295 pci_warn(dev, "PCIe settings rev %d not supported\n",
296 hpx->revision);
297 return;
298 }
299
300 /*
301 * Don't allow _HPX to change MPS or MRRS settings. We manage
302 * those to make sure they're consistent with the rest of the
303 * platform.
304 */
305 hpx->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
306 PCI_EXP_DEVCTL_READRQ;
307 hpx->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
308 PCI_EXP_DEVCTL_READRQ);
309
310 /* Initialize Device Control Register */
311 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
312 ~hpx->pci_exp_devctl_and, hpx->pci_exp_devctl_or);
313
314 /* Initialize Link Control Register */
315 if (pcie_cap_has_lnkctl(dev)) {
316
317 /*
318 * If the Root Port supports Read Completion Boundary of
319 * 128, set RCB to 128. Otherwise, clear it.
320 */
321 hpx->pci_exp_lnkctl_and |= PCI_EXP_LNKCTL_RCB;
322 hpx->pci_exp_lnkctl_or &= ~PCI_EXP_LNKCTL_RCB;
323 if (pcie_root_rcb_set(dev))
324 hpx->pci_exp_lnkctl_or |= PCI_EXP_LNKCTL_RCB;
325
326 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
327 ~hpx->pci_exp_lnkctl_and, hpx->pci_exp_lnkctl_or);
328 }
329
330 /* Find Advanced Error Reporting Enhanced Capability */
331 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
332 if (!pos)
333 return;
334
335 /* Initialize Uncorrectable Error Mask Register */
336 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32);
337 reg32 = (reg32 & hpx->unc_err_mask_and) | hpx->unc_err_mask_or;
338 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
339
340 /* Initialize Uncorrectable Error Severity Register */
341 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32);
342 reg32 = (reg32 & hpx->unc_err_sever_and) | hpx->unc_err_sever_or;
343 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
344
345 /* Initialize Correctable Error Mask Register */
346 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32);
347 reg32 = (reg32 & hpx->cor_err_mask_and) | hpx->cor_err_mask_or;
348 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
349
350 /* Initialize Advanced Error Capabilities and Control Register */
351 pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32);
352 reg32 = (reg32 & hpx->adv_err_cap_and) | hpx->adv_err_cap_or;
353
354 /* Don't enable ECRC generation or checking if unsupported */
355 if (!(reg32 & PCI_ERR_CAP_ECRC_GENC))
356 reg32 &= ~PCI_ERR_CAP_ECRC_GENE;
357 if (!(reg32 & PCI_ERR_CAP_ECRC_CHKC))
358 reg32 &= ~PCI_ERR_CAP_ECRC_CHKE;
359 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
360
361 /*
362 * FIXME: The following two registers are not supported yet.
363 *
364 * o Secondary Uncorrectable Error Severity Register
365 * o Secondary Uncorrectable Error Mask Register
366 */
367}
368
369static acpi_status decode_type2_hpx_record(union acpi_object *record,
370 struct hpx_type2 *hpx2)
371{
372 int i;
373 union acpi_object *fields = record->package.elements;
374 u32 revision = fields[1].integer.value;
375
376 switch (revision) {
377 case 1:
378 if (record->package.count != 18)
379 return AE_ERROR;
380 for (i = 2; i < 18; i++)
381 if (fields[i].type != ACPI_TYPE_INTEGER)
382 return AE_ERROR;
383 hpx2->revision = revision;
384 hpx2->unc_err_mask_and = fields[2].integer.value;
385 hpx2->unc_err_mask_or = fields[3].integer.value;
386 hpx2->unc_err_sever_and = fields[4].integer.value;
387 hpx2->unc_err_sever_or = fields[5].integer.value;
388 hpx2->cor_err_mask_and = fields[6].integer.value;
389 hpx2->cor_err_mask_or = fields[7].integer.value;
390 hpx2->adv_err_cap_and = fields[8].integer.value;
391 hpx2->adv_err_cap_or = fields[9].integer.value;
392 hpx2->pci_exp_devctl_and = fields[10].integer.value;
393 hpx2->pci_exp_devctl_or = fields[11].integer.value;
394 hpx2->pci_exp_lnkctl_and = fields[12].integer.value;
395 hpx2->pci_exp_lnkctl_or = fields[13].integer.value;
396 hpx2->sec_unc_err_sever_and = fields[14].integer.value;
397 hpx2->sec_unc_err_sever_or = fields[15].integer.value;
398 hpx2->sec_unc_err_mask_and = fields[16].integer.value;
399 hpx2->sec_unc_err_mask_or = fields[17].integer.value;
400 break;
401 default:
402 pr_warn("%s: Type 2 Revision %d record not supported\n",
403 __func__, revision);
404 return AE_ERROR;
405 }
406 return AE_OK;
407}
408
409/* _HPX PCI Express Setting Record (Type 3) */
410struct hpx_type3 {
411 u16 device_type;
412 u16 function_type;
413 u16 config_space_location;
414 u16 pci_exp_cap_id;
415 u16 pci_exp_cap_ver;
416 u16 pci_exp_vendor_id;
417 u16 dvsec_id;
418 u16 dvsec_rev;
419 u16 match_offset;
420 u32 match_mask_and;
421 u32 match_value;
422 u16 reg_offset;
423 u32 reg_mask_and;
424 u32 reg_mask_or;
425};
426
427enum hpx_type3_dev_type {
428 HPX_TYPE_ENDPOINT = BIT(0),
429 HPX_TYPE_LEG_END = BIT(1),
430 HPX_TYPE_RC_END = BIT(2),
431 HPX_TYPE_RC_EC = BIT(3),
432 HPX_TYPE_ROOT_PORT = BIT(4),
433 HPX_TYPE_UPSTREAM = BIT(5),
434 HPX_TYPE_DOWNSTREAM = BIT(6),
435 HPX_TYPE_PCI_BRIDGE = BIT(7),
436 HPX_TYPE_PCIE_BRIDGE = BIT(8),
437};
438
439static u16 hpx3_device_type(struct pci_dev *dev)
440{
441 u16 pcie_type = pci_pcie_type(dev);
442 const int pcie_to_hpx3_type[] = {
443 [PCI_EXP_TYPE_ENDPOINT] = HPX_TYPE_ENDPOINT,
444 [PCI_EXP_TYPE_LEG_END] = HPX_TYPE_LEG_END,
445 [PCI_EXP_TYPE_RC_END] = HPX_TYPE_RC_END,
446 [PCI_EXP_TYPE_RC_EC] = HPX_TYPE_RC_EC,
447 [PCI_EXP_TYPE_ROOT_PORT] = HPX_TYPE_ROOT_PORT,
448 [PCI_EXP_TYPE_UPSTREAM] = HPX_TYPE_UPSTREAM,
449 [PCI_EXP_TYPE_DOWNSTREAM] = HPX_TYPE_DOWNSTREAM,
450 [PCI_EXP_TYPE_PCI_BRIDGE] = HPX_TYPE_PCI_BRIDGE,
451 [PCI_EXP_TYPE_PCIE_BRIDGE] = HPX_TYPE_PCIE_BRIDGE,
452 };
453
454 if (pcie_type >= ARRAY_SIZE(pcie_to_hpx3_type))
455 return 0;
456
457 return pcie_to_hpx3_type[pcie_type];
458}
459
460enum hpx_type3_fn_type {
461 HPX_FN_NORMAL = BIT(0),
462 HPX_FN_SRIOV_PHYS = BIT(1),
463 HPX_FN_SRIOV_VIRT = BIT(2),
464};
465
466static u8 hpx3_function_type(struct pci_dev *dev)
467{
468 if (dev->is_virtfn)
469 return HPX_FN_SRIOV_VIRT;
470 else if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV) > 0)
471 return HPX_FN_SRIOV_PHYS;
472 else
473 return HPX_FN_NORMAL;
474}
475
476static bool hpx3_cap_ver_matches(u8 pcie_cap_id, u8 hpx3_cap_id)
477{
478 u8 cap_ver = hpx3_cap_id & 0xf;
479
480 if ((hpx3_cap_id & BIT(4)) && cap_ver >= pcie_cap_id)
481 return true;
482 else if (cap_ver == pcie_cap_id)
483 return true;
484
485 return false;
486}
487
488enum hpx_type3_cfg_loc {
489 HPX_CFG_PCICFG = 0,
490 HPX_CFG_PCIE_CAP = 1,
491 HPX_CFG_PCIE_CAP_EXT = 2,
492 HPX_CFG_VEND_CAP = 3,
493 HPX_CFG_DVSEC = 4,
494 HPX_CFG_MAX,
495};
496
497static void program_hpx_type3_register(struct pci_dev *dev,
498 const struct hpx_type3 *reg)
499{
500 u32 match_reg, write_reg, header, orig_value;
501 u16 pos;
502
503 if (!(hpx3_device_type(dev) & reg->device_type))
504 return;
505
506 if (!(hpx3_function_type(dev) & reg->function_type))
507 return;
508
509 switch (reg->config_space_location) {
510 case HPX_CFG_PCICFG:
511 pos = 0;
512 break;
513 case HPX_CFG_PCIE_CAP:
514 pos = pci_find_capability(dev, reg->pci_exp_cap_id);
515 if (pos == 0)
516 return;
517
518 break;
519 case HPX_CFG_PCIE_CAP_EXT:
520 pos = pci_find_ext_capability(dev, reg->pci_exp_cap_id);
521 if (pos == 0)
522 return;
523
524 pci_read_config_dword(dev, pos, &header);
525 if (!hpx3_cap_ver_matches(PCI_EXT_CAP_VER(header),
526 reg->pci_exp_cap_ver))
527 return;
528
529 break;
530 case HPX_CFG_VEND_CAP: /* Fall through */
531 case HPX_CFG_DVSEC: /* Fall through */
532 default:
533 pci_warn(dev, "Encountered _HPX type 3 with unsupported config space location");
534 return;
535 }
536
537 pci_read_config_dword(dev, pos + reg->match_offset, &match_reg);
538
539 if ((match_reg & reg->match_mask_and) != reg->match_value)
540 return;
541
542 pci_read_config_dword(dev, pos + reg->reg_offset, &write_reg);
543 orig_value = write_reg;
544 write_reg &= reg->reg_mask_and;
545 write_reg |= reg->reg_mask_or;
546
547 if (orig_value == write_reg)
548 return;
549
550 pci_write_config_dword(dev, pos + reg->reg_offset, write_reg);
551
552 pci_dbg(dev, "Applied _HPX3 at [0x%x]: 0x%08x -> 0x%08x",
553 pos, orig_value, write_reg);
554}
555
556static void program_hpx_type3(struct pci_dev *dev, struct hpx_type3 *hpx)
557{
558 if (!hpx)
559 return;
560
561 if (!pci_is_pcie(dev))
562 return;
563
564 program_hpx_type3_register(dev, hpx);
565}
566
567static void parse_hpx3_register(struct hpx_type3 *hpx3_reg,
568 union acpi_object *reg_fields)
569{
570 hpx3_reg->device_type = reg_fields[0].integer.value;
571 hpx3_reg->function_type = reg_fields[1].integer.value;
572 hpx3_reg->config_space_location = reg_fields[2].integer.value;
573 hpx3_reg->pci_exp_cap_id = reg_fields[3].integer.value;
574 hpx3_reg->pci_exp_cap_ver = reg_fields[4].integer.value;
575 hpx3_reg->pci_exp_vendor_id = reg_fields[5].integer.value;
576 hpx3_reg->dvsec_id = reg_fields[6].integer.value;
577 hpx3_reg->dvsec_rev = reg_fields[7].integer.value;
578 hpx3_reg->match_offset = reg_fields[8].integer.value;
579 hpx3_reg->match_mask_and = reg_fields[9].integer.value;
580 hpx3_reg->match_value = reg_fields[10].integer.value;
581 hpx3_reg->reg_offset = reg_fields[11].integer.value;
582 hpx3_reg->reg_mask_and = reg_fields[12].integer.value;
583 hpx3_reg->reg_mask_or = reg_fields[13].integer.value;
584}
585
586static acpi_status program_type3_hpx_record(struct pci_dev *dev,
587 union acpi_object *record)
588{
589 union acpi_object *fields = record->package.elements;
590 u32 desc_count, expected_length, revision;
591 union acpi_object *reg_fields;
592 struct hpx_type3 hpx3;
593 int i;
594
595 revision = fields[1].integer.value;
596 switch (revision) {
597 case 1:
598 desc_count = fields[2].integer.value;
599 expected_length = 3 + desc_count * 14;
600
601 if (record->package.count != expected_length)
602 return AE_ERROR;
603
604 for (i = 2; i < expected_length; i++)
605 if (fields[i].type != ACPI_TYPE_INTEGER)
606 return AE_ERROR;
607
608 for (i = 0; i < desc_count; i++) {
609 reg_fields = fields + 3 + i * 14;
610 parse_hpx3_register(&hpx3, reg_fields);
611 program_hpx_type3(dev, &hpx3);
612 }
613
614 break;
615 default:
616 printk(KERN_WARNING
617 "%s: Type 3 Revision %d record not supported\n",
618 __func__, revision);
619 return AE_ERROR;
620 }
621 return AE_OK;
622}
623
624static acpi_status acpi_run_hpx(struct pci_dev *dev, acpi_handle handle)
625{
626 acpi_status status;
627 struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL};
628 union acpi_object *package, *record, *fields;
629 struct hpx_type0 hpx0;
630 struct hpx_type1 hpx1;
631 struct hpx_type2 hpx2;
632 u32 type;
633 int i;
634
635 status = acpi_evaluate_object(handle, "_HPX", NULL, &buffer);
636 if (ACPI_FAILURE(status))
637 return status;
638
639 package = (union acpi_object *)buffer.pointer;
640 if (package->type != ACPI_TYPE_PACKAGE) {
641 status = AE_ERROR;
642 goto exit;
643 }
644
645 for (i = 0; i < package->package.count; i++) {
646 record = &package->package.elements[i];
647 if (record->type != ACPI_TYPE_PACKAGE) {
648 status = AE_ERROR;
649 goto exit;
650 }
651
652 fields = record->package.elements;
653 if (fields[0].type != ACPI_TYPE_INTEGER ||
654 fields[1].type != ACPI_TYPE_INTEGER) {
655 status = AE_ERROR;
656 goto exit;
657 }
658
659 type = fields[0].integer.value;
660 switch (type) {
661 case 0:
662 memset(&hpx0, 0, sizeof(hpx0));
663 status = decode_type0_hpx_record(record, &hpx0);
664 if (ACPI_FAILURE(status))
665 goto exit;
666 program_hpx_type0(dev, &hpx0);
667 break;
668 case 1:
669 memset(&hpx1, 0, sizeof(hpx1));
670 status = decode_type1_hpx_record(record, &hpx1);
671 if (ACPI_FAILURE(status))
672 goto exit;
673 program_hpx_type1(dev, &hpx1);
674 break;
675 case 2:
676 memset(&hpx2, 0, sizeof(hpx2));
677 status = decode_type2_hpx_record(record, &hpx2);
678 if (ACPI_FAILURE(status))
679 goto exit;
680 program_hpx_type2(dev, &hpx2);
681 break;
682 case 3:
683 status = program_type3_hpx_record(dev, record);
684 if (ACPI_FAILURE(status))
685 goto exit;
686 break;
687 default:
688 pr_err("%s: Type %d record not supported\n",
689 __func__, type);
690 status = AE_ERROR;
691 goto exit;
692 }
693 }
694 exit:
695 kfree(buffer.pointer);
696 return status;
697}
698
699static acpi_status acpi_run_hpp(struct pci_dev *dev, acpi_handle handle)
700{
701 acpi_status status;
702 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
703 union acpi_object *package, *fields;
704 struct hpx_type0 hpx0;
705 int i;
706
707 memset(&hpx0, 0, sizeof(hpx0));
708
709 status = acpi_evaluate_object(handle, "_HPP", NULL, &buffer);
710 if (ACPI_FAILURE(status))
711 return status;
712
713 package = (union acpi_object *) buffer.pointer;
714 if (package->type != ACPI_TYPE_PACKAGE ||
715 package->package.count != 4) {
716 status = AE_ERROR;
717 goto exit;
718 }
719
720 fields = package->package.elements;
721 for (i = 0; i < 4; i++) {
722 if (fields[i].type != ACPI_TYPE_INTEGER) {
723 status = AE_ERROR;
724 goto exit;
725 }
726 }
727
728 hpx0.revision = 1;
729 hpx0.cache_line_size = fields[0].integer.value;
730 hpx0.latency_timer = fields[1].integer.value;
731 hpx0.enable_serr = fields[2].integer.value;
732 hpx0.enable_perr = fields[3].integer.value;
733
734 program_hpx_type0(dev, &hpx0);
735
736exit:
737 kfree(buffer.pointer);
738 return status;
739}
740
741/* pci_acpi_program_hp_params
742 *
743 * @dev - the pci_dev for which we want parameters
744 */
745int pci_acpi_program_hp_params(struct pci_dev *dev)
746{
747 acpi_status status;
748 acpi_handle handle, phandle;
749 struct pci_bus *pbus;
750
751 if (acpi_pci_disabled)
752 return -ENODEV;
753
754 handle = NULL;
755 for (pbus = dev->bus; pbus; pbus = pbus->parent) {
756 handle = acpi_pci_get_bridge_handle(pbus);
757 if (handle)
758 break;
759 }
760
761 /*
762 * _HPP settings apply to all child buses, until another _HPP is
763 * encountered. If we don't find an _HPP for the input pci dev,
764 * look for it in the parent device scope since that would apply to
765 * this pci dev.
766 */
767 while (handle) {
768 status = acpi_run_hpx(dev, handle);
769 if (ACPI_SUCCESS(status))
770 return 0;
771 status = acpi_run_hpp(dev, handle);
772 if (ACPI_SUCCESS(status))
773 return 0;
774 if (acpi_is_root_bridge(handle))
775 break;
776 status = acpi_get_parent(handle, &phandle);
777 if (ACPI_FAILURE(status))
778 break;
779 handle = phandle;
780 }
781 return -ENODEV;
782}
783
784/**
785 * pciehp_is_native - Check whether a hotplug port is handled by the OS
786 * @bridge: Hotplug port to check
787 *
788 * Returns true if the given @bridge is handled by the native PCIe hotplug
789 * driver.
790 */
791bool pciehp_is_native(struct pci_dev *bridge)
792{
793 const struct pci_host_bridge *host;
794 u32 slot_cap;
795
796 if (!IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE))
797 return false;
798
799 pcie_capability_read_dword(bridge, PCI_EXP_SLTCAP, &slot_cap);
800 if (!(slot_cap & PCI_EXP_SLTCAP_HPC))
801 return false;
802
803 if (pcie_ports_native)
804 return true;
805
806 host = pci_find_host_bridge(bridge->bus);
807 return host->native_pcie_hotplug;
808}
809
810/**
811 * shpchp_is_native - Check whether a hotplug port is handled by the OS
812 * @bridge: Hotplug port to check
813 *
814 * Returns true if the given @bridge is handled by the native SHPC hotplug
815 * driver.
816 */
817bool shpchp_is_native(struct pci_dev *bridge)
818{
819 return bridge->shpc_managed;
820}
821
822/**
823 * pci_acpi_wake_bus - Root bus wakeup notification fork function.
824 * @context: Device wakeup context.
825 */
826static void pci_acpi_wake_bus(struct acpi_device_wakeup_context *context)
827{
828 struct acpi_device *adev;
829 struct acpi_pci_root *root;
830
831 adev = container_of(context, struct acpi_device, wakeup.context);
832 root = acpi_driver_data(adev);
833 pci_pme_wakeup_bus(root->bus);
834}
835
836/**
837 * pci_acpi_wake_dev - PCI device wakeup notification work function.
838 * @context: Device wakeup context.
839 */
840static void pci_acpi_wake_dev(struct acpi_device_wakeup_context *context)
841{
842 struct pci_dev *pci_dev;
843
844 pci_dev = to_pci_dev(context->dev);
845
846 if (pci_dev->pme_poll)
847 pci_dev->pme_poll = false;
848
849 if (pci_dev->current_state == PCI_D3cold) {
850 pci_wakeup_event(pci_dev);
851 pm_request_resume(&pci_dev->dev);
852 return;
853 }
854
855 /* Clear PME Status if set. */
856 if (pci_dev->pme_support)
857 pci_check_pme_status(pci_dev);
858
859 pci_wakeup_event(pci_dev);
860 pm_request_resume(&pci_dev->dev);
861
862 pci_pme_wakeup_bus(pci_dev->subordinate);
863}
864
865/**
866 * pci_acpi_add_bus_pm_notifier - Register PM notifier for root PCI bus.
867 * @dev: PCI root bridge ACPI device.
868 */
869acpi_status pci_acpi_add_bus_pm_notifier(struct acpi_device *dev)
870{
871 return acpi_add_pm_notifier(dev, NULL, pci_acpi_wake_bus);
872}
873
874/**
875 * pci_acpi_add_pm_notifier - Register PM notifier for given PCI device.
876 * @dev: ACPI device to add the notifier for.
877 * @pci_dev: PCI device to check for the PME status if an event is signaled.
878 */
879acpi_status pci_acpi_add_pm_notifier(struct acpi_device *dev,
880 struct pci_dev *pci_dev)
881{
882 return acpi_add_pm_notifier(dev, &pci_dev->dev, pci_acpi_wake_dev);
883}
884
885/*
886 * _SxD returns the D-state with the highest power
887 * (lowest D-state number) supported in the S-state "x".
888 *
889 * If the devices does not have a _PRW
890 * (Power Resources for Wake) supporting system wakeup from "x"
891 * then the OS is free to choose a lower power (higher number
892 * D-state) than the return value from _SxD.
893 *
894 * But if _PRW is enabled at S-state "x", the OS
895 * must not choose a power lower than _SxD --
896 * unless the device has an _SxW method specifying
897 * the lowest power (highest D-state number) the device
898 * may enter while still able to wake the system.
899 *
900 * ie. depending on global OS policy:
901 *
902 * if (_PRW at S-state x)
903 * choose from highest power _SxD to lowest power _SxW
904 * else // no _PRW at S-state x
905 * choose highest power _SxD or any lower power
906 */
907
908static pci_power_t acpi_pci_choose_state(struct pci_dev *pdev)
909{
910 int acpi_state, d_max;
911
912 if (pdev->no_d3cold)
913 d_max = ACPI_STATE_D3_HOT;
914 else
915 d_max = ACPI_STATE_D3_COLD;
916 acpi_state = acpi_pm_device_sleep_state(&pdev->dev, NULL, d_max);
917 if (acpi_state < 0)
918 return PCI_POWER_ERROR;
919
920 switch (acpi_state) {
921 case ACPI_STATE_D0:
922 return PCI_D0;
923 case ACPI_STATE_D1:
924 return PCI_D1;
925 case ACPI_STATE_D2:
926 return PCI_D2;
927 case ACPI_STATE_D3_HOT:
928 return PCI_D3hot;
929 case ACPI_STATE_D3_COLD:
930 return PCI_D3cold;
931 }
932 return PCI_POWER_ERROR;
933}
934
935static struct acpi_device *acpi_pci_find_companion(struct device *dev);
936
937static bool acpi_pci_bridge_d3(struct pci_dev *dev)
938{
939 const struct fwnode_handle *fwnode;
940 struct acpi_device *adev;
941 struct pci_dev *root;
942 u8 val;
943
944 if (!dev->is_hotplug_bridge)
945 return false;
946
947 /*
948 * Look for a special _DSD property for the root port and if it
949 * is set we know the hierarchy behind it supports D3 just fine.
950 */
951 root = pci_find_pcie_root_port(dev);
952 if (!root)
953 return false;
954
955 adev = ACPI_COMPANION(&root->dev);
956 if (root == dev) {
957 /*
958 * It is possible that the ACPI companion is not yet bound
959 * for the root port so look it up manually here.
960 */
961 if (!adev && !pci_dev_is_added(root))
962 adev = acpi_pci_find_companion(&root->dev);
963 }
964
965 if (!adev)
966 return false;
967
968 fwnode = acpi_fwnode_handle(adev);
969 if (fwnode_property_read_u8(fwnode, "HotPlugSupportInD3", &val))
970 return false;
971
972 return val == 1;
973}
974
975static bool acpi_pci_power_manageable(struct pci_dev *dev)
976{
977 struct acpi_device *adev = ACPI_COMPANION(&dev->dev);
978 return adev ? acpi_device_power_manageable(adev) : false;
979}
980
981static int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state)
982{
983 struct acpi_device *adev = ACPI_COMPANION(&dev->dev);
984 static const u8 state_conv[] = {
985 [PCI_D0] = ACPI_STATE_D0,
986 [PCI_D1] = ACPI_STATE_D1,
987 [PCI_D2] = ACPI_STATE_D2,
988 [PCI_D3hot] = ACPI_STATE_D3_HOT,
989 [PCI_D3cold] = ACPI_STATE_D3_COLD,
990 };
991 int error = -EINVAL;
992
993 /* If the ACPI device has _EJ0, ignore the device */
994 if (!adev || acpi_has_method(adev->handle, "_EJ0"))
995 return -ENODEV;
996
997 switch (state) {
998 case PCI_D3cold:
999 if (dev_pm_qos_flags(&dev->dev, PM_QOS_FLAG_NO_POWER_OFF) ==
1000 PM_QOS_FLAGS_ALL) {
1001 error = -EBUSY;
1002 break;
1003 }
1004 /* Fall through */
1005 case PCI_D0:
1006 case PCI_D1:
1007 case PCI_D2:
1008 case PCI_D3hot:
1009 error = acpi_device_set_power(adev, state_conv[state]);
1010 }
1011
1012 if (!error)
1013 pci_dbg(dev, "power state changed by ACPI to %s\n",
1014 acpi_power_state_string(state_conv[state]));
1015
1016 return error;
1017}
1018
1019static pci_power_t acpi_pci_get_power_state(struct pci_dev *dev)
1020{
1021 struct acpi_device *adev = ACPI_COMPANION(&dev->dev);
1022 static const pci_power_t state_conv[] = {
1023 [ACPI_STATE_D0] = PCI_D0,
1024 [ACPI_STATE_D1] = PCI_D1,
1025 [ACPI_STATE_D2] = PCI_D2,
1026 [ACPI_STATE_D3_HOT] = PCI_D3hot,
1027 [ACPI_STATE_D3_COLD] = PCI_D3cold,
1028 };
1029 int state;
1030
1031 if (!adev || !acpi_device_power_manageable(adev))
1032 return PCI_UNKNOWN;
1033
1034 state = adev->power.state;
1035 if (state == ACPI_STATE_UNKNOWN)
1036 return PCI_UNKNOWN;
1037
1038 return state_conv[state];
1039}
1040
1041static void acpi_pci_refresh_power_state(struct pci_dev *dev)
1042{
1043 struct acpi_device *adev = ACPI_COMPANION(&dev->dev);
1044
1045 if (adev && acpi_device_power_manageable(adev))
1046 acpi_device_update_power(adev, NULL);
1047}
1048
1049static int acpi_pci_propagate_wakeup(struct pci_bus *bus, bool enable)
1050{
1051 while (bus->parent) {
1052 if (acpi_pm_device_can_wakeup(&bus->self->dev))
1053 return acpi_pm_set_bridge_wakeup(&bus->self->dev, enable);
1054
1055 bus = bus->parent;
1056 }
1057
1058 /* We have reached the root bus. */
1059 if (bus->bridge) {
1060 if (acpi_pm_device_can_wakeup(bus->bridge))
1061 return acpi_pm_set_bridge_wakeup(bus->bridge, enable);
1062 }
1063 return 0;
1064}
1065
1066static int acpi_pci_wakeup(struct pci_dev *dev, bool enable)
1067{
1068 if (acpi_pm_device_can_wakeup(&dev->dev))
1069 return acpi_pm_set_device_wakeup(&dev->dev, enable);
1070
1071 return acpi_pci_propagate_wakeup(dev->bus, enable);
1072}
1073
1074static bool acpi_pci_need_resume(struct pci_dev *dev)
1075{
1076 struct acpi_device *adev = ACPI_COMPANION(&dev->dev);
1077
1078 /*
1079 * In some cases (eg. Samsung 305V4A) leaving a bridge in suspend over
1080 * system-wide suspend/resume confuses the platform firmware, so avoid
1081 * doing that. According to Section 16.1.6 of ACPI 6.2, endpoint
1082 * devices are expected to be in D3 before invoking the S3 entry path
1083 * from the firmware, so they should not be affected by this issue.
1084 */
1085 if (pci_is_bridge(dev) && acpi_target_system_state() != ACPI_STATE_S0)
1086 return true;
1087
1088 if (!adev || !acpi_device_power_manageable(adev))
1089 return false;
1090
1091 if (adev->wakeup.flags.valid &&
1092 device_may_wakeup(&dev->dev) != !!adev->wakeup.prepare_count)
1093 return true;
1094
1095 if (acpi_target_system_state() == ACPI_STATE_S0)
1096 return false;
1097
1098 return !!adev->power.flags.dsw_present;
1099}
1100
1101static const struct pci_platform_pm_ops acpi_pci_platform_pm = {
1102 .bridge_d3 = acpi_pci_bridge_d3,
1103 .is_manageable = acpi_pci_power_manageable,
1104 .set_state = acpi_pci_set_power_state,
1105 .get_state = acpi_pci_get_power_state,
1106 .refresh_state = acpi_pci_refresh_power_state,
1107 .choose_state = acpi_pci_choose_state,
1108 .set_wakeup = acpi_pci_wakeup,
1109 .need_resume = acpi_pci_need_resume,
1110};
1111
1112void acpi_pci_add_bus(struct pci_bus *bus)
1113{
1114 union acpi_object *obj;
1115 struct pci_host_bridge *bridge;
1116
1117 if (acpi_pci_disabled || !bus->bridge || !ACPI_HANDLE(bus->bridge))
1118 return;
1119
1120 acpi_pci_slot_enumerate(bus);
1121 acpiphp_enumerate_slots(bus);
1122
1123 /*
1124 * For a host bridge, check its _DSM for function 8 and if
1125 * that is available, mark it in pci_host_bridge.
1126 */
1127 if (!pci_is_root_bus(bus))
1128 return;
1129
1130 obj = acpi_evaluate_dsm(ACPI_HANDLE(bus->bridge), &pci_acpi_dsm_guid, 3,
1131 RESET_DELAY_DSM, NULL);
1132 if (!obj)
1133 return;
1134
1135 if (obj->type == ACPI_TYPE_INTEGER && obj->integer.value == 1) {
1136 bridge = pci_find_host_bridge(bus);
1137 bridge->ignore_reset_delay = 1;
1138 }
1139 ACPI_FREE(obj);
1140}
1141
1142void acpi_pci_remove_bus(struct pci_bus *bus)
1143{
1144 if (acpi_pci_disabled || !bus->bridge)
1145 return;
1146
1147 acpiphp_remove_slots(bus);
1148 acpi_pci_slot_remove(bus);
1149}
1150
1151/* ACPI bus type */
1152static struct acpi_device *acpi_pci_find_companion(struct device *dev)
1153{
1154 struct pci_dev *pci_dev = to_pci_dev(dev);
1155 bool check_children;
1156 u64 addr;
1157
1158 check_children = pci_is_bridge(pci_dev);
1159 /* Please ref to ACPI spec for the syntax of _ADR */
1160 addr = (PCI_SLOT(pci_dev->devfn) << 16) | PCI_FUNC(pci_dev->devfn);
1161 return acpi_find_child_device(ACPI_COMPANION(dev->parent), addr,
1162 check_children);
1163}
1164
1165/**
1166 * pci_acpi_optimize_delay - optimize PCI D3 and D3cold delay from ACPI
1167 * @pdev: the PCI device whose delay is to be updated
1168 * @handle: ACPI handle of this device
1169 *
1170 * Update the d3_delay and d3cold_delay of a PCI device from the ACPI _DSM
1171 * control method of either the device itself or the PCI host bridge.
1172 *
1173 * Function 8, "Reset Delay," applies to the entire hierarchy below a PCI
1174 * host bridge. If it returns one, the OS may assume that all devices in
1175 * the hierarchy have already completed power-on reset delays.
1176 *
1177 * Function 9, "Device Readiness Durations," applies only to the object
1178 * where it is located. It returns delay durations required after various
1179 * events if the device requires less time than the spec requires. Delays
1180 * from this function take precedence over the Reset Delay function.
1181 *
1182 * These _DSM functions are defined by the draft ECN of January 28, 2014,
1183 * titled "ACPI additions for FW latency optimizations."
1184 */
1185static void pci_acpi_optimize_delay(struct pci_dev *pdev,
1186 acpi_handle handle)
1187{
1188 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
1189 int value;
1190 union acpi_object *obj, *elements;
1191
1192 if (bridge->ignore_reset_delay)
1193 pdev->d3cold_delay = 0;
1194
1195 obj = acpi_evaluate_dsm(handle, &pci_acpi_dsm_guid, 3,
1196 FUNCTION_DELAY_DSM, NULL);
1197 if (!obj)
1198 return;
1199
1200 if (obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 5) {
1201 elements = obj->package.elements;
1202 if (elements[0].type == ACPI_TYPE_INTEGER) {
1203 value = (int)elements[0].integer.value / 1000;
1204 if (value < PCI_PM_D3COLD_WAIT)
1205 pdev->d3cold_delay = value;
1206 }
1207 if (elements[3].type == ACPI_TYPE_INTEGER) {
1208 value = (int)elements[3].integer.value / 1000;
1209 if (value < PCI_PM_D3_WAIT)
1210 pdev->d3_delay = value;
1211 }
1212 }
1213 ACPI_FREE(obj);
1214}
1215
1216static void pci_acpi_set_untrusted(struct pci_dev *dev)
1217{
1218 u8 val;
1219
1220 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
1221 return;
1222 if (device_property_read_u8(&dev->dev, "ExternalFacingPort", &val))
1223 return;
1224
1225 /*
1226 * These root ports expose PCIe (including DMA) outside of the
1227 * system so make sure we treat them and everything behind as
1228 * untrusted.
1229 */
1230 if (val)
1231 dev->untrusted = 1;
1232}
1233
1234static void pci_acpi_setup(struct device *dev)
1235{
1236 struct pci_dev *pci_dev = to_pci_dev(dev);
1237 struct acpi_device *adev = ACPI_COMPANION(dev);
1238
1239 if (!adev)
1240 return;
1241
1242 pci_acpi_optimize_delay(pci_dev, adev->handle);
1243 pci_acpi_set_untrusted(pci_dev);
1244
1245 pci_acpi_add_pm_notifier(adev, pci_dev);
1246 if (!adev->wakeup.flags.valid)
1247 return;
1248
1249 device_set_wakeup_capable(dev, true);
1250 /*
1251 * For bridges that can do D3 we enable wake automatically (as
1252 * we do for the power management itself in that case). The
1253 * reason is that the bridge may have additional methods such as
1254 * _DSW that need to be called.
1255 */
1256 if (pci_dev->bridge_d3)
1257 device_wakeup_enable(dev);
1258
1259 acpi_pci_wakeup(pci_dev, false);
1260 acpi_device_power_add_dependent(adev, dev);
1261}
1262
1263static void pci_acpi_cleanup(struct device *dev)
1264{
1265 struct acpi_device *adev = ACPI_COMPANION(dev);
1266 struct pci_dev *pci_dev = to_pci_dev(dev);
1267
1268 if (!adev)
1269 return;
1270
1271 pci_acpi_remove_pm_notifier(adev);
1272 if (adev->wakeup.flags.valid) {
1273 acpi_device_power_remove_dependent(adev, dev);
1274 if (pci_dev->bridge_d3)
1275 device_wakeup_disable(dev);
1276
1277 device_set_wakeup_capable(dev, false);
1278 }
1279}
1280
1281static bool pci_acpi_bus_match(struct device *dev)
1282{
1283 return dev_is_pci(dev);
1284}
1285
1286static struct acpi_bus_type acpi_pci_bus = {
1287 .name = "PCI",
1288 .match = pci_acpi_bus_match,
1289 .find_companion = acpi_pci_find_companion,
1290 .setup = pci_acpi_setup,
1291 .cleanup = pci_acpi_cleanup,
1292};
1293
1294
1295static struct fwnode_handle *(*pci_msi_get_fwnode_cb)(struct device *dev);
1296
1297/**
1298 * pci_msi_register_fwnode_provider - Register callback to retrieve fwnode
1299 * @fn: Callback matching a device to a fwnode that identifies a PCI
1300 * MSI domain.
1301 *
1302 * This should be called by irqchip driver, which is the parent of
1303 * the MSI domain to provide callback interface to query fwnode.
1304 */
1305void
1306pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *))
1307{
1308 pci_msi_get_fwnode_cb = fn;
1309}
1310
1311/**
1312 * pci_host_bridge_acpi_msi_domain - Retrieve MSI domain of a PCI host bridge
1313 * @bus: The PCI host bridge bus.
1314 *
1315 * This function uses the callback function registered by
1316 * pci_msi_register_fwnode_provider() to retrieve the irq_domain with
1317 * type DOMAIN_BUS_PCI_MSI of the specified host bridge bus.
1318 * This returns NULL on error or when the domain is not found.
1319 */
1320struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus)
1321{
1322 struct fwnode_handle *fwnode;
1323
1324 if (!pci_msi_get_fwnode_cb)
1325 return NULL;
1326
1327 fwnode = pci_msi_get_fwnode_cb(&bus->dev);
1328 if (!fwnode)
1329 return NULL;
1330
1331 return irq_find_matching_fwnode(fwnode, DOMAIN_BUS_PCI_MSI);
1332}
1333
1334static int __init acpi_pci_init(void)
1335{
1336 int ret;
1337
1338 if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_MSI) {
1339 pr_info("ACPI FADT declares the system doesn't support MSI, so disable it\n");
1340 pci_no_msi();
1341 }
1342
1343 if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) {
1344 pr_info("ACPI FADT declares the system doesn't support PCIe ASPM, so disable it\n");
1345 pcie_no_aspm();
1346 }
1347
1348 ret = register_acpi_bus_type(&acpi_pci_bus);
1349 if (ret)
1350 return 0;
1351
1352 pci_set_platform_pm(&acpi_pci_platform_pm);
1353 acpi_pci_slot_init();
1354 acpiphp_init();
1355
1356 return 0;
1357}
1358arch_initcall(acpi_pci_init);
1/*
2 * File: pci-acpi.c
3 * Purpose: Provide PCI support in ACPI
4 *
5 * Copyright (C) 2005 David Shaohua Li <shaohua.li@intel.com>
6 * Copyright (C) 2004 Tom Long Nguyen <tom.l.nguyen@intel.com>
7 * Copyright (C) 2004 Intel Corp.
8 */
9
10#include <linux/delay.h>
11#include <linux/init.h>
12#include <linux/irqdomain.h>
13#include <linux/pci.h>
14#include <linux/msi.h>
15#include <linux/pci_hotplug.h>
16#include <linux/module.h>
17#include <linux/pci-aspm.h>
18#include <linux/pci-acpi.h>
19#include <linux/pm_runtime.h>
20#include <linux/pm_qos.h>
21#include "pci.h"
22
23/*
24 * The UUID is defined in the PCI Firmware Specification available here:
25 * https://www.pcisig.com/members/downloads/pcifw_r3_1_13Dec10.pdf
26 */
27const u8 pci_acpi_dsm_uuid[] = {
28 0xd0, 0x37, 0xc9, 0xe5, 0x53, 0x35, 0x7a, 0x4d,
29 0x91, 0x17, 0xea, 0x4d, 0x19, 0xc3, 0x43, 0x4d
30};
31
32#if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
33static int acpi_get_rc_addr(struct acpi_device *adev, struct resource *res)
34{
35 struct device *dev = &adev->dev;
36 struct resource_entry *entry;
37 struct list_head list;
38 unsigned long flags;
39 int ret;
40
41 INIT_LIST_HEAD(&list);
42 flags = IORESOURCE_MEM;
43 ret = acpi_dev_get_resources(adev, &list,
44 acpi_dev_filter_resource_type_cb,
45 (void *) flags);
46 if (ret < 0) {
47 dev_err(dev, "failed to parse _CRS method, error code %d\n",
48 ret);
49 return ret;
50 }
51
52 if (ret == 0) {
53 dev_err(dev, "no IO and memory resources present in _CRS\n");
54 return -EINVAL;
55 }
56
57 entry = list_first_entry(&list, struct resource_entry, node);
58 *res = *entry->res;
59 acpi_dev_free_resource_list(&list);
60 return 0;
61}
62
63static acpi_status acpi_match_rc(acpi_handle handle, u32 lvl, void *context,
64 void **retval)
65{
66 u16 *segment = context;
67 unsigned long long uid;
68 acpi_status status;
69
70 status = acpi_evaluate_integer(handle, "_UID", NULL, &uid);
71 if (ACPI_FAILURE(status) || uid != *segment)
72 return AE_CTRL_DEPTH;
73
74 *(acpi_handle *)retval = handle;
75 return AE_CTRL_TERMINATE;
76}
77
78int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
79 struct resource *res)
80{
81 struct acpi_device *adev;
82 acpi_status status;
83 acpi_handle handle;
84 int ret;
85
86 status = acpi_get_devices(hid, acpi_match_rc, &segment, &handle);
87 if (ACPI_FAILURE(status)) {
88 dev_err(dev, "can't find _HID %s device to locate resources\n",
89 hid);
90 return -ENODEV;
91 }
92
93 ret = acpi_bus_get_device(handle, &adev);
94 if (ret)
95 return ret;
96
97 ret = acpi_get_rc_addr(adev, res);
98 if (ret) {
99 dev_err(dev, "can't get resource from %s\n",
100 dev_name(&adev->dev));
101 return ret;
102 }
103
104 return 0;
105}
106#endif
107
108phys_addr_t acpi_pci_root_get_mcfg_addr(acpi_handle handle)
109{
110 acpi_status status = AE_NOT_EXIST;
111 unsigned long long mcfg_addr;
112
113 if (handle)
114 status = acpi_evaluate_integer(handle, METHOD_NAME__CBA,
115 NULL, &mcfg_addr);
116 if (ACPI_FAILURE(status))
117 return 0;
118
119 return (phys_addr_t)mcfg_addr;
120}
121
122static acpi_status decode_type0_hpx_record(union acpi_object *record,
123 struct hotplug_params *hpx)
124{
125 int i;
126 union acpi_object *fields = record->package.elements;
127 u32 revision = fields[1].integer.value;
128
129 switch (revision) {
130 case 1:
131 if (record->package.count != 6)
132 return AE_ERROR;
133 for (i = 2; i < 6; i++)
134 if (fields[i].type != ACPI_TYPE_INTEGER)
135 return AE_ERROR;
136 hpx->t0 = &hpx->type0_data;
137 hpx->t0->revision = revision;
138 hpx->t0->cache_line_size = fields[2].integer.value;
139 hpx->t0->latency_timer = fields[3].integer.value;
140 hpx->t0->enable_serr = fields[4].integer.value;
141 hpx->t0->enable_perr = fields[5].integer.value;
142 break;
143 default:
144 printk(KERN_WARNING
145 "%s: Type 0 Revision %d record not supported\n",
146 __func__, revision);
147 return AE_ERROR;
148 }
149 return AE_OK;
150}
151
152static acpi_status decode_type1_hpx_record(union acpi_object *record,
153 struct hotplug_params *hpx)
154{
155 int i;
156 union acpi_object *fields = record->package.elements;
157 u32 revision = fields[1].integer.value;
158
159 switch (revision) {
160 case 1:
161 if (record->package.count != 5)
162 return AE_ERROR;
163 for (i = 2; i < 5; i++)
164 if (fields[i].type != ACPI_TYPE_INTEGER)
165 return AE_ERROR;
166 hpx->t1 = &hpx->type1_data;
167 hpx->t1->revision = revision;
168 hpx->t1->max_mem_read = fields[2].integer.value;
169 hpx->t1->avg_max_split = fields[3].integer.value;
170 hpx->t1->tot_max_split = fields[4].integer.value;
171 break;
172 default:
173 printk(KERN_WARNING
174 "%s: Type 1 Revision %d record not supported\n",
175 __func__, revision);
176 return AE_ERROR;
177 }
178 return AE_OK;
179}
180
181static acpi_status decode_type2_hpx_record(union acpi_object *record,
182 struct hotplug_params *hpx)
183{
184 int i;
185 union acpi_object *fields = record->package.elements;
186 u32 revision = fields[1].integer.value;
187
188 switch (revision) {
189 case 1:
190 if (record->package.count != 18)
191 return AE_ERROR;
192 for (i = 2; i < 18; i++)
193 if (fields[i].type != ACPI_TYPE_INTEGER)
194 return AE_ERROR;
195 hpx->t2 = &hpx->type2_data;
196 hpx->t2->revision = revision;
197 hpx->t2->unc_err_mask_and = fields[2].integer.value;
198 hpx->t2->unc_err_mask_or = fields[3].integer.value;
199 hpx->t2->unc_err_sever_and = fields[4].integer.value;
200 hpx->t2->unc_err_sever_or = fields[5].integer.value;
201 hpx->t2->cor_err_mask_and = fields[6].integer.value;
202 hpx->t2->cor_err_mask_or = fields[7].integer.value;
203 hpx->t2->adv_err_cap_and = fields[8].integer.value;
204 hpx->t2->adv_err_cap_or = fields[9].integer.value;
205 hpx->t2->pci_exp_devctl_and = fields[10].integer.value;
206 hpx->t2->pci_exp_devctl_or = fields[11].integer.value;
207 hpx->t2->pci_exp_lnkctl_and = fields[12].integer.value;
208 hpx->t2->pci_exp_lnkctl_or = fields[13].integer.value;
209 hpx->t2->sec_unc_err_sever_and = fields[14].integer.value;
210 hpx->t2->sec_unc_err_sever_or = fields[15].integer.value;
211 hpx->t2->sec_unc_err_mask_and = fields[16].integer.value;
212 hpx->t2->sec_unc_err_mask_or = fields[17].integer.value;
213 break;
214 default:
215 printk(KERN_WARNING
216 "%s: Type 2 Revision %d record not supported\n",
217 __func__, revision);
218 return AE_ERROR;
219 }
220 return AE_OK;
221}
222
223static acpi_status acpi_run_hpx(acpi_handle handle, struct hotplug_params *hpx)
224{
225 acpi_status status;
226 struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL};
227 union acpi_object *package, *record, *fields;
228 u32 type;
229 int i;
230
231 /* Clear the return buffer with zeros */
232 memset(hpx, 0, sizeof(struct hotplug_params));
233
234 status = acpi_evaluate_object(handle, "_HPX", NULL, &buffer);
235 if (ACPI_FAILURE(status))
236 return status;
237
238 package = (union acpi_object *)buffer.pointer;
239 if (package->type != ACPI_TYPE_PACKAGE) {
240 status = AE_ERROR;
241 goto exit;
242 }
243
244 for (i = 0; i < package->package.count; i++) {
245 record = &package->package.elements[i];
246 if (record->type != ACPI_TYPE_PACKAGE) {
247 status = AE_ERROR;
248 goto exit;
249 }
250
251 fields = record->package.elements;
252 if (fields[0].type != ACPI_TYPE_INTEGER ||
253 fields[1].type != ACPI_TYPE_INTEGER) {
254 status = AE_ERROR;
255 goto exit;
256 }
257
258 type = fields[0].integer.value;
259 switch (type) {
260 case 0:
261 status = decode_type0_hpx_record(record, hpx);
262 if (ACPI_FAILURE(status))
263 goto exit;
264 break;
265 case 1:
266 status = decode_type1_hpx_record(record, hpx);
267 if (ACPI_FAILURE(status))
268 goto exit;
269 break;
270 case 2:
271 status = decode_type2_hpx_record(record, hpx);
272 if (ACPI_FAILURE(status))
273 goto exit;
274 break;
275 default:
276 printk(KERN_ERR "%s: Type %d record not supported\n",
277 __func__, type);
278 status = AE_ERROR;
279 goto exit;
280 }
281 }
282 exit:
283 kfree(buffer.pointer);
284 return status;
285}
286
287static acpi_status acpi_run_hpp(acpi_handle handle, struct hotplug_params *hpp)
288{
289 acpi_status status;
290 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
291 union acpi_object *package, *fields;
292 int i;
293
294 memset(hpp, 0, sizeof(struct hotplug_params));
295
296 status = acpi_evaluate_object(handle, "_HPP", NULL, &buffer);
297 if (ACPI_FAILURE(status))
298 return status;
299
300 package = (union acpi_object *) buffer.pointer;
301 if (package->type != ACPI_TYPE_PACKAGE ||
302 package->package.count != 4) {
303 status = AE_ERROR;
304 goto exit;
305 }
306
307 fields = package->package.elements;
308 for (i = 0; i < 4; i++) {
309 if (fields[i].type != ACPI_TYPE_INTEGER) {
310 status = AE_ERROR;
311 goto exit;
312 }
313 }
314
315 hpp->t0 = &hpp->type0_data;
316 hpp->t0->revision = 1;
317 hpp->t0->cache_line_size = fields[0].integer.value;
318 hpp->t0->latency_timer = fields[1].integer.value;
319 hpp->t0->enable_serr = fields[2].integer.value;
320 hpp->t0->enable_perr = fields[3].integer.value;
321
322exit:
323 kfree(buffer.pointer);
324 return status;
325}
326
327/* pci_get_hp_params
328 *
329 * @dev - the pci_dev for which we want parameters
330 * @hpp - allocated by the caller
331 */
332int pci_get_hp_params(struct pci_dev *dev, struct hotplug_params *hpp)
333{
334 acpi_status status;
335 acpi_handle handle, phandle;
336 struct pci_bus *pbus;
337
338 if (acpi_pci_disabled)
339 return -ENODEV;
340
341 handle = NULL;
342 for (pbus = dev->bus; pbus; pbus = pbus->parent) {
343 handle = acpi_pci_get_bridge_handle(pbus);
344 if (handle)
345 break;
346 }
347
348 /*
349 * _HPP settings apply to all child buses, until another _HPP is
350 * encountered. If we don't find an _HPP for the input pci dev,
351 * look for it in the parent device scope since that would apply to
352 * this pci dev.
353 */
354 while (handle) {
355 status = acpi_run_hpx(handle, hpp);
356 if (ACPI_SUCCESS(status))
357 return 0;
358 status = acpi_run_hpp(handle, hpp);
359 if (ACPI_SUCCESS(status))
360 return 0;
361 if (acpi_is_root_bridge(handle))
362 break;
363 status = acpi_get_parent(handle, &phandle);
364 if (ACPI_FAILURE(status))
365 break;
366 handle = phandle;
367 }
368 return -ENODEV;
369}
370EXPORT_SYMBOL_GPL(pci_get_hp_params);
371
372/**
373 * pciehp_is_native - Check whether a hotplug port is handled by the OS
374 * @pdev: Hotplug port to check
375 *
376 * Walk up from @pdev to the host bridge, obtain its cached _OSC Control Field
377 * and return the value of the "PCI Express Native Hot Plug control" bit.
378 * On failure to obtain the _OSC Control Field return %false.
379 */
380bool pciehp_is_native(struct pci_dev *pdev)
381{
382 struct acpi_pci_root *root;
383 acpi_handle handle;
384
385 handle = acpi_find_root_bridge_handle(pdev);
386 if (!handle)
387 return false;
388
389 root = acpi_pci_find_root(handle);
390 if (!root)
391 return false;
392
393 return root->osc_control_set & OSC_PCI_EXPRESS_NATIVE_HP_CONTROL;
394}
395
396/**
397 * pci_acpi_wake_bus - Root bus wakeup notification fork function.
398 * @work: Work item to handle.
399 */
400static void pci_acpi_wake_bus(struct work_struct *work)
401{
402 struct acpi_device *adev;
403 struct acpi_pci_root *root;
404
405 adev = container_of(work, struct acpi_device, wakeup.context.work);
406 root = acpi_driver_data(adev);
407 pci_pme_wakeup_bus(root->bus);
408}
409
410/**
411 * pci_acpi_wake_dev - PCI device wakeup notification work function.
412 * @handle: ACPI handle of a device the notification is for.
413 * @work: Work item to handle.
414 */
415static void pci_acpi_wake_dev(struct work_struct *work)
416{
417 struct acpi_device_wakeup_context *context;
418 struct pci_dev *pci_dev;
419
420 context = container_of(work, struct acpi_device_wakeup_context, work);
421 pci_dev = to_pci_dev(context->dev);
422
423 if (pci_dev->pme_poll)
424 pci_dev->pme_poll = false;
425
426 if (pci_dev->current_state == PCI_D3cold) {
427 pci_wakeup_event(pci_dev);
428 pm_runtime_resume(&pci_dev->dev);
429 return;
430 }
431
432 /* Clear PME Status if set. */
433 if (pci_dev->pme_support)
434 pci_check_pme_status(pci_dev);
435
436 pci_wakeup_event(pci_dev);
437 pm_runtime_resume(&pci_dev->dev);
438
439 pci_pme_wakeup_bus(pci_dev->subordinate);
440}
441
442/**
443 * pci_acpi_add_bus_pm_notifier - Register PM notifier for root PCI bus.
444 * @dev: PCI root bridge ACPI device.
445 */
446acpi_status pci_acpi_add_bus_pm_notifier(struct acpi_device *dev)
447{
448 return acpi_add_pm_notifier(dev, NULL, pci_acpi_wake_bus);
449}
450
451/**
452 * pci_acpi_add_pm_notifier - Register PM notifier for given PCI device.
453 * @dev: ACPI device to add the notifier for.
454 * @pci_dev: PCI device to check for the PME status if an event is signaled.
455 */
456acpi_status pci_acpi_add_pm_notifier(struct acpi_device *dev,
457 struct pci_dev *pci_dev)
458{
459 return acpi_add_pm_notifier(dev, &pci_dev->dev, pci_acpi_wake_dev);
460}
461
462/*
463 * _SxD returns the D-state with the highest power
464 * (lowest D-state number) supported in the S-state "x".
465 *
466 * If the devices does not have a _PRW
467 * (Power Resources for Wake) supporting system wakeup from "x"
468 * then the OS is free to choose a lower power (higher number
469 * D-state) than the return value from _SxD.
470 *
471 * But if _PRW is enabled at S-state "x", the OS
472 * must not choose a power lower than _SxD --
473 * unless the device has an _SxW method specifying
474 * the lowest power (highest D-state number) the device
475 * may enter while still able to wake the system.
476 *
477 * ie. depending on global OS policy:
478 *
479 * if (_PRW at S-state x)
480 * choose from highest power _SxD to lowest power _SxW
481 * else // no _PRW at S-state x
482 * choose highest power _SxD or any lower power
483 */
484
485static pci_power_t acpi_pci_choose_state(struct pci_dev *pdev)
486{
487 int acpi_state, d_max;
488
489 if (pdev->no_d3cold)
490 d_max = ACPI_STATE_D3_HOT;
491 else
492 d_max = ACPI_STATE_D3_COLD;
493 acpi_state = acpi_pm_device_sleep_state(&pdev->dev, NULL, d_max);
494 if (acpi_state < 0)
495 return PCI_POWER_ERROR;
496
497 switch (acpi_state) {
498 case ACPI_STATE_D0:
499 return PCI_D0;
500 case ACPI_STATE_D1:
501 return PCI_D1;
502 case ACPI_STATE_D2:
503 return PCI_D2;
504 case ACPI_STATE_D3_HOT:
505 return PCI_D3hot;
506 case ACPI_STATE_D3_COLD:
507 return PCI_D3cold;
508 }
509 return PCI_POWER_ERROR;
510}
511
512static bool acpi_pci_power_manageable(struct pci_dev *dev)
513{
514 struct acpi_device *adev = ACPI_COMPANION(&dev->dev);
515 return adev ? acpi_device_power_manageable(adev) : false;
516}
517
518static int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state)
519{
520 struct acpi_device *adev = ACPI_COMPANION(&dev->dev);
521 static const u8 state_conv[] = {
522 [PCI_D0] = ACPI_STATE_D0,
523 [PCI_D1] = ACPI_STATE_D1,
524 [PCI_D2] = ACPI_STATE_D2,
525 [PCI_D3hot] = ACPI_STATE_D3_HOT,
526 [PCI_D3cold] = ACPI_STATE_D3_COLD,
527 };
528 int error = -EINVAL;
529
530 /* If the ACPI device has _EJ0, ignore the device */
531 if (!adev || acpi_has_method(adev->handle, "_EJ0"))
532 return -ENODEV;
533
534 switch (state) {
535 case PCI_D3cold:
536 if (dev_pm_qos_flags(&dev->dev, PM_QOS_FLAG_NO_POWER_OFF) ==
537 PM_QOS_FLAGS_ALL) {
538 error = -EBUSY;
539 break;
540 }
541 case PCI_D0:
542 case PCI_D1:
543 case PCI_D2:
544 case PCI_D3hot:
545 error = acpi_device_set_power(adev, state_conv[state]);
546 }
547
548 if (!error)
549 dev_dbg(&dev->dev, "power state changed by ACPI to %s\n",
550 acpi_power_state_string(state_conv[state]));
551
552 return error;
553}
554
555static pci_power_t acpi_pci_get_power_state(struct pci_dev *dev)
556{
557 struct acpi_device *adev = ACPI_COMPANION(&dev->dev);
558 static const pci_power_t state_conv[] = {
559 [ACPI_STATE_D0] = PCI_D0,
560 [ACPI_STATE_D1] = PCI_D1,
561 [ACPI_STATE_D2] = PCI_D2,
562 [ACPI_STATE_D3_HOT] = PCI_D3hot,
563 [ACPI_STATE_D3_COLD] = PCI_D3cold,
564 };
565 int state;
566
567 if (!adev || !acpi_device_power_manageable(adev))
568 return PCI_UNKNOWN;
569
570 if (acpi_device_get_power(adev, &state) || state == ACPI_STATE_UNKNOWN)
571 return PCI_UNKNOWN;
572
573 return state_conv[state];
574}
575
576static bool acpi_pci_can_wakeup(struct pci_dev *dev)
577{
578 struct acpi_device *adev = ACPI_COMPANION(&dev->dev);
579 return adev ? acpi_device_can_wakeup(adev) : false;
580}
581
582static void acpi_pci_propagate_wakeup_enable(struct pci_bus *bus, bool enable)
583{
584 while (bus->parent) {
585 if (!acpi_pm_device_sleep_wake(&bus->self->dev, enable))
586 return;
587 bus = bus->parent;
588 }
589
590 /* We have reached the root bus. */
591 if (bus->bridge)
592 acpi_pm_device_sleep_wake(bus->bridge, enable);
593}
594
595static int acpi_pci_sleep_wake(struct pci_dev *dev, bool enable)
596{
597 if (acpi_pci_can_wakeup(dev))
598 return acpi_pm_device_sleep_wake(&dev->dev, enable);
599
600 acpi_pci_propagate_wakeup_enable(dev->bus, enable);
601 return 0;
602}
603
604static void acpi_pci_propagate_run_wake(struct pci_bus *bus, bool enable)
605{
606 while (bus->parent) {
607 struct pci_dev *bridge = bus->self;
608
609 if (bridge->pme_interrupt)
610 return;
611 if (!acpi_pm_device_run_wake(&bridge->dev, enable))
612 return;
613 bus = bus->parent;
614 }
615
616 /* We have reached the root bus. */
617 if (bus->bridge)
618 acpi_pm_device_run_wake(bus->bridge, enable);
619}
620
621static int acpi_pci_run_wake(struct pci_dev *dev, bool enable)
622{
623 /*
624 * Per PCI Express Base Specification Revision 2.0 section
625 * 5.3.3.2 Link Wakeup, platform support is needed for D3cold
626 * waking up to power on the main link even if there is PME
627 * support for D3cold
628 */
629 if (dev->pme_interrupt && !dev->runtime_d3cold)
630 return 0;
631
632 if (!acpi_pm_device_run_wake(&dev->dev, enable))
633 return 0;
634
635 acpi_pci_propagate_run_wake(dev->bus, enable);
636 return 0;
637}
638
639static bool acpi_pci_need_resume(struct pci_dev *dev)
640{
641 struct acpi_device *adev = ACPI_COMPANION(&dev->dev);
642
643 if (!adev || !acpi_device_power_manageable(adev))
644 return false;
645
646 if (device_may_wakeup(&dev->dev) != !!adev->wakeup.prepare_count)
647 return true;
648
649 if (acpi_target_system_state() == ACPI_STATE_S0)
650 return false;
651
652 return !!adev->power.flags.dsw_present;
653}
654
655static const struct pci_platform_pm_ops acpi_pci_platform_pm = {
656 .is_manageable = acpi_pci_power_manageable,
657 .set_state = acpi_pci_set_power_state,
658 .get_state = acpi_pci_get_power_state,
659 .choose_state = acpi_pci_choose_state,
660 .sleep_wake = acpi_pci_sleep_wake,
661 .run_wake = acpi_pci_run_wake,
662 .need_resume = acpi_pci_need_resume,
663};
664
665void acpi_pci_add_bus(struct pci_bus *bus)
666{
667 union acpi_object *obj;
668 struct pci_host_bridge *bridge;
669
670 if (acpi_pci_disabled || !bus->bridge)
671 return;
672
673 acpi_pci_slot_enumerate(bus);
674 acpiphp_enumerate_slots(bus);
675
676 /*
677 * For a host bridge, check its _DSM for function 8 and if
678 * that is available, mark it in pci_host_bridge.
679 */
680 if (!pci_is_root_bus(bus))
681 return;
682
683 obj = acpi_evaluate_dsm(ACPI_HANDLE(bus->bridge), pci_acpi_dsm_uuid, 3,
684 RESET_DELAY_DSM, NULL);
685 if (!obj)
686 return;
687
688 if (obj->type == ACPI_TYPE_INTEGER && obj->integer.value == 1) {
689 bridge = pci_find_host_bridge(bus);
690 bridge->ignore_reset_delay = 1;
691 }
692 ACPI_FREE(obj);
693}
694
695void acpi_pci_remove_bus(struct pci_bus *bus)
696{
697 if (acpi_pci_disabled || !bus->bridge)
698 return;
699
700 acpiphp_remove_slots(bus);
701 acpi_pci_slot_remove(bus);
702}
703
704/* ACPI bus type */
705static struct acpi_device *acpi_pci_find_companion(struct device *dev)
706{
707 struct pci_dev *pci_dev = to_pci_dev(dev);
708 bool check_children;
709 u64 addr;
710
711 check_children = pci_is_bridge(pci_dev);
712 /* Please ref to ACPI spec for the syntax of _ADR */
713 addr = (PCI_SLOT(pci_dev->devfn) << 16) | PCI_FUNC(pci_dev->devfn);
714 return acpi_find_child_device(ACPI_COMPANION(dev->parent), addr,
715 check_children);
716}
717
718/**
719 * pci_acpi_optimize_delay - optimize PCI D3 and D3cold delay from ACPI
720 * @pdev: the PCI device whose delay is to be updated
721 * @handle: ACPI handle of this device
722 *
723 * Update the d3_delay and d3cold_delay of a PCI device from the ACPI _DSM
724 * control method of either the device itself or the PCI host bridge.
725 *
726 * Function 8, "Reset Delay," applies to the entire hierarchy below a PCI
727 * host bridge. If it returns one, the OS may assume that all devices in
728 * the hierarchy have already completed power-on reset delays.
729 *
730 * Function 9, "Device Readiness Durations," applies only to the object
731 * where it is located. It returns delay durations required after various
732 * events if the device requires less time than the spec requires. Delays
733 * from this function take precedence over the Reset Delay function.
734 *
735 * These _DSM functions are defined by the draft ECN of January 28, 2014,
736 * titled "ACPI additions for FW latency optimizations."
737 */
738static void pci_acpi_optimize_delay(struct pci_dev *pdev,
739 acpi_handle handle)
740{
741 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
742 int value;
743 union acpi_object *obj, *elements;
744
745 if (bridge->ignore_reset_delay)
746 pdev->d3cold_delay = 0;
747
748 obj = acpi_evaluate_dsm(handle, pci_acpi_dsm_uuid, 3,
749 FUNCTION_DELAY_DSM, NULL);
750 if (!obj)
751 return;
752
753 if (obj->type == ACPI_TYPE_PACKAGE && obj->package.count == 5) {
754 elements = obj->package.elements;
755 if (elements[0].type == ACPI_TYPE_INTEGER) {
756 value = (int)elements[0].integer.value / 1000;
757 if (value < PCI_PM_D3COLD_WAIT)
758 pdev->d3cold_delay = value;
759 }
760 if (elements[3].type == ACPI_TYPE_INTEGER) {
761 value = (int)elements[3].integer.value / 1000;
762 if (value < PCI_PM_D3_WAIT)
763 pdev->d3_delay = value;
764 }
765 }
766 ACPI_FREE(obj);
767}
768
769static void pci_acpi_setup(struct device *dev)
770{
771 struct pci_dev *pci_dev = to_pci_dev(dev);
772 struct acpi_device *adev = ACPI_COMPANION(dev);
773
774 if (!adev)
775 return;
776
777 pci_acpi_optimize_delay(pci_dev, adev->handle);
778
779 pci_acpi_add_pm_notifier(adev, pci_dev);
780 if (!adev->wakeup.flags.valid)
781 return;
782
783 device_set_wakeup_capable(dev, true);
784 acpi_pci_sleep_wake(pci_dev, false);
785 if (adev->wakeup.flags.run_wake)
786 device_set_run_wake(dev, true);
787}
788
789static void pci_acpi_cleanup(struct device *dev)
790{
791 struct acpi_device *adev = ACPI_COMPANION(dev);
792
793 if (!adev)
794 return;
795
796 pci_acpi_remove_pm_notifier(adev);
797 if (adev->wakeup.flags.valid) {
798 device_set_wakeup_capable(dev, false);
799 device_set_run_wake(dev, false);
800 }
801}
802
803static bool pci_acpi_bus_match(struct device *dev)
804{
805 return dev_is_pci(dev);
806}
807
808static struct acpi_bus_type acpi_pci_bus = {
809 .name = "PCI",
810 .match = pci_acpi_bus_match,
811 .find_companion = acpi_pci_find_companion,
812 .setup = pci_acpi_setup,
813 .cleanup = pci_acpi_cleanup,
814};
815
816
817static struct fwnode_handle *(*pci_msi_get_fwnode_cb)(struct device *dev);
818
819/**
820 * pci_msi_register_fwnode_provider - Register callback to retrieve fwnode
821 * @fn: Callback matching a device to a fwnode that identifies a PCI
822 * MSI domain.
823 *
824 * This should be called by irqchip driver, which is the parent of
825 * the MSI domain to provide callback interface to query fwnode.
826 */
827void
828pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *))
829{
830 pci_msi_get_fwnode_cb = fn;
831}
832
833/**
834 * pci_host_bridge_acpi_msi_domain - Retrieve MSI domain of a PCI host bridge
835 * @bus: The PCI host bridge bus.
836 *
837 * This function uses the callback function registered by
838 * pci_msi_register_fwnode_provider() to retrieve the irq_domain with
839 * type DOMAIN_BUS_PCI_MSI of the specified host bridge bus.
840 * This returns NULL on error or when the domain is not found.
841 */
842struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus)
843{
844 struct fwnode_handle *fwnode;
845
846 if (!pci_msi_get_fwnode_cb)
847 return NULL;
848
849 fwnode = pci_msi_get_fwnode_cb(&bus->dev);
850 if (!fwnode)
851 return NULL;
852
853 return irq_find_matching_fwnode(fwnode, DOMAIN_BUS_PCI_MSI);
854}
855
856static int __init acpi_pci_init(void)
857{
858 int ret;
859
860 if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_MSI) {
861 pr_info("ACPI FADT declares the system doesn't support MSI, so disable it\n");
862 pci_no_msi();
863 }
864
865 if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) {
866 pr_info("ACPI FADT declares the system doesn't support PCIe ASPM, so disable it\n");
867 pcie_no_aspm();
868 }
869
870 ret = register_acpi_bus_type(&acpi_pci_bus);
871 if (ret)
872 return 0;
873
874 pci_set_platform_pm(&acpi_pci_platform_pm);
875 acpi_pci_slot_init();
876 acpiphp_init();
877
878 return 0;
879}
880arch_initcall(acpi_pci_init);