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1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Compaq Hot Plug Controller Driver
4 *
5 * Copyright (C) 1995,2001 Compaq Computer Corporation
6 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
7 * Copyright (C) 2001 IBM Corp.
8 *
9 * All rights reserved.
10 *
11 * Send feedback to <greg@kroah.com>
12 *
13 */
14
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/types.h>
18#include <linux/slab.h>
19#include <linux/workqueue.h>
20#include <linux/proc_fs.h>
21#include <linux/pci.h>
22#include <linux/pci_hotplug.h>
23#include "../pci.h"
24#include "cpqphp.h"
25#include "cpqphp_nvram.h"
26
27
28u8 cpqhp_nic_irq;
29u8 cpqhp_disk_irq;
30
31static u16 unused_IRQ;
32
33/*
34 * detect_HRT_floating_pointer
35 *
36 * find the Hot Plug Resource Table in the specified region of memory.
37 *
38 */
39static void __iomem *detect_HRT_floating_pointer(void __iomem *begin, void __iomem *end)
40{
41 void __iomem *fp;
42 void __iomem *endp;
43 u8 temp1, temp2, temp3, temp4;
44 int status = 0;
45
46 endp = (end - sizeof(struct hrt) + 1);
47
48 for (fp = begin; fp <= endp; fp += 16) {
49 temp1 = readb(fp + SIG0);
50 temp2 = readb(fp + SIG1);
51 temp3 = readb(fp + SIG2);
52 temp4 = readb(fp + SIG3);
53 if (temp1 == '$' &&
54 temp2 == 'H' &&
55 temp3 == 'R' &&
56 temp4 == 'T') {
57 status = 1;
58 break;
59 }
60 }
61
62 if (!status)
63 fp = NULL;
64
65 dbg("Discovered Hotplug Resource Table at %p\n", fp);
66 return fp;
67}
68
69
70int cpqhp_configure_device(struct controller *ctrl, struct pci_func *func)
71{
72 struct pci_bus *child;
73 int num;
74
75 pci_lock_rescan_remove();
76
77 if (func->pci_dev == NULL)
78 func->pci_dev = pci_get_domain_bus_and_slot(0, func->bus,
79 PCI_DEVFN(func->device,
80 func->function));
81
82 /* No pci device, we need to create it then */
83 if (func->pci_dev == NULL) {
84 dbg("INFO: pci_dev still null\n");
85
86 num = pci_scan_slot(ctrl->pci_dev->bus, PCI_DEVFN(func->device, func->function));
87 if (num)
88 pci_bus_add_devices(ctrl->pci_dev->bus);
89
90 func->pci_dev = pci_get_domain_bus_and_slot(0, func->bus,
91 PCI_DEVFN(func->device,
92 func->function));
93 if (func->pci_dev == NULL) {
94 dbg("ERROR: pci_dev still null\n");
95 goto out;
96 }
97 }
98
99 if (func->pci_dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
100 pci_hp_add_bridge(func->pci_dev);
101 child = func->pci_dev->subordinate;
102 if (child)
103 pci_bus_add_devices(child);
104 }
105
106 pci_dev_put(func->pci_dev);
107
108 out:
109 pci_unlock_rescan_remove();
110 return 0;
111}
112
113
114int cpqhp_unconfigure_device(struct pci_func *func)
115{
116 int j;
117
118 dbg("%s: bus/dev/func = %x/%x/%x\n", __func__, func->bus, func->device, func->function);
119
120 pci_lock_rescan_remove();
121 for (j = 0; j < 8 ; j++) {
122 struct pci_dev *temp = pci_get_domain_bus_and_slot(0,
123 func->bus,
124 PCI_DEVFN(func->device,
125 j));
126 if (temp) {
127 pci_dev_put(temp);
128 pci_stop_and_remove_bus_device(temp);
129 }
130 }
131 pci_unlock_rescan_remove();
132 return 0;
133}
134
135static int PCI_RefinedAccessConfig(struct pci_bus *bus, unsigned int devfn, u8 offset, u32 *value)
136{
137 u32 vendID = 0;
138
139 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &vendID) == -1)
140 return -1;
141 if (vendID == 0xffffffff)
142 return -1;
143 return pci_bus_read_config_dword(bus, devfn, offset, value);
144}
145
146
147/*
148 * cpqhp_set_irq
149 *
150 * @bus_num: bus number of PCI device
151 * @dev_num: device number of PCI device
152 * @slot: pointer to u8 where slot number will be returned
153 */
154int cpqhp_set_irq(u8 bus_num, u8 dev_num, u8 int_pin, u8 irq_num)
155{
156 int rc = 0;
157
158 if (cpqhp_legacy_mode) {
159 struct pci_dev *fakedev;
160 struct pci_bus *fakebus;
161 u16 temp_word;
162
163 fakedev = kmalloc(sizeof(*fakedev), GFP_KERNEL);
164 fakebus = kmalloc(sizeof(*fakebus), GFP_KERNEL);
165 if (!fakedev || !fakebus) {
166 kfree(fakedev);
167 kfree(fakebus);
168 return -ENOMEM;
169 }
170
171 fakedev->devfn = dev_num << 3;
172 fakedev->bus = fakebus;
173 fakebus->number = bus_num;
174 dbg("%s: dev %d, bus %d, pin %d, num %d\n",
175 __func__, dev_num, bus_num, int_pin, irq_num);
176 rc = pcibios_set_irq_routing(fakedev, int_pin - 1, irq_num);
177 kfree(fakedev);
178 kfree(fakebus);
179 dbg("%s: rc %d\n", __func__, rc);
180 if (!rc)
181 return !rc;
182
183 /* set the Edge Level Control Register (ELCR) */
184 temp_word = inb(0x4d0);
185 temp_word |= inb(0x4d1) << 8;
186
187 temp_word |= 0x01 << irq_num;
188
189 /* This should only be for x86 as it sets the Edge Level
190 * Control Register
191 */
192 outb((u8) (temp_word & 0xFF), 0x4d0); outb((u8) ((temp_word &
193 0xFF00) >> 8), 0x4d1); rc = 0; }
194
195 return rc;
196}
197
198
199static int PCI_ScanBusForNonBridge(struct controller *ctrl, u8 bus_num, u8 *dev_num)
200{
201 u16 tdevice;
202 u32 work;
203 u8 tbus;
204
205 ctrl->pci_bus->number = bus_num;
206
207 for (tdevice = 0; tdevice < 0xFF; tdevice++) {
208 /* Scan for access first */
209 if (PCI_RefinedAccessConfig(ctrl->pci_bus, tdevice, 0x08, &work) == -1)
210 continue;
211 dbg("Looking for nonbridge bus_num %d dev_num %d\n", bus_num, tdevice);
212 /* Yep we got one. Not a bridge ? */
213 if ((work >> 8) != PCI_TO_PCI_BRIDGE_CLASS) {
214 *dev_num = tdevice;
215 dbg("found it !\n");
216 return 0;
217 }
218 }
219 for (tdevice = 0; tdevice < 0xFF; tdevice++) {
220 /* Scan for access first */
221 if (PCI_RefinedAccessConfig(ctrl->pci_bus, tdevice, 0x08, &work) == -1)
222 continue;
223 dbg("Looking for bridge bus_num %d dev_num %d\n", bus_num, tdevice);
224 /* Yep we got one. bridge ? */
225 if ((work >> 8) == PCI_TO_PCI_BRIDGE_CLASS) {
226 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(tdevice, 0), PCI_SECONDARY_BUS, &tbus);
227 /* XXX: no recursion, wtf? */
228 dbg("Recurse on bus_num %d tdevice %d\n", tbus, tdevice);
229 return 0;
230 }
231 }
232
233 return -1;
234}
235
236
237static int PCI_GetBusDevHelper(struct controller *ctrl, u8 *bus_num, u8 *dev_num, u8 slot, u8 nobridge)
238{
239 int loop, len;
240 u32 work;
241 u8 tbus, tdevice, tslot;
242
243 len = cpqhp_routing_table_length();
244 for (loop = 0; loop < len; ++loop) {
245 tbus = cpqhp_routing_table->slots[loop].bus;
246 tdevice = cpqhp_routing_table->slots[loop].devfn;
247 tslot = cpqhp_routing_table->slots[loop].slot;
248
249 if (tslot == slot) {
250 *bus_num = tbus;
251 *dev_num = tdevice;
252 ctrl->pci_bus->number = tbus;
253 pci_bus_read_config_dword(ctrl->pci_bus, *dev_num, PCI_VENDOR_ID, &work);
254 if (!nobridge || (work == 0xffffffff))
255 return 0;
256
257 dbg("bus_num %d devfn %d\n", *bus_num, *dev_num);
258 pci_bus_read_config_dword(ctrl->pci_bus, *dev_num, PCI_CLASS_REVISION, &work);
259 dbg("work >> 8 (%x) = BRIDGE (%x)\n", work >> 8, PCI_TO_PCI_BRIDGE_CLASS);
260
261 if ((work >> 8) == PCI_TO_PCI_BRIDGE_CLASS) {
262 pci_bus_read_config_byte(ctrl->pci_bus, *dev_num, PCI_SECONDARY_BUS, &tbus);
263 dbg("Scan bus for Non Bridge: bus %d\n", tbus);
264 if (PCI_ScanBusForNonBridge(ctrl, tbus, dev_num) == 0) {
265 *bus_num = tbus;
266 return 0;
267 }
268 } else
269 return 0;
270 }
271 }
272 return -1;
273}
274
275
276int cpqhp_get_bus_dev(struct controller *ctrl, u8 *bus_num, u8 *dev_num, u8 slot)
277{
278 /* plain (bridges allowed) */
279 return PCI_GetBusDevHelper(ctrl, bus_num, dev_num, slot, 0);
280}
281
282
283/* More PCI configuration routines; this time centered around hotplug
284 * controller
285 */
286
287
288/*
289 * cpqhp_save_config
290 *
291 * Reads configuration for all slots in a PCI bus and saves info.
292 *
293 * Note: For non-hot plug buses, the slot # saved is the device #
294 *
295 * returns 0 if success
296 */
297int cpqhp_save_config(struct controller *ctrl, int busnumber, int is_hot_plug)
298{
299 long rc;
300 u8 class_code;
301 u8 header_type;
302 u32 ID;
303 u8 secondary_bus;
304 struct pci_func *new_slot;
305 int sub_bus;
306 int FirstSupported;
307 int LastSupported;
308 int max_functions;
309 int function;
310 u8 DevError;
311 int device = 0;
312 int cloop = 0;
313 int stop_it;
314 int index;
315 u16 devfn;
316
317 /* Decide which slots are supported */
318
319 if (is_hot_plug) {
320 /*
321 * is_hot_plug is the slot mask
322 */
323 FirstSupported = is_hot_plug >> 4;
324 LastSupported = FirstSupported + (is_hot_plug & 0x0F) - 1;
325 } else {
326 FirstSupported = 0;
327 LastSupported = 0x1F;
328 }
329
330 /* Save PCI configuration space for all devices in supported slots */
331 ctrl->pci_bus->number = busnumber;
332 for (device = FirstSupported; device <= LastSupported; device++) {
333 ID = 0xFFFFFFFF;
334 rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, 0), PCI_VENDOR_ID, &ID);
335
336 if (ID == 0xFFFFFFFF) {
337 if (is_hot_plug) {
338 /* Setup slot structure with entry for empty
339 * slot
340 */
341 new_slot = cpqhp_slot_create(busnumber);
342 if (new_slot == NULL)
343 return 1;
344
345 new_slot->bus = (u8) busnumber;
346 new_slot->device = (u8) device;
347 new_slot->function = 0;
348 new_slot->is_a_board = 0;
349 new_slot->presence_save = 0;
350 new_slot->switch_save = 0;
351 }
352 continue;
353 }
354
355 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, 0), 0x0B, &class_code);
356 if (rc)
357 return rc;
358
359 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, 0), PCI_HEADER_TYPE, &header_type);
360 if (rc)
361 return rc;
362
363 /* If multi-function device, set max_functions to 8 */
364 if (header_type & 0x80)
365 max_functions = 8;
366 else
367 max_functions = 1;
368
369 function = 0;
370
371 do {
372 DevError = 0;
373 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
374 /* Recurse the subordinate bus
375 * get the subordinate bus number
376 */
377 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, function), PCI_SECONDARY_BUS, &secondary_bus);
378 if (rc) {
379 return rc;
380 } else {
381 sub_bus = (int) secondary_bus;
382
383 /* Save secondary bus cfg spc
384 * with this recursive call.
385 */
386 rc = cpqhp_save_config(ctrl, sub_bus, 0);
387 if (rc)
388 return rc;
389 ctrl->pci_bus->number = busnumber;
390 }
391 }
392
393 index = 0;
394 new_slot = cpqhp_slot_find(busnumber, device, index++);
395 while (new_slot &&
396 (new_slot->function != (u8) function))
397 new_slot = cpqhp_slot_find(busnumber, device, index++);
398
399 if (!new_slot) {
400 /* Setup slot structure. */
401 new_slot = cpqhp_slot_create(busnumber);
402 if (new_slot == NULL)
403 return 1;
404 }
405
406 new_slot->bus = (u8) busnumber;
407 new_slot->device = (u8) device;
408 new_slot->function = (u8) function;
409 new_slot->is_a_board = 1;
410 new_slot->switch_save = 0x10;
411 /* In case of unsupported board */
412 new_slot->status = DevError;
413 devfn = (new_slot->device << 3) | new_slot->function;
414 new_slot->pci_dev = pci_get_domain_bus_and_slot(0,
415 new_slot->bus, devfn);
416
417 for (cloop = 0; cloop < 0x20; cloop++) {
418 rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, function), cloop << 2, (u32 *) &(new_slot->config_space[cloop]));
419 if (rc)
420 return rc;
421 }
422
423 pci_dev_put(new_slot->pci_dev);
424
425 function++;
426
427 stop_it = 0;
428
429 /* this loop skips to the next present function
430 * reading in Class Code and Header type.
431 */
432 while ((function < max_functions) && (!stop_it)) {
433 rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, function), PCI_VENDOR_ID, &ID);
434 if (ID == 0xFFFFFFFF) {
435 function++;
436 continue;
437 }
438 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, function), 0x0B, &class_code);
439 if (rc)
440 return rc;
441
442 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, function), PCI_HEADER_TYPE, &header_type);
443 if (rc)
444 return rc;
445
446 stop_it++;
447 }
448
449 } while (function < max_functions);
450 } /* End of FOR loop */
451
452 return 0;
453}
454
455
456/*
457 * cpqhp_save_slot_config
458 *
459 * Saves configuration info for all PCI devices in a given slot
460 * including subordinate buses.
461 *
462 * returns 0 if success
463 */
464int cpqhp_save_slot_config(struct controller *ctrl, struct pci_func *new_slot)
465{
466 long rc;
467 u8 class_code;
468 u8 header_type;
469 u32 ID;
470 u8 secondary_bus;
471 int sub_bus;
472 int max_functions;
473 int function = 0;
474 int cloop = 0;
475 int stop_it;
476
477 ID = 0xFFFFFFFF;
478
479 ctrl->pci_bus->number = new_slot->bus;
480 pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), PCI_VENDOR_ID, &ID);
481
482 if (ID == 0xFFFFFFFF)
483 return 2;
484
485 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), 0x0B, &class_code);
486 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), PCI_HEADER_TYPE, &header_type);
487
488 if (header_type & 0x80) /* Multi-function device */
489 max_functions = 8;
490 else
491 max_functions = 1;
492
493 while (function < max_functions) {
494 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
495 /* Recurse the subordinate bus */
496 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_SECONDARY_BUS, &secondary_bus);
497
498 sub_bus = (int) secondary_bus;
499
500 /* Save the config headers for the secondary
501 * bus.
502 */
503 rc = cpqhp_save_config(ctrl, sub_bus, 0);
504 if (rc)
505 return(rc);
506 ctrl->pci_bus->number = new_slot->bus;
507
508 }
509
510 new_slot->status = 0;
511
512 for (cloop = 0; cloop < 0x20; cloop++)
513 pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), cloop << 2, (u32 *) &(new_slot->config_space[cloop]));
514
515 function++;
516
517 stop_it = 0;
518
519 /* this loop skips to the next present function
520 * reading in the Class Code and the Header type.
521 */
522 while ((function < max_functions) && (!stop_it)) {
523 pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_VENDOR_ID, &ID);
524
525 if (ID == 0xFFFFFFFF)
526 function++;
527 else {
528 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), 0x0B, &class_code);
529 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_HEADER_TYPE, &header_type);
530 stop_it++;
531 }
532 }
533
534 }
535
536 return 0;
537}
538
539
540/*
541 * cpqhp_save_base_addr_length
542 *
543 * Saves the length of all base address registers for the
544 * specified slot. this is for hot plug REPLACE
545 *
546 * returns 0 if success
547 */
548int cpqhp_save_base_addr_length(struct controller *ctrl, struct pci_func *func)
549{
550 u8 cloop;
551 u8 header_type;
552 u8 secondary_bus;
553 u8 type;
554 int sub_bus;
555 u32 temp_register;
556 u32 base;
557 u32 rc;
558 struct pci_func *next;
559 int index = 0;
560 struct pci_bus *pci_bus = ctrl->pci_bus;
561 unsigned int devfn;
562
563 func = cpqhp_slot_find(func->bus, func->device, index++);
564
565 while (func != NULL) {
566 pci_bus->number = func->bus;
567 devfn = PCI_DEVFN(func->device, func->function);
568
569 /* Check for Bridge */
570 pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
571
572 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
573 pci_bus_read_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus);
574
575 sub_bus = (int) secondary_bus;
576
577 next = cpqhp_slot_list[sub_bus];
578
579 while (next != NULL) {
580 rc = cpqhp_save_base_addr_length(ctrl, next);
581 if (rc)
582 return rc;
583
584 next = next->next;
585 }
586 pci_bus->number = func->bus;
587
588 /* FIXME: this loop is duplicated in the non-bridge
589 * case. The two could be rolled together Figure out
590 * IO and memory base lengths
591 */
592 for (cloop = 0x10; cloop <= 0x14; cloop += 4) {
593 temp_register = 0xFFFFFFFF;
594 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
595 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
596 /* If this register is implemented */
597 if (base) {
598 if (base & 0x01L) {
599 /* IO base
600 * set base = amount of IO space
601 * requested
602 */
603 base = base & 0xFFFFFFFE;
604 base = (~base) + 1;
605
606 type = 1;
607 } else {
608 /* memory base */
609 base = base & 0xFFFFFFF0;
610 base = (~base) + 1;
611
612 type = 0;
613 }
614 } else {
615 base = 0x0L;
616 type = 0;
617 }
618
619 /* Save information in slot structure */
620 func->base_length[(cloop - 0x10) >> 2] =
621 base;
622 func->base_type[(cloop - 0x10) >> 2] = type;
623
624 } /* End of base register loop */
625
626 } else if ((header_type & 0x7F) == 0x00) {
627 /* Figure out IO and memory base lengths */
628 for (cloop = 0x10; cloop <= 0x24; cloop += 4) {
629 temp_register = 0xFFFFFFFF;
630 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
631 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
632
633 /* If this register is implemented */
634 if (base) {
635 if (base & 0x01L) {
636 /* IO base
637 * base = amount of IO space
638 * requested
639 */
640 base = base & 0xFFFFFFFE;
641 base = (~base) + 1;
642
643 type = 1;
644 } else {
645 /* memory base
646 * base = amount of memory
647 * space requested
648 */
649 base = base & 0xFFFFFFF0;
650 base = (~base) + 1;
651
652 type = 0;
653 }
654 } else {
655 base = 0x0L;
656 type = 0;
657 }
658
659 /* Save information in slot structure */
660 func->base_length[(cloop - 0x10) >> 2] = base;
661 func->base_type[(cloop - 0x10) >> 2] = type;
662
663 } /* End of base register loop */
664
665 } else { /* Some other unknown header type */
666 }
667
668 /* find the next device in this slot */
669 func = cpqhp_slot_find(func->bus, func->device, index++);
670 }
671
672 return(0);
673}
674
675
676/*
677 * cpqhp_save_used_resources
678 *
679 * Stores used resource information for existing boards. this is
680 * for boards that were in the system when this driver was loaded.
681 * this function is for hot plug ADD
682 *
683 * returns 0 if success
684 */
685int cpqhp_save_used_resources(struct controller *ctrl, struct pci_func *func)
686{
687 u8 cloop;
688 u8 header_type;
689 u8 secondary_bus;
690 u8 temp_byte;
691 u8 b_base;
692 u8 b_length;
693 u16 command;
694 u16 save_command;
695 u16 w_base;
696 u16 w_length;
697 u32 temp_register;
698 u32 save_base;
699 u32 base;
700 int index = 0;
701 struct pci_resource *mem_node;
702 struct pci_resource *p_mem_node;
703 struct pci_resource *io_node;
704 struct pci_resource *bus_node;
705 struct pci_bus *pci_bus = ctrl->pci_bus;
706 unsigned int devfn;
707
708 func = cpqhp_slot_find(func->bus, func->device, index++);
709
710 while ((func != NULL) && func->is_a_board) {
711 pci_bus->number = func->bus;
712 devfn = PCI_DEVFN(func->device, func->function);
713
714 /* Save the command register */
715 pci_bus_read_config_word(pci_bus, devfn, PCI_COMMAND, &save_command);
716
717 /* disable card */
718 command = 0x00;
719 pci_bus_write_config_word(pci_bus, devfn, PCI_COMMAND, command);
720
721 /* Check for Bridge */
722 pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
723
724 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
725 /* Clear Bridge Control Register */
726 command = 0x00;
727 pci_bus_write_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, command);
728 pci_bus_read_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus);
729 pci_bus_read_config_byte(pci_bus, devfn, PCI_SUBORDINATE_BUS, &temp_byte);
730
731 bus_node = kmalloc(sizeof(*bus_node), GFP_KERNEL);
732 if (!bus_node)
733 return -ENOMEM;
734
735 bus_node->base = secondary_bus;
736 bus_node->length = temp_byte - secondary_bus + 1;
737
738 bus_node->next = func->bus_head;
739 func->bus_head = bus_node;
740
741 /* Save IO base and Limit registers */
742 pci_bus_read_config_byte(pci_bus, devfn, PCI_IO_BASE, &b_base);
743 pci_bus_read_config_byte(pci_bus, devfn, PCI_IO_LIMIT, &b_length);
744
745 if ((b_base <= b_length) && (save_command & 0x01)) {
746 io_node = kmalloc(sizeof(*io_node), GFP_KERNEL);
747 if (!io_node)
748 return -ENOMEM;
749
750 io_node->base = (b_base & 0xF0) << 8;
751 io_node->length = (b_length - b_base + 0x10) << 8;
752
753 io_node->next = func->io_head;
754 func->io_head = io_node;
755 }
756
757 /* Save memory base and Limit registers */
758 pci_bus_read_config_word(pci_bus, devfn, PCI_MEMORY_BASE, &w_base);
759 pci_bus_read_config_word(pci_bus, devfn, PCI_MEMORY_LIMIT, &w_length);
760
761 if ((w_base <= w_length) && (save_command & 0x02)) {
762 mem_node = kmalloc(sizeof(*mem_node), GFP_KERNEL);
763 if (!mem_node)
764 return -ENOMEM;
765
766 mem_node->base = w_base << 16;
767 mem_node->length = (w_length - w_base + 0x10) << 16;
768
769 mem_node->next = func->mem_head;
770 func->mem_head = mem_node;
771 }
772
773 /* Save prefetchable memory base and Limit registers */
774 pci_bus_read_config_word(pci_bus, devfn, PCI_PREF_MEMORY_BASE, &w_base);
775 pci_bus_read_config_word(pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, &w_length);
776
777 if ((w_base <= w_length) && (save_command & 0x02)) {
778 p_mem_node = kmalloc(sizeof(*p_mem_node), GFP_KERNEL);
779 if (!p_mem_node)
780 return -ENOMEM;
781
782 p_mem_node->base = w_base << 16;
783 p_mem_node->length = (w_length - w_base + 0x10) << 16;
784
785 p_mem_node->next = func->p_mem_head;
786 func->p_mem_head = p_mem_node;
787 }
788 /* Figure out IO and memory base lengths */
789 for (cloop = 0x10; cloop <= 0x14; cloop += 4) {
790 pci_bus_read_config_dword(pci_bus, devfn, cloop, &save_base);
791
792 temp_register = 0xFFFFFFFF;
793 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
794 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
795
796 temp_register = base;
797
798 /* If this register is implemented */
799 if (base) {
800 if (((base & 0x03L) == 0x01)
801 && (save_command & 0x01)) {
802 /* IO base
803 * set temp_register = amount
804 * of IO space requested
805 */
806 temp_register = base & 0xFFFFFFFE;
807 temp_register = (~temp_register) + 1;
808
809 io_node = kmalloc(sizeof(*io_node),
810 GFP_KERNEL);
811 if (!io_node)
812 return -ENOMEM;
813
814 io_node->base =
815 save_base & (~0x03L);
816 io_node->length = temp_register;
817
818 io_node->next = func->io_head;
819 func->io_head = io_node;
820 } else
821 if (((base & 0x0BL) == 0x08)
822 && (save_command & 0x02)) {
823 /* prefetchable memory base */
824 temp_register = base & 0xFFFFFFF0;
825 temp_register = (~temp_register) + 1;
826
827 p_mem_node = kmalloc(sizeof(*p_mem_node),
828 GFP_KERNEL);
829 if (!p_mem_node)
830 return -ENOMEM;
831
832 p_mem_node->base = save_base & (~0x0FL);
833 p_mem_node->length = temp_register;
834
835 p_mem_node->next = func->p_mem_head;
836 func->p_mem_head = p_mem_node;
837 } else
838 if (((base & 0x0BL) == 0x00)
839 && (save_command & 0x02)) {
840 /* prefetchable memory base */
841 temp_register = base & 0xFFFFFFF0;
842 temp_register = (~temp_register) + 1;
843
844 mem_node = kmalloc(sizeof(*mem_node),
845 GFP_KERNEL);
846 if (!mem_node)
847 return -ENOMEM;
848
849 mem_node->base = save_base & (~0x0FL);
850 mem_node->length = temp_register;
851
852 mem_node->next = func->mem_head;
853 func->mem_head = mem_node;
854 } else
855 return(1);
856 }
857 } /* End of base register loop */
858 /* Standard header */
859 } else if ((header_type & 0x7F) == 0x00) {
860 /* Figure out IO and memory base lengths */
861 for (cloop = 0x10; cloop <= 0x24; cloop += 4) {
862 pci_bus_read_config_dword(pci_bus, devfn, cloop, &save_base);
863
864 temp_register = 0xFFFFFFFF;
865 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
866 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
867
868 temp_register = base;
869
870 /* If this register is implemented */
871 if (base) {
872 if (((base & 0x03L) == 0x01)
873 && (save_command & 0x01)) {
874 /* IO base
875 * set temp_register = amount
876 * of IO space requested
877 */
878 temp_register = base & 0xFFFFFFFE;
879 temp_register = (~temp_register) + 1;
880
881 io_node = kmalloc(sizeof(*io_node),
882 GFP_KERNEL);
883 if (!io_node)
884 return -ENOMEM;
885
886 io_node->base = save_base & (~0x01L);
887 io_node->length = temp_register;
888
889 io_node->next = func->io_head;
890 func->io_head = io_node;
891 } else
892 if (((base & 0x0BL) == 0x08)
893 && (save_command & 0x02)) {
894 /* prefetchable memory base */
895 temp_register = base & 0xFFFFFFF0;
896 temp_register = (~temp_register) + 1;
897
898 p_mem_node = kmalloc(sizeof(*p_mem_node),
899 GFP_KERNEL);
900 if (!p_mem_node)
901 return -ENOMEM;
902
903 p_mem_node->base = save_base & (~0x0FL);
904 p_mem_node->length = temp_register;
905
906 p_mem_node->next = func->p_mem_head;
907 func->p_mem_head = p_mem_node;
908 } else
909 if (((base & 0x0BL) == 0x00)
910 && (save_command & 0x02)) {
911 /* prefetchable memory base */
912 temp_register = base & 0xFFFFFFF0;
913 temp_register = (~temp_register) + 1;
914
915 mem_node = kmalloc(sizeof(*mem_node),
916 GFP_KERNEL);
917 if (!mem_node)
918 return -ENOMEM;
919
920 mem_node->base = save_base & (~0x0FL);
921 mem_node->length = temp_register;
922
923 mem_node->next = func->mem_head;
924 func->mem_head = mem_node;
925 } else
926 return(1);
927 }
928 } /* End of base register loop */
929 }
930
931 /* find the next device in this slot */
932 func = cpqhp_slot_find(func->bus, func->device, index++);
933 }
934
935 return 0;
936}
937
938
939/*
940 * cpqhp_configure_board
941 *
942 * Copies saved configuration information to one slot.
943 * this is called recursively for bridge devices.
944 * this is for hot plug REPLACE!
945 *
946 * returns 0 if success
947 */
948int cpqhp_configure_board(struct controller *ctrl, struct pci_func *func)
949{
950 int cloop;
951 u8 header_type;
952 u8 secondary_bus;
953 int sub_bus;
954 struct pci_func *next;
955 u32 temp;
956 u32 rc;
957 int index = 0;
958 struct pci_bus *pci_bus = ctrl->pci_bus;
959 unsigned int devfn;
960
961 func = cpqhp_slot_find(func->bus, func->device, index++);
962
963 while (func != NULL) {
964 pci_bus->number = func->bus;
965 devfn = PCI_DEVFN(func->device, func->function);
966
967 /* Start at the top of config space so that the control
968 * registers are programmed last
969 */
970 for (cloop = 0x3C; cloop > 0; cloop -= 4)
971 pci_bus_write_config_dword(pci_bus, devfn, cloop, func->config_space[cloop >> 2]);
972
973 pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
974
975 /* If this is a bridge device, restore subordinate devices */
976 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
977 pci_bus_read_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus);
978
979 sub_bus = (int) secondary_bus;
980
981 next = cpqhp_slot_list[sub_bus];
982
983 while (next != NULL) {
984 rc = cpqhp_configure_board(ctrl, next);
985 if (rc)
986 return rc;
987
988 next = next->next;
989 }
990 } else {
991
992 /* Check all the base Address Registers to make sure
993 * they are the same. If not, the board is different.
994 */
995
996 for (cloop = 16; cloop < 40; cloop += 4) {
997 pci_bus_read_config_dword(pci_bus, devfn, cloop, &temp);
998
999 if (temp != func->config_space[cloop >> 2]) {
1000 dbg("Config space compare failure!!! offset = %x\n", cloop);
1001 dbg("bus = %x, device = %x, function = %x\n", func->bus, func->device, func->function);
1002 dbg("temp = %x, config space = %x\n\n", temp, func->config_space[cloop >> 2]);
1003 return 1;
1004 }
1005 }
1006 }
1007
1008 func->configured = 1;
1009
1010 func = cpqhp_slot_find(func->bus, func->device, index++);
1011 }
1012
1013 return 0;
1014}
1015
1016
1017/*
1018 * cpqhp_valid_replace
1019 *
1020 * this function checks to see if a board is the same as the
1021 * one it is replacing. this check will detect if the device's
1022 * vendor or device id's are the same
1023 *
1024 * returns 0 if the board is the same nonzero otherwise
1025 */
1026int cpqhp_valid_replace(struct controller *ctrl, struct pci_func *func)
1027{
1028 u8 cloop;
1029 u8 header_type;
1030 u8 secondary_bus;
1031 u8 type;
1032 u32 temp_register = 0;
1033 u32 base;
1034 u32 rc;
1035 struct pci_func *next;
1036 int index = 0;
1037 struct pci_bus *pci_bus = ctrl->pci_bus;
1038 unsigned int devfn;
1039
1040 if (!func->is_a_board)
1041 return(ADD_NOT_SUPPORTED);
1042
1043 func = cpqhp_slot_find(func->bus, func->device, index++);
1044
1045 while (func != NULL) {
1046 pci_bus->number = func->bus;
1047 devfn = PCI_DEVFN(func->device, func->function);
1048
1049 pci_bus_read_config_dword(pci_bus, devfn, PCI_VENDOR_ID, &temp_register);
1050
1051 /* No adapter present */
1052 if (temp_register == 0xFFFFFFFF)
1053 return(NO_ADAPTER_PRESENT);
1054
1055 if (temp_register != func->config_space[0])
1056 return(ADAPTER_NOT_SAME);
1057
1058 /* Check for same revision number and class code */
1059 pci_bus_read_config_dword(pci_bus, devfn, PCI_CLASS_REVISION, &temp_register);
1060
1061 /* Adapter not the same */
1062 if (temp_register != func->config_space[0x08 >> 2])
1063 return(ADAPTER_NOT_SAME);
1064
1065 /* Check for Bridge */
1066 pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
1067
1068 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
1069 /* In order to continue checking, we must program the
1070 * bus registers in the bridge to respond to accesses
1071 * for its subordinate bus(es)
1072 */
1073
1074 temp_register = func->config_space[0x18 >> 2];
1075 pci_bus_write_config_dword(pci_bus, devfn, PCI_PRIMARY_BUS, temp_register);
1076
1077 secondary_bus = (temp_register >> 8) & 0xFF;
1078
1079 next = cpqhp_slot_list[secondary_bus];
1080
1081 while (next != NULL) {
1082 rc = cpqhp_valid_replace(ctrl, next);
1083 if (rc)
1084 return rc;
1085
1086 next = next->next;
1087 }
1088
1089 }
1090 /* Check to see if it is a standard config header */
1091 else if ((header_type & 0x7F) == PCI_HEADER_TYPE_NORMAL) {
1092 /* Check subsystem vendor and ID */
1093 pci_bus_read_config_dword(pci_bus, devfn, PCI_SUBSYSTEM_VENDOR_ID, &temp_register);
1094
1095 if (temp_register != func->config_space[0x2C >> 2]) {
1096 /* If it's a SMART-2 and the register isn't
1097 * filled in, ignore the difference because
1098 * they just have an old rev of the firmware
1099 */
1100 if (!((func->config_space[0] == 0xAE100E11)
1101 && (temp_register == 0x00L)))
1102 return(ADAPTER_NOT_SAME);
1103 }
1104 /* Figure out IO and memory base lengths */
1105 for (cloop = 0x10; cloop <= 0x24; cloop += 4) {
1106 temp_register = 0xFFFFFFFF;
1107 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
1108 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
1109
1110 /* If this register is implemented */
1111 if (base) {
1112 if (base & 0x01L) {
1113 /* IO base
1114 * set base = amount of IO
1115 * space requested
1116 */
1117 base = base & 0xFFFFFFFE;
1118 base = (~base) + 1;
1119
1120 type = 1;
1121 } else {
1122 /* memory base */
1123 base = base & 0xFFFFFFF0;
1124 base = (~base) + 1;
1125
1126 type = 0;
1127 }
1128 } else {
1129 base = 0x0L;
1130 type = 0;
1131 }
1132
1133 /* Check information in slot structure */
1134 if (func->base_length[(cloop - 0x10) >> 2] != base)
1135 return(ADAPTER_NOT_SAME);
1136
1137 if (func->base_type[(cloop - 0x10) >> 2] != type)
1138 return(ADAPTER_NOT_SAME);
1139
1140 } /* End of base register loop */
1141
1142 } /* End of (type 0 config space) else */
1143 else {
1144 /* this is not a type 0 or 1 config space header so
1145 * we don't know how to do it
1146 */
1147 return(DEVICE_TYPE_NOT_SUPPORTED);
1148 }
1149
1150 /* Get the next function */
1151 func = cpqhp_slot_find(func->bus, func->device, index++);
1152 }
1153
1154
1155 return 0;
1156}
1157
1158
1159/*
1160 * cpqhp_find_available_resources
1161 *
1162 * Finds available memory, IO, and IRQ resources for programming
1163 * devices which may be added to the system
1164 * this function is for hot plug ADD!
1165 *
1166 * returns 0 if success
1167 */
1168int cpqhp_find_available_resources(struct controller *ctrl, void __iomem *rom_start)
1169{
1170 u8 temp;
1171 u8 populated_slot;
1172 u8 bridged_slot;
1173 void __iomem *one_slot;
1174 void __iomem *rom_resource_table;
1175 struct pci_func *func = NULL;
1176 int i = 10, index;
1177 u32 temp_dword, rc;
1178 struct pci_resource *mem_node;
1179 struct pci_resource *p_mem_node;
1180 struct pci_resource *io_node;
1181 struct pci_resource *bus_node;
1182
1183 rom_resource_table = detect_HRT_floating_pointer(rom_start, rom_start+0xffff);
1184 dbg("rom_resource_table = %p\n", rom_resource_table);
1185
1186 if (rom_resource_table == NULL)
1187 return -ENODEV;
1188
1189 /* Sum all resources and setup resource maps */
1190 unused_IRQ = readl(rom_resource_table + UNUSED_IRQ);
1191 dbg("unused_IRQ = %x\n", unused_IRQ);
1192
1193 temp = 0;
1194 while (unused_IRQ) {
1195 if (unused_IRQ & 1) {
1196 cpqhp_disk_irq = temp;
1197 break;
1198 }
1199 unused_IRQ = unused_IRQ >> 1;
1200 temp++;
1201 }
1202
1203 dbg("cpqhp_disk_irq= %d\n", cpqhp_disk_irq);
1204 unused_IRQ = unused_IRQ >> 1;
1205 temp++;
1206
1207 while (unused_IRQ) {
1208 if (unused_IRQ & 1) {
1209 cpqhp_nic_irq = temp;
1210 break;
1211 }
1212 unused_IRQ = unused_IRQ >> 1;
1213 temp++;
1214 }
1215
1216 dbg("cpqhp_nic_irq= %d\n", cpqhp_nic_irq);
1217 unused_IRQ = readl(rom_resource_table + PCIIRQ);
1218
1219 temp = 0;
1220
1221 if (!cpqhp_nic_irq)
1222 cpqhp_nic_irq = ctrl->cfgspc_irq;
1223
1224 if (!cpqhp_disk_irq)
1225 cpqhp_disk_irq = ctrl->cfgspc_irq;
1226
1227 dbg("cpqhp_disk_irq, cpqhp_nic_irq= %d, %d\n", cpqhp_disk_irq, cpqhp_nic_irq);
1228
1229 rc = compaq_nvram_load(rom_start, ctrl);
1230 if (rc)
1231 return rc;
1232
1233 one_slot = rom_resource_table + sizeof(struct hrt);
1234
1235 i = readb(rom_resource_table + NUMBER_OF_ENTRIES);
1236 dbg("number_of_entries = %d\n", i);
1237
1238 if (!readb(one_slot + SECONDARY_BUS))
1239 return 1;
1240
1241 dbg("dev|IO base|length|Mem base|length|Pre base|length|PB SB MB\n");
1242
1243 while (i && readb(one_slot + SECONDARY_BUS)) {
1244 u8 dev_func = readb(one_slot + DEV_FUNC);
1245 u8 primary_bus = readb(one_slot + PRIMARY_BUS);
1246 u8 secondary_bus = readb(one_slot + SECONDARY_BUS);
1247 u8 max_bus = readb(one_slot + MAX_BUS);
1248 u16 io_base = readw(one_slot + IO_BASE);
1249 u16 io_length = readw(one_slot + IO_LENGTH);
1250 u16 mem_base = readw(one_slot + MEM_BASE);
1251 u16 mem_length = readw(one_slot + MEM_LENGTH);
1252 u16 pre_mem_base = readw(one_slot + PRE_MEM_BASE);
1253 u16 pre_mem_length = readw(one_slot + PRE_MEM_LENGTH);
1254
1255 dbg("%2.2x | %4.4x | %4.4x | %4.4x | %4.4x | %4.4x | %4.4x |%2.2x %2.2x %2.2x\n",
1256 dev_func, io_base, io_length, mem_base, mem_length, pre_mem_base, pre_mem_length,
1257 primary_bus, secondary_bus, max_bus);
1258
1259 /* If this entry isn't for our controller's bus, ignore it */
1260 if (primary_bus != ctrl->bus) {
1261 i--;
1262 one_slot += sizeof(struct slot_rt);
1263 continue;
1264 }
1265 /* find out if this entry is for an occupied slot */
1266 ctrl->pci_bus->number = primary_bus;
1267 pci_bus_read_config_dword(ctrl->pci_bus, dev_func, PCI_VENDOR_ID, &temp_dword);
1268 dbg("temp_D_word = %x\n", temp_dword);
1269
1270 if (temp_dword != 0xFFFFFFFF) {
1271 index = 0;
1272 func = cpqhp_slot_find(primary_bus, dev_func >> 3, 0);
1273
1274 while (func && (func->function != (dev_func & 0x07))) {
1275 dbg("func = %p (bus, dev, fun) = (%d, %d, %d)\n", func, primary_bus, dev_func >> 3, index);
1276 func = cpqhp_slot_find(primary_bus, dev_func >> 3, index++);
1277 }
1278
1279 /* If we can't find a match, skip this table entry */
1280 if (!func) {
1281 i--;
1282 one_slot += sizeof(struct slot_rt);
1283 continue;
1284 }
1285 /* this may not work and shouldn't be used */
1286 if (secondary_bus != primary_bus)
1287 bridged_slot = 1;
1288 else
1289 bridged_slot = 0;
1290
1291 populated_slot = 1;
1292 } else {
1293 populated_slot = 0;
1294 bridged_slot = 0;
1295 }
1296
1297
1298 /* If we've got a valid IO base, use it */
1299
1300 temp_dword = io_base + io_length;
1301
1302 if ((io_base) && (temp_dword < 0x10000)) {
1303 io_node = kmalloc(sizeof(*io_node), GFP_KERNEL);
1304 if (!io_node)
1305 return -ENOMEM;
1306
1307 io_node->base = io_base;
1308 io_node->length = io_length;
1309
1310 dbg("found io_node(base, length) = %x, %x\n",
1311 io_node->base, io_node->length);
1312 dbg("populated slot =%d \n", populated_slot);
1313 if (!populated_slot) {
1314 io_node->next = ctrl->io_head;
1315 ctrl->io_head = io_node;
1316 } else {
1317 io_node->next = func->io_head;
1318 func->io_head = io_node;
1319 }
1320 }
1321
1322 /* If we've got a valid memory base, use it */
1323 temp_dword = mem_base + mem_length;
1324 if ((mem_base) && (temp_dword < 0x10000)) {
1325 mem_node = kmalloc(sizeof(*mem_node), GFP_KERNEL);
1326 if (!mem_node)
1327 return -ENOMEM;
1328
1329 mem_node->base = mem_base << 16;
1330
1331 mem_node->length = mem_length << 16;
1332
1333 dbg("found mem_node(base, length) = %x, %x\n",
1334 mem_node->base, mem_node->length);
1335 dbg("populated slot =%d \n", populated_slot);
1336 if (!populated_slot) {
1337 mem_node->next = ctrl->mem_head;
1338 ctrl->mem_head = mem_node;
1339 } else {
1340 mem_node->next = func->mem_head;
1341 func->mem_head = mem_node;
1342 }
1343 }
1344
1345 /* If we've got a valid prefetchable memory base, and
1346 * the base + length isn't greater than 0xFFFF
1347 */
1348 temp_dword = pre_mem_base + pre_mem_length;
1349 if ((pre_mem_base) && (temp_dword < 0x10000)) {
1350 p_mem_node = kmalloc(sizeof(*p_mem_node), GFP_KERNEL);
1351 if (!p_mem_node)
1352 return -ENOMEM;
1353
1354 p_mem_node->base = pre_mem_base << 16;
1355
1356 p_mem_node->length = pre_mem_length << 16;
1357 dbg("found p_mem_node(base, length) = %x, %x\n",
1358 p_mem_node->base, p_mem_node->length);
1359 dbg("populated slot =%d \n", populated_slot);
1360
1361 if (!populated_slot) {
1362 p_mem_node->next = ctrl->p_mem_head;
1363 ctrl->p_mem_head = p_mem_node;
1364 } else {
1365 p_mem_node->next = func->p_mem_head;
1366 func->p_mem_head = p_mem_node;
1367 }
1368 }
1369
1370 /* If we've got a valid bus number, use it
1371 * The second condition is to ignore bus numbers on
1372 * populated slots that don't have PCI-PCI bridges
1373 */
1374 if (secondary_bus && (secondary_bus != primary_bus)) {
1375 bus_node = kmalloc(sizeof(*bus_node), GFP_KERNEL);
1376 if (!bus_node)
1377 return -ENOMEM;
1378
1379 bus_node->base = secondary_bus;
1380 bus_node->length = max_bus - secondary_bus + 1;
1381 dbg("found bus_node(base, length) = %x, %x\n",
1382 bus_node->base, bus_node->length);
1383 dbg("populated slot =%d \n", populated_slot);
1384 if (!populated_slot) {
1385 bus_node->next = ctrl->bus_head;
1386 ctrl->bus_head = bus_node;
1387 } else {
1388 bus_node->next = func->bus_head;
1389 func->bus_head = bus_node;
1390 }
1391 }
1392
1393 i--;
1394 one_slot += sizeof(struct slot_rt);
1395 }
1396
1397 /* If all of the following fail, we don't have any resources for
1398 * hot plug add
1399 */
1400 rc = 1;
1401 rc &= cpqhp_resource_sort_and_combine(&(ctrl->mem_head));
1402 rc &= cpqhp_resource_sort_and_combine(&(ctrl->p_mem_head));
1403 rc &= cpqhp_resource_sort_and_combine(&(ctrl->io_head));
1404 rc &= cpqhp_resource_sort_and_combine(&(ctrl->bus_head));
1405
1406 return rc;
1407}
1408
1409
1410/*
1411 * cpqhp_return_board_resources
1412 *
1413 * this routine returns all resources allocated to a board to
1414 * the available pool.
1415 *
1416 * returns 0 if success
1417 */
1418int cpqhp_return_board_resources(struct pci_func *func, struct resource_lists *resources)
1419{
1420 int rc = 0;
1421 struct pci_resource *node;
1422 struct pci_resource *t_node;
1423 dbg("%s\n", __func__);
1424
1425 if (!func)
1426 return 1;
1427
1428 node = func->io_head;
1429 func->io_head = NULL;
1430 while (node) {
1431 t_node = node->next;
1432 return_resource(&(resources->io_head), node);
1433 node = t_node;
1434 }
1435
1436 node = func->mem_head;
1437 func->mem_head = NULL;
1438 while (node) {
1439 t_node = node->next;
1440 return_resource(&(resources->mem_head), node);
1441 node = t_node;
1442 }
1443
1444 node = func->p_mem_head;
1445 func->p_mem_head = NULL;
1446 while (node) {
1447 t_node = node->next;
1448 return_resource(&(resources->p_mem_head), node);
1449 node = t_node;
1450 }
1451
1452 node = func->bus_head;
1453 func->bus_head = NULL;
1454 while (node) {
1455 t_node = node->next;
1456 return_resource(&(resources->bus_head), node);
1457 node = t_node;
1458 }
1459
1460 rc |= cpqhp_resource_sort_and_combine(&(resources->mem_head));
1461 rc |= cpqhp_resource_sort_and_combine(&(resources->p_mem_head));
1462 rc |= cpqhp_resource_sort_and_combine(&(resources->io_head));
1463 rc |= cpqhp_resource_sort_and_combine(&(resources->bus_head));
1464
1465 return rc;
1466}
1467
1468
1469/*
1470 * cpqhp_destroy_resource_list
1471 *
1472 * Puts node back in the resource list pointed to by head
1473 */
1474void cpqhp_destroy_resource_list(struct resource_lists *resources)
1475{
1476 struct pci_resource *res, *tres;
1477
1478 res = resources->io_head;
1479 resources->io_head = NULL;
1480
1481 while (res) {
1482 tres = res;
1483 res = res->next;
1484 kfree(tres);
1485 }
1486
1487 res = resources->mem_head;
1488 resources->mem_head = NULL;
1489
1490 while (res) {
1491 tres = res;
1492 res = res->next;
1493 kfree(tres);
1494 }
1495
1496 res = resources->p_mem_head;
1497 resources->p_mem_head = NULL;
1498
1499 while (res) {
1500 tres = res;
1501 res = res->next;
1502 kfree(tres);
1503 }
1504
1505 res = resources->bus_head;
1506 resources->bus_head = NULL;
1507
1508 while (res) {
1509 tres = res;
1510 res = res->next;
1511 kfree(tres);
1512 }
1513}
1514
1515
1516/*
1517 * cpqhp_destroy_board_resources
1518 *
1519 * Puts node back in the resource list pointed to by head
1520 */
1521void cpqhp_destroy_board_resources(struct pci_func *func)
1522{
1523 struct pci_resource *res, *tres;
1524
1525 res = func->io_head;
1526 func->io_head = NULL;
1527
1528 while (res) {
1529 tres = res;
1530 res = res->next;
1531 kfree(tres);
1532 }
1533
1534 res = func->mem_head;
1535 func->mem_head = NULL;
1536
1537 while (res) {
1538 tres = res;
1539 res = res->next;
1540 kfree(tres);
1541 }
1542
1543 res = func->p_mem_head;
1544 func->p_mem_head = NULL;
1545
1546 while (res) {
1547 tres = res;
1548 res = res->next;
1549 kfree(tres);
1550 }
1551
1552 res = func->bus_head;
1553 func->bus_head = NULL;
1554
1555 while (res) {
1556 tres = res;
1557 res = res->next;
1558 kfree(tres);
1559 }
1560}
1/*
2 * Compaq Hot Plug Controller Driver
3 *
4 * Copyright (C) 1995,2001 Compaq Computer Corporation
5 * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
6 * Copyright (C) 2001 IBM Corp.
7 *
8 * All rights reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or (at
13 * your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful, but
16 * WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
18 * NON INFRINGEMENT. See the GNU General Public License for more
19 * details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 * Send feedback to <greg@kroah.com>
26 *
27 */
28
29#include <linux/module.h>
30#include <linux/kernel.h>
31#include <linux/types.h>
32#include <linux/slab.h>
33#include <linux/workqueue.h>
34#include <linux/proc_fs.h>
35#include <linux/pci.h>
36#include <linux/pci_hotplug.h>
37#include "../pci.h"
38#include "cpqphp.h"
39#include "cpqphp_nvram.h"
40
41
42u8 cpqhp_nic_irq;
43u8 cpqhp_disk_irq;
44
45static u16 unused_IRQ;
46
47/*
48 * detect_HRT_floating_pointer
49 *
50 * find the Hot Plug Resource Table in the specified region of memory.
51 *
52 */
53static void __iomem *detect_HRT_floating_pointer(void __iomem *begin, void __iomem *end)
54{
55 void __iomem *fp;
56 void __iomem *endp;
57 u8 temp1, temp2, temp3, temp4;
58 int status = 0;
59
60 endp = (end - sizeof(struct hrt) + 1);
61
62 for (fp = begin; fp <= endp; fp += 16) {
63 temp1 = readb(fp + SIG0);
64 temp2 = readb(fp + SIG1);
65 temp3 = readb(fp + SIG2);
66 temp4 = readb(fp + SIG3);
67 if (temp1 == '$' &&
68 temp2 == 'H' &&
69 temp3 == 'R' &&
70 temp4 == 'T') {
71 status = 1;
72 break;
73 }
74 }
75
76 if (!status)
77 fp = NULL;
78
79 dbg("Discovered Hotplug Resource Table at %p\n", fp);
80 return fp;
81}
82
83
84int cpqhp_configure_device(struct controller *ctrl, struct pci_func *func)
85{
86 struct pci_bus *child;
87 int num;
88
89 pci_lock_rescan_remove();
90
91 if (func->pci_dev == NULL)
92 func->pci_dev = pci_get_bus_and_slot(func->bus, PCI_DEVFN(func->device, func->function));
93
94 /* No pci device, we need to create it then */
95 if (func->pci_dev == NULL) {
96 dbg("INFO: pci_dev still null\n");
97
98 num = pci_scan_slot(ctrl->pci_dev->bus, PCI_DEVFN(func->device, func->function));
99 if (num)
100 pci_bus_add_devices(ctrl->pci_dev->bus);
101
102 func->pci_dev = pci_get_bus_and_slot(func->bus, PCI_DEVFN(func->device, func->function));
103 if (func->pci_dev == NULL) {
104 dbg("ERROR: pci_dev still null\n");
105 goto out;
106 }
107 }
108
109 if (func->pci_dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
110 pci_hp_add_bridge(func->pci_dev);
111 child = func->pci_dev->subordinate;
112 if (child)
113 pci_bus_add_devices(child);
114 }
115
116 pci_dev_put(func->pci_dev);
117
118 out:
119 pci_unlock_rescan_remove();
120 return 0;
121}
122
123
124int cpqhp_unconfigure_device(struct pci_func *func)
125{
126 int j;
127
128 dbg("%s: bus/dev/func = %x/%x/%x\n", __func__, func->bus, func->device, func->function);
129
130 pci_lock_rescan_remove();
131 for (j = 0; j < 8 ; j++) {
132 struct pci_dev *temp = pci_get_bus_and_slot(func->bus, PCI_DEVFN(func->device, j));
133 if (temp) {
134 pci_dev_put(temp);
135 pci_stop_and_remove_bus_device(temp);
136 }
137 }
138 pci_unlock_rescan_remove();
139 return 0;
140}
141
142static int PCI_RefinedAccessConfig(struct pci_bus *bus, unsigned int devfn, u8 offset, u32 *value)
143{
144 u32 vendID = 0;
145
146 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &vendID) == -1)
147 return -1;
148 if (vendID == 0xffffffff)
149 return -1;
150 return pci_bus_read_config_dword(bus, devfn, offset, value);
151}
152
153
154/*
155 * cpqhp_set_irq
156 *
157 * @bus_num: bus number of PCI device
158 * @dev_num: device number of PCI device
159 * @slot: pointer to u8 where slot number will be returned
160 */
161int cpqhp_set_irq(u8 bus_num, u8 dev_num, u8 int_pin, u8 irq_num)
162{
163 int rc = 0;
164
165 if (cpqhp_legacy_mode) {
166 struct pci_dev *fakedev;
167 struct pci_bus *fakebus;
168 u16 temp_word;
169
170 fakedev = kmalloc(sizeof(*fakedev), GFP_KERNEL);
171 fakebus = kmalloc(sizeof(*fakebus), GFP_KERNEL);
172 if (!fakedev || !fakebus) {
173 kfree(fakedev);
174 kfree(fakebus);
175 return -ENOMEM;
176 }
177
178 fakedev->devfn = dev_num << 3;
179 fakedev->bus = fakebus;
180 fakebus->number = bus_num;
181 dbg("%s: dev %d, bus %d, pin %d, num %d\n",
182 __func__, dev_num, bus_num, int_pin, irq_num);
183 rc = pcibios_set_irq_routing(fakedev, int_pin - 1, irq_num);
184 kfree(fakedev);
185 kfree(fakebus);
186 dbg("%s: rc %d\n", __func__, rc);
187 if (!rc)
188 return !rc;
189
190 /* set the Edge Level Control Register (ELCR) */
191 temp_word = inb(0x4d0);
192 temp_word |= inb(0x4d1) << 8;
193
194 temp_word |= 0x01 << irq_num;
195
196 /* This should only be for x86 as it sets the Edge Level
197 * Control Register
198 */
199 outb((u8) (temp_word & 0xFF), 0x4d0); outb((u8) ((temp_word &
200 0xFF00) >> 8), 0x4d1); rc = 0; }
201
202 return rc;
203}
204
205
206static int PCI_ScanBusForNonBridge(struct controller *ctrl, u8 bus_num, u8 *dev_num)
207{
208 u16 tdevice;
209 u32 work;
210 u8 tbus;
211
212 ctrl->pci_bus->number = bus_num;
213
214 for (tdevice = 0; tdevice < 0xFF; tdevice++) {
215 /* Scan for access first */
216 if (PCI_RefinedAccessConfig(ctrl->pci_bus, tdevice, 0x08, &work) == -1)
217 continue;
218 dbg("Looking for nonbridge bus_num %d dev_num %d\n", bus_num, tdevice);
219 /* Yep we got one. Not a bridge ? */
220 if ((work >> 8) != PCI_TO_PCI_BRIDGE_CLASS) {
221 *dev_num = tdevice;
222 dbg("found it !\n");
223 return 0;
224 }
225 }
226 for (tdevice = 0; tdevice < 0xFF; tdevice++) {
227 /* Scan for access first */
228 if (PCI_RefinedAccessConfig(ctrl->pci_bus, tdevice, 0x08, &work) == -1)
229 continue;
230 dbg("Looking for bridge bus_num %d dev_num %d\n", bus_num, tdevice);
231 /* Yep we got one. bridge ? */
232 if ((work >> 8) == PCI_TO_PCI_BRIDGE_CLASS) {
233 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(tdevice, 0), PCI_SECONDARY_BUS, &tbus);
234 /* XXX: no recursion, wtf? */
235 dbg("Recurse on bus_num %d tdevice %d\n", tbus, tdevice);
236 return 0;
237 }
238 }
239
240 return -1;
241}
242
243
244static int PCI_GetBusDevHelper(struct controller *ctrl, u8 *bus_num, u8 *dev_num, u8 slot, u8 nobridge)
245{
246 int loop, len;
247 u32 work;
248 u8 tbus, tdevice, tslot;
249
250 len = cpqhp_routing_table_length();
251 for (loop = 0; loop < len; ++loop) {
252 tbus = cpqhp_routing_table->slots[loop].bus;
253 tdevice = cpqhp_routing_table->slots[loop].devfn;
254 tslot = cpqhp_routing_table->slots[loop].slot;
255
256 if (tslot == slot) {
257 *bus_num = tbus;
258 *dev_num = tdevice;
259 ctrl->pci_bus->number = tbus;
260 pci_bus_read_config_dword(ctrl->pci_bus, *dev_num, PCI_VENDOR_ID, &work);
261 if (!nobridge || (work == 0xffffffff))
262 return 0;
263
264 dbg("bus_num %d devfn %d\n", *bus_num, *dev_num);
265 pci_bus_read_config_dword(ctrl->pci_bus, *dev_num, PCI_CLASS_REVISION, &work);
266 dbg("work >> 8 (%x) = BRIDGE (%x)\n", work >> 8, PCI_TO_PCI_BRIDGE_CLASS);
267
268 if ((work >> 8) == PCI_TO_PCI_BRIDGE_CLASS) {
269 pci_bus_read_config_byte(ctrl->pci_bus, *dev_num, PCI_SECONDARY_BUS, &tbus);
270 dbg("Scan bus for Non Bridge: bus %d\n", tbus);
271 if (PCI_ScanBusForNonBridge(ctrl, tbus, dev_num) == 0) {
272 *bus_num = tbus;
273 return 0;
274 }
275 } else
276 return 0;
277 }
278 }
279 return -1;
280}
281
282
283int cpqhp_get_bus_dev(struct controller *ctrl, u8 *bus_num, u8 *dev_num, u8 slot)
284{
285 /* plain (bridges allowed) */
286 return PCI_GetBusDevHelper(ctrl, bus_num, dev_num, slot, 0);
287}
288
289
290/* More PCI configuration routines; this time centered around hotplug
291 * controller
292 */
293
294
295/*
296 * cpqhp_save_config
297 *
298 * Reads configuration for all slots in a PCI bus and saves info.
299 *
300 * Note: For non-hot plug buses, the slot # saved is the device #
301 *
302 * returns 0 if success
303 */
304int cpqhp_save_config(struct controller *ctrl, int busnumber, int is_hot_plug)
305{
306 long rc;
307 u8 class_code;
308 u8 header_type;
309 u32 ID;
310 u8 secondary_bus;
311 struct pci_func *new_slot;
312 int sub_bus;
313 int FirstSupported;
314 int LastSupported;
315 int max_functions;
316 int function;
317 u8 DevError;
318 int device = 0;
319 int cloop = 0;
320 int stop_it;
321 int index;
322
323 /* Decide which slots are supported */
324
325 if (is_hot_plug) {
326 /*
327 * is_hot_plug is the slot mask
328 */
329 FirstSupported = is_hot_plug >> 4;
330 LastSupported = FirstSupported + (is_hot_plug & 0x0F) - 1;
331 } else {
332 FirstSupported = 0;
333 LastSupported = 0x1F;
334 }
335
336 /* Save PCI configuration space for all devices in supported slots */
337 ctrl->pci_bus->number = busnumber;
338 for (device = FirstSupported; device <= LastSupported; device++) {
339 ID = 0xFFFFFFFF;
340 rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, 0), PCI_VENDOR_ID, &ID);
341
342 if (ID == 0xFFFFFFFF) {
343 if (is_hot_plug) {
344 /* Setup slot structure with entry for empty
345 * slot
346 */
347 new_slot = cpqhp_slot_create(busnumber);
348 if (new_slot == NULL)
349 return 1;
350
351 new_slot->bus = (u8) busnumber;
352 new_slot->device = (u8) device;
353 new_slot->function = 0;
354 new_slot->is_a_board = 0;
355 new_slot->presence_save = 0;
356 new_slot->switch_save = 0;
357 }
358 continue;
359 }
360
361 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, 0), 0x0B, &class_code);
362 if (rc)
363 return rc;
364
365 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, 0), PCI_HEADER_TYPE, &header_type);
366 if (rc)
367 return rc;
368
369 /* If multi-function device, set max_functions to 8 */
370 if (header_type & 0x80)
371 max_functions = 8;
372 else
373 max_functions = 1;
374
375 function = 0;
376
377 do {
378 DevError = 0;
379 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
380 /* Recurse the subordinate bus
381 * get the subordinate bus number
382 */
383 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, function), PCI_SECONDARY_BUS, &secondary_bus);
384 if (rc) {
385 return rc;
386 } else {
387 sub_bus = (int) secondary_bus;
388
389 /* Save secondary bus cfg spc
390 * with this recursive call.
391 */
392 rc = cpqhp_save_config(ctrl, sub_bus, 0);
393 if (rc)
394 return rc;
395 ctrl->pci_bus->number = busnumber;
396 }
397 }
398
399 index = 0;
400 new_slot = cpqhp_slot_find(busnumber, device, index++);
401 while (new_slot &&
402 (new_slot->function != (u8) function))
403 new_slot = cpqhp_slot_find(busnumber, device, index++);
404
405 if (!new_slot) {
406 /* Setup slot structure. */
407 new_slot = cpqhp_slot_create(busnumber);
408 if (new_slot == NULL)
409 return 1;
410 }
411
412 new_slot->bus = (u8) busnumber;
413 new_slot->device = (u8) device;
414 new_slot->function = (u8) function;
415 new_slot->is_a_board = 1;
416 new_slot->switch_save = 0x10;
417 /* In case of unsupported board */
418 new_slot->status = DevError;
419 new_slot->pci_dev = pci_get_bus_and_slot(new_slot->bus, (new_slot->device << 3) | new_slot->function);
420
421 for (cloop = 0; cloop < 0x20; cloop++) {
422 rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, function), cloop << 2, (u32 *) &(new_slot->config_space[cloop]));
423 if (rc)
424 return rc;
425 }
426
427 pci_dev_put(new_slot->pci_dev);
428
429 function++;
430
431 stop_it = 0;
432
433 /* this loop skips to the next present function
434 * reading in Class Code and Header type.
435 */
436 while ((function < max_functions) && (!stop_it)) {
437 rc = pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(device, function), PCI_VENDOR_ID, &ID);
438 if (ID == 0xFFFFFFFF) {
439 function++;
440 continue;
441 }
442 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, function), 0x0B, &class_code);
443 if (rc)
444 return rc;
445
446 rc = pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(device, function), PCI_HEADER_TYPE, &header_type);
447 if (rc)
448 return rc;
449
450 stop_it++;
451 }
452
453 } while (function < max_functions);
454 } /* End of FOR loop */
455
456 return 0;
457}
458
459
460/*
461 * cpqhp_save_slot_config
462 *
463 * Saves configuration info for all PCI devices in a given slot
464 * including subordinate buses.
465 *
466 * returns 0 if success
467 */
468int cpqhp_save_slot_config(struct controller *ctrl, struct pci_func *new_slot)
469{
470 long rc;
471 u8 class_code;
472 u8 header_type;
473 u32 ID;
474 u8 secondary_bus;
475 int sub_bus;
476 int max_functions;
477 int function = 0;
478 int cloop = 0;
479 int stop_it;
480
481 ID = 0xFFFFFFFF;
482
483 ctrl->pci_bus->number = new_slot->bus;
484 pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), PCI_VENDOR_ID, &ID);
485
486 if (ID == 0xFFFFFFFF)
487 return 2;
488
489 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), 0x0B, &class_code);
490 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, 0), PCI_HEADER_TYPE, &header_type);
491
492 if (header_type & 0x80) /* Multi-function device */
493 max_functions = 8;
494 else
495 max_functions = 1;
496
497 while (function < max_functions) {
498 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
499 /* Recurse the subordinate bus */
500 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_SECONDARY_BUS, &secondary_bus);
501
502 sub_bus = (int) secondary_bus;
503
504 /* Save the config headers for the secondary
505 * bus.
506 */
507 rc = cpqhp_save_config(ctrl, sub_bus, 0);
508 if (rc)
509 return(rc);
510 ctrl->pci_bus->number = new_slot->bus;
511
512 }
513
514 new_slot->status = 0;
515
516 for (cloop = 0; cloop < 0x20; cloop++)
517 pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), cloop << 2, (u32 *) &(new_slot->config_space[cloop]));
518
519 function++;
520
521 stop_it = 0;
522
523 /* this loop skips to the next present function
524 * reading in the Class Code and the Header type.
525 */
526 while ((function < max_functions) && (!stop_it)) {
527 pci_bus_read_config_dword(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_VENDOR_ID, &ID);
528
529 if (ID == 0xFFFFFFFF)
530 function++;
531 else {
532 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), 0x0B, &class_code);
533 pci_bus_read_config_byte(ctrl->pci_bus, PCI_DEVFN(new_slot->device, function), PCI_HEADER_TYPE, &header_type);
534 stop_it++;
535 }
536 }
537
538 }
539
540 return 0;
541}
542
543
544/*
545 * cpqhp_save_base_addr_length
546 *
547 * Saves the length of all base address registers for the
548 * specified slot. this is for hot plug REPLACE
549 *
550 * returns 0 if success
551 */
552int cpqhp_save_base_addr_length(struct controller *ctrl, struct pci_func *func)
553{
554 u8 cloop;
555 u8 header_type;
556 u8 secondary_bus;
557 u8 type;
558 int sub_bus;
559 u32 temp_register;
560 u32 base;
561 u32 rc;
562 struct pci_func *next;
563 int index = 0;
564 struct pci_bus *pci_bus = ctrl->pci_bus;
565 unsigned int devfn;
566
567 func = cpqhp_slot_find(func->bus, func->device, index++);
568
569 while (func != NULL) {
570 pci_bus->number = func->bus;
571 devfn = PCI_DEVFN(func->device, func->function);
572
573 /* Check for Bridge */
574 pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
575
576 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
577 pci_bus_read_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus);
578
579 sub_bus = (int) secondary_bus;
580
581 next = cpqhp_slot_list[sub_bus];
582
583 while (next != NULL) {
584 rc = cpqhp_save_base_addr_length(ctrl, next);
585 if (rc)
586 return rc;
587
588 next = next->next;
589 }
590 pci_bus->number = func->bus;
591
592 /* FIXME: this loop is duplicated in the non-bridge
593 * case. The two could be rolled together Figure out
594 * IO and memory base lengths
595 */
596 for (cloop = 0x10; cloop <= 0x14; cloop += 4) {
597 temp_register = 0xFFFFFFFF;
598 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
599 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
600 /* If this register is implemented */
601 if (base) {
602 if (base & 0x01L) {
603 /* IO base
604 * set base = amount of IO space
605 * requested
606 */
607 base = base & 0xFFFFFFFE;
608 base = (~base) + 1;
609
610 type = 1;
611 } else {
612 /* memory base */
613 base = base & 0xFFFFFFF0;
614 base = (~base) + 1;
615
616 type = 0;
617 }
618 } else {
619 base = 0x0L;
620 type = 0;
621 }
622
623 /* Save information in slot structure */
624 func->base_length[(cloop - 0x10) >> 2] =
625 base;
626 func->base_type[(cloop - 0x10) >> 2] = type;
627
628 } /* End of base register loop */
629
630 } else if ((header_type & 0x7F) == 0x00) {
631 /* Figure out IO and memory base lengths */
632 for (cloop = 0x10; cloop <= 0x24; cloop += 4) {
633 temp_register = 0xFFFFFFFF;
634 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
635 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
636
637 /* If this register is implemented */
638 if (base) {
639 if (base & 0x01L) {
640 /* IO base
641 * base = amount of IO space
642 * requested
643 */
644 base = base & 0xFFFFFFFE;
645 base = (~base) + 1;
646
647 type = 1;
648 } else {
649 /* memory base
650 * base = amount of memory
651 * space requested
652 */
653 base = base & 0xFFFFFFF0;
654 base = (~base) + 1;
655
656 type = 0;
657 }
658 } else {
659 base = 0x0L;
660 type = 0;
661 }
662
663 /* Save information in slot structure */
664 func->base_length[(cloop - 0x10) >> 2] = base;
665 func->base_type[(cloop - 0x10) >> 2] = type;
666
667 } /* End of base register loop */
668
669 } else { /* Some other unknown header type */
670 }
671
672 /* find the next device in this slot */
673 func = cpqhp_slot_find(func->bus, func->device, index++);
674 }
675
676 return(0);
677}
678
679
680/*
681 * cpqhp_save_used_resources
682 *
683 * Stores used resource information for existing boards. this is
684 * for boards that were in the system when this driver was loaded.
685 * this function is for hot plug ADD
686 *
687 * returns 0 if success
688 */
689int cpqhp_save_used_resources(struct controller *ctrl, struct pci_func *func)
690{
691 u8 cloop;
692 u8 header_type;
693 u8 secondary_bus;
694 u8 temp_byte;
695 u8 b_base;
696 u8 b_length;
697 u16 command;
698 u16 save_command;
699 u16 w_base;
700 u16 w_length;
701 u32 temp_register;
702 u32 save_base;
703 u32 base;
704 int index = 0;
705 struct pci_resource *mem_node;
706 struct pci_resource *p_mem_node;
707 struct pci_resource *io_node;
708 struct pci_resource *bus_node;
709 struct pci_bus *pci_bus = ctrl->pci_bus;
710 unsigned int devfn;
711
712 func = cpqhp_slot_find(func->bus, func->device, index++);
713
714 while ((func != NULL) && func->is_a_board) {
715 pci_bus->number = func->bus;
716 devfn = PCI_DEVFN(func->device, func->function);
717
718 /* Save the command register */
719 pci_bus_read_config_word(pci_bus, devfn, PCI_COMMAND, &save_command);
720
721 /* disable card */
722 command = 0x00;
723 pci_bus_write_config_word(pci_bus, devfn, PCI_COMMAND, command);
724
725 /* Check for Bridge */
726 pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
727
728 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
729 /* Clear Bridge Control Register */
730 command = 0x00;
731 pci_bus_write_config_word(pci_bus, devfn, PCI_BRIDGE_CONTROL, command);
732 pci_bus_read_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus);
733 pci_bus_read_config_byte(pci_bus, devfn, PCI_SUBORDINATE_BUS, &temp_byte);
734
735 bus_node = kmalloc(sizeof(*bus_node), GFP_KERNEL);
736 if (!bus_node)
737 return -ENOMEM;
738
739 bus_node->base = secondary_bus;
740 bus_node->length = temp_byte - secondary_bus + 1;
741
742 bus_node->next = func->bus_head;
743 func->bus_head = bus_node;
744
745 /* Save IO base and Limit registers */
746 pci_bus_read_config_byte(pci_bus, devfn, PCI_IO_BASE, &b_base);
747 pci_bus_read_config_byte(pci_bus, devfn, PCI_IO_LIMIT, &b_length);
748
749 if ((b_base <= b_length) && (save_command & 0x01)) {
750 io_node = kmalloc(sizeof(*io_node), GFP_KERNEL);
751 if (!io_node)
752 return -ENOMEM;
753
754 io_node->base = (b_base & 0xF0) << 8;
755 io_node->length = (b_length - b_base + 0x10) << 8;
756
757 io_node->next = func->io_head;
758 func->io_head = io_node;
759 }
760
761 /* Save memory base and Limit registers */
762 pci_bus_read_config_word(pci_bus, devfn, PCI_MEMORY_BASE, &w_base);
763 pci_bus_read_config_word(pci_bus, devfn, PCI_MEMORY_LIMIT, &w_length);
764
765 if ((w_base <= w_length) && (save_command & 0x02)) {
766 mem_node = kmalloc(sizeof(*mem_node), GFP_KERNEL);
767 if (!mem_node)
768 return -ENOMEM;
769
770 mem_node->base = w_base << 16;
771 mem_node->length = (w_length - w_base + 0x10) << 16;
772
773 mem_node->next = func->mem_head;
774 func->mem_head = mem_node;
775 }
776
777 /* Save prefetchable memory base and Limit registers */
778 pci_bus_read_config_word(pci_bus, devfn, PCI_PREF_MEMORY_BASE, &w_base);
779 pci_bus_read_config_word(pci_bus, devfn, PCI_PREF_MEMORY_LIMIT, &w_length);
780
781 if ((w_base <= w_length) && (save_command & 0x02)) {
782 p_mem_node = kmalloc(sizeof(*p_mem_node), GFP_KERNEL);
783 if (!p_mem_node)
784 return -ENOMEM;
785
786 p_mem_node->base = w_base << 16;
787 p_mem_node->length = (w_length - w_base + 0x10) << 16;
788
789 p_mem_node->next = func->p_mem_head;
790 func->p_mem_head = p_mem_node;
791 }
792 /* Figure out IO and memory base lengths */
793 for (cloop = 0x10; cloop <= 0x14; cloop += 4) {
794 pci_bus_read_config_dword(pci_bus, devfn, cloop, &save_base);
795
796 temp_register = 0xFFFFFFFF;
797 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
798 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
799
800 temp_register = base;
801
802 /* If this register is implemented */
803 if (base) {
804 if (((base & 0x03L) == 0x01)
805 && (save_command & 0x01)) {
806 /* IO base
807 * set temp_register = amount
808 * of IO space requested
809 */
810 temp_register = base & 0xFFFFFFFE;
811 temp_register = (~temp_register) + 1;
812
813 io_node = kmalloc(sizeof(*io_node),
814 GFP_KERNEL);
815 if (!io_node)
816 return -ENOMEM;
817
818 io_node->base =
819 save_base & (~0x03L);
820 io_node->length = temp_register;
821
822 io_node->next = func->io_head;
823 func->io_head = io_node;
824 } else
825 if (((base & 0x0BL) == 0x08)
826 && (save_command & 0x02)) {
827 /* prefetchable memory base */
828 temp_register = base & 0xFFFFFFF0;
829 temp_register = (~temp_register) + 1;
830
831 p_mem_node = kmalloc(sizeof(*p_mem_node),
832 GFP_KERNEL);
833 if (!p_mem_node)
834 return -ENOMEM;
835
836 p_mem_node->base = save_base & (~0x0FL);
837 p_mem_node->length = temp_register;
838
839 p_mem_node->next = func->p_mem_head;
840 func->p_mem_head = p_mem_node;
841 } else
842 if (((base & 0x0BL) == 0x00)
843 && (save_command & 0x02)) {
844 /* prefetchable memory base */
845 temp_register = base & 0xFFFFFFF0;
846 temp_register = (~temp_register) + 1;
847
848 mem_node = kmalloc(sizeof(*mem_node),
849 GFP_KERNEL);
850 if (!mem_node)
851 return -ENOMEM;
852
853 mem_node->base = save_base & (~0x0FL);
854 mem_node->length = temp_register;
855
856 mem_node->next = func->mem_head;
857 func->mem_head = mem_node;
858 } else
859 return(1);
860 }
861 } /* End of base register loop */
862 /* Standard header */
863 } else if ((header_type & 0x7F) == 0x00) {
864 /* Figure out IO and memory base lengths */
865 for (cloop = 0x10; cloop <= 0x24; cloop += 4) {
866 pci_bus_read_config_dword(pci_bus, devfn, cloop, &save_base);
867
868 temp_register = 0xFFFFFFFF;
869 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
870 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
871
872 temp_register = base;
873
874 /* If this register is implemented */
875 if (base) {
876 if (((base & 0x03L) == 0x01)
877 && (save_command & 0x01)) {
878 /* IO base
879 * set temp_register = amount
880 * of IO space requested
881 */
882 temp_register = base & 0xFFFFFFFE;
883 temp_register = (~temp_register) + 1;
884
885 io_node = kmalloc(sizeof(*io_node),
886 GFP_KERNEL);
887 if (!io_node)
888 return -ENOMEM;
889
890 io_node->base = save_base & (~0x01L);
891 io_node->length = temp_register;
892
893 io_node->next = func->io_head;
894 func->io_head = io_node;
895 } else
896 if (((base & 0x0BL) == 0x08)
897 && (save_command & 0x02)) {
898 /* prefetchable memory base */
899 temp_register = base & 0xFFFFFFF0;
900 temp_register = (~temp_register) + 1;
901
902 p_mem_node = kmalloc(sizeof(*p_mem_node),
903 GFP_KERNEL);
904 if (!p_mem_node)
905 return -ENOMEM;
906
907 p_mem_node->base = save_base & (~0x0FL);
908 p_mem_node->length = temp_register;
909
910 p_mem_node->next = func->p_mem_head;
911 func->p_mem_head = p_mem_node;
912 } else
913 if (((base & 0x0BL) == 0x00)
914 && (save_command & 0x02)) {
915 /* prefetchable memory base */
916 temp_register = base & 0xFFFFFFF0;
917 temp_register = (~temp_register) + 1;
918
919 mem_node = kmalloc(sizeof(*mem_node),
920 GFP_KERNEL);
921 if (!mem_node)
922 return -ENOMEM;
923
924 mem_node->base = save_base & (~0x0FL);
925 mem_node->length = temp_register;
926
927 mem_node->next = func->mem_head;
928 func->mem_head = mem_node;
929 } else
930 return(1);
931 }
932 } /* End of base register loop */
933 }
934
935 /* find the next device in this slot */
936 func = cpqhp_slot_find(func->bus, func->device, index++);
937 }
938
939 return 0;
940}
941
942
943/*
944 * cpqhp_configure_board
945 *
946 * Copies saved configuration information to one slot.
947 * this is called recursively for bridge devices.
948 * this is for hot plug REPLACE!
949 *
950 * returns 0 if success
951 */
952int cpqhp_configure_board(struct controller *ctrl, struct pci_func *func)
953{
954 int cloop;
955 u8 header_type;
956 u8 secondary_bus;
957 int sub_bus;
958 struct pci_func *next;
959 u32 temp;
960 u32 rc;
961 int index = 0;
962 struct pci_bus *pci_bus = ctrl->pci_bus;
963 unsigned int devfn;
964
965 func = cpqhp_slot_find(func->bus, func->device, index++);
966
967 while (func != NULL) {
968 pci_bus->number = func->bus;
969 devfn = PCI_DEVFN(func->device, func->function);
970
971 /* Start at the top of config space so that the control
972 * registers are programmed last
973 */
974 for (cloop = 0x3C; cloop > 0; cloop -= 4)
975 pci_bus_write_config_dword(pci_bus, devfn, cloop, func->config_space[cloop >> 2]);
976
977 pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
978
979 /* If this is a bridge device, restore subordinate devices */
980 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
981 pci_bus_read_config_byte(pci_bus, devfn, PCI_SECONDARY_BUS, &secondary_bus);
982
983 sub_bus = (int) secondary_bus;
984
985 next = cpqhp_slot_list[sub_bus];
986
987 while (next != NULL) {
988 rc = cpqhp_configure_board(ctrl, next);
989 if (rc)
990 return rc;
991
992 next = next->next;
993 }
994 } else {
995
996 /* Check all the base Address Registers to make sure
997 * they are the same. If not, the board is different.
998 */
999
1000 for (cloop = 16; cloop < 40; cloop += 4) {
1001 pci_bus_read_config_dword(pci_bus, devfn, cloop, &temp);
1002
1003 if (temp != func->config_space[cloop >> 2]) {
1004 dbg("Config space compare failure!!! offset = %x\n", cloop);
1005 dbg("bus = %x, device = %x, function = %x\n", func->bus, func->device, func->function);
1006 dbg("temp = %x, config space = %x\n\n", temp, func->config_space[cloop >> 2]);
1007 return 1;
1008 }
1009 }
1010 }
1011
1012 func->configured = 1;
1013
1014 func = cpqhp_slot_find(func->bus, func->device, index++);
1015 }
1016
1017 return 0;
1018}
1019
1020
1021/*
1022 * cpqhp_valid_replace
1023 *
1024 * this function checks to see if a board is the same as the
1025 * one it is replacing. this check will detect if the device's
1026 * vendor or device id's are the same
1027 *
1028 * returns 0 if the board is the same nonzero otherwise
1029 */
1030int cpqhp_valid_replace(struct controller *ctrl, struct pci_func *func)
1031{
1032 u8 cloop;
1033 u8 header_type;
1034 u8 secondary_bus;
1035 u8 type;
1036 u32 temp_register = 0;
1037 u32 base;
1038 u32 rc;
1039 struct pci_func *next;
1040 int index = 0;
1041 struct pci_bus *pci_bus = ctrl->pci_bus;
1042 unsigned int devfn;
1043
1044 if (!func->is_a_board)
1045 return(ADD_NOT_SUPPORTED);
1046
1047 func = cpqhp_slot_find(func->bus, func->device, index++);
1048
1049 while (func != NULL) {
1050 pci_bus->number = func->bus;
1051 devfn = PCI_DEVFN(func->device, func->function);
1052
1053 pci_bus_read_config_dword(pci_bus, devfn, PCI_VENDOR_ID, &temp_register);
1054
1055 /* No adapter present */
1056 if (temp_register == 0xFFFFFFFF)
1057 return(NO_ADAPTER_PRESENT);
1058
1059 if (temp_register != func->config_space[0])
1060 return(ADAPTER_NOT_SAME);
1061
1062 /* Check for same revision number and class code */
1063 pci_bus_read_config_dword(pci_bus, devfn, PCI_CLASS_REVISION, &temp_register);
1064
1065 /* Adapter not the same */
1066 if (temp_register != func->config_space[0x08 >> 2])
1067 return(ADAPTER_NOT_SAME);
1068
1069 /* Check for Bridge */
1070 pci_bus_read_config_byte(pci_bus, devfn, PCI_HEADER_TYPE, &header_type);
1071
1072 if ((header_type & 0x7F) == PCI_HEADER_TYPE_BRIDGE) {
1073 /* In order to continue checking, we must program the
1074 * bus registers in the bridge to respond to accesses
1075 * for its subordinate bus(es)
1076 */
1077
1078 temp_register = func->config_space[0x18 >> 2];
1079 pci_bus_write_config_dword(pci_bus, devfn, PCI_PRIMARY_BUS, temp_register);
1080
1081 secondary_bus = (temp_register >> 8) & 0xFF;
1082
1083 next = cpqhp_slot_list[secondary_bus];
1084
1085 while (next != NULL) {
1086 rc = cpqhp_valid_replace(ctrl, next);
1087 if (rc)
1088 return rc;
1089
1090 next = next->next;
1091 }
1092
1093 }
1094 /* Check to see if it is a standard config header */
1095 else if ((header_type & 0x7F) == PCI_HEADER_TYPE_NORMAL) {
1096 /* Check subsystem vendor and ID */
1097 pci_bus_read_config_dword(pci_bus, devfn, PCI_SUBSYSTEM_VENDOR_ID, &temp_register);
1098
1099 if (temp_register != func->config_space[0x2C >> 2]) {
1100 /* If it's a SMART-2 and the register isn't
1101 * filled in, ignore the difference because
1102 * they just have an old rev of the firmware
1103 */
1104 if (!((func->config_space[0] == 0xAE100E11)
1105 && (temp_register == 0x00L)))
1106 return(ADAPTER_NOT_SAME);
1107 }
1108 /* Figure out IO and memory base lengths */
1109 for (cloop = 0x10; cloop <= 0x24; cloop += 4) {
1110 temp_register = 0xFFFFFFFF;
1111 pci_bus_write_config_dword(pci_bus, devfn, cloop, temp_register);
1112 pci_bus_read_config_dword(pci_bus, devfn, cloop, &base);
1113
1114 /* If this register is implemented */
1115 if (base) {
1116 if (base & 0x01L) {
1117 /* IO base
1118 * set base = amount of IO
1119 * space requested
1120 */
1121 base = base & 0xFFFFFFFE;
1122 base = (~base) + 1;
1123
1124 type = 1;
1125 } else {
1126 /* memory base */
1127 base = base & 0xFFFFFFF0;
1128 base = (~base) + 1;
1129
1130 type = 0;
1131 }
1132 } else {
1133 base = 0x0L;
1134 type = 0;
1135 }
1136
1137 /* Check information in slot structure */
1138 if (func->base_length[(cloop - 0x10) >> 2] != base)
1139 return(ADAPTER_NOT_SAME);
1140
1141 if (func->base_type[(cloop - 0x10) >> 2] != type)
1142 return(ADAPTER_NOT_SAME);
1143
1144 } /* End of base register loop */
1145
1146 } /* End of (type 0 config space) else */
1147 else {
1148 /* this is not a type 0 or 1 config space header so
1149 * we don't know how to do it
1150 */
1151 return(DEVICE_TYPE_NOT_SUPPORTED);
1152 }
1153
1154 /* Get the next function */
1155 func = cpqhp_slot_find(func->bus, func->device, index++);
1156 }
1157
1158
1159 return 0;
1160}
1161
1162
1163/*
1164 * cpqhp_find_available_resources
1165 *
1166 * Finds available memory, IO, and IRQ resources for programming
1167 * devices which may be added to the system
1168 * this function is for hot plug ADD!
1169 *
1170 * returns 0 if success
1171 */
1172int cpqhp_find_available_resources(struct controller *ctrl, void __iomem *rom_start)
1173{
1174 u8 temp;
1175 u8 populated_slot;
1176 u8 bridged_slot;
1177 void __iomem *one_slot;
1178 void __iomem *rom_resource_table;
1179 struct pci_func *func = NULL;
1180 int i = 10, index;
1181 u32 temp_dword, rc;
1182 struct pci_resource *mem_node;
1183 struct pci_resource *p_mem_node;
1184 struct pci_resource *io_node;
1185 struct pci_resource *bus_node;
1186
1187 rom_resource_table = detect_HRT_floating_pointer(rom_start, rom_start+0xffff);
1188 dbg("rom_resource_table = %p\n", rom_resource_table);
1189
1190 if (rom_resource_table == NULL)
1191 return -ENODEV;
1192
1193 /* Sum all resources and setup resource maps */
1194 unused_IRQ = readl(rom_resource_table + UNUSED_IRQ);
1195 dbg("unused_IRQ = %x\n", unused_IRQ);
1196
1197 temp = 0;
1198 while (unused_IRQ) {
1199 if (unused_IRQ & 1) {
1200 cpqhp_disk_irq = temp;
1201 break;
1202 }
1203 unused_IRQ = unused_IRQ >> 1;
1204 temp++;
1205 }
1206
1207 dbg("cpqhp_disk_irq= %d\n", cpqhp_disk_irq);
1208 unused_IRQ = unused_IRQ >> 1;
1209 temp++;
1210
1211 while (unused_IRQ) {
1212 if (unused_IRQ & 1) {
1213 cpqhp_nic_irq = temp;
1214 break;
1215 }
1216 unused_IRQ = unused_IRQ >> 1;
1217 temp++;
1218 }
1219
1220 dbg("cpqhp_nic_irq= %d\n", cpqhp_nic_irq);
1221 unused_IRQ = readl(rom_resource_table + PCIIRQ);
1222
1223 temp = 0;
1224
1225 if (!cpqhp_nic_irq)
1226 cpqhp_nic_irq = ctrl->cfgspc_irq;
1227
1228 if (!cpqhp_disk_irq)
1229 cpqhp_disk_irq = ctrl->cfgspc_irq;
1230
1231 dbg("cpqhp_disk_irq, cpqhp_nic_irq= %d, %d\n", cpqhp_disk_irq, cpqhp_nic_irq);
1232
1233 rc = compaq_nvram_load(rom_start, ctrl);
1234 if (rc)
1235 return rc;
1236
1237 one_slot = rom_resource_table + sizeof(struct hrt);
1238
1239 i = readb(rom_resource_table + NUMBER_OF_ENTRIES);
1240 dbg("number_of_entries = %d\n", i);
1241
1242 if (!readb(one_slot + SECONDARY_BUS))
1243 return 1;
1244
1245 dbg("dev|IO base|length|Mem base|length|Pre base|length|PB SB MB\n");
1246
1247 while (i && readb(one_slot + SECONDARY_BUS)) {
1248 u8 dev_func = readb(one_slot + DEV_FUNC);
1249 u8 primary_bus = readb(one_slot + PRIMARY_BUS);
1250 u8 secondary_bus = readb(one_slot + SECONDARY_BUS);
1251 u8 max_bus = readb(one_slot + MAX_BUS);
1252 u16 io_base = readw(one_slot + IO_BASE);
1253 u16 io_length = readw(one_slot + IO_LENGTH);
1254 u16 mem_base = readw(one_slot + MEM_BASE);
1255 u16 mem_length = readw(one_slot + MEM_LENGTH);
1256 u16 pre_mem_base = readw(one_slot + PRE_MEM_BASE);
1257 u16 pre_mem_length = readw(one_slot + PRE_MEM_LENGTH);
1258
1259 dbg("%2.2x | %4.4x | %4.4x | %4.4x | %4.4x | %4.4x | %4.4x |%2.2x %2.2x %2.2x\n",
1260 dev_func, io_base, io_length, mem_base, mem_length, pre_mem_base, pre_mem_length,
1261 primary_bus, secondary_bus, max_bus);
1262
1263 /* If this entry isn't for our controller's bus, ignore it */
1264 if (primary_bus != ctrl->bus) {
1265 i--;
1266 one_slot += sizeof(struct slot_rt);
1267 continue;
1268 }
1269 /* find out if this entry is for an occupied slot */
1270 ctrl->pci_bus->number = primary_bus;
1271 pci_bus_read_config_dword(ctrl->pci_bus, dev_func, PCI_VENDOR_ID, &temp_dword);
1272 dbg("temp_D_word = %x\n", temp_dword);
1273
1274 if (temp_dword != 0xFFFFFFFF) {
1275 index = 0;
1276 func = cpqhp_slot_find(primary_bus, dev_func >> 3, 0);
1277
1278 while (func && (func->function != (dev_func & 0x07))) {
1279 dbg("func = %p (bus, dev, fun) = (%d, %d, %d)\n", func, primary_bus, dev_func >> 3, index);
1280 func = cpqhp_slot_find(primary_bus, dev_func >> 3, index++);
1281 }
1282
1283 /* If we can't find a match, skip this table entry */
1284 if (!func) {
1285 i--;
1286 one_slot += sizeof(struct slot_rt);
1287 continue;
1288 }
1289 /* this may not work and shouldn't be used */
1290 if (secondary_bus != primary_bus)
1291 bridged_slot = 1;
1292 else
1293 bridged_slot = 0;
1294
1295 populated_slot = 1;
1296 } else {
1297 populated_slot = 0;
1298 bridged_slot = 0;
1299 }
1300
1301
1302 /* If we've got a valid IO base, use it */
1303
1304 temp_dword = io_base + io_length;
1305
1306 if ((io_base) && (temp_dword < 0x10000)) {
1307 io_node = kmalloc(sizeof(*io_node), GFP_KERNEL);
1308 if (!io_node)
1309 return -ENOMEM;
1310
1311 io_node->base = io_base;
1312 io_node->length = io_length;
1313
1314 dbg("found io_node(base, length) = %x, %x\n",
1315 io_node->base, io_node->length);
1316 dbg("populated slot =%d \n", populated_slot);
1317 if (!populated_slot) {
1318 io_node->next = ctrl->io_head;
1319 ctrl->io_head = io_node;
1320 } else {
1321 io_node->next = func->io_head;
1322 func->io_head = io_node;
1323 }
1324 }
1325
1326 /* If we've got a valid memory base, use it */
1327 temp_dword = mem_base + mem_length;
1328 if ((mem_base) && (temp_dword < 0x10000)) {
1329 mem_node = kmalloc(sizeof(*mem_node), GFP_KERNEL);
1330 if (!mem_node)
1331 return -ENOMEM;
1332
1333 mem_node->base = mem_base << 16;
1334
1335 mem_node->length = mem_length << 16;
1336
1337 dbg("found mem_node(base, length) = %x, %x\n",
1338 mem_node->base, mem_node->length);
1339 dbg("populated slot =%d \n", populated_slot);
1340 if (!populated_slot) {
1341 mem_node->next = ctrl->mem_head;
1342 ctrl->mem_head = mem_node;
1343 } else {
1344 mem_node->next = func->mem_head;
1345 func->mem_head = mem_node;
1346 }
1347 }
1348
1349 /* If we've got a valid prefetchable memory base, and
1350 * the base + length isn't greater than 0xFFFF
1351 */
1352 temp_dword = pre_mem_base + pre_mem_length;
1353 if ((pre_mem_base) && (temp_dword < 0x10000)) {
1354 p_mem_node = kmalloc(sizeof(*p_mem_node), GFP_KERNEL);
1355 if (!p_mem_node)
1356 return -ENOMEM;
1357
1358 p_mem_node->base = pre_mem_base << 16;
1359
1360 p_mem_node->length = pre_mem_length << 16;
1361 dbg("found p_mem_node(base, length) = %x, %x\n",
1362 p_mem_node->base, p_mem_node->length);
1363 dbg("populated slot =%d \n", populated_slot);
1364
1365 if (!populated_slot) {
1366 p_mem_node->next = ctrl->p_mem_head;
1367 ctrl->p_mem_head = p_mem_node;
1368 } else {
1369 p_mem_node->next = func->p_mem_head;
1370 func->p_mem_head = p_mem_node;
1371 }
1372 }
1373
1374 /* If we've got a valid bus number, use it
1375 * The second condition is to ignore bus numbers on
1376 * populated slots that don't have PCI-PCI bridges
1377 */
1378 if (secondary_bus && (secondary_bus != primary_bus)) {
1379 bus_node = kmalloc(sizeof(*bus_node), GFP_KERNEL);
1380 if (!bus_node)
1381 return -ENOMEM;
1382
1383 bus_node->base = secondary_bus;
1384 bus_node->length = max_bus - secondary_bus + 1;
1385 dbg("found bus_node(base, length) = %x, %x\n",
1386 bus_node->base, bus_node->length);
1387 dbg("populated slot =%d \n", populated_slot);
1388 if (!populated_slot) {
1389 bus_node->next = ctrl->bus_head;
1390 ctrl->bus_head = bus_node;
1391 } else {
1392 bus_node->next = func->bus_head;
1393 func->bus_head = bus_node;
1394 }
1395 }
1396
1397 i--;
1398 one_slot += sizeof(struct slot_rt);
1399 }
1400
1401 /* If all of the following fail, we don't have any resources for
1402 * hot plug add
1403 */
1404 rc = 1;
1405 rc &= cpqhp_resource_sort_and_combine(&(ctrl->mem_head));
1406 rc &= cpqhp_resource_sort_and_combine(&(ctrl->p_mem_head));
1407 rc &= cpqhp_resource_sort_and_combine(&(ctrl->io_head));
1408 rc &= cpqhp_resource_sort_and_combine(&(ctrl->bus_head));
1409
1410 return rc;
1411}
1412
1413
1414/*
1415 * cpqhp_return_board_resources
1416 *
1417 * this routine returns all resources allocated to a board to
1418 * the available pool.
1419 *
1420 * returns 0 if success
1421 */
1422int cpqhp_return_board_resources(struct pci_func *func, struct resource_lists *resources)
1423{
1424 int rc = 0;
1425 struct pci_resource *node;
1426 struct pci_resource *t_node;
1427 dbg("%s\n", __func__);
1428
1429 if (!func)
1430 return 1;
1431
1432 node = func->io_head;
1433 func->io_head = NULL;
1434 while (node) {
1435 t_node = node->next;
1436 return_resource(&(resources->io_head), node);
1437 node = t_node;
1438 }
1439
1440 node = func->mem_head;
1441 func->mem_head = NULL;
1442 while (node) {
1443 t_node = node->next;
1444 return_resource(&(resources->mem_head), node);
1445 node = t_node;
1446 }
1447
1448 node = func->p_mem_head;
1449 func->p_mem_head = NULL;
1450 while (node) {
1451 t_node = node->next;
1452 return_resource(&(resources->p_mem_head), node);
1453 node = t_node;
1454 }
1455
1456 node = func->bus_head;
1457 func->bus_head = NULL;
1458 while (node) {
1459 t_node = node->next;
1460 return_resource(&(resources->bus_head), node);
1461 node = t_node;
1462 }
1463
1464 rc |= cpqhp_resource_sort_and_combine(&(resources->mem_head));
1465 rc |= cpqhp_resource_sort_and_combine(&(resources->p_mem_head));
1466 rc |= cpqhp_resource_sort_and_combine(&(resources->io_head));
1467 rc |= cpqhp_resource_sort_and_combine(&(resources->bus_head));
1468
1469 return rc;
1470}
1471
1472
1473/*
1474 * cpqhp_destroy_resource_list
1475 *
1476 * Puts node back in the resource list pointed to by head
1477 */
1478void cpqhp_destroy_resource_list(struct resource_lists *resources)
1479{
1480 struct pci_resource *res, *tres;
1481
1482 res = resources->io_head;
1483 resources->io_head = NULL;
1484
1485 while (res) {
1486 tres = res;
1487 res = res->next;
1488 kfree(tres);
1489 }
1490
1491 res = resources->mem_head;
1492 resources->mem_head = NULL;
1493
1494 while (res) {
1495 tres = res;
1496 res = res->next;
1497 kfree(tres);
1498 }
1499
1500 res = resources->p_mem_head;
1501 resources->p_mem_head = NULL;
1502
1503 while (res) {
1504 tres = res;
1505 res = res->next;
1506 kfree(tres);
1507 }
1508
1509 res = resources->bus_head;
1510 resources->bus_head = NULL;
1511
1512 while (res) {
1513 tres = res;
1514 res = res->next;
1515 kfree(tres);
1516 }
1517}
1518
1519
1520/*
1521 * cpqhp_destroy_board_resources
1522 *
1523 * Puts node back in the resource list pointed to by head
1524 */
1525void cpqhp_destroy_board_resources(struct pci_func *func)
1526{
1527 struct pci_resource *res, *tres;
1528
1529 res = func->io_head;
1530 func->io_head = NULL;
1531
1532 while (res) {
1533 tres = res;
1534 res = res->next;
1535 kfree(tres);
1536 }
1537
1538 res = func->mem_head;
1539 func->mem_head = NULL;
1540
1541 while (res) {
1542 tres = res;
1543 res = res->next;
1544 kfree(tres);
1545 }
1546
1547 res = func->p_mem_head;
1548 func->p_mem_head = NULL;
1549
1550 while (res) {
1551 tres = res;
1552 res = res->next;
1553 kfree(tres);
1554 }
1555
1556 res = func->bus_head;
1557 func->bus_head = NULL;
1558
1559 while (res) {
1560 tres = res;
1561 res = res->next;
1562 kfree(tres);
1563 }
1564}