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1// SPDX-License-Identifier: GPL-2.0
2/* Copyright(c) 2013 - 2018 Intel Corporation. */
3
4#include <linux/prefetch.h>
5#include <linux/bpf_trace.h>
6#include <net/xdp.h>
7#include "i40e.h"
8#include "i40e_trace.h"
9#include "i40e_prototype.h"
10#include "i40e_txrx_common.h"
11#include "i40e_xsk.h"
12
13#define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
14/**
15 * i40e_fdir - Generate a Flow Director descriptor based on fdata
16 * @tx_ring: Tx ring to send buffer on
17 * @fdata: Flow director filter data
18 * @add: Indicate if we are adding a rule or deleting one
19 *
20 **/
21static void i40e_fdir(struct i40e_ring *tx_ring,
22 struct i40e_fdir_filter *fdata, bool add)
23{
24 struct i40e_filter_program_desc *fdir_desc;
25 struct i40e_pf *pf = tx_ring->vsi->back;
26 u32 flex_ptype, dtype_cmd;
27 u16 i;
28
29 /* grab the next descriptor */
30 i = tx_ring->next_to_use;
31 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
32
33 i++;
34 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
35
36 flex_ptype = I40E_TXD_FLTR_QW0_QINDEX_MASK &
37 (fdata->q_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT);
38
39 flex_ptype |= I40E_TXD_FLTR_QW0_FLEXOFF_MASK &
40 (fdata->flex_off << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT);
41
42 flex_ptype |= I40E_TXD_FLTR_QW0_PCTYPE_MASK &
43 (fdata->pctype << I40E_TXD_FLTR_QW0_PCTYPE_SHIFT);
44
45 flex_ptype |= I40E_TXD_FLTR_QW0_PCTYPE_MASK &
46 (fdata->flex_offset << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT);
47
48 /* Use LAN VSI Id if not programmed by user */
49 flex_ptype |= I40E_TXD_FLTR_QW0_DEST_VSI_MASK &
50 ((u32)(fdata->dest_vsi ? : pf->vsi[pf->lan_vsi]->id) <<
51 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT);
52
53 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG;
54
55 dtype_cmd |= add ?
56 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
57 I40E_TXD_FLTR_QW1_PCMD_SHIFT :
58 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
59 I40E_TXD_FLTR_QW1_PCMD_SHIFT;
60
61 dtype_cmd |= I40E_TXD_FLTR_QW1_DEST_MASK &
62 (fdata->dest_ctl << I40E_TXD_FLTR_QW1_DEST_SHIFT);
63
64 dtype_cmd |= I40E_TXD_FLTR_QW1_FD_STATUS_MASK &
65 (fdata->fd_status << I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT);
66
67 if (fdata->cnt_index) {
68 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
69 dtype_cmd |= I40E_TXD_FLTR_QW1_CNTINDEX_MASK &
70 ((u32)fdata->cnt_index <<
71 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT);
72 }
73
74 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);
75 fdir_desc->rsvd = cpu_to_le32(0);
76 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd);
77 fdir_desc->fd_id = cpu_to_le32(fdata->fd_id);
78}
79
80#define I40E_FD_CLEAN_DELAY 10
81/**
82 * i40e_program_fdir_filter - Program a Flow Director filter
83 * @fdir_data: Packet data that will be filter parameters
84 * @raw_packet: the pre-allocated packet buffer for FDir
85 * @pf: The PF pointer
86 * @add: True for add/update, False for remove
87 **/
88static int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data,
89 u8 *raw_packet, struct i40e_pf *pf,
90 bool add)
91{
92 struct i40e_tx_buffer *tx_buf, *first;
93 struct i40e_tx_desc *tx_desc;
94 struct i40e_ring *tx_ring;
95 struct i40e_vsi *vsi;
96 struct device *dev;
97 dma_addr_t dma;
98 u32 td_cmd = 0;
99 u16 i;
100
101 /* find existing FDIR VSI */
102 vsi = i40e_find_vsi_by_type(pf, I40E_VSI_FDIR);
103 if (!vsi)
104 return -ENOENT;
105
106 tx_ring = vsi->tx_rings[0];
107 dev = tx_ring->dev;
108
109 /* we need two descriptors to add/del a filter and we can wait */
110 for (i = I40E_FD_CLEAN_DELAY; I40E_DESC_UNUSED(tx_ring) < 2; i--) {
111 if (!i)
112 return -EAGAIN;
113 msleep_interruptible(1);
114 }
115
116 dma = dma_map_single(dev, raw_packet,
117 I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE);
118 if (dma_mapping_error(dev, dma))
119 goto dma_fail;
120
121 /* grab the next descriptor */
122 i = tx_ring->next_to_use;
123 first = &tx_ring->tx_bi[i];
124 i40e_fdir(tx_ring, fdir_data, add);
125
126 /* Now program a dummy descriptor */
127 i = tx_ring->next_to_use;
128 tx_desc = I40E_TX_DESC(tx_ring, i);
129 tx_buf = &tx_ring->tx_bi[i];
130
131 tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0;
132
133 memset(tx_buf, 0, sizeof(struct i40e_tx_buffer));
134
135 /* record length, and DMA address */
136 dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE);
137 dma_unmap_addr_set(tx_buf, dma, dma);
138
139 tx_desc->buffer_addr = cpu_to_le64(dma);
140 td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY;
141
142 tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB;
143 tx_buf->raw_buf = (void *)raw_packet;
144
145 tx_desc->cmd_type_offset_bsz =
146 build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0);
147
148 /* Force memory writes to complete before letting h/w
149 * know there are new descriptors to fetch.
150 */
151 wmb();
152
153 /* Mark the data descriptor to be watched */
154 first->next_to_watch = tx_desc;
155
156 writel(tx_ring->next_to_use, tx_ring->tail);
157 return 0;
158
159dma_fail:
160 return -1;
161}
162
163#define IP_HEADER_OFFSET 14
164#define I40E_UDPIP_DUMMY_PACKET_LEN 42
165/**
166 * i40e_add_del_fdir_udpv4 - Add/Remove UDPv4 filters
167 * @vsi: pointer to the targeted VSI
168 * @fd_data: the flow director data required for the FDir descriptor
169 * @add: true adds a filter, false removes it
170 *
171 * Returns 0 if the filters were successfully added or removed
172 **/
173static int i40e_add_del_fdir_udpv4(struct i40e_vsi *vsi,
174 struct i40e_fdir_filter *fd_data,
175 bool add)
176{
177 struct i40e_pf *pf = vsi->back;
178 struct udphdr *udp;
179 struct iphdr *ip;
180 u8 *raw_packet;
181 int ret;
182 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
183 0x45, 0, 0, 0x1c, 0, 0, 0x40, 0, 0x40, 0x11, 0, 0, 0, 0, 0, 0,
184 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
185
186 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
187 if (!raw_packet)
188 return -ENOMEM;
189 memcpy(raw_packet, packet, I40E_UDPIP_DUMMY_PACKET_LEN);
190
191 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
192 udp = (struct udphdr *)(raw_packet + IP_HEADER_OFFSET
193 + sizeof(struct iphdr));
194
195 ip->daddr = fd_data->dst_ip;
196 udp->dest = fd_data->dst_port;
197 ip->saddr = fd_data->src_ip;
198 udp->source = fd_data->src_port;
199
200 if (fd_data->flex_filter) {
201 u8 *payload = raw_packet + I40E_UDPIP_DUMMY_PACKET_LEN;
202 __be16 pattern = fd_data->flex_word;
203 u16 off = fd_data->flex_offset;
204
205 *((__force __be16 *)(payload + off)) = pattern;
206 }
207
208 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
209 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
210 if (ret) {
211 dev_info(&pf->pdev->dev,
212 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
213 fd_data->pctype, fd_data->fd_id, ret);
214 /* Free the packet buffer since it wasn't added to the ring */
215 kfree(raw_packet);
216 return -EOPNOTSUPP;
217 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
218 if (add)
219 dev_info(&pf->pdev->dev,
220 "Filter OK for PCTYPE %d loc = %d\n",
221 fd_data->pctype, fd_data->fd_id);
222 else
223 dev_info(&pf->pdev->dev,
224 "Filter deleted for PCTYPE %d loc = %d\n",
225 fd_data->pctype, fd_data->fd_id);
226 }
227
228 if (add)
229 pf->fd_udp4_filter_cnt++;
230 else
231 pf->fd_udp4_filter_cnt--;
232
233 return 0;
234}
235
236#define I40E_TCPIP_DUMMY_PACKET_LEN 54
237/**
238 * i40e_add_del_fdir_tcpv4 - Add/Remove TCPv4 filters
239 * @vsi: pointer to the targeted VSI
240 * @fd_data: the flow director data required for the FDir descriptor
241 * @add: true adds a filter, false removes it
242 *
243 * Returns 0 if the filters were successfully added or removed
244 **/
245static int i40e_add_del_fdir_tcpv4(struct i40e_vsi *vsi,
246 struct i40e_fdir_filter *fd_data,
247 bool add)
248{
249 struct i40e_pf *pf = vsi->back;
250 struct tcphdr *tcp;
251 struct iphdr *ip;
252 u8 *raw_packet;
253 int ret;
254 /* Dummy packet */
255 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
256 0x45, 0, 0, 0x28, 0, 0, 0x40, 0, 0x40, 0x6, 0, 0, 0, 0, 0, 0,
257 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x80, 0x11,
258 0x0, 0x72, 0, 0, 0, 0};
259
260 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
261 if (!raw_packet)
262 return -ENOMEM;
263 memcpy(raw_packet, packet, I40E_TCPIP_DUMMY_PACKET_LEN);
264
265 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
266 tcp = (struct tcphdr *)(raw_packet + IP_HEADER_OFFSET
267 + sizeof(struct iphdr));
268
269 ip->daddr = fd_data->dst_ip;
270 tcp->dest = fd_data->dst_port;
271 ip->saddr = fd_data->src_ip;
272 tcp->source = fd_data->src_port;
273
274 if (fd_data->flex_filter) {
275 u8 *payload = raw_packet + I40E_TCPIP_DUMMY_PACKET_LEN;
276 __be16 pattern = fd_data->flex_word;
277 u16 off = fd_data->flex_offset;
278
279 *((__force __be16 *)(payload + off)) = pattern;
280 }
281
282 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
283 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
284 if (ret) {
285 dev_info(&pf->pdev->dev,
286 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
287 fd_data->pctype, fd_data->fd_id, ret);
288 /* Free the packet buffer since it wasn't added to the ring */
289 kfree(raw_packet);
290 return -EOPNOTSUPP;
291 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
292 if (add)
293 dev_info(&pf->pdev->dev, "Filter OK for PCTYPE %d loc = %d)\n",
294 fd_data->pctype, fd_data->fd_id);
295 else
296 dev_info(&pf->pdev->dev,
297 "Filter deleted for PCTYPE %d loc = %d\n",
298 fd_data->pctype, fd_data->fd_id);
299 }
300
301 if (add) {
302 pf->fd_tcp4_filter_cnt++;
303 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
304 I40E_DEBUG_FD & pf->hw.debug_mask)
305 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n");
306 set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state);
307 } else {
308 pf->fd_tcp4_filter_cnt--;
309 }
310
311 return 0;
312}
313
314#define I40E_SCTPIP_DUMMY_PACKET_LEN 46
315/**
316 * i40e_add_del_fdir_sctpv4 - Add/Remove SCTPv4 Flow Director filters for
317 * a specific flow spec
318 * @vsi: pointer to the targeted VSI
319 * @fd_data: the flow director data required for the FDir descriptor
320 * @add: true adds a filter, false removes it
321 *
322 * Returns 0 if the filters were successfully added or removed
323 **/
324static int i40e_add_del_fdir_sctpv4(struct i40e_vsi *vsi,
325 struct i40e_fdir_filter *fd_data,
326 bool add)
327{
328 struct i40e_pf *pf = vsi->back;
329 struct sctphdr *sctp;
330 struct iphdr *ip;
331 u8 *raw_packet;
332 int ret;
333 /* Dummy packet */
334 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
335 0x45, 0, 0, 0x20, 0, 0, 0x40, 0, 0x40, 0x84, 0, 0, 0, 0, 0, 0,
336 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
337
338 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
339 if (!raw_packet)
340 return -ENOMEM;
341 memcpy(raw_packet, packet, I40E_SCTPIP_DUMMY_PACKET_LEN);
342
343 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
344 sctp = (struct sctphdr *)(raw_packet + IP_HEADER_OFFSET
345 + sizeof(struct iphdr));
346
347 ip->daddr = fd_data->dst_ip;
348 sctp->dest = fd_data->dst_port;
349 ip->saddr = fd_data->src_ip;
350 sctp->source = fd_data->src_port;
351
352 if (fd_data->flex_filter) {
353 u8 *payload = raw_packet + I40E_SCTPIP_DUMMY_PACKET_LEN;
354 __be16 pattern = fd_data->flex_word;
355 u16 off = fd_data->flex_offset;
356
357 *((__force __be16 *)(payload + off)) = pattern;
358 }
359
360 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
361 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
362 if (ret) {
363 dev_info(&pf->pdev->dev,
364 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
365 fd_data->pctype, fd_data->fd_id, ret);
366 /* Free the packet buffer since it wasn't added to the ring */
367 kfree(raw_packet);
368 return -EOPNOTSUPP;
369 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
370 if (add)
371 dev_info(&pf->pdev->dev,
372 "Filter OK for PCTYPE %d loc = %d\n",
373 fd_data->pctype, fd_data->fd_id);
374 else
375 dev_info(&pf->pdev->dev,
376 "Filter deleted for PCTYPE %d loc = %d\n",
377 fd_data->pctype, fd_data->fd_id);
378 }
379
380 if (add)
381 pf->fd_sctp4_filter_cnt++;
382 else
383 pf->fd_sctp4_filter_cnt--;
384
385 return 0;
386}
387
388#define I40E_IP_DUMMY_PACKET_LEN 34
389/**
390 * i40e_add_del_fdir_ipv4 - Add/Remove IPv4 Flow Director filters for
391 * a specific flow spec
392 * @vsi: pointer to the targeted VSI
393 * @fd_data: the flow director data required for the FDir descriptor
394 * @add: true adds a filter, false removes it
395 *
396 * Returns 0 if the filters were successfully added or removed
397 **/
398static int i40e_add_del_fdir_ipv4(struct i40e_vsi *vsi,
399 struct i40e_fdir_filter *fd_data,
400 bool add)
401{
402 struct i40e_pf *pf = vsi->back;
403 struct iphdr *ip;
404 u8 *raw_packet;
405 int ret;
406 int i;
407 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
408 0x45, 0, 0, 0x14, 0, 0, 0x40, 0, 0x40, 0x10, 0, 0, 0, 0, 0, 0,
409 0, 0, 0, 0};
410
411 for (i = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
412 i <= I40E_FILTER_PCTYPE_FRAG_IPV4; i++) {
413 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
414 if (!raw_packet)
415 return -ENOMEM;
416 memcpy(raw_packet, packet, I40E_IP_DUMMY_PACKET_LEN);
417 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
418
419 ip->saddr = fd_data->src_ip;
420 ip->daddr = fd_data->dst_ip;
421 ip->protocol = 0;
422
423 if (fd_data->flex_filter) {
424 u8 *payload = raw_packet + I40E_IP_DUMMY_PACKET_LEN;
425 __be16 pattern = fd_data->flex_word;
426 u16 off = fd_data->flex_offset;
427
428 *((__force __be16 *)(payload + off)) = pattern;
429 }
430
431 fd_data->pctype = i;
432 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
433 if (ret) {
434 dev_info(&pf->pdev->dev,
435 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
436 fd_data->pctype, fd_data->fd_id, ret);
437 /* The packet buffer wasn't added to the ring so we
438 * need to free it now.
439 */
440 kfree(raw_packet);
441 return -EOPNOTSUPP;
442 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
443 if (add)
444 dev_info(&pf->pdev->dev,
445 "Filter OK for PCTYPE %d loc = %d\n",
446 fd_data->pctype, fd_data->fd_id);
447 else
448 dev_info(&pf->pdev->dev,
449 "Filter deleted for PCTYPE %d loc = %d\n",
450 fd_data->pctype, fd_data->fd_id);
451 }
452 }
453
454 if (add)
455 pf->fd_ip4_filter_cnt++;
456 else
457 pf->fd_ip4_filter_cnt--;
458
459 return 0;
460}
461
462/**
463 * i40e_add_del_fdir - Build raw packets to add/del fdir filter
464 * @vsi: pointer to the targeted VSI
465 * @input: filter to add or delete
466 * @add: true adds a filter, false removes it
467 *
468 **/
469int i40e_add_del_fdir(struct i40e_vsi *vsi,
470 struct i40e_fdir_filter *input, bool add)
471{
472 struct i40e_pf *pf = vsi->back;
473 int ret;
474
475 switch (input->flow_type & ~FLOW_EXT) {
476 case TCP_V4_FLOW:
477 ret = i40e_add_del_fdir_tcpv4(vsi, input, add);
478 break;
479 case UDP_V4_FLOW:
480 ret = i40e_add_del_fdir_udpv4(vsi, input, add);
481 break;
482 case SCTP_V4_FLOW:
483 ret = i40e_add_del_fdir_sctpv4(vsi, input, add);
484 break;
485 case IP_USER_FLOW:
486 switch (input->ip4_proto) {
487 case IPPROTO_TCP:
488 ret = i40e_add_del_fdir_tcpv4(vsi, input, add);
489 break;
490 case IPPROTO_UDP:
491 ret = i40e_add_del_fdir_udpv4(vsi, input, add);
492 break;
493 case IPPROTO_SCTP:
494 ret = i40e_add_del_fdir_sctpv4(vsi, input, add);
495 break;
496 case IPPROTO_IP:
497 ret = i40e_add_del_fdir_ipv4(vsi, input, add);
498 break;
499 default:
500 /* We cannot support masking based on protocol */
501 dev_info(&pf->pdev->dev, "Unsupported IPv4 protocol 0x%02x\n",
502 input->ip4_proto);
503 return -EINVAL;
504 }
505 break;
506 default:
507 dev_info(&pf->pdev->dev, "Unsupported flow type 0x%02x\n",
508 input->flow_type);
509 return -EINVAL;
510 }
511
512 /* The buffer allocated here will be normally be freed by
513 * i40e_clean_fdir_tx_irq() as it reclaims resources after transmit
514 * completion. In the event of an error adding the buffer to the FDIR
515 * ring, it will immediately be freed. It may also be freed by
516 * i40e_clean_tx_ring() when closing the VSI.
517 */
518 return ret;
519}
520
521/**
522 * i40e_fd_handle_status - check the Programming Status for FD
523 * @rx_ring: the Rx ring for this descriptor
524 * @rx_desc: the Rx descriptor for programming Status, not a packet descriptor.
525 * @prog_id: the id originally used for programming
526 *
527 * This is used to verify if the FD programming or invalidation
528 * requested by SW to the HW is successful or not and take actions accordingly.
529 **/
530void i40e_fd_handle_status(struct i40e_ring *rx_ring,
531 union i40e_rx_desc *rx_desc, u8 prog_id)
532{
533 struct i40e_pf *pf = rx_ring->vsi->back;
534 struct pci_dev *pdev = pf->pdev;
535 u32 fcnt_prog, fcnt_avail;
536 u32 error;
537 u64 qw;
538
539 qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
540 error = (qw & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
541 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
542
543 if (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
544 pf->fd_inv = le32_to_cpu(rx_desc->wb.qword0.hi_dword.fd_id);
545 if ((rx_desc->wb.qword0.hi_dword.fd_id != 0) ||
546 (I40E_DEBUG_FD & pf->hw.debug_mask))
547 dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n",
548 pf->fd_inv);
549
550 /* Check if the programming error is for ATR.
551 * If so, auto disable ATR and set a state for
552 * flush in progress. Next time we come here if flush is in
553 * progress do nothing, once flush is complete the state will
554 * be cleared.
555 */
556 if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state))
557 return;
558
559 pf->fd_add_err++;
560 /* store the current atr filter count */
561 pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf);
562
563 if ((rx_desc->wb.qword0.hi_dword.fd_id == 0) &&
564 test_bit(__I40E_FD_SB_AUTO_DISABLED, pf->state)) {
565 /* These set_bit() calls aren't atomic with the
566 * test_bit() here, but worse case we potentially
567 * disable ATR and queue a flush right after SB
568 * support is re-enabled. That shouldn't cause an
569 * issue in practice
570 */
571 set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state);
572 set_bit(__I40E_FD_FLUSH_REQUESTED, pf->state);
573 }
574
575 /* filter programming failed most likely due to table full */
576 fcnt_prog = i40e_get_global_fd_count(pf);
577 fcnt_avail = pf->fdir_pf_filter_count;
578 /* If ATR is running fcnt_prog can quickly change,
579 * if we are very close to full, it makes sense to disable
580 * FD ATR/SB and then re-enable it when there is room.
581 */
582 if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) {
583 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
584 !test_and_set_bit(__I40E_FD_SB_AUTO_DISABLED,
585 pf->state))
586 if (I40E_DEBUG_FD & pf->hw.debug_mask)
587 dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n");
588 }
589 } else if (error == BIT(I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
590 if (I40E_DEBUG_FD & pf->hw.debug_mask)
591 dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n",
592 rx_desc->wb.qword0.hi_dword.fd_id);
593 }
594}
595
596/**
597 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
598 * @ring: the ring that owns the buffer
599 * @tx_buffer: the buffer to free
600 **/
601static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
602 struct i40e_tx_buffer *tx_buffer)
603{
604 if (tx_buffer->skb) {
605 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
606 kfree(tx_buffer->raw_buf);
607 else if (ring_is_xdp(ring))
608 xdp_return_frame(tx_buffer->xdpf);
609 else
610 dev_kfree_skb_any(tx_buffer->skb);
611 if (dma_unmap_len(tx_buffer, len))
612 dma_unmap_single(ring->dev,
613 dma_unmap_addr(tx_buffer, dma),
614 dma_unmap_len(tx_buffer, len),
615 DMA_TO_DEVICE);
616 } else if (dma_unmap_len(tx_buffer, len)) {
617 dma_unmap_page(ring->dev,
618 dma_unmap_addr(tx_buffer, dma),
619 dma_unmap_len(tx_buffer, len),
620 DMA_TO_DEVICE);
621 }
622
623 tx_buffer->next_to_watch = NULL;
624 tx_buffer->skb = NULL;
625 dma_unmap_len_set(tx_buffer, len, 0);
626 /* tx_buffer must be completely set up in the transmit path */
627}
628
629/**
630 * i40e_clean_tx_ring - Free any empty Tx buffers
631 * @tx_ring: ring to be cleaned
632 **/
633void i40e_clean_tx_ring(struct i40e_ring *tx_ring)
634{
635 unsigned long bi_size;
636 u16 i;
637
638 if (ring_is_xdp(tx_ring) && tx_ring->xsk_umem) {
639 i40e_xsk_clean_tx_ring(tx_ring);
640 } else {
641 /* ring already cleared, nothing to do */
642 if (!tx_ring->tx_bi)
643 return;
644
645 /* Free all the Tx ring sk_buffs */
646 for (i = 0; i < tx_ring->count; i++)
647 i40e_unmap_and_free_tx_resource(tx_ring,
648 &tx_ring->tx_bi[i]);
649 }
650
651 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
652 memset(tx_ring->tx_bi, 0, bi_size);
653
654 /* Zero out the descriptor ring */
655 memset(tx_ring->desc, 0, tx_ring->size);
656
657 tx_ring->next_to_use = 0;
658 tx_ring->next_to_clean = 0;
659
660 if (!tx_ring->netdev)
661 return;
662
663 /* cleanup Tx queue statistics */
664 netdev_tx_reset_queue(txring_txq(tx_ring));
665}
666
667/**
668 * i40e_free_tx_resources - Free Tx resources per queue
669 * @tx_ring: Tx descriptor ring for a specific queue
670 *
671 * Free all transmit software resources
672 **/
673void i40e_free_tx_resources(struct i40e_ring *tx_ring)
674{
675 i40e_clean_tx_ring(tx_ring);
676 kfree(tx_ring->tx_bi);
677 tx_ring->tx_bi = NULL;
678
679 if (tx_ring->desc) {
680 dma_free_coherent(tx_ring->dev, tx_ring->size,
681 tx_ring->desc, tx_ring->dma);
682 tx_ring->desc = NULL;
683 }
684}
685
686/**
687 * i40e_get_tx_pending - how many tx descriptors not processed
688 * @ring: the ring of descriptors
689 * @in_sw: use SW variables
690 *
691 * Since there is no access to the ring head register
692 * in XL710, we need to use our local copies
693 **/
694u32 i40e_get_tx_pending(struct i40e_ring *ring, bool in_sw)
695{
696 u32 head, tail;
697
698 if (!in_sw) {
699 head = i40e_get_head(ring);
700 tail = readl(ring->tail);
701 } else {
702 head = ring->next_to_clean;
703 tail = ring->next_to_use;
704 }
705
706 if (head != tail)
707 return (head < tail) ?
708 tail - head : (tail + ring->count - head);
709
710 return 0;
711}
712
713/**
714 * i40e_detect_recover_hung - Function to detect and recover hung_queues
715 * @vsi: pointer to vsi struct with tx queues
716 *
717 * VSI has netdev and netdev has TX queues. This function is to check each of
718 * those TX queues if they are hung, trigger recovery by issuing SW interrupt.
719 **/
720void i40e_detect_recover_hung(struct i40e_vsi *vsi)
721{
722 struct i40e_ring *tx_ring = NULL;
723 struct net_device *netdev;
724 unsigned int i;
725 int packets;
726
727 if (!vsi)
728 return;
729
730 if (test_bit(__I40E_VSI_DOWN, vsi->state))
731 return;
732
733 netdev = vsi->netdev;
734 if (!netdev)
735 return;
736
737 if (!netif_carrier_ok(netdev))
738 return;
739
740 for (i = 0; i < vsi->num_queue_pairs; i++) {
741 tx_ring = vsi->tx_rings[i];
742 if (tx_ring && tx_ring->desc) {
743 /* If packet counter has not changed the queue is
744 * likely stalled, so force an interrupt for this
745 * queue.
746 *
747 * prev_pkt_ctr would be negative if there was no
748 * pending work.
749 */
750 packets = tx_ring->stats.packets & INT_MAX;
751 if (tx_ring->tx_stats.prev_pkt_ctr == packets) {
752 i40e_force_wb(vsi, tx_ring->q_vector);
753 continue;
754 }
755
756 /* Memory barrier between read of packet count and call
757 * to i40e_get_tx_pending()
758 */
759 smp_rmb();
760 tx_ring->tx_stats.prev_pkt_ctr =
761 i40e_get_tx_pending(tx_ring, true) ? packets : -1;
762 }
763 }
764}
765
766/**
767 * i40e_clean_tx_irq - Reclaim resources after transmit completes
768 * @vsi: the VSI we care about
769 * @tx_ring: Tx ring to clean
770 * @napi_budget: Used to determine if we are in netpoll
771 *
772 * Returns true if there's any budget left (e.g. the clean is finished)
773 **/
774static bool i40e_clean_tx_irq(struct i40e_vsi *vsi,
775 struct i40e_ring *tx_ring, int napi_budget)
776{
777 int i = tx_ring->next_to_clean;
778 struct i40e_tx_buffer *tx_buf;
779 struct i40e_tx_desc *tx_head;
780 struct i40e_tx_desc *tx_desc;
781 unsigned int total_bytes = 0, total_packets = 0;
782 unsigned int budget = vsi->work_limit;
783
784 tx_buf = &tx_ring->tx_bi[i];
785 tx_desc = I40E_TX_DESC(tx_ring, i);
786 i -= tx_ring->count;
787
788 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
789
790 do {
791 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
792
793 /* if next_to_watch is not set then there is no work pending */
794 if (!eop_desc)
795 break;
796
797 /* prevent any other reads prior to eop_desc */
798 smp_rmb();
799
800 i40e_trace(clean_tx_irq, tx_ring, tx_desc, tx_buf);
801 /* we have caught up to head, no work left to do */
802 if (tx_head == tx_desc)
803 break;
804
805 /* clear next_to_watch to prevent false hangs */
806 tx_buf->next_to_watch = NULL;
807
808 /* update the statistics for this packet */
809 total_bytes += tx_buf->bytecount;
810 total_packets += tx_buf->gso_segs;
811
812 /* free the skb/XDP data */
813 if (ring_is_xdp(tx_ring))
814 xdp_return_frame(tx_buf->xdpf);
815 else
816 napi_consume_skb(tx_buf->skb, napi_budget);
817
818 /* unmap skb header data */
819 dma_unmap_single(tx_ring->dev,
820 dma_unmap_addr(tx_buf, dma),
821 dma_unmap_len(tx_buf, len),
822 DMA_TO_DEVICE);
823
824 /* clear tx_buffer data */
825 tx_buf->skb = NULL;
826 dma_unmap_len_set(tx_buf, len, 0);
827
828 /* unmap remaining buffers */
829 while (tx_desc != eop_desc) {
830 i40e_trace(clean_tx_irq_unmap,
831 tx_ring, tx_desc, tx_buf);
832
833 tx_buf++;
834 tx_desc++;
835 i++;
836 if (unlikely(!i)) {
837 i -= tx_ring->count;
838 tx_buf = tx_ring->tx_bi;
839 tx_desc = I40E_TX_DESC(tx_ring, 0);
840 }
841
842 /* unmap any remaining paged data */
843 if (dma_unmap_len(tx_buf, len)) {
844 dma_unmap_page(tx_ring->dev,
845 dma_unmap_addr(tx_buf, dma),
846 dma_unmap_len(tx_buf, len),
847 DMA_TO_DEVICE);
848 dma_unmap_len_set(tx_buf, len, 0);
849 }
850 }
851
852 /* move us one more past the eop_desc for start of next pkt */
853 tx_buf++;
854 tx_desc++;
855 i++;
856 if (unlikely(!i)) {
857 i -= tx_ring->count;
858 tx_buf = tx_ring->tx_bi;
859 tx_desc = I40E_TX_DESC(tx_ring, 0);
860 }
861
862 prefetch(tx_desc);
863
864 /* update budget accounting */
865 budget--;
866 } while (likely(budget));
867
868 i += tx_ring->count;
869 tx_ring->next_to_clean = i;
870 i40e_update_tx_stats(tx_ring, total_packets, total_bytes);
871 i40e_arm_wb(tx_ring, vsi, budget);
872
873 if (ring_is_xdp(tx_ring))
874 return !!budget;
875
876 /* notify netdev of completed buffers */
877 netdev_tx_completed_queue(txring_txq(tx_ring),
878 total_packets, total_bytes);
879
880#define TX_WAKE_THRESHOLD ((s16)(DESC_NEEDED * 2))
881 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
882 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
883 /* Make sure that anybody stopping the queue after this
884 * sees the new next_to_clean.
885 */
886 smp_mb();
887 if (__netif_subqueue_stopped(tx_ring->netdev,
888 tx_ring->queue_index) &&
889 !test_bit(__I40E_VSI_DOWN, vsi->state)) {
890 netif_wake_subqueue(tx_ring->netdev,
891 tx_ring->queue_index);
892 ++tx_ring->tx_stats.restart_queue;
893 }
894 }
895
896 return !!budget;
897}
898
899/**
900 * i40e_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled
901 * @vsi: the VSI we care about
902 * @q_vector: the vector on which to enable writeback
903 *
904 **/
905static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi,
906 struct i40e_q_vector *q_vector)
907{
908 u16 flags = q_vector->tx.ring[0].flags;
909 u32 val;
910
911 if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR))
912 return;
913
914 if (q_vector->arm_wb_state)
915 return;
916
917 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
918 val = I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK |
919 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK; /* set noitr */
920
921 wr32(&vsi->back->hw,
922 I40E_PFINT_DYN_CTLN(q_vector->reg_idx),
923 val);
924 } else {
925 val = I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK |
926 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK; /* set noitr */
927
928 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val);
929 }
930 q_vector->arm_wb_state = true;
931}
932
933/**
934 * i40e_force_wb - Issue SW Interrupt so HW does a wb
935 * @vsi: the VSI we care about
936 * @q_vector: the vector on which to force writeback
937 *
938 **/
939void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
940{
941 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
942 u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
943 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK | /* set noitr */
944 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK |
945 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK;
946 /* allow 00 to be written to the index */
947
948 wr32(&vsi->back->hw,
949 I40E_PFINT_DYN_CTLN(q_vector->reg_idx), val);
950 } else {
951 u32 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
952 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK | /* set noitr */
953 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK |
954 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK;
955 /* allow 00 to be written to the index */
956
957 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val);
958 }
959}
960
961static inline bool i40e_container_is_rx(struct i40e_q_vector *q_vector,
962 struct i40e_ring_container *rc)
963{
964 return &q_vector->rx == rc;
965}
966
967static inline unsigned int i40e_itr_divisor(struct i40e_q_vector *q_vector)
968{
969 unsigned int divisor;
970
971 switch (q_vector->vsi->back->hw.phy.link_info.link_speed) {
972 case I40E_LINK_SPEED_40GB:
973 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 1024;
974 break;
975 case I40E_LINK_SPEED_25GB:
976 case I40E_LINK_SPEED_20GB:
977 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 512;
978 break;
979 default:
980 case I40E_LINK_SPEED_10GB:
981 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 256;
982 break;
983 case I40E_LINK_SPEED_1GB:
984 case I40E_LINK_SPEED_100MB:
985 divisor = I40E_ITR_ADAPTIVE_MIN_INC * 32;
986 break;
987 }
988
989 return divisor;
990}
991
992/**
993 * i40e_update_itr - update the dynamic ITR value based on statistics
994 * @q_vector: structure containing interrupt and ring information
995 * @rc: structure containing ring performance data
996 *
997 * Stores a new ITR value based on packets and byte
998 * counts during the last interrupt. The advantage of per interrupt
999 * computation is faster updates and more accurate ITR for the current
1000 * traffic pattern. Constants in this function were computed
1001 * based on theoretical maximum wire speed and thresholds were set based
1002 * on testing data as well as attempting to minimize response time
1003 * while increasing bulk throughput.
1004 **/
1005static void i40e_update_itr(struct i40e_q_vector *q_vector,
1006 struct i40e_ring_container *rc)
1007{
1008 unsigned int avg_wire_size, packets, bytes, itr;
1009 unsigned long next_update = jiffies;
1010
1011 /* If we don't have any rings just leave ourselves set for maximum
1012 * possible latency so we take ourselves out of the equation.
1013 */
1014 if (!rc->ring || !ITR_IS_DYNAMIC(rc->ring->itr_setting))
1015 return;
1016
1017 /* For Rx we want to push the delay up and default to low latency.
1018 * for Tx we want to pull the delay down and default to high latency.
1019 */
1020 itr = i40e_container_is_rx(q_vector, rc) ?
1021 I40E_ITR_ADAPTIVE_MIN_USECS | I40E_ITR_ADAPTIVE_LATENCY :
1022 I40E_ITR_ADAPTIVE_MAX_USECS | I40E_ITR_ADAPTIVE_LATENCY;
1023
1024 /* If we didn't update within up to 1 - 2 jiffies we can assume
1025 * that either packets are coming in so slow there hasn't been
1026 * any work, or that there is so much work that NAPI is dealing
1027 * with interrupt moderation and we don't need to do anything.
1028 */
1029 if (time_after(next_update, rc->next_update))
1030 goto clear_counts;
1031
1032 /* If itr_countdown is set it means we programmed an ITR within
1033 * the last 4 interrupt cycles. This has a side effect of us
1034 * potentially firing an early interrupt. In order to work around
1035 * this we need to throw out any data received for a few
1036 * interrupts following the update.
1037 */
1038 if (q_vector->itr_countdown) {
1039 itr = rc->target_itr;
1040 goto clear_counts;
1041 }
1042
1043 packets = rc->total_packets;
1044 bytes = rc->total_bytes;
1045
1046 if (i40e_container_is_rx(q_vector, rc)) {
1047 /* If Rx there are 1 to 4 packets and bytes are less than
1048 * 9000 assume insufficient data to use bulk rate limiting
1049 * approach unless Tx is already in bulk rate limiting. We
1050 * are likely latency driven.
1051 */
1052 if (packets && packets < 4 && bytes < 9000 &&
1053 (q_vector->tx.target_itr & I40E_ITR_ADAPTIVE_LATENCY)) {
1054 itr = I40E_ITR_ADAPTIVE_LATENCY;
1055 goto adjust_by_size;
1056 }
1057 } else if (packets < 4) {
1058 /* If we have Tx and Rx ITR maxed and Tx ITR is running in
1059 * bulk mode and we are receiving 4 or fewer packets just
1060 * reset the ITR_ADAPTIVE_LATENCY bit for latency mode so
1061 * that the Rx can relax.
1062 */
1063 if (rc->target_itr == I40E_ITR_ADAPTIVE_MAX_USECS &&
1064 (q_vector->rx.target_itr & I40E_ITR_MASK) ==
1065 I40E_ITR_ADAPTIVE_MAX_USECS)
1066 goto clear_counts;
1067 } else if (packets > 32) {
1068 /* If we have processed over 32 packets in a single interrupt
1069 * for Tx assume we need to switch over to "bulk" mode.
1070 */
1071 rc->target_itr &= ~I40E_ITR_ADAPTIVE_LATENCY;
1072 }
1073
1074 /* We have no packets to actually measure against. This means
1075 * either one of the other queues on this vector is active or
1076 * we are a Tx queue doing TSO with too high of an interrupt rate.
1077 *
1078 * Between 4 and 56 we can assume that our current interrupt delay
1079 * is only slightly too low. As such we should increase it by a small
1080 * fixed amount.
1081 */
1082 if (packets < 56) {
1083 itr = rc->target_itr + I40E_ITR_ADAPTIVE_MIN_INC;
1084 if ((itr & I40E_ITR_MASK) > I40E_ITR_ADAPTIVE_MAX_USECS) {
1085 itr &= I40E_ITR_ADAPTIVE_LATENCY;
1086 itr += I40E_ITR_ADAPTIVE_MAX_USECS;
1087 }
1088 goto clear_counts;
1089 }
1090
1091 if (packets <= 256) {
1092 itr = min(q_vector->tx.current_itr, q_vector->rx.current_itr);
1093 itr &= I40E_ITR_MASK;
1094
1095 /* Between 56 and 112 is our "goldilocks" zone where we are
1096 * working out "just right". Just report that our current
1097 * ITR is good for us.
1098 */
1099 if (packets <= 112)
1100 goto clear_counts;
1101
1102 /* If packet count is 128 or greater we are likely looking
1103 * at a slight overrun of the delay we want. Try halving
1104 * our delay to see if that will cut the number of packets
1105 * in half per interrupt.
1106 */
1107 itr /= 2;
1108 itr &= I40E_ITR_MASK;
1109 if (itr < I40E_ITR_ADAPTIVE_MIN_USECS)
1110 itr = I40E_ITR_ADAPTIVE_MIN_USECS;
1111
1112 goto clear_counts;
1113 }
1114
1115 /* The paths below assume we are dealing with a bulk ITR since
1116 * number of packets is greater than 256. We are just going to have
1117 * to compute a value and try to bring the count under control,
1118 * though for smaller packet sizes there isn't much we can do as
1119 * NAPI polling will likely be kicking in sooner rather than later.
1120 */
1121 itr = I40E_ITR_ADAPTIVE_BULK;
1122
1123adjust_by_size:
1124 /* If packet counts are 256 or greater we can assume we have a gross
1125 * overestimation of what the rate should be. Instead of trying to fine
1126 * tune it just use the formula below to try and dial in an exact value
1127 * give the current packet size of the frame.
1128 */
1129 avg_wire_size = bytes / packets;
1130
1131 /* The following is a crude approximation of:
1132 * wmem_default / (size + overhead) = desired_pkts_per_int
1133 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate
1134 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value
1135 *
1136 * Assuming wmem_default is 212992 and overhead is 640 bytes per
1137 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the
1138 * formula down to
1139 *
1140 * (170 * (size + 24)) / (size + 640) = ITR
1141 *
1142 * We first do some math on the packet size and then finally bitshift
1143 * by 8 after rounding up. We also have to account for PCIe link speed
1144 * difference as ITR scales based on this.
1145 */
1146 if (avg_wire_size <= 60) {
1147 /* Start at 250k ints/sec */
1148 avg_wire_size = 4096;
1149 } else if (avg_wire_size <= 380) {
1150 /* 250K ints/sec to 60K ints/sec */
1151 avg_wire_size *= 40;
1152 avg_wire_size += 1696;
1153 } else if (avg_wire_size <= 1084) {
1154 /* 60K ints/sec to 36K ints/sec */
1155 avg_wire_size *= 15;
1156 avg_wire_size += 11452;
1157 } else if (avg_wire_size <= 1980) {
1158 /* 36K ints/sec to 30K ints/sec */
1159 avg_wire_size *= 5;
1160 avg_wire_size += 22420;
1161 } else {
1162 /* plateau at a limit of 30K ints/sec */
1163 avg_wire_size = 32256;
1164 }
1165
1166 /* If we are in low latency mode halve our delay which doubles the
1167 * rate to somewhere between 100K to 16K ints/sec
1168 */
1169 if (itr & I40E_ITR_ADAPTIVE_LATENCY)
1170 avg_wire_size /= 2;
1171
1172 /* Resultant value is 256 times larger than it needs to be. This
1173 * gives us room to adjust the value as needed to either increase
1174 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc.
1175 *
1176 * Use addition as we have already recorded the new latency flag
1177 * for the ITR value.
1178 */
1179 itr += DIV_ROUND_UP(avg_wire_size, i40e_itr_divisor(q_vector)) *
1180 I40E_ITR_ADAPTIVE_MIN_INC;
1181
1182 if ((itr & I40E_ITR_MASK) > I40E_ITR_ADAPTIVE_MAX_USECS) {
1183 itr &= I40E_ITR_ADAPTIVE_LATENCY;
1184 itr += I40E_ITR_ADAPTIVE_MAX_USECS;
1185 }
1186
1187clear_counts:
1188 /* write back value */
1189 rc->target_itr = itr;
1190
1191 /* next update should occur within next jiffy */
1192 rc->next_update = next_update + 1;
1193
1194 rc->total_bytes = 0;
1195 rc->total_packets = 0;
1196}
1197
1198/**
1199 * i40e_reuse_rx_page - page flip buffer and store it back on the ring
1200 * @rx_ring: rx descriptor ring to store buffers on
1201 * @old_buff: donor buffer to have page reused
1202 *
1203 * Synchronizes page for reuse by the adapter
1204 **/
1205static void i40e_reuse_rx_page(struct i40e_ring *rx_ring,
1206 struct i40e_rx_buffer *old_buff)
1207{
1208 struct i40e_rx_buffer *new_buff;
1209 u16 nta = rx_ring->next_to_alloc;
1210
1211 new_buff = &rx_ring->rx_bi[nta];
1212
1213 /* update, and store next to alloc */
1214 nta++;
1215 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1216
1217 /* transfer page from old buffer to new buffer */
1218 new_buff->dma = old_buff->dma;
1219 new_buff->page = old_buff->page;
1220 new_buff->page_offset = old_buff->page_offset;
1221 new_buff->pagecnt_bias = old_buff->pagecnt_bias;
1222
1223 rx_ring->rx_stats.page_reuse_count++;
1224
1225 /* clear contents of buffer_info */
1226 old_buff->page = NULL;
1227}
1228
1229/**
1230 * i40e_rx_is_programming_status - check for programming status descriptor
1231 * @qw: qword representing status_error_len in CPU ordering
1232 *
1233 * The value of in the descriptor length field indicate if this
1234 * is a programming status descriptor for flow director or FCoE
1235 * by the value of I40E_RX_PROG_STATUS_DESC_LENGTH, otherwise
1236 * it is a packet descriptor.
1237 **/
1238static inline bool i40e_rx_is_programming_status(u64 qw)
1239{
1240 /* The Rx filter programming status and SPH bit occupy the same
1241 * spot in the descriptor. Since we don't support packet split we
1242 * can just reuse the bit as an indication that this is a
1243 * programming status descriptor.
1244 */
1245 return qw & I40E_RXD_QW1_LENGTH_SPH_MASK;
1246}
1247
1248/**
1249 * i40e_clean_programming_status - try clean the programming status descriptor
1250 * @rx_ring: the rx ring that has this descriptor
1251 * @rx_desc: the rx descriptor written back by HW
1252 * @qw: qword representing status_error_len in CPU ordering
1253 *
1254 * Flow director should handle FD_FILTER_STATUS to check its filter programming
1255 * status being successful or not and take actions accordingly. FCoE should
1256 * handle its context/filter programming/invalidation status and take actions.
1257 *
1258 * Returns an i40e_rx_buffer to reuse if the cleanup occurred, otherwise NULL.
1259 **/
1260struct i40e_rx_buffer *i40e_clean_programming_status(
1261 struct i40e_ring *rx_ring,
1262 union i40e_rx_desc *rx_desc,
1263 u64 qw)
1264{
1265 struct i40e_rx_buffer *rx_buffer;
1266 u32 ntc;
1267 u8 id;
1268
1269 if (!i40e_rx_is_programming_status(qw))
1270 return NULL;
1271
1272 ntc = rx_ring->next_to_clean;
1273
1274 /* fetch, update, and store next to clean */
1275 rx_buffer = &rx_ring->rx_bi[ntc++];
1276 ntc = (ntc < rx_ring->count) ? ntc : 0;
1277 rx_ring->next_to_clean = ntc;
1278
1279 prefetch(I40E_RX_DESC(rx_ring, ntc));
1280
1281 id = (qw & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
1282 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
1283
1284 if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS)
1285 i40e_fd_handle_status(rx_ring, rx_desc, id);
1286
1287 return rx_buffer;
1288}
1289
1290/**
1291 * i40e_setup_tx_descriptors - Allocate the Tx descriptors
1292 * @tx_ring: the tx ring to set up
1293 *
1294 * Return 0 on success, negative on error
1295 **/
1296int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring)
1297{
1298 struct device *dev = tx_ring->dev;
1299 int bi_size;
1300
1301 if (!dev)
1302 return -ENOMEM;
1303
1304 /* warn if we are about to overwrite the pointer */
1305 WARN_ON(tx_ring->tx_bi);
1306 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
1307 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
1308 if (!tx_ring->tx_bi)
1309 goto err;
1310
1311 u64_stats_init(&tx_ring->syncp);
1312
1313 /* round up to nearest 4K */
1314 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
1315 /* add u32 for head writeback, align after this takes care of
1316 * guaranteeing this is at least one cache line in size
1317 */
1318 tx_ring->size += sizeof(u32);
1319 tx_ring->size = ALIGN(tx_ring->size, 4096);
1320 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
1321 &tx_ring->dma, GFP_KERNEL);
1322 if (!tx_ring->desc) {
1323 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
1324 tx_ring->size);
1325 goto err;
1326 }
1327
1328 tx_ring->next_to_use = 0;
1329 tx_ring->next_to_clean = 0;
1330 tx_ring->tx_stats.prev_pkt_ctr = -1;
1331 return 0;
1332
1333err:
1334 kfree(tx_ring->tx_bi);
1335 tx_ring->tx_bi = NULL;
1336 return -ENOMEM;
1337}
1338
1339/**
1340 * i40e_clean_rx_ring - Free Rx buffers
1341 * @rx_ring: ring to be cleaned
1342 **/
1343void i40e_clean_rx_ring(struct i40e_ring *rx_ring)
1344{
1345 unsigned long bi_size;
1346 u16 i;
1347
1348 /* ring already cleared, nothing to do */
1349 if (!rx_ring->rx_bi)
1350 return;
1351
1352 if (rx_ring->skb) {
1353 dev_kfree_skb(rx_ring->skb);
1354 rx_ring->skb = NULL;
1355 }
1356
1357 if (rx_ring->xsk_umem) {
1358 i40e_xsk_clean_rx_ring(rx_ring);
1359 goto skip_free;
1360 }
1361
1362 /* Free all the Rx ring sk_buffs */
1363 for (i = 0; i < rx_ring->count; i++) {
1364 struct i40e_rx_buffer *rx_bi = &rx_ring->rx_bi[i];
1365
1366 if (!rx_bi->page)
1367 continue;
1368
1369 /* Invalidate cache lines that may have been written to by
1370 * device so that we avoid corrupting memory.
1371 */
1372 dma_sync_single_range_for_cpu(rx_ring->dev,
1373 rx_bi->dma,
1374 rx_bi->page_offset,
1375 rx_ring->rx_buf_len,
1376 DMA_FROM_DEVICE);
1377
1378 /* free resources associated with mapping */
1379 dma_unmap_page_attrs(rx_ring->dev, rx_bi->dma,
1380 i40e_rx_pg_size(rx_ring),
1381 DMA_FROM_DEVICE,
1382 I40E_RX_DMA_ATTR);
1383
1384 __page_frag_cache_drain(rx_bi->page, rx_bi->pagecnt_bias);
1385
1386 rx_bi->page = NULL;
1387 rx_bi->page_offset = 0;
1388 }
1389
1390skip_free:
1391 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
1392 memset(rx_ring->rx_bi, 0, bi_size);
1393
1394 /* Zero out the descriptor ring */
1395 memset(rx_ring->desc, 0, rx_ring->size);
1396
1397 rx_ring->next_to_alloc = 0;
1398 rx_ring->next_to_clean = 0;
1399 rx_ring->next_to_use = 0;
1400}
1401
1402/**
1403 * i40e_free_rx_resources - Free Rx resources
1404 * @rx_ring: ring to clean the resources from
1405 *
1406 * Free all receive software resources
1407 **/
1408void i40e_free_rx_resources(struct i40e_ring *rx_ring)
1409{
1410 i40e_clean_rx_ring(rx_ring);
1411 if (rx_ring->vsi->type == I40E_VSI_MAIN)
1412 xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
1413 rx_ring->xdp_prog = NULL;
1414 kfree(rx_ring->rx_bi);
1415 rx_ring->rx_bi = NULL;
1416
1417 if (rx_ring->desc) {
1418 dma_free_coherent(rx_ring->dev, rx_ring->size,
1419 rx_ring->desc, rx_ring->dma);
1420 rx_ring->desc = NULL;
1421 }
1422}
1423
1424/**
1425 * i40e_setup_rx_descriptors - Allocate Rx descriptors
1426 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
1427 *
1428 * Returns 0 on success, negative on failure
1429 **/
1430int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring)
1431{
1432 struct device *dev = rx_ring->dev;
1433 int err = -ENOMEM;
1434 int bi_size;
1435
1436 /* warn if we are about to overwrite the pointer */
1437 WARN_ON(rx_ring->rx_bi);
1438 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
1439 rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
1440 if (!rx_ring->rx_bi)
1441 goto err;
1442
1443 u64_stats_init(&rx_ring->syncp);
1444
1445 /* Round up to nearest 4K */
1446 rx_ring->size = rx_ring->count * sizeof(union i40e_32byte_rx_desc);
1447 rx_ring->size = ALIGN(rx_ring->size, 4096);
1448 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1449 &rx_ring->dma, GFP_KERNEL);
1450
1451 if (!rx_ring->desc) {
1452 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
1453 rx_ring->size);
1454 goto err;
1455 }
1456
1457 rx_ring->next_to_alloc = 0;
1458 rx_ring->next_to_clean = 0;
1459 rx_ring->next_to_use = 0;
1460
1461 /* XDP RX-queue info only needed for RX rings exposed to XDP */
1462 if (rx_ring->vsi->type == I40E_VSI_MAIN) {
1463 err = xdp_rxq_info_reg(&rx_ring->xdp_rxq, rx_ring->netdev,
1464 rx_ring->queue_index);
1465 if (err < 0)
1466 goto err;
1467 }
1468
1469 rx_ring->xdp_prog = rx_ring->vsi->xdp_prog;
1470
1471 return 0;
1472err:
1473 kfree(rx_ring->rx_bi);
1474 rx_ring->rx_bi = NULL;
1475 return err;
1476}
1477
1478/**
1479 * i40e_release_rx_desc - Store the new tail and head values
1480 * @rx_ring: ring to bump
1481 * @val: new head index
1482 **/
1483void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
1484{
1485 rx_ring->next_to_use = val;
1486
1487 /* update next to alloc since we have filled the ring */
1488 rx_ring->next_to_alloc = val;
1489
1490 /* Force memory writes to complete before letting h/w
1491 * know there are new descriptors to fetch. (Only
1492 * applicable for weak-ordered memory model archs,
1493 * such as IA-64).
1494 */
1495 wmb();
1496 writel(val, rx_ring->tail);
1497}
1498
1499/**
1500 * i40e_rx_offset - Return expected offset into page to access data
1501 * @rx_ring: Ring we are requesting offset of
1502 *
1503 * Returns the offset value for ring into the data buffer.
1504 */
1505static inline unsigned int i40e_rx_offset(struct i40e_ring *rx_ring)
1506{
1507 return ring_uses_build_skb(rx_ring) ? I40E_SKB_PAD : 0;
1508}
1509
1510/**
1511 * i40e_alloc_mapped_page - recycle or make a new page
1512 * @rx_ring: ring to use
1513 * @bi: rx_buffer struct to modify
1514 *
1515 * Returns true if the page was successfully allocated or
1516 * reused.
1517 **/
1518static bool i40e_alloc_mapped_page(struct i40e_ring *rx_ring,
1519 struct i40e_rx_buffer *bi)
1520{
1521 struct page *page = bi->page;
1522 dma_addr_t dma;
1523
1524 /* since we are recycling buffers we should seldom need to alloc */
1525 if (likely(page)) {
1526 rx_ring->rx_stats.page_reuse_count++;
1527 return true;
1528 }
1529
1530 /* alloc new page for storage */
1531 page = dev_alloc_pages(i40e_rx_pg_order(rx_ring));
1532 if (unlikely(!page)) {
1533 rx_ring->rx_stats.alloc_page_failed++;
1534 return false;
1535 }
1536
1537 /* map page for use */
1538 dma = dma_map_page_attrs(rx_ring->dev, page, 0,
1539 i40e_rx_pg_size(rx_ring),
1540 DMA_FROM_DEVICE,
1541 I40E_RX_DMA_ATTR);
1542
1543 /* if mapping failed free memory back to system since
1544 * there isn't much point in holding memory we can't use
1545 */
1546 if (dma_mapping_error(rx_ring->dev, dma)) {
1547 __free_pages(page, i40e_rx_pg_order(rx_ring));
1548 rx_ring->rx_stats.alloc_page_failed++;
1549 return false;
1550 }
1551
1552 bi->dma = dma;
1553 bi->page = page;
1554 bi->page_offset = i40e_rx_offset(rx_ring);
1555 page_ref_add(page, USHRT_MAX - 1);
1556 bi->pagecnt_bias = USHRT_MAX;
1557
1558 return true;
1559}
1560
1561/**
1562 * i40e_alloc_rx_buffers - Replace used receive buffers
1563 * @rx_ring: ring to place buffers on
1564 * @cleaned_count: number of buffers to replace
1565 *
1566 * Returns false if all allocations were successful, true if any fail
1567 **/
1568bool i40e_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count)
1569{
1570 u16 ntu = rx_ring->next_to_use;
1571 union i40e_rx_desc *rx_desc;
1572 struct i40e_rx_buffer *bi;
1573
1574 /* do nothing if no valid netdev defined */
1575 if (!rx_ring->netdev || !cleaned_count)
1576 return false;
1577
1578 rx_desc = I40E_RX_DESC(rx_ring, ntu);
1579 bi = &rx_ring->rx_bi[ntu];
1580
1581 do {
1582 if (!i40e_alloc_mapped_page(rx_ring, bi))
1583 goto no_buffers;
1584
1585 /* sync the buffer for use by the device */
1586 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
1587 bi->page_offset,
1588 rx_ring->rx_buf_len,
1589 DMA_FROM_DEVICE);
1590
1591 /* Refresh the desc even if buffer_addrs didn't change
1592 * because each write-back erases this info.
1593 */
1594 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1595
1596 rx_desc++;
1597 bi++;
1598 ntu++;
1599 if (unlikely(ntu == rx_ring->count)) {
1600 rx_desc = I40E_RX_DESC(rx_ring, 0);
1601 bi = rx_ring->rx_bi;
1602 ntu = 0;
1603 }
1604
1605 /* clear the status bits for the next_to_use descriptor */
1606 rx_desc->wb.qword1.status_error_len = 0;
1607
1608 cleaned_count--;
1609 } while (cleaned_count);
1610
1611 if (rx_ring->next_to_use != ntu)
1612 i40e_release_rx_desc(rx_ring, ntu);
1613
1614 return false;
1615
1616no_buffers:
1617 if (rx_ring->next_to_use != ntu)
1618 i40e_release_rx_desc(rx_ring, ntu);
1619
1620 /* make sure to come back via polling to try again after
1621 * allocation failure
1622 */
1623 return true;
1624}
1625
1626/**
1627 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
1628 * @vsi: the VSI we care about
1629 * @skb: skb currently being received and modified
1630 * @rx_desc: the receive descriptor
1631 **/
1632static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
1633 struct sk_buff *skb,
1634 union i40e_rx_desc *rx_desc)
1635{
1636 struct i40e_rx_ptype_decoded decoded;
1637 u32 rx_error, rx_status;
1638 bool ipv4, ipv6;
1639 u8 ptype;
1640 u64 qword;
1641
1642 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1643 ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT;
1644 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1645 I40E_RXD_QW1_ERROR_SHIFT;
1646 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1647 I40E_RXD_QW1_STATUS_SHIFT;
1648 decoded = decode_rx_desc_ptype(ptype);
1649
1650 skb->ip_summed = CHECKSUM_NONE;
1651
1652 skb_checksum_none_assert(skb);
1653
1654 /* Rx csum enabled and ip headers found? */
1655 if (!(vsi->netdev->features & NETIF_F_RXCSUM))
1656 return;
1657
1658 /* did the hardware decode the packet and checksum? */
1659 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
1660 return;
1661
1662 /* both known and outer_ip must be set for the below code to work */
1663 if (!(decoded.known && decoded.outer_ip))
1664 return;
1665
1666 ipv4 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) &&
1667 (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4);
1668 ipv6 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) &&
1669 (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6);
1670
1671 if (ipv4 &&
1672 (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
1673 BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
1674 goto checksum_fail;
1675
1676 /* likely incorrect csum if alternate IP extension headers found */
1677 if (ipv6 &&
1678 rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
1679 /* don't increment checksum err here, non-fatal err */
1680 return;
1681
1682 /* there was some L4 error, count error and punt packet to the stack */
1683 if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
1684 goto checksum_fail;
1685
1686 /* handle packets that were not able to be checksummed due
1687 * to arrival speed, in this case the stack can compute
1688 * the csum.
1689 */
1690 if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
1691 return;
1692
1693 /* If there is an outer header present that might contain a checksum
1694 * we need to bump the checksum level by 1 to reflect the fact that
1695 * we are indicating we validated the inner checksum.
1696 */
1697 if (decoded.tunnel_type >= I40E_RX_PTYPE_TUNNEL_IP_GRENAT)
1698 skb->csum_level = 1;
1699
1700 /* Only report checksum unnecessary for TCP, UDP, or SCTP */
1701 switch (decoded.inner_prot) {
1702 case I40E_RX_PTYPE_INNER_PROT_TCP:
1703 case I40E_RX_PTYPE_INNER_PROT_UDP:
1704 case I40E_RX_PTYPE_INNER_PROT_SCTP:
1705 skb->ip_summed = CHECKSUM_UNNECESSARY;
1706 /* fall though */
1707 default:
1708 break;
1709 }
1710
1711 return;
1712
1713checksum_fail:
1714 vsi->back->hw_csum_rx_error++;
1715}
1716
1717/**
1718 * i40e_ptype_to_htype - get a hash type
1719 * @ptype: the ptype value from the descriptor
1720 *
1721 * Returns a hash type to be used by skb_set_hash
1722 **/
1723static inline int i40e_ptype_to_htype(u8 ptype)
1724{
1725 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
1726
1727 if (!decoded.known)
1728 return PKT_HASH_TYPE_NONE;
1729
1730 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1731 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
1732 return PKT_HASH_TYPE_L4;
1733 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1734 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
1735 return PKT_HASH_TYPE_L3;
1736 else
1737 return PKT_HASH_TYPE_L2;
1738}
1739
1740/**
1741 * i40e_rx_hash - set the hash value in the skb
1742 * @ring: descriptor ring
1743 * @rx_desc: specific descriptor
1744 * @skb: skb currently being received and modified
1745 * @rx_ptype: Rx packet type
1746 **/
1747static inline void i40e_rx_hash(struct i40e_ring *ring,
1748 union i40e_rx_desc *rx_desc,
1749 struct sk_buff *skb,
1750 u8 rx_ptype)
1751{
1752 u32 hash;
1753 const __le64 rss_mask =
1754 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
1755 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
1756
1757 if (!(ring->netdev->features & NETIF_F_RXHASH))
1758 return;
1759
1760 if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) {
1761 hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
1762 skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype));
1763 }
1764}
1765
1766/**
1767 * i40e_process_skb_fields - Populate skb header fields from Rx descriptor
1768 * @rx_ring: rx descriptor ring packet is being transacted on
1769 * @rx_desc: pointer to the EOP Rx descriptor
1770 * @skb: pointer to current skb being populated
1771 * @rx_ptype: the packet type decoded by hardware
1772 *
1773 * This function checks the ring, descriptor, and packet information in
1774 * order to populate the hash, checksum, VLAN, protocol, and
1775 * other fields within the skb.
1776 **/
1777void i40e_process_skb_fields(struct i40e_ring *rx_ring,
1778 union i40e_rx_desc *rx_desc, struct sk_buff *skb)
1779{
1780 u64 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1781 u32 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1782 I40E_RXD_QW1_STATUS_SHIFT;
1783 u32 tsynvalid = rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK;
1784 u32 tsyn = (rx_status & I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >>
1785 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT;
1786 u8 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1787 I40E_RXD_QW1_PTYPE_SHIFT;
1788
1789 if (unlikely(tsynvalid))
1790 i40e_ptp_rx_hwtstamp(rx_ring->vsi->back, skb, tsyn);
1791
1792 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1793
1794 i40e_rx_checksum(rx_ring->vsi, skb, rx_desc);
1795
1796 skb_record_rx_queue(skb, rx_ring->queue_index);
1797
1798 if (qword & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
1799 u16 vlan_tag = rx_desc->wb.qword0.lo_dword.l2tag1;
1800
1801 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1802 le16_to_cpu(vlan_tag));
1803 }
1804
1805 /* modifies the skb - consumes the enet header */
1806 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1807}
1808
1809/**
1810 * i40e_cleanup_headers - Correct empty headers
1811 * @rx_ring: rx descriptor ring packet is being transacted on
1812 * @skb: pointer to current skb being fixed
1813 * @rx_desc: pointer to the EOP Rx descriptor
1814 *
1815 * Also address the case where we are pulling data in on pages only
1816 * and as such no data is present in the skb header.
1817 *
1818 * In addition if skb is not at least 60 bytes we need to pad it so that
1819 * it is large enough to qualify as a valid Ethernet frame.
1820 *
1821 * Returns true if an error was encountered and skb was freed.
1822 **/
1823static bool i40e_cleanup_headers(struct i40e_ring *rx_ring, struct sk_buff *skb,
1824 union i40e_rx_desc *rx_desc)
1825
1826{
1827 /* XDP packets use error pointer so abort at this point */
1828 if (IS_ERR(skb))
1829 return true;
1830
1831 /* ERR_MASK will only have valid bits if EOP set, and
1832 * what we are doing here is actually checking
1833 * I40E_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in
1834 * the error field
1835 */
1836 if (unlikely(i40e_test_staterr(rx_desc,
1837 BIT(I40E_RXD_QW1_ERROR_SHIFT)))) {
1838 dev_kfree_skb_any(skb);
1839 return true;
1840 }
1841
1842 /* if eth_skb_pad returns an error the skb was freed */
1843 if (eth_skb_pad(skb))
1844 return true;
1845
1846 return false;
1847}
1848
1849/**
1850 * i40e_page_is_reusable - check if any reuse is possible
1851 * @page: page struct to check
1852 *
1853 * A page is not reusable if it was allocated under low memory
1854 * conditions, or it's not in the same NUMA node as this CPU.
1855 */
1856static inline bool i40e_page_is_reusable(struct page *page)
1857{
1858 return (page_to_nid(page) == numa_mem_id()) &&
1859 !page_is_pfmemalloc(page);
1860}
1861
1862/**
1863 * i40e_can_reuse_rx_page - Determine if this page can be reused by
1864 * the adapter for another receive
1865 *
1866 * @rx_buffer: buffer containing the page
1867 *
1868 * If page is reusable, rx_buffer->page_offset is adjusted to point to
1869 * an unused region in the page.
1870 *
1871 * For small pages, @truesize will be a constant value, half the size
1872 * of the memory at page. We'll attempt to alternate between high and
1873 * low halves of the page, with one half ready for use by the hardware
1874 * and the other half being consumed by the stack. We use the page
1875 * ref count to determine whether the stack has finished consuming the
1876 * portion of this page that was passed up with a previous packet. If
1877 * the page ref count is >1, we'll assume the "other" half page is
1878 * still busy, and this page cannot be reused.
1879 *
1880 * For larger pages, @truesize will be the actual space used by the
1881 * received packet (adjusted upward to an even multiple of the cache
1882 * line size). This will advance through the page by the amount
1883 * actually consumed by the received packets while there is still
1884 * space for a buffer. Each region of larger pages will be used at
1885 * most once, after which the page will not be reused.
1886 *
1887 * In either case, if the page is reusable its refcount is increased.
1888 **/
1889static bool i40e_can_reuse_rx_page(struct i40e_rx_buffer *rx_buffer)
1890{
1891 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
1892 struct page *page = rx_buffer->page;
1893
1894 /* Is any reuse possible? */
1895 if (unlikely(!i40e_page_is_reusable(page)))
1896 return false;
1897
1898#if (PAGE_SIZE < 8192)
1899 /* if we are only owner of page we can reuse it */
1900 if (unlikely((page_count(page) - pagecnt_bias) > 1))
1901 return false;
1902#else
1903#define I40E_LAST_OFFSET \
1904 (SKB_WITH_OVERHEAD(PAGE_SIZE) - I40E_RXBUFFER_2048)
1905 if (rx_buffer->page_offset > I40E_LAST_OFFSET)
1906 return false;
1907#endif
1908
1909 /* If we have drained the page fragment pool we need to update
1910 * the pagecnt_bias and page count so that we fully restock the
1911 * number of references the driver holds.
1912 */
1913 if (unlikely(pagecnt_bias == 1)) {
1914 page_ref_add(page, USHRT_MAX - 1);
1915 rx_buffer->pagecnt_bias = USHRT_MAX;
1916 }
1917
1918 return true;
1919}
1920
1921/**
1922 * i40e_add_rx_frag - Add contents of Rx buffer to sk_buff
1923 * @rx_ring: rx descriptor ring to transact packets on
1924 * @rx_buffer: buffer containing page to add
1925 * @skb: sk_buff to place the data into
1926 * @size: packet length from rx_desc
1927 *
1928 * This function will add the data contained in rx_buffer->page to the skb.
1929 * It will just attach the page as a frag to the skb.
1930 *
1931 * The function will then update the page offset.
1932 **/
1933static void i40e_add_rx_frag(struct i40e_ring *rx_ring,
1934 struct i40e_rx_buffer *rx_buffer,
1935 struct sk_buff *skb,
1936 unsigned int size)
1937{
1938#if (PAGE_SIZE < 8192)
1939 unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2;
1940#else
1941 unsigned int truesize = SKB_DATA_ALIGN(size + i40e_rx_offset(rx_ring));
1942#endif
1943
1944 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
1945 rx_buffer->page_offset, size, truesize);
1946
1947 /* page is being used so we must update the page offset */
1948#if (PAGE_SIZE < 8192)
1949 rx_buffer->page_offset ^= truesize;
1950#else
1951 rx_buffer->page_offset += truesize;
1952#endif
1953}
1954
1955/**
1956 * i40e_get_rx_buffer - Fetch Rx buffer and synchronize data for use
1957 * @rx_ring: rx descriptor ring to transact packets on
1958 * @size: size of buffer to add to skb
1959 *
1960 * This function will pull an Rx buffer from the ring and synchronize it
1961 * for use by the CPU.
1962 */
1963static struct i40e_rx_buffer *i40e_get_rx_buffer(struct i40e_ring *rx_ring,
1964 const unsigned int size)
1965{
1966 struct i40e_rx_buffer *rx_buffer;
1967
1968 rx_buffer = &rx_ring->rx_bi[rx_ring->next_to_clean];
1969 prefetchw(rx_buffer->page);
1970
1971 /* we are reusing so sync this buffer for CPU use */
1972 dma_sync_single_range_for_cpu(rx_ring->dev,
1973 rx_buffer->dma,
1974 rx_buffer->page_offset,
1975 size,
1976 DMA_FROM_DEVICE);
1977
1978 /* We have pulled a buffer for use, so decrement pagecnt_bias */
1979 rx_buffer->pagecnt_bias--;
1980
1981 return rx_buffer;
1982}
1983
1984/**
1985 * i40e_construct_skb - Allocate skb and populate it
1986 * @rx_ring: rx descriptor ring to transact packets on
1987 * @rx_buffer: rx buffer to pull data from
1988 * @xdp: xdp_buff pointing to the data
1989 *
1990 * This function allocates an skb. It then populates it with the page
1991 * data from the current receive descriptor, taking care to set up the
1992 * skb correctly.
1993 */
1994static struct sk_buff *i40e_construct_skb(struct i40e_ring *rx_ring,
1995 struct i40e_rx_buffer *rx_buffer,
1996 struct xdp_buff *xdp)
1997{
1998 unsigned int size = xdp->data_end - xdp->data;
1999#if (PAGE_SIZE < 8192)
2000 unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2;
2001#else
2002 unsigned int truesize = SKB_DATA_ALIGN(size);
2003#endif
2004 unsigned int headlen;
2005 struct sk_buff *skb;
2006
2007 /* prefetch first cache line of first page */
2008 prefetch(xdp->data);
2009#if L1_CACHE_BYTES < 128
2010 prefetch(xdp->data + L1_CACHE_BYTES);
2011#endif
2012 /* Note, we get here by enabling legacy-rx via:
2013 *
2014 * ethtool --set-priv-flags <dev> legacy-rx on
2015 *
2016 * In this mode, we currently get 0 extra XDP headroom as
2017 * opposed to having legacy-rx off, where we process XDP
2018 * packets going to stack via i40e_build_skb(). The latter
2019 * provides us currently with 192 bytes of headroom.
2020 *
2021 * For i40e_construct_skb() mode it means that the
2022 * xdp->data_meta will always point to xdp->data, since
2023 * the helper cannot expand the head. Should this ever
2024 * change in future for legacy-rx mode on, then lets also
2025 * add xdp->data_meta handling here.
2026 */
2027
2028 /* allocate a skb to store the frags */
2029 skb = __napi_alloc_skb(&rx_ring->q_vector->napi,
2030 I40E_RX_HDR_SIZE,
2031 GFP_ATOMIC | __GFP_NOWARN);
2032 if (unlikely(!skb))
2033 return NULL;
2034
2035 /* Determine available headroom for copy */
2036 headlen = size;
2037 if (headlen > I40E_RX_HDR_SIZE)
2038 headlen = eth_get_headlen(skb->dev, xdp->data,
2039 I40E_RX_HDR_SIZE);
2040
2041 /* align pull length to size of long to optimize memcpy performance */
2042 memcpy(__skb_put(skb, headlen), xdp->data,
2043 ALIGN(headlen, sizeof(long)));
2044
2045 /* update all of the pointers */
2046 size -= headlen;
2047 if (size) {
2048 skb_add_rx_frag(skb, 0, rx_buffer->page,
2049 rx_buffer->page_offset + headlen,
2050 size, truesize);
2051
2052 /* buffer is used by skb, update page_offset */
2053#if (PAGE_SIZE < 8192)
2054 rx_buffer->page_offset ^= truesize;
2055#else
2056 rx_buffer->page_offset += truesize;
2057#endif
2058 } else {
2059 /* buffer is unused, reset bias back to rx_buffer */
2060 rx_buffer->pagecnt_bias++;
2061 }
2062
2063 return skb;
2064}
2065
2066/**
2067 * i40e_build_skb - Build skb around an existing buffer
2068 * @rx_ring: Rx descriptor ring to transact packets on
2069 * @rx_buffer: Rx buffer to pull data from
2070 * @xdp: xdp_buff pointing to the data
2071 *
2072 * This function builds an skb around an existing Rx buffer, taking care
2073 * to set up the skb correctly and avoid any memcpy overhead.
2074 */
2075static struct sk_buff *i40e_build_skb(struct i40e_ring *rx_ring,
2076 struct i40e_rx_buffer *rx_buffer,
2077 struct xdp_buff *xdp)
2078{
2079 unsigned int metasize = xdp->data - xdp->data_meta;
2080#if (PAGE_SIZE < 8192)
2081 unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2;
2082#else
2083 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
2084 SKB_DATA_ALIGN(xdp->data_end -
2085 xdp->data_hard_start);
2086#endif
2087 struct sk_buff *skb;
2088
2089 /* Prefetch first cache line of first page. If xdp->data_meta
2090 * is unused, this points exactly as xdp->data, otherwise we
2091 * likely have a consumer accessing first few bytes of meta
2092 * data, and then actual data.
2093 */
2094 prefetch(xdp->data_meta);
2095#if L1_CACHE_BYTES < 128
2096 prefetch(xdp->data_meta + L1_CACHE_BYTES);
2097#endif
2098 /* build an skb around the page buffer */
2099 skb = build_skb(xdp->data_hard_start, truesize);
2100 if (unlikely(!skb))
2101 return NULL;
2102
2103 /* update pointers within the skb to store the data */
2104 skb_reserve(skb, xdp->data - xdp->data_hard_start);
2105 __skb_put(skb, xdp->data_end - xdp->data);
2106 if (metasize)
2107 skb_metadata_set(skb, metasize);
2108
2109 /* buffer is used by skb, update page_offset */
2110#if (PAGE_SIZE < 8192)
2111 rx_buffer->page_offset ^= truesize;
2112#else
2113 rx_buffer->page_offset += truesize;
2114#endif
2115
2116 return skb;
2117}
2118
2119/**
2120 * i40e_put_rx_buffer - Clean up used buffer and either recycle or free
2121 * @rx_ring: rx descriptor ring to transact packets on
2122 * @rx_buffer: rx buffer to pull data from
2123 *
2124 * This function will clean up the contents of the rx_buffer. It will
2125 * either recycle the buffer or unmap it and free the associated resources.
2126 */
2127static void i40e_put_rx_buffer(struct i40e_ring *rx_ring,
2128 struct i40e_rx_buffer *rx_buffer)
2129{
2130 if (i40e_can_reuse_rx_page(rx_buffer)) {
2131 /* hand second half of page back to the ring */
2132 i40e_reuse_rx_page(rx_ring, rx_buffer);
2133 } else {
2134 /* we are not reusing the buffer so unmap it */
2135 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
2136 i40e_rx_pg_size(rx_ring),
2137 DMA_FROM_DEVICE, I40E_RX_DMA_ATTR);
2138 __page_frag_cache_drain(rx_buffer->page,
2139 rx_buffer->pagecnt_bias);
2140 /* clear contents of buffer_info */
2141 rx_buffer->page = NULL;
2142 }
2143}
2144
2145/**
2146 * i40e_is_non_eop - process handling of non-EOP buffers
2147 * @rx_ring: Rx ring being processed
2148 * @rx_desc: Rx descriptor for current buffer
2149 * @skb: Current socket buffer containing buffer in progress
2150 *
2151 * This function updates next to clean. If the buffer is an EOP buffer
2152 * this function exits returning false, otherwise it will place the
2153 * sk_buff in the next buffer to be chained and return true indicating
2154 * that this is in fact a non-EOP buffer.
2155 **/
2156static bool i40e_is_non_eop(struct i40e_ring *rx_ring,
2157 union i40e_rx_desc *rx_desc,
2158 struct sk_buff *skb)
2159{
2160 u32 ntc = rx_ring->next_to_clean + 1;
2161
2162 /* fetch, update, and store next to clean */
2163 ntc = (ntc < rx_ring->count) ? ntc : 0;
2164 rx_ring->next_to_clean = ntc;
2165
2166 prefetch(I40E_RX_DESC(rx_ring, ntc));
2167
2168 /* if we are the last buffer then there is nothing else to do */
2169#define I40E_RXD_EOF BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)
2170 if (likely(i40e_test_staterr(rx_desc, I40E_RXD_EOF)))
2171 return false;
2172
2173 rx_ring->rx_stats.non_eop_descs++;
2174
2175 return true;
2176}
2177
2178static int i40e_xmit_xdp_ring(struct xdp_frame *xdpf,
2179 struct i40e_ring *xdp_ring);
2180
2181int i40e_xmit_xdp_tx_ring(struct xdp_buff *xdp, struct i40e_ring *xdp_ring)
2182{
2183 struct xdp_frame *xdpf = convert_to_xdp_frame(xdp);
2184
2185 if (unlikely(!xdpf))
2186 return I40E_XDP_CONSUMED;
2187
2188 return i40e_xmit_xdp_ring(xdpf, xdp_ring);
2189}
2190
2191/**
2192 * i40e_run_xdp - run an XDP program
2193 * @rx_ring: Rx ring being processed
2194 * @xdp: XDP buffer containing the frame
2195 **/
2196static struct sk_buff *i40e_run_xdp(struct i40e_ring *rx_ring,
2197 struct xdp_buff *xdp)
2198{
2199 int err, result = I40E_XDP_PASS;
2200 struct i40e_ring *xdp_ring;
2201 struct bpf_prog *xdp_prog;
2202 u32 act;
2203
2204 rcu_read_lock();
2205 xdp_prog = READ_ONCE(rx_ring->xdp_prog);
2206
2207 if (!xdp_prog)
2208 goto xdp_out;
2209
2210 prefetchw(xdp->data_hard_start); /* xdp_frame write */
2211
2212 act = bpf_prog_run_xdp(xdp_prog, xdp);
2213 switch (act) {
2214 case XDP_PASS:
2215 break;
2216 case XDP_TX:
2217 xdp_ring = rx_ring->vsi->xdp_rings[rx_ring->queue_index];
2218 result = i40e_xmit_xdp_tx_ring(xdp, xdp_ring);
2219 break;
2220 case XDP_REDIRECT:
2221 err = xdp_do_redirect(rx_ring->netdev, xdp, xdp_prog);
2222 result = !err ? I40E_XDP_REDIR : I40E_XDP_CONSUMED;
2223 break;
2224 default:
2225 bpf_warn_invalid_xdp_action(act);
2226 /* fall through */
2227 case XDP_ABORTED:
2228 trace_xdp_exception(rx_ring->netdev, xdp_prog, act);
2229 /* fall through -- handle aborts by dropping packet */
2230 case XDP_DROP:
2231 result = I40E_XDP_CONSUMED;
2232 break;
2233 }
2234xdp_out:
2235 rcu_read_unlock();
2236 return ERR_PTR(-result);
2237}
2238
2239/**
2240 * i40e_rx_buffer_flip - adjusted rx_buffer to point to an unused region
2241 * @rx_ring: Rx ring
2242 * @rx_buffer: Rx buffer to adjust
2243 * @size: Size of adjustment
2244 **/
2245static void i40e_rx_buffer_flip(struct i40e_ring *rx_ring,
2246 struct i40e_rx_buffer *rx_buffer,
2247 unsigned int size)
2248{
2249#if (PAGE_SIZE < 8192)
2250 unsigned int truesize = i40e_rx_pg_size(rx_ring) / 2;
2251
2252 rx_buffer->page_offset ^= truesize;
2253#else
2254 unsigned int truesize = SKB_DATA_ALIGN(i40e_rx_offset(rx_ring) + size);
2255
2256 rx_buffer->page_offset += truesize;
2257#endif
2258}
2259
2260/**
2261 * i40e_xdp_ring_update_tail - Updates the XDP Tx ring tail register
2262 * @xdp_ring: XDP Tx ring
2263 *
2264 * This function updates the XDP Tx ring tail register.
2265 **/
2266void i40e_xdp_ring_update_tail(struct i40e_ring *xdp_ring)
2267{
2268 /* Force memory writes to complete before letting h/w
2269 * know there are new descriptors to fetch.
2270 */
2271 wmb();
2272 writel_relaxed(xdp_ring->next_to_use, xdp_ring->tail);
2273}
2274
2275/**
2276 * i40e_update_rx_stats - Update Rx ring statistics
2277 * @rx_ring: rx descriptor ring
2278 * @total_rx_bytes: number of bytes received
2279 * @total_rx_packets: number of packets received
2280 *
2281 * This function updates the Rx ring statistics.
2282 **/
2283void i40e_update_rx_stats(struct i40e_ring *rx_ring,
2284 unsigned int total_rx_bytes,
2285 unsigned int total_rx_packets)
2286{
2287 u64_stats_update_begin(&rx_ring->syncp);
2288 rx_ring->stats.packets += total_rx_packets;
2289 rx_ring->stats.bytes += total_rx_bytes;
2290 u64_stats_update_end(&rx_ring->syncp);
2291 rx_ring->q_vector->rx.total_packets += total_rx_packets;
2292 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
2293}
2294
2295/**
2296 * i40e_finalize_xdp_rx - Bump XDP Tx tail and/or flush redirect map
2297 * @rx_ring: Rx ring
2298 * @xdp_res: Result of the receive batch
2299 *
2300 * This function bumps XDP Tx tail and/or flush redirect map, and
2301 * should be called when a batch of packets has been processed in the
2302 * napi loop.
2303 **/
2304void i40e_finalize_xdp_rx(struct i40e_ring *rx_ring, unsigned int xdp_res)
2305{
2306 if (xdp_res & I40E_XDP_REDIR)
2307 xdp_do_flush_map();
2308
2309 if (xdp_res & I40E_XDP_TX) {
2310 struct i40e_ring *xdp_ring =
2311 rx_ring->vsi->xdp_rings[rx_ring->queue_index];
2312
2313 i40e_xdp_ring_update_tail(xdp_ring);
2314 }
2315}
2316
2317/**
2318 * i40e_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2319 * @rx_ring: rx descriptor ring to transact packets on
2320 * @budget: Total limit on number of packets to process
2321 *
2322 * This function provides a "bounce buffer" approach to Rx interrupt
2323 * processing. The advantage to this is that on systems that have
2324 * expensive overhead for IOMMU access this provides a means of avoiding
2325 * it by maintaining the mapping of the page to the system.
2326 *
2327 * Returns amount of work completed
2328 **/
2329static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget)
2330{
2331 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
2332 struct sk_buff *skb = rx_ring->skb;
2333 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
2334 unsigned int xdp_xmit = 0;
2335 bool failure = false;
2336 struct xdp_buff xdp;
2337
2338 xdp.rxq = &rx_ring->xdp_rxq;
2339
2340 while (likely(total_rx_packets < (unsigned int)budget)) {
2341 struct i40e_rx_buffer *rx_buffer;
2342 union i40e_rx_desc *rx_desc;
2343 unsigned int size;
2344 u64 qword;
2345
2346 /* return some buffers to hardware, one at a time is too slow */
2347 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
2348 failure = failure ||
2349 i40e_alloc_rx_buffers(rx_ring, cleaned_count);
2350 cleaned_count = 0;
2351 }
2352
2353 rx_desc = I40E_RX_DESC(rx_ring, rx_ring->next_to_clean);
2354
2355 /* status_error_len will always be zero for unused descriptors
2356 * because it's cleared in cleanup, and overlaps with hdr_addr
2357 * which is always zero because packet split isn't used, if the
2358 * hardware wrote DD then the length will be non-zero
2359 */
2360 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
2361
2362 /* This memory barrier is needed to keep us from reading
2363 * any other fields out of the rx_desc until we have
2364 * verified the descriptor has been written back.
2365 */
2366 dma_rmb();
2367
2368 rx_buffer = i40e_clean_programming_status(rx_ring, rx_desc,
2369 qword);
2370 if (unlikely(rx_buffer)) {
2371 i40e_reuse_rx_page(rx_ring, rx_buffer);
2372 cleaned_count++;
2373 continue;
2374 }
2375
2376 size = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
2377 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
2378 if (!size)
2379 break;
2380
2381 i40e_trace(clean_rx_irq, rx_ring, rx_desc, skb);
2382 rx_buffer = i40e_get_rx_buffer(rx_ring, size);
2383
2384 /* retrieve a buffer from the ring */
2385 if (!skb) {
2386 xdp.data = page_address(rx_buffer->page) +
2387 rx_buffer->page_offset;
2388 xdp.data_meta = xdp.data;
2389 xdp.data_hard_start = xdp.data -
2390 i40e_rx_offset(rx_ring);
2391 xdp.data_end = xdp.data + size;
2392
2393 skb = i40e_run_xdp(rx_ring, &xdp);
2394 }
2395
2396 if (IS_ERR(skb)) {
2397 unsigned int xdp_res = -PTR_ERR(skb);
2398
2399 if (xdp_res & (I40E_XDP_TX | I40E_XDP_REDIR)) {
2400 xdp_xmit |= xdp_res;
2401 i40e_rx_buffer_flip(rx_ring, rx_buffer, size);
2402 } else {
2403 rx_buffer->pagecnt_bias++;
2404 }
2405 total_rx_bytes += size;
2406 total_rx_packets++;
2407 } else if (skb) {
2408 i40e_add_rx_frag(rx_ring, rx_buffer, skb, size);
2409 } else if (ring_uses_build_skb(rx_ring)) {
2410 skb = i40e_build_skb(rx_ring, rx_buffer, &xdp);
2411 } else {
2412 skb = i40e_construct_skb(rx_ring, rx_buffer, &xdp);
2413 }
2414
2415 /* exit if we failed to retrieve a buffer */
2416 if (!skb) {
2417 rx_ring->rx_stats.alloc_buff_failed++;
2418 rx_buffer->pagecnt_bias++;
2419 break;
2420 }
2421
2422 i40e_put_rx_buffer(rx_ring, rx_buffer);
2423 cleaned_count++;
2424
2425 if (i40e_is_non_eop(rx_ring, rx_desc, skb))
2426 continue;
2427
2428 if (i40e_cleanup_headers(rx_ring, skb, rx_desc)) {
2429 skb = NULL;
2430 continue;
2431 }
2432
2433 /* probably a little skewed due to removing CRC */
2434 total_rx_bytes += skb->len;
2435
2436 /* populate checksum, VLAN, and protocol */
2437 i40e_process_skb_fields(rx_ring, rx_desc, skb);
2438
2439 i40e_trace(clean_rx_irq_rx, rx_ring, rx_desc, skb);
2440 napi_gro_receive(&rx_ring->q_vector->napi, skb);
2441 skb = NULL;
2442
2443 /* update budget accounting */
2444 total_rx_packets++;
2445 }
2446
2447 i40e_finalize_xdp_rx(rx_ring, xdp_xmit);
2448 rx_ring->skb = skb;
2449
2450 i40e_update_rx_stats(rx_ring, total_rx_bytes, total_rx_packets);
2451
2452 /* guarantee a trip back through this routine if there was a failure */
2453 return failure ? budget : (int)total_rx_packets;
2454}
2455
2456static inline u32 i40e_buildreg_itr(const int type, u16 itr)
2457{
2458 u32 val;
2459
2460 /* We don't bother with setting the CLEARPBA bit as the data sheet
2461 * points out doing so is "meaningless since it was already
2462 * auto-cleared". The auto-clearing happens when the interrupt is
2463 * asserted.
2464 *
2465 * Hardware errata 28 for also indicates that writing to a
2466 * xxINT_DYN_CTLx CSR with INTENA_MSK (bit 31) set to 0 will clear
2467 * an event in the PBA anyway so we need to rely on the automask
2468 * to hold pending events for us until the interrupt is re-enabled
2469 *
2470 * The itr value is reported in microseconds, and the register
2471 * value is recorded in 2 microsecond units. For this reason we
2472 * only need to shift by the interval shift - 1 instead of the
2473 * full value.
2474 */
2475 itr &= I40E_ITR_MASK;
2476
2477 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
2478 (type << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
2479 (itr << (I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT - 1));
2480
2481 return val;
2482}
2483
2484/* a small macro to shorten up some long lines */
2485#define INTREG I40E_PFINT_DYN_CTLN
2486
2487/* The act of updating the ITR will cause it to immediately trigger. In order
2488 * to prevent this from throwing off adaptive update statistics we defer the
2489 * update so that it can only happen so often. So after either Tx or Rx are
2490 * updated we make the adaptive scheme wait until either the ITR completely
2491 * expires via the next_update expiration or we have been through at least
2492 * 3 interrupts.
2493 */
2494#define ITR_COUNTDOWN_START 3
2495
2496/**
2497 * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
2498 * @vsi: the VSI we care about
2499 * @q_vector: q_vector for which itr is being updated and interrupt enabled
2500 *
2501 **/
2502static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
2503 struct i40e_q_vector *q_vector)
2504{
2505 struct i40e_hw *hw = &vsi->back->hw;
2506 u32 intval;
2507
2508 /* If we don't have MSIX, then we only need to re-enable icr0 */
2509 if (!(vsi->back->flags & I40E_FLAG_MSIX_ENABLED)) {
2510 i40e_irq_dynamic_enable_icr0(vsi->back);
2511 return;
2512 }
2513
2514 /* These will do nothing if dynamic updates are not enabled */
2515 i40e_update_itr(q_vector, &q_vector->tx);
2516 i40e_update_itr(q_vector, &q_vector->rx);
2517
2518 /* This block of logic allows us to get away with only updating
2519 * one ITR value with each interrupt. The idea is to perform a
2520 * pseudo-lazy update with the following criteria.
2521 *
2522 * 1. Rx is given higher priority than Tx if both are in same state
2523 * 2. If we must reduce an ITR that is given highest priority.
2524 * 3. We then give priority to increasing ITR based on amount.
2525 */
2526 if (q_vector->rx.target_itr < q_vector->rx.current_itr) {
2527 /* Rx ITR needs to be reduced, this is highest priority */
2528 intval = i40e_buildreg_itr(I40E_RX_ITR,
2529 q_vector->rx.target_itr);
2530 q_vector->rx.current_itr = q_vector->rx.target_itr;
2531 q_vector->itr_countdown = ITR_COUNTDOWN_START;
2532 } else if ((q_vector->tx.target_itr < q_vector->tx.current_itr) ||
2533 ((q_vector->rx.target_itr - q_vector->rx.current_itr) <
2534 (q_vector->tx.target_itr - q_vector->tx.current_itr))) {
2535 /* Tx ITR needs to be reduced, this is second priority
2536 * Tx ITR needs to be increased more than Rx, fourth priority
2537 */
2538 intval = i40e_buildreg_itr(I40E_TX_ITR,
2539 q_vector->tx.target_itr);
2540 q_vector->tx.current_itr = q_vector->tx.target_itr;
2541 q_vector->itr_countdown = ITR_COUNTDOWN_START;
2542 } else if (q_vector->rx.current_itr != q_vector->rx.target_itr) {
2543 /* Rx ITR needs to be increased, third priority */
2544 intval = i40e_buildreg_itr(I40E_RX_ITR,
2545 q_vector->rx.target_itr);
2546 q_vector->rx.current_itr = q_vector->rx.target_itr;
2547 q_vector->itr_countdown = ITR_COUNTDOWN_START;
2548 } else {
2549 /* No ITR update, lowest priority */
2550 intval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
2551 if (q_vector->itr_countdown)
2552 q_vector->itr_countdown--;
2553 }
2554
2555 if (!test_bit(__I40E_VSI_DOWN, vsi->state))
2556 wr32(hw, INTREG(q_vector->reg_idx), intval);
2557}
2558
2559/**
2560 * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine
2561 * @napi: napi struct with our devices info in it
2562 * @budget: amount of work driver is allowed to do this pass, in packets
2563 *
2564 * This function will clean all queues associated with a q_vector.
2565 *
2566 * Returns the amount of work done
2567 **/
2568int i40e_napi_poll(struct napi_struct *napi, int budget)
2569{
2570 struct i40e_q_vector *q_vector =
2571 container_of(napi, struct i40e_q_vector, napi);
2572 struct i40e_vsi *vsi = q_vector->vsi;
2573 struct i40e_ring *ring;
2574 bool clean_complete = true;
2575 bool arm_wb = false;
2576 int budget_per_ring;
2577 int work_done = 0;
2578
2579 if (test_bit(__I40E_VSI_DOWN, vsi->state)) {
2580 napi_complete(napi);
2581 return 0;
2582 }
2583
2584 /* Since the actual Tx work is minimal, we can give the Tx a larger
2585 * budget and be more aggressive about cleaning up the Tx descriptors.
2586 */
2587 i40e_for_each_ring(ring, q_vector->tx) {
2588 bool wd = ring->xsk_umem ?
2589 i40e_clean_xdp_tx_irq(vsi, ring, budget) :
2590 i40e_clean_tx_irq(vsi, ring, budget);
2591
2592 if (!wd) {
2593 clean_complete = false;
2594 continue;
2595 }
2596 arm_wb |= ring->arm_wb;
2597 ring->arm_wb = false;
2598 }
2599
2600 /* Handle case where we are called by netpoll with a budget of 0 */
2601 if (budget <= 0)
2602 goto tx_only;
2603
2604 /* We attempt to distribute budget to each Rx queue fairly, but don't
2605 * allow the budget to go below 1 because that would exit polling early.
2606 */
2607 budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
2608
2609 i40e_for_each_ring(ring, q_vector->rx) {
2610 int cleaned = ring->xsk_umem ?
2611 i40e_clean_rx_irq_zc(ring, budget_per_ring) :
2612 i40e_clean_rx_irq(ring, budget_per_ring);
2613
2614 work_done += cleaned;
2615 /* if we clean as many as budgeted, we must not be done */
2616 if (cleaned >= budget_per_ring)
2617 clean_complete = false;
2618 }
2619
2620 /* If work not completed, return budget and polling will return */
2621 if (!clean_complete) {
2622 int cpu_id = smp_processor_id();
2623
2624 /* It is possible that the interrupt affinity has changed but,
2625 * if the cpu is pegged at 100%, polling will never exit while
2626 * traffic continues and the interrupt will be stuck on this
2627 * cpu. We check to make sure affinity is correct before we
2628 * continue to poll, otherwise we must stop polling so the
2629 * interrupt can move to the correct cpu.
2630 */
2631 if (!cpumask_test_cpu(cpu_id, &q_vector->affinity_mask)) {
2632 /* Tell napi that we are done polling */
2633 napi_complete_done(napi, work_done);
2634
2635 /* Force an interrupt */
2636 i40e_force_wb(vsi, q_vector);
2637
2638 /* Return budget-1 so that polling stops */
2639 return budget - 1;
2640 }
2641tx_only:
2642 if (arm_wb) {
2643 q_vector->tx.ring[0].tx_stats.tx_force_wb++;
2644 i40e_enable_wb_on_itr(vsi, q_vector);
2645 }
2646 return budget;
2647 }
2648
2649 if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
2650 q_vector->arm_wb_state = false;
2651
2652 /* Exit the polling mode, but don't re-enable interrupts if stack might
2653 * poll us due to busy-polling
2654 */
2655 if (likely(napi_complete_done(napi, work_done)))
2656 i40e_update_enable_itr(vsi, q_vector);
2657
2658 return min(work_done, budget - 1);
2659}
2660
2661/**
2662 * i40e_atr - Add a Flow Director ATR filter
2663 * @tx_ring: ring to add programming descriptor to
2664 * @skb: send buffer
2665 * @tx_flags: send tx flags
2666 **/
2667static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb,
2668 u32 tx_flags)
2669{
2670 struct i40e_filter_program_desc *fdir_desc;
2671 struct i40e_pf *pf = tx_ring->vsi->back;
2672 union {
2673 unsigned char *network;
2674 struct iphdr *ipv4;
2675 struct ipv6hdr *ipv6;
2676 } hdr;
2677 struct tcphdr *th;
2678 unsigned int hlen;
2679 u32 flex_ptype, dtype_cmd;
2680 int l4_proto;
2681 u16 i;
2682
2683 /* make sure ATR is enabled */
2684 if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED))
2685 return;
2686
2687 if (test_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state))
2688 return;
2689
2690 /* if sampling is disabled do nothing */
2691 if (!tx_ring->atr_sample_rate)
2692 return;
2693
2694 /* Currently only IPv4/IPv6 with TCP is supported */
2695 if (!(tx_flags & (I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6)))
2696 return;
2697
2698 /* snag network header to get L4 type and address */
2699 hdr.network = (tx_flags & I40E_TX_FLAGS_UDP_TUNNEL) ?
2700 skb_inner_network_header(skb) : skb_network_header(skb);
2701
2702 /* Note: tx_flags gets modified to reflect inner protocols in
2703 * tx_enable_csum function if encap is enabled.
2704 */
2705 if (tx_flags & I40E_TX_FLAGS_IPV4) {
2706 /* access ihl as u8 to avoid unaligned access on ia64 */
2707 hlen = (hdr.network[0] & 0x0F) << 2;
2708 l4_proto = hdr.ipv4->protocol;
2709 } else {
2710 /* find the start of the innermost ipv6 header */
2711 unsigned int inner_hlen = hdr.network - skb->data;
2712 unsigned int h_offset = inner_hlen;
2713
2714 /* this function updates h_offset to the end of the header */
2715 l4_proto =
2716 ipv6_find_hdr(skb, &h_offset, IPPROTO_TCP, NULL, NULL);
2717 /* hlen will contain our best estimate of the tcp header */
2718 hlen = h_offset - inner_hlen;
2719 }
2720
2721 if (l4_proto != IPPROTO_TCP)
2722 return;
2723
2724 th = (struct tcphdr *)(hdr.network + hlen);
2725
2726 /* Due to lack of space, no more new filters can be programmed */
2727 if (th->syn && test_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state))
2728 return;
2729 if (pf->flags & I40E_FLAG_HW_ATR_EVICT_ENABLED) {
2730 /* HW ATR eviction will take care of removing filters on FIN
2731 * and RST packets.
2732 */
2733 if (th->fin || th->rst)
2734 return;
2735 }
2736
2737 tx_ring->atr_count++;
2738
2739 /* sample on all syn/fin/rst packets or once every atr sample rate */
2740 if (!th->fin &&
2741 !th->syn &&
2742 !th->rst &&
2743 (tx_ring->atr_count < tx_ring->atr_sample_rate))
2744 return;
2745
2746 tx_ring->atr_count = 0;
2747
2748 /* grab the next descriptor */
2749 i = tx_ring->next_to_use;
2750 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
2751
2752 i++;
2753 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
2754
2755 flex_ptype = (tx_ring->queue_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
2756 I40E_TXD_FLTR_QW0_QINDEX_MASK;
2757 flex_ptype |= (tx_flags & I40E_TX_FLAGS_IPV4) ?
2758 (I40E_FILTER_PCTYPE_NONF_IPV4_TCP <<
2759 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) :
2760 (I40E_FILTER_PCTYPE_NONF_IPV6_TCP <<
2761 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT);
2762
2763 flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT;
2764
2765 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG;
2766
2767 dtype_cmd |= (th->fin || th->rst) ?
2768 (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
2769 I40E_TXD_FLTR_QW1_PCMD_SHIFT) :
2770 (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
2771 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
2772
2773 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX <<
2774 I40E_TXD_FLTR_QW1_DEST_SHIFT;
2775
2776 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID <<
2777 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT;
2778
2779 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
2780 if (!(tx_flags & I40E_TX_FLAGS_UDP_TUNNEL))
2781 dtype_cmd |=
2782 ((u32)I40E_FD_ATR_STAT_IDX(pf->hw.pf_id) <<
2783 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2784 I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
2785 else
2786 dtype_cmd |=
2787 ((u32)I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id) <<
2788 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2789 I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
2790
2791 if (pf->flags & I40E_FLAG_HW_ATR_EVICT_ENABLED)
2792 dtype_cmd |= I40E_TXD_FLTR_QW1_ATR_MASK;
2793
2794 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);
2795 fdir_desc->rsvd = cpu_to_le32(0);
2796 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd);
2797 fdir_desc->fd_id = cpu_to_le32(0);
2798}
2799
2800/**
2801 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
2802 * @skb: send buffer
2803 * @tx_ring: ring to send buffer on
2804 * @flags: the tx flags to be set
2805 *
2806 * Checks the skb and set up correspondingly several generic transmit flags
2807 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
2808 *
2809 * Returns error code indicate the frame should be dropped upon error and the
2810 * otherwise returns 0 to indicate the flags has been set properly.
2811 **/
2812static inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
2813 struct i40e_ring *tx_ring,
2814 u32 *flags)
2815{
2816 __be16 protocol = skb->protocol;
2817 u32 tx_flags = 0;
2818
2819 if (protocol == htons(ETH_P_8021Q) &&
2820 !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
2821 /* When HW VLAN acceleration is turned off by the user the
2822 * stack sets the protocol to 8021q so that the driver
2823 * can take any steps required to support the SW only
2824 * VLAN handling. In our case the driver doesn't need
2825 * to take any further steps so just set the protocol
2826 * to the encapsulated ethertype.
2827 */
2828 skb->protocol = vlan_get_protocol(skb);
2829 goto out;
2830 }
2831
2832 /* if we have a HW VLAN tag being added, default to the HW one */
2833 if (skb_vlan_tag_present(skb)) {
2834 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
2835 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
2836 /* else if it is a SW VLAN, check the next protocol and store the tag */
2837 } else if (protocol == htons(ETH_P_8021Q)) {
2838 struct vlan_hdr *vhdr, _vhdr;
2839
2840 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
2841 if (!vhdr)
2842 return -EINVAL;
2843
2844 protocol = vhdr->h_vlan_encapsulated_proto;
2845 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
2846 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
2847 }
2848
2849 if (!(tx_ring->vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2850 goto out;
2851
2852 /* Insert 802.1p priority into VLAN header */
2853 if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) ||
2854 (skb->priority != TC_PRIO_CONTROL)) {
2855 tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK;
2856 tx_flags |= (skb->priority & 0x7) <<
2857 I40E_TX_FLAGS_VLAN_PRIO_SHIFT;
2858 if (tx_flags & I40E_TX_FLAGS_SW_VLAN) {
2859 struct vlan_ethhdr *vhdr;
2860 int rc;
2861
2862 rc = skb_cow_head(skb, 0);
2863 if (rc < 0)
2864 return rc;
2865 vhdr = (struct vlan_ethhdr *)skb->data;
2866 vhdr->h_vlan_TCI = htons(tx_flags >>
2867 I40E_TX_FLAGS_VLAN_SHIFT);
2868 } else {
2869 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
2870 }
2871 }
2872
2873out:
2874 *flags = tx_flags;
2875 return 0;
2876}
2877
2878/**
2879 * i40e_tso - set up the tso context descriptor
2880 * @first: pointer to first Tx buffer for xmit
2881 * @hdr_len: ptr to the size of the packet header
2882 * @cd_type_cmd_tso_mss: Quad Word 1
2883 *
2884 * Returns 0 if no TSO can happen, 1 if tso is going, or error
2885 **/
2886static int i40e_tso(struct i40e_tx_buffer *first, u8 *hdr_len,
2887 u64 *cd_type_cmd_tso_mss)
2888{
2889 struct sk_buff *skb = first->skb;
2890 u64 cd_cmd, cd_tso_len, cd_mss;
2891 union {
2892 struct iphdr *v4;
2893 struct ipv6hdr *v6;
2894 unsigned char *hdr;
2895 } ip;
2896 union {
2897 struct tcphdr *tcp;
2898 struct udphdr *udp;
2899 unsigned char *hdr;
2900 } l4;
2901 u32 paylen, l4_offset;
2902 u16 gso_segs, gso_size;
2903 int err;
2904
2905 if (skb->ip_summed != CHECKSUM_PARTIAL)
2906 return 0;
2907
2908 if (!skb_is_gso(skb))
2909 return 0;
2910
2911 err = skb_cow_head(skb, 0);
2912 if (err < 0)
2913 return err;
2914
2915 ip.hdr = skb_network_header(skb);
2916 l4.hdr = skb_transport_header(skb);
2917
2918 /* initialize outer IP header fields */
2919 if (ip.v4->version == 4) {
2920 ip.v4->tot_len = 0;
2921 ip.v4->check = 0;
2922 } else {
2923 ip.v6->payload_len = 0;
2924 }
2925
2926 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
2927 SKB_GSO_GRE_CSUM |
2928 SKB_GSO_IPXIP4 |
2929 SKB_GSO_IPXIP6 |
2930 SKB_GSO_UDP_TUNNEL |
2931 SKB_GSO_UDP_TUNNEL_CSUM)) {
2932 if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
2933 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) {
2934 l4.udp->len = 0;
2935
2936 /* determine offset of outer transport header */
2937 l4_offset = l4.hdr - skb->data;
2938
2939 /* remove payload length from outer checksum */
2940 paylen = skb->len - l4_offset;
2941 csum_replace_by_diff(&l4.udp->check,
2942 (__force __wsum)htonl(paylen));
2943 }
2944
2945 /* reset pointers to inner headers */
2946 ip.hdr = skb_inner_network_header(skb);
2947 l4.hdr = skb_inner_transport_header(skb);
2948
2949 /* initialize inner IP header fields */
2950 if (ip.v4->version == 4) {
2951 ip.v4->tot_len = 0;
2952 ip.v4->check = 0;
2953 } else {
2954 ip.v6->payload_len = 0;
2955 }
2956 }
2957
2958 /* determine offset of inner transport header */
2959 l4_offset = l4.hdr - skb->data;
2960
2961 /* remove payload length from inner checksum */
2962 paylen = skb->len - l4_offset;
2963 csum_replace_by_diff(&l4.tcp->check, (__force __wsum)htonl(paylen));
2964
2965 /* compute length of segmentation header */
2966 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
2967
2968 /* pull values out of skb_shinfo */
2969 gso_size = skb_shinfo(skb)->gso_size;
2970 gso_segs = skb_shinfo(skb)->gso_segs;
2971
2972 /* update GSO size and bytecount with header size */
2973 first->gso_segs = gso_segs;
2974 first->bytecount += (first->gso_segs - 1) * *hdr_len;
2975
2976 /* find the field values */
2977 cd_cmd = I40E_TX_CTX_DESC_TSO;
2978 cd_tso_len = skb->len - *hdr_len;
2979 cd_mss = gso_size;
2980 *cd_type_cmd_tso_mss |= (cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
2981 (cd_tso_len << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
2982 (cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
2983 return 1;
2984}
2985
2986/**
2987 * i40e_tsyn - set up the tsyn context descriptor
2988 * @tx_ring: ptr to the ring to send
2989 * @skb: ptr to the skb we're sending
2990 * @tx_flags: the collected send information
2991 * @cd_type_cmd_tso_mss: Quad Word 1
2992 *
2993 * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen
2994 **/
2995static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb,
2996 u32 tx_flags, u64 *cd_type_cmd_tso_mss)
2997{
2998 struct i40e_pf *pf;
2999
3000 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)))
3001 return 0;
3002
3003 /* Tx timestamps cannot be sampled when doing TSO */
3004 if (tx_flags & I40E_TX_FLAGS_TSO)
3005 return 0;
3006
3007 /* only timestamp the outbound packet if the user has requested it and
3008 * we are not already transmitting a packet to be timestamped
3009 */
3010 pf = i40e_netdev_to_pf(tx_ring->netdev);
3011 if (!(pf->flags & I40E_FLAG_PTP))
3012 return 0;
3013
3014 if (pf->ptp_tx &&
3015 !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, pf->state)) {
3016 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
3017 pf->ptp_tx_start = jiffies;
3018 pf->ptp_tx_skb = skb_get(skb);
3019 } else {
3020 pf->tx_hwtstamp_skipped++;
3021 return 0;
3022 }
3023
3024 *cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN <<
3025 I40E_TXD_CTX_QW1_CMD_SHIFT;
3026
3027 return 1;
3028}
3029
3030/**
3031 * i40e_tx_enable_csum - Enable Tx checksum offloads
3032 * @skb: send buffer
3033 * @tx_flags: pointer to Tx flags currently set
3034 * @td_cmd: Tx descriptor command bits to set
3035 * @td_offset: Tx descriptor header offsets to set
3036 * @tx_ring: Tx descriptor ring
3037 * @cd_tunneling: ptr to context desc bits
3038 **/
3039static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
3040 u32 *td_cmd, u32 *td_offset,
3041 struct i40e_ring *tx_ring,
3042 u32 *cd_tunneling)
3043{
3044 union {
3045 struct iphdr *v4;
3046 struct ipv6hdr *v6;
3047 unsigned char *hdr;
3048 } ip;
3049 union {
3050 struct tcphdr *tcp;
3051 struct udphdr *udp;
3052 unsigned char *hdr;
3053 } l4;
3054 unsigned char *exthdr;
3055 u32 offset, cmd = 0;
3056 __be16 frag_off;
3057 u8 l4_proto = 0;
3058
3059 if (skb->ip_summed != CHECKSUM_PARTIAL)
3060 return 0;
3061
3062 ip.hdr = skb_network_header(skb);
3063 l4.hdr = skb_transport_header(skb);
3064
3065 /* compute outer L2 header size */
3066 offset = ((ip.hdr - skb->data) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
3067
3068 if (skb->encapsulation) {
3069 u32 tunnel = 0;
3070 /* define outer network header type */
3071 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
3072 tunnel |= (*tx_flags & I40E_TX_FLAGS_TSO) ?
3073 I40E_TX_CTX_EXT_IP_IPV4 :
3074 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
3075
3076 l4_proto = ip.v4->protocol;
3077 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
3078 tunnel |= I40E_TX_CTX_EXT_IP_IPV6;
3079
3080 exthdr = ip.hdr + sizeof(*ip.v6);
3081 l4_proto = ip.v6->nexthdr;
3082 if (l4.hdr != exthdr)
3083 ipv6_skip_exthdr(skb, exthdr - skb->data,
3084 &l4_proto, &frag_off);
3085 }
3086
3087 /* define outer transport */
3088 switch (l4_proto) {
3089 case IPPROTO_UDP:
3090 tunnel |= I40E_TXD_CTX_UDP_TUNNELING;
3091 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
3092 break;
3093 case IPPROTO_GRE:
3094 tunnel |= I40E_TXD_CTX_GRE_TUNNELING;
3095 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
3096 break;
3097 case IPPROTO_IPIP:
3098 case IPPROTO_IPV6:
3099 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
3100 l4.hdr = skb_inner_network_header(skb);
3101 break;
3102 default:
3103 if (*tx_flags & I40E_TX_FLAGS_TSO)
3104 return -1;
3105
3106 skb_checksum_help(skb);
3107 return 0;
3108 }
3109
3110 /* compute outer L3 header size */
3111 tunnel |= ((l4.hdr - ip.hdr) / 4) <<
3112 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
3113
3114 /* switch IP header pointer from outer to inner header */
3115 ip.hdr = skb_inner_network_header(skb);
3116
3117 /* compute tunnel header size */
3118 tunnel |= ((ip.hdr - l4.hdr) / 2) <<
3119 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
3120
3121 /* indicate if we need to offload outer UDP header */
3122 if ((*tx_flags & I40E_TX_FLAGS_TSO) &&
3123 !(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
3124 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM))
3125 tunnel |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
3126
3127 /* record tunnel offload values */
3128 *cd_tunneling |= tunnel;
3129
3130 /* switch L4 header pointer from outer to inner */
3131 l4.hdr = skb_inner_transport_header(skb);
3132 l4_proto = 0;
3133
3134 /* reset type as we transition from outer to inner headers */
3135 *tx_flags &= ~(I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6);
3136 if (ip.v4->version == 4)
3137 *tx_flags |= I40E_TX_FLAGS_IPV4;
3138 if (ip.v6->version == 6)
3139 *tx_flags |= I40E_TX_FLAGS_IPV6;
3140 }
3141
3142 /* Enable IP checksum offloads */
3143 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
3144 l4_proto = ip.v4->protocol;
3145 /* the stack computes the IP header already, the only time we
3146 * need the hardware to recompute it is in the case of TSO.
3147 */
3148 cmd |= (*tx_flags & I40E_TX_FLAGS_TSO) ?
3149 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM :
3150 I40E_TX_DESC_CMD_IIPT_IPV4;
3151 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
3152 cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
3153
3154 exthdr = ip.hdr + sizeof(*ip.v6);
3155 l4_proto = ip.v6->nexthdr;
3156 if (l4.hdr != exthdr)
3157 ipv6_skip_exthdr(skb, exthdr - skb->data,
3158 &l4_proto, &frag_off);
3159 }
3160
3161 /* compute inner L3 header size */
3162 offset |= ((l4.hdr - ip.hdr) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
3163
3164 /* Enable L4 checksum offloads */
3165 switch (l4_proto) {
3166 case IPPROTO_TCP:
3167 /* enable checksum offloads */
3168 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
3169 offset |= l4.tcp->doff << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
3170 break;
3171 case IPPROTO_SCTP:
3172 /* enable SCTP checksum offload */
3173 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
3174 offset |= (sizeof(struct sctphdr) >> 2) <<
3175 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
3176 break;
3177 case IPPROTO_UDP:
3178 /* enable UDP checksum offload */
3179 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
3180 offset |= (sizeof(struct udphdr) >> 2) <<
3181 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
3182 break;
3183 default:
3184 if (*tx_flags & I40E_TX_FLAGS_TSO)
3185 return -1;
3186 skb_checksum_help(skb);
3187 return 0;
3188 }
3189
3190 *td_cmd |= cmd;
3191 *td_offset |= offset;
3192
3193 return 1;
3194}
3195
3196/**
3197 * i40e_create_tx_ctx Build the Tx context descriptor
3198 * @tx_ring: ring to create the descriptor on
3199 * @cd_type_cmd_tso_mss: Quad Word 1
3200 * @cd_tunneling: Quad Word 0 - bits 0-31
3201 * @cd_l2tag2: Quad Word 0 - bits 32-63
3202 **/
3203static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
3204 const u64 cd_type_cmd_tso_mss,
3205 const u32 cd_tunneling, const u32 cd_l2tag2)
3206{
3207 struct i40e_tx_context_desc *context_desc;
3208 int i = tx_ring->next_to_use;
3209
3210 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
3211 !cd_tunneling && !cd_l2tag2)
3212 return;
3213
3214 /* grab the next descriptor */
3215 context_desc = I40E_TX_CTXTDESC(tx_ring, i);
3216
3217 i++;
3218 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
3219
3220 /* cpu_to_le32 and assign to struct fields */
3221 context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
3222 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
3223 context_desc->rsvd = cpu_to_le16(0);
3224 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
3225}
3226
3227/**
3228 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
3229 * @tx_ring: the ring to be checked
3230 * @size: the size buffer we want to assure is available
3231 *
3232 * Returns -EBUSY if a stop is needed, else 0
3233 **/
3234int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
3235{
3236 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
3237 /* Memory barrier before checking head and tail */
3238 smp_mb();
3239
3240 /* Check again in a case another CPU has just made room available. */
3241 if (likely(I40E_DESC_UNUSED(tx_ring) < size))
3242 return -EBUSY;
3243
3244 /* A reprieve! - use start_queue because it doesn't call schedule */
3245 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
3246 ++tx_ring->tx_stats.restart_queue;
3247 return 0;
3248}
3249
3250/**
3251 * __i40e_chk_linearize - Check if there are more than 8 buffers per packet
3252 * @skb: send buffer
3253 *
3254 * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire
3255 * and so we need to figure out the cases where we need to linearize the skb.
3256 *
3257 * For TSO we need to count the TSO header and segment payload separately.
3258 * As such we need to check cases where we have 7 fragments or more as we
3259 * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for
3260 * the segment payload in the first descriptor, and another 7 for the
3261 * fragments.
3262 **/
3263bool __i40e_chk_linearize(struct sk_buff *skb)
3264{
3265 const skb_frag_t *frag, *stale;
3266 int nr_frags, sum;
3267
3268 /* no need to check if number of frags is less than 7 */
3269 nr_frags = skb_shinfo(skb)->nr_frags;
3270 if (nr_frags < (I40E_MAX_BUFFER_TXD - 1))
3271 return false;
3272
3273 /* We need to walk through the list and validate that each group
3274 * of 6 fragments totals at least gso_size.
3275 */
3276 nr_frags -= I40E_MAX_BUFFER_TXD - 2;
3277 frag = &skb_shinfo(skb)->frags[0];
3278
3279 /* Initialize size to the negative value of gso_size minus 1. We
3280 * use this as the worst case scenerio in which the frag ahead
3281 * of us only provides one byte which is why we are limited to 6
3282 * descriptors for a single transmit as the header and previous
3283 * fragment are already consuming 2 descriptors.
3284 */
3285 sum = 1 - skb_shinfo(skb)->gso_size;
3286
3287 /* Add size of frags 0 through 4 to create our initial sum */
3288 sum += skb_frag_size(frag++);
3289 sum += skb_frag_size(frag++);
3290 sum += skb_frag_size(frag++);
3291 sum += skb_frag_size(frag++);
3292 sum += skb_frag_size(frag++);
3293
3294 /* Walk through fragments adding latest fragment, testing it, and
3295 * then removing stale fragments from the sum.
3296 */
3297 for (stale = &skb_shinfo(skb)->frags[0];; stale++) {
3298 int stale_size = skb_frag_size(stale);
3299
3300 sum += skb_frag_size(frag++);
3301
3302 /* The stale fragment may present us with a smaller
3303 * descriptor than the actual fragment size. To account
3304 * for that we need to remove all the data on the front and
3305 * figure out what the remainder would be in the last
3306 * descriptor associated with the fragment.
3307 */
3308 if (stale_size > I40E_MAX_DATA_PER_TXD) {
3309 int align_pad = -(skb_frag_off(stale)) &
3310 (I40E_MAX_READ_REQ_SIZE - 1);
3311
3312 sum -= align_pad;
3313 stale_size -= align_pad;
3314
3315 do {
3316 sum -= I40E_MAX_DATA_PER_TXD_ALIGNED;
3317 stale_size -= I40E_MAX_DATA_PER_TXD_ALIGNED;
3318 } while (stale_size > I40E_MAX_DATA_PER_TXD);
3319 }
3320
3321 /* if sum is negative we failed to make sufficient progress */
3322 if (sum < 0)
3323 return true;
3324
3325 if (!nr_frags--)
3326 break;
3327
3328 sum -= stale_size;
3329 }
3330
3331 return false;
3332}
3333
3334/**
3335 * i40e_tx_map - Build the Tx descriptor
3336 * @tx_ring: ring to send buffer on
3337 * @skb: send buffer
3338 * @first: first buffer info buffer to use
3339 * @tx_flags: collected send information
3340 * @hdr_len: size of the packet header
3341 * @td_cmd: the command field in the descriptor
3342 * @td_offset: offset for checksum or crc
3343 *
3344 * Returns 0 on success, -1 on failure to DMA
3345 **/
3346static inline int i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
3347 struct i40e_tx_buffer *first, u32 tx_flags,
3348 const u8 hdr_len, u32 td_cmd, u32 td_offset)
3349{
3350 unsigned int data_len = skb->data_len;
3351 unsigned int size = skb_headlen(skb);
3352 skb_frag_t *frag;
3353 struct i40e_tx_buffer *tx_bi;
3354 struct i40e_tx_desc *tx_desc;
3355 u16 i = tx_ring->next_to_use;
3356 u32 td_tag = 0;
3357 dma_addr_t dma;
3358 u16 desc_count = 1;
3359
3360 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
3361 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
3362 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
3363 I40E_TX_FLAGS_VLAN_SHIFT;
3364 }
3365
3366 first->tx_flags = tx_flags;
3367
3368 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
3369
3370 tx_desc = I40E_TX_DESC(tx_ring, i);
3371 tx_bi = first;
3372
3373 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
3374 unsigned int max_data = I40E_MAX_DATA_PER_TXD_ALIGNED;
3375
3376 if (dma_mapping_error(tx_ring->dev, dma))
3377 goto dma_error;
3378
3379 /* record length, and DMA address */
3380 dma_unmap_len_set(tx_bi, len, size);
3381 dma_unmap_addr_set(tx_bi, dma, dma);
3382
3383 /* align size to end of page */
3384 max_data += -dma & (I40E_MAX_READ_REQ_SIZE - 1);
3385 tx_desc->buffer_addr = cpu_to_le64(dma);
3386
3387 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
3388 tx_desc->cmd_type_offset_bsz =
3389 build_ctob(td_cmd, td_offset,
3390 max_data, td_tag);
3391
3392 tx_desc++;
3393 i++;
3394 desc_count++;
3395
3396 if (i == tx_ring->count) {
3397 tx_desc = I40E_TX_DESC(tx_ring, 0);
3398 i = 0;
3399 }
3400
3401 dma += max_data;
3402 size -= max_data;
3403
3404 max_data = I40E_MAX_DATA_PER_TXD_ALIGNED;
3405 tx_desc->buffer_addr = cpu_to_le64(dma);
3406 }
3407
3408 if (likely(!data_len))
3409 break;
3410
3411 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
3412 size, td_tag);
3413
3414 tx_desc++;
3415 i++;
3416 desc_count++;
3417
3418 if (i == tx_ring->count) {
3419 tx_desc = I40E_TX_DESC(tx_ring, 0);
3420 i = 0;
3421 }
3422
3423 size = skb_frag_size(frag);
3424 data_len -= size;
3425
3426 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
3427 DMA_TO_DEVICE);
3428
3429 tx_bi = &tx_ring->tx_bi[i];
3430 }
3431
3432 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
3433
3434 i++;
3435 if (i == tx_ring->count)
3436 i = 0;
3437
3438 tx_ring->next_to_use = i;
3439
3440 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
3441
3442 /* write last descriptor with EOP bit */
3443 td_cmd |= I40E_TX_DESC_CMD_EOP;
3444
3445 /* We OR these values together to check both against 4 (WB_STRIDE)
3446 * below. This is safe since we don't re-use desc_count afterwards.
3447 */
3448 desc_count |= ++tx_ring->packet_stride;
3449
3450 if (desc_count >= WB_STRIDE) {
3451 /* write last descriptor with RS bit set */
3452 td_cmd |= I40E_TX_DESC_CMD_RS;
3453 tx_ring->packet_stride = 0;
3454 }
3455
3456 tx_desc->cmd_type_offset_bsz =
3457 build_ctob(td_cmd, td_offset, size, td_tag);
3458
3459 skb_tx_timestamp(skb);
3460
3461 /* Force memory writes to complete before letting h/w know there
3462 * are new descriptors to fetch.
3463 *
3464 * We also use this memory barrier to make certain all of the
3465 * status bits have been updated before next_to_watch is written.
3466 */
3467 wmb();
3468
3469 /* set next_to_watch value indicating a packet is present */
3470 first->next_to_watch = tx_desc;
3471
3472 /* notify HW of packet */
3473 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) {
3474 writel(i, tx_ring->tail);
3475 }
3476
3477 return 0;
3478
3479dma_error:
3480 dev_info(tx_ring->dev, "TX DMA map failed\n");
3481
3482 /* clear dma mappings for failed tx_bi map */
3483 for (;;) {
3484 tx_bi = &tx_ring->tx_bi[i];
3485 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
3486 if (tx_bi == first)
3487 break;
3488 if (i == 0)
3489 i = tx_ring->count;
3490 i--;
3491 }
3492
3493 tx_ring->next_to_use = i;
3494
3495 return -1;
3496}
3497
3498/**
3499 * i40e_xmit_xdp_ring - transmits an XDP buffer to an XDP Tx ring
3500 * @xdp: data to transmit
3501 * @xdp_ring: XDP Tx ring
3502 **/
3503static int i40e_xmit_xdp_ring(struct xdp_frame *xdpf,
3504 struct i40e_ring *xdp_ring)
3505{
3506 u16 i = xdp_ring->next_to_use;
3507 struct i40e_tx_buffer *tx_bi;
3508 struct i40e_tx_desc *tx_desc;
3509 void *data = xdpf->data;
3510 u32 size = xdpf->len;
3511 dma_addr_t dma;
3512
3513 if (!unlikely(I40E_DESC_UNUSED(xdp_ring))) {
3514 xdp_ring->tx_stats.tx_busy++;
3515 return I40E_XDP_CONSUMED;
3516 }
3517 dma = dma_map_single(xdp_ring->dev, data, size, DMA_TO_DEVICE);
3518 if (dma_mapping_error(xdp_ring->dev, dma))
3519 return I40E_XDP_CONSUMED;
3520
3521 tx_bi = &xdp_ring->tx_bi[i];
3522 tx_bi->bytecount = size;
3523 tx_bi->gso_segs = 1;
3524 tx_bi->xdpf = xdpf;
3525
3526 /* record length, and DMA address */
3527 dma_unmap_len_set(tx_bi, len, size);
3528 dma_unmap_addr_set(tx_bi, dma, dma);
3529
3530 tx_desc = I40E_TX_DESC(xdp_ring, i);
3531 tx_desc->buffer_addr = cpu_to_le64(dma);
3532 tx_desc->cmd_type_offset_bsz = build_ctob(I40E_TX_DESC_CMD_ICRC
3533 | I40E_TXD_CMD,
3534 0, size, 0);
3535
3536 /* Make certain all of the status bits have been updated
3537 * before next_to_watch is written.
3538 */
3539 smp_wmb();
3540
3541 i++;
3542 if (i == xdp_ring->count)
3543 i = 0;
3544
3545 tx_bi->next_to_watch = tx_desc;
3546 xdp_ring->next_to_use = i;
3547
3548 return I40E_XDP_TX;
3549}
3550
3551/**
3552 * i40e_xmit_frame_ring - Sends buffer on Tx ring
3553 * @skb: send buffer
3554 * @tx_ring: ring to send buffer on
3555 *
3556 * Returns NETDEV_TX_OK if sent, else an error code
3557 **/
3558static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
3559 struct i40e_ring *tx_ring)
3560{
3561 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
3562 u32 cd_tunneling = 0, cd_l2tag2 = 0;
3563 struct i40e_tx_buffer *first;
3564 u32 td_offset = 0;
3565 u32 tx_flags = 0;
3566 __be16 protocol;
3567 u32 td_cmd = 0;
3568 u8 hdr_len = 0;
3569 int tso, count;
3570 int tsyn;
3571
3572 /* prefetch the data, we'll need it later */
3573 prefetch(skb->data);
3574
3575 i40e_trace(xmit_frame_ring, skb, tx_ring);
3576
3577 count = i40e_xmit_descriptor_count(skb);
3578 if (i40e_chk_linearize(skb, count)) {
3579 if (__skb_linearize(skb)) {
3580 dev_kfree_skb_any(skb);
3581 return NETDEV_TX_OK;
3582 }
3583 count = i40e_txd_use_count(skb->len);
3584 tx_ring->tx_stats.tx_linearize++;
3585 }
3586
3587 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
3588 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
3589 * + 4 desc gap to avoid the cache line where head is,
3590 * + 1 desc for context descriptor,
3591 * otherwise try next time
3592 */
3593 if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) {
3594 tx_ring->tx_stats.tx_busy++;
3595 return NETDEV_TX_BUSY;
3596 }
3597
3598 /* record the location of the first descriptor for this packet */
3599 first = &tx_ring->tx_bi[tx_ring->next_to_use];
3600 first->skb = skb;
3601 first->bytecount = skb->len;
3602 first->gso_segs = 1;
3603
3604 /* prepare the xmit flags */
3605 if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
3606 goto out_drop;
3607
3608 /* obtain protocol of skb */
3609 protocol = vlan_get_protocol(skb);
3610
3611 /* setup IPv4/IPv6 offloads */
3612 if (protocol == htons(ETH_P_IP))
3613 tx_flags |= I40E_TX_FLAGS_IPV4;
3614 else if (protocol == htons(ETH_P_IPV6))
3615 tx_flags |= I40E_TX_FLAGS_IPV6;
3616
3617 tso = i40e_tso(first, &hdr_len, &cd_type_cmd_tso_mss);
3618
3619 if (tso < 0)
3620 goto out_drop;
3621 else if (tso)
3622 tx_flags |= I40E_TX_FLAGS_TSO;
3623
3624 /* Always offload the checksum, since it's in the data descriptor */
3625 tso = i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
3626 tx_ring, &cd_tunneling);
3627 if (tso < 0)
3628 goto out_drop;
3629
3630 tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss);
3631
3632 if (tsyn)
3633 tx_flags |= I40E_TX_FLAGS_TSYN;
3634
3635 /* always enable CRC insertion offload */
3636 td_cmd |= I40E_TX_DESC_CMD_ICRC;
3637
3638 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
3639 cd_tunneling, cd_l2tag2);
3640
3641 /* Add Flow Director ATR if it's enabled.
3642 *
3643 * NOTE: this must always be directly before the data descriptor.
3644 */
3645 i40e_atr(tx_ring, skb, tx_flags);
3646
3647 if (i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
3648 td_cmd, td_offset))
3649 goto cleanup_tx_tstamp;
3650
3651 return NETDEV_TX_OK;
3652
3653out_drop:
3654 i40e_trace(xmit_frame_ring_drop, first->skb, tx_ring);
3655 dev_kfree_skb_any(first->skb);
3656 first->skb = NULL;
3657cleanup_tx_tstamp:
3658 if (unlikely(tx_flags & I40E_TX_FLAGS_TSYN)) {
3659 struct i40e_pf *pf = i40e_netdev_to_pf(tx_ring->netdev);
3660
3661 dev_kfree_skb_any(pf->ptp_tx_skb);
3662 pf->ptp_tx_skb = NULL;
3663 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state);
3664 }
3665
3666 return NETDEV_TX_OK;
3667}
3668
3669/**
3670 * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer
3671 * @skb: send buffer
3672 * @netdev: network interface device structure
3673 *
3674 * Returns NETDEV_TX_OK if sent, else an error code
3675 **/
3676netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
3677{
3678 struct i40e_netdev_priv *np = netdev_priv(netdev);
3679 struct i40e_vsi *vsi = np->vsi;
3680 struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping];
3681
3682 /* hardware can't handle really short frames, hardware padding works
3683 * beyond this point
3684 */
3685 if (skb_put_padto(skb, I40E_MIN_TX_LEN))
3686 return NETDEV_TX_OK;
3687
3688 return i40e_xmit_frame_ring(skb, tx_ring);
3689}
3690
3691/**
3692 * i40e_xdp_xmit - Implements ndo_xdp_xmit
3693 * @dev: netdev
3694 * @xdp: XDP buffer
3695 *
3696 * Returns number of frames successfully sent. Frames that fail are
3697 * free'ed via XDP return API.
3698 *
3699 * For error cases, a negative errno code is returned and no-frames
3700 * are transmitted (caller must handle freeing frames).
3701 **/
3702int i40e_xdp_xmit(struct net_device *dev, int n, struct xdp_frame **frames,
3703 u32 flags)
3704{
3705 struct i40e_netdev_priv *np = netdev_priv(dev);
3706 unsigned int queue_index = smp_processor_id();
3707 struct i40e_vsi *vsi = np->vsi;
3708 struct i40e_pf *pf = vsi->back;
3709 struct i40e_ring *xdp_ring;
3710 int drops = 0;
3711 int i;
3712
3713 if (test_bit(__I40E_VSI_DOWN, vsi->state))
3714 return -ENETDOWN;
3715
3716 if (!i40e_enabled_xdp_vsi(vsi) || queue_index >= vsi->num_queue_pairs ||
3717 test_bit(__I40E_CONFIG_BUSY, pf->state))
3718 return -ENXIO;
3719
3720 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
3721 return -EINVAL;
3722
3723 xdp_ring = vsi->xdp_rings[queue_index];
3724
3725 for (i = 0; i < n; i++) {
3726 struct xdp_frame *xdpf = frames[i];
3727 int err;
3728
3729 err = i40e_xmit_xdp_ring(xdpf, xdp_ring);
3730 if (err != I40E_XDP_TX) {
3731 xdp_return_frame_rx_napi(xdpf);
3732 drops++;
3733 }
3734 }
3735
3736 if (unlikely(flags & XDP_XMIT_FLUSH))
3737 i40e_xdp_ring_update_tail(xdp_ring);
3738
3739 return n - drops;
3740}
1/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Driver
4 * Copyright(c) 2013 - 2016 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#include <linux/prefetch.h>
28#include <net/busy_poll.h>
29#include "i40e.h"
30#include "i40e_prototype.h"
31
32static inline __le64 build_ctob(u32 td_cmd, u32 td_offset, unsigned int size,
33 u32 td_tag)
34{
35 return cpu_to_le64(I40E_TX_DESC_DTYPE_DATA |
36 ((u64)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
37 ((u64)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
38 ((u64)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
39 ((u64)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
40}
41
42#define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
43/**
44 * i40e_fdir - Generate a Flow Director descriptor based on fdata
45 * @tx_ring: Tx ring to send buffer on
46 * @fdata: Flow director filter data
47 * @add: Indicate if we are adding a rule or deleting one
48 *
49 **/
50static void i40e_fdir(struct i40e_ring *tx_ring,
51 struct i40e_fdir_filter *fdata, bool add)
52{
53 struct i40e_filter_program_desc *fdir_desc;
54 struct i40e_pf *pf = tx_ring->vsi->back;
55 u32 flex_ptype, dtype_cmd;
56 u16 i;
57
58 /* grab the next descriptor */
59 i = tx_ring->next_to_use;
60 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
61
62 i++;
63 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
64
65 flex_ptype = I40E_TXD_FLTR_QW0_QINDEX_MASK &
66 (fdata->q_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT);
67
68 flex_ptype |= I40E_TXD_FLTR_QW0_FLEXOFF_MASK &
69 (fdata->flex_off << I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT);
70
71 flex_ptype |= I40E_TXD_FLTR_QW0_PCTYPE_MASK &
72 (fdata->pctype << I40E_TXD_FLTR_QW0_PCTYPE_SHIFT);
73
74 /* Use LAN VSI Id if not programmed by user */
75 flex_ptype |= I40E_TXD_FLTR_QW0_DEST_VSI_MASK &
76 ((u32)(fdata->dest_vsi ? : pf->vsi[pf->lan_vsi]->id) <<
77 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT);
78
79 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG;
80
81 dtype_cmd |= add ?
82 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
83 I40E_TXD_FLTR_QW1_PCMD_SHIFT :
84 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
85 I40E_TXD_FLTR_QW1_PCMD_SHIFT;
86
87 dtype_cmd |= I40E_TXD_FLTR_QW1_DEST_MASK &
88 (fdata->dest_ctl << I40E_TXD_FLTR_QW1_DEST_SHIFT);
89
90 dtype_cmd |= I40E_TXD_FLTR_QW1_FD_STATUS_MASK &
91 (fdata->fd_status << I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT);
92
93 if (fdata->cnt_index) {
94 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
95 dtype_cmd |= I40E_TXD_FLTR_QW1_CNTINDEX_MASK &
96 ((u32)fdata->cnt_index <<
97 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT);
98 }
99
100 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);
101 fdir_desc->rsvd = cpu_to_le32(0);
102 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd);
103 fdir_desc->fd_id = cpu_to_le32(fdata->fd_id);
104}
105
106#define I40E_FD_CLEAN_DELAY 10
107/**
108 * i40e_program_fdir_filter - Program a Flow Director filter
109 * @fdir_data: Packet data that will be filter parameters
110 * @raw_packet: the pre-allocated packet buffer for FDir
111 * @pf: The PF pointer
112 * @add: True for add/update, False for remove
113 **/
114static int i40e_program_fdir_filter(struct i40e_fdir_filter *fdir_data,
115 u8 *raw_packet, struct i40e_pf *pf,
116 bool add)
117{
118 struct i40e_tx_buffer *tx_buf, *first;
119 struct i40e_tx_desc *tx_desc;
120 struct i40e_ring *tx_ring;
121 struct i40e_vsi *vsi;
122 struct device *dev;
123 dma_addr_t dma;
124 u32 td_cmd = 0;
125 u16 i;
126
127 /* find existing FDIR VSI */
128 vsi = i40e_find_vsi_by_type(pf, I40E_VSI_FDIR);
129 if (!vsi)
130 return -ENOENT;
131
132 tx_ring = vsi->tx_rings[0];
133 dev = tx_ring->dev;
134
135 /* we need two descriptors to add/del a filter and we can wait */
136 for (i = I40E_FD_CLEAN_DELAY; I40E_DESC_UNUSED(tx_ring) < 2; i--) {
137 if (!i)
138 return -EAGAIN;
139 msleep_interruptible(1);
140 }
141
142 dma = dma_map_single(dev, raw_packet,
143 I40E_FDIR_MAX_RAW_PACKET_SIZE, DMA_TO_DEVICE);
144 if (dma_mapping_error(dev, dma))
145 goto dma_fail;
146
147 /* grab the next descriptor */
148 i = tx_ring->next_to_use;
149 first = &tx_ring->tx_bi[i];
150 i40e_fdir(tx_ring, fdir_data, add);
151
152 /* Now program a dummy descriptor */
153 i = tx_ring->next_to_use;
154 tx_desc = I40E_TX_DESC(tx_ring, i);
155 tx_buf = &tx_ring->tx_bi[i];
156
157 tx_ring->next_to_use = ((i + 1) < tx_ring->count) ? i + 1 : 0;
158
159 memset(tx_buf, 0, sizeof(struct i40e_tx_buffer));
160
161 /* record length, and DMA address */
162 dma_unmap_len_set(tx_buf, len, I40E_FDIR_MAX_RAW_PACKET_SIZE);
163 dma_unmap_addr_set(tx_buf, dma, dma);
164
165 tx_desc->buffer_addr = cpu_to_le64(dma);
166 td_cmd = I40E_TXD_CMD | I40E_TX_DESC_CMD_DUMMY;
167
168 tx_buf->tx_flags = I40E_TX_FLAGS_FD_SB;
169 tx_buf->raw_buf = (void *)raw_packet;
170
171 tx_desc->cmd_type_offset_bsz =
172 build_ctob(td_cmd, 0, I40E_FDIR_MAX_RAW_PACKET_SIZE, 0);
173
174 /* Force memory writes to complete before letting h/w
175 * know there are new descriptors to fetch.
176 */
177 wmb();
178
179 /* Mark the data descriptor to be watched */
180 first->next_to_watch = tx_desc;
181
182 writel(tx_ring->next_to_use, tx_ring->tail);
183 return 0;
184
185dma_fail:
186 return -1;
187}
188
189#define IP_HEADER_OFFSET 14
190#define I40E_UDPIP_DUMMY_PACKET_LEN 42
191/**
192 * i40e_add_del_fdir_udpv4 - Add/Remove UDPv4 filters
193 * @vsi: pointer to the targeted VSI
194 * @fd_data: the flow director data required for the FDir descriptor
195 * @add: true adds a filter, false removes it
196 *
197 * Returns 0 if the filters were successfully added or removed
198 **/
199static int i40e_add_del_fdir_udpv4(struct i40e_vsi *vsi,
200 struct i40e_fdir_filter *fd_data,
201 bool add)
202{
203 struct i40e_pf *pf = vsi->back;
204 struct udphdr *udp;
205 struct iphdr *ip;
206 bool err = false;
207 u8 *raw_packet;
208 int ret;
209 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
210 0x45, 0, 0, 0x1c, 0, 0, 0x40, 0, 0x40, 0x11, 0, 0, 0, 0, 0, 0,
211 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
212
213 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
214 if (!raw_packet)
215 return -ENOMEM;
216 memcpy(raw_packet, packet, I40E_UDPIP_DUMMY_PACKET_LEN);
217
218 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
219 udp = (struct udphdr *)(raw_packet + IP_HEADER_OFFSET
220 + sizeof(struct iphdr));
221
222 ip->daddr = fd_data->dst_ip[0];
223 udp->dest = fd_data->dst_port;
224 ip->saddr = fd_data->src_ip[0];
225 udp->source = fd_data->src_port;
226
227 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
228 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
229 if (ret) {
230 dev_info(&pf->pdev->dev,
231 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
232 fd_data->pctype, fd_data->fd_id, ret);
233 err = true;
234 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
235 if (add)
236 dev_info(&pf->pdev->dev,
237 "Filter OK for PCTYPE %d loc = %d\n",
238 fd_data->pctype, fd_data->fd_id);
239 else
240 dev_info(&pf->pdev->dev,
241 "Filter deleted for PCTYPE %d loc = %d\n",
242 fd_data->pctype, fd_data->fd_id);
243 }
244 if (err)
245 kfree(raw_packet);
246
247 return err ? -EOPNOTSUPP : 0;
248}
249
250#define I40E_TCPIP_DUMMY_PACKET_LEN 54
251/**
252 * i40e_add_del_fdir_tcpv4 - Add/Remove TCPv4 filters
253 * @vsi: pointer to the targeted VSI
254 * @fd_data: the flow director data required for the FDir descriptor
255 * @add: true adds a filter, false removes it
256 *
257 * Returns 0 if the filters were successfully added or removed
258 **/
259static int i40e_add_del_fdir_tcpv4(struct i40e_vsi *vsi,
260 struct i40e_fdir_filter *fd_data,
261 bool add)
262{
263 struct i40e_pf *pf = vsi->back;
264 struct tcphdr *tcp;
265 struct iphdr *ip;
266 bool err = false;
267 u8 *raw_packet;
268 int ret;
269 /* Dummy packet */
270 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
271 0x45, 0, 0, 0x28, 0, 0, 0x40, 0, 0x40, 0x6, 0, 0, 0, 0, 0, 0,
272 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x80, 0x11,
273 0x0, 0x72, 0, 0, 0, 0};
274
275 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
276 if (!raw_packet)
277 return -ENOMEM;
278 memcpy(raw_packet, packet, I40E_TCPIP_DUMMY_PACKET_LEN);
279
280 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
281 tcp = (struct tcphdr *)(raw_packet + IP_HEADER_OFFSET
282 + sizeof(struct iphdr));
283
284 ip->daddr = fd_data->dst_ip[0];
285 tcp->dest = fd_data->dst_port;
286 ip->saddr = fd_data->src_ip[0];
287 tcp->source = fd_data->src_port;
288
289 if (add) {
290 pf->fd_tcp_rule++;
291 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
292 I40E_DEBUG_FD & pf->hw.debug_mask)
293 dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n");
294 pf->auto_disable_flags |= I40E_FLAG_FD_ATR_ENABLED;
295 } else {
296 pf->fd_tcp_rule = (pf->fd_tcp_rule > 0) ?
297 (pf->fd_tcp_rule - 1) : 0;
298 if (pf->fd_tcp_rule == 0) {
299 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
300 I40E_DEBUG_FD & pf->hw.debug_mask)
301 dev_info(&pf->pdev->dev, "ATR re-enabled due to no sideband TCP/IPv4 rules\n");
302 pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
303 }
304 }
305
306 fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
307 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
308
309 if (ret) {
310 dev_info(&pf->pdev->dev,
311 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
312 fd_data->pctype, fd_data->fd_id, ret);
313 err = true;
314 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
315 if (add)
316 dev_info(&pf->pdev->dev, "Filter OK for PCTYPE %d loc = %d)\n",
317 fd_data->pctype, fd_data->fd_id);
318 else
319 dev_info(&pf->pdev->dev,
320 "Filter deleted for PCTYPE %d loc = %d\n",
321 fd_data->pctype, fd_data->fd_id);
322 }
323
324 if (err)
325 kfree(raw_packet);
326
327 return err ? -EOPNOTSUPP : 0;
328}
329
330#define I40E_IP_DUMMY_PACKET_LEN 34
331/**
332 * i40e_add_del_fdir_ipv4 - Add/Remove IPv4 Flow Director filters for
333 * a specific flow spec
334 * @vsi: pointer to the targeted VSI
335 * @fd_data: the flow director data required for the FDir descriptor
336 * @add: true adds a filter, false removes it
337 *
338 * Returns 0 if the filters were successfully added or removed
339 **/
340static int i40e_add_del_fdir_ipv4(struct i40e_vsi *vsi,
341 struct i40e_fdir_filter *fd_data,
342 bool add)
343{
344 struct i40e_pf *pf = vsi->back;
345 struct iphdr *ip;
346 bool err = false;
347 u8 *raw_packet;
348 int ret;
349 int i;
350 static char packet[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x08, 0,
351 0x45, 0, 0, 0x14, 0, 0, 0x40, 0, 0x40, 0x10, 0, 0, 0, 0, 0, 0,
352 0, 0, 0, 0};
353
354 for (i = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
355 i <= I40E_FILTER_PCTYPE_FRAG_IPV4; i++) {
356 raw_packet = kzalloc(I40E_FDIR_MAX_RAW_PACKET_SIZE, GFP_KERNEL);
357 if (!raw_packet)
358 return -ENOMEM;
359 memcpy(raw_packet, packet, I40E_IP_DUMMY_PACKET_LEN);
360 ip = (struct iphdr *)(raw_packet + IP_HEADER_OFFSET);
361
362 ip->saddr = fd_data->src_ip[0];
363 ip->daddr = fd_data->dst_ip[0];
364 ip->protocol = 0;
365
366 fd_data->pctype = i;
367 ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
368
369 if (ret) {
370 dev_info(&pf->pdev->dev,
371 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
372 fd_data->pctype, fd_data->fd_id, ret);
373 err = true;
374 } else if (I40E_DEBUG_FD & pf->hw.debug_mask) {
375 if (add)
376 dev_info(&pf->pdev->dev,
377 "Filter OK for PCTYPE %d loc = %d\n",
378 fd_data->pctype, fd_data->fd_id);
379 else
380 dev_info(&pf->pdev->dev,
381 "Filter deleted for PCTYPE %d loc = %d\n",
382 fd_data->pctype, fd_data->fd_id);
383 }
384 }
385
386 if (err)
387 kfree(raw_packet);
388
389 return err ? -EOPNOTSUPP : 0;
390}
391
392/**
393 * i40e_add_del_fdir - Build raw packets to add/del fdir filter
394 * @vsi: pointer to the targeted VSI
395 * @cmd: command to get or set RX flow classification rules
396 * @add: true adds a filter, false removes it
397 *
398 **/
399int i40e_add_del_fdir(struct i40e_vsi *vsi,
400 struct i40e_fdir_filter *input, bool add)
401{
402 struct i40e_pf *pf = vsi->back;
403 int ret;
404
405 switch (input->flow_type & ~FLOW_EXT) {
406 case TCP_V4_FLOW:
407 ret = i40e_add_del_fdir_tcpv4(vsi, input, add);
408 break;
409 case UDP_V4_FLOW:
410 ret = i40e_add_del_fdir_udpv4(vsi, input, add);
411 break;
412 case IP_USER_FLOW:
413 switch (input->ip4_proto) {
414 case IPPROTO_TCP:
415 ret = i40e_add_del_fdir_tcpv4(vsi, input, add);
416 break;
417 case IPPROTO_UDP:
418 ret = i40e_add_del_fdir_udpv4(vsi, input, add);
419 break;
420 case IPPROTO_IP:
421 ret = i40e_add_del_fdir_ipv4(vsi, input, add);
422 break;
423 default:
424 /* We cannot support masking based on protocol */
425 goto unsupported_flow;
426 }
427 break;
428 default:
429unsupported_flow:
430 dev_info(&pf->pdev->dev, "Could not specify spec type %d\n",
431 input->flow_type);
432 ret = -EINVAL;
433 }
434
435 /* The buffer allocated here is freed by the i40e_clean_tx_ring() */
436 return ret;
437}
438
439/**
440 * i40e_fd_handle_status - check the Programming Status for FD
441 * @rx_ring: the Rx ring for this descriptor
442 * @rx_desc: the Rx descriptor for programming Status, not a packet descriptor.
443 * @prog_id: the id originally used for programming
444 *
445 * This is used to verify if the FD programming or invalidation
446 * requested by SW to the HW is successful or not and take actions accordingly.
447 **/
448static void i40e_fd_handle_status(struct i40e_ring *rx_ring,
449 union i40e_rx_desc *rx_desc, u8 prog_id)
450{
451 struct i40e_pf *pf = rx_ring->vsi->back;
452 struct pci_dev *pdev = pf->pdev;
453 u32 fcnt_prog, fcnt_avail;
454 u32 error;
455 u64 qw;
456
457 qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
458 error = (qw & I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
459 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
460
461 if (error == BIT(I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
462 pf->fd_inv = le32_to_cpu(rx_desc->wb.qword0.hi_dword.fd_id);
463 if ((rx_desc->wb.qword0.hi_dword.fd_id != 0) ||
464 (I40E_DEBUG_FD & pf->hw.debug_mask))
465 dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n",
466 pf->fd_inv);
467
468 /* Check if the programming error is for ATR.
469 * If so, auto disable ATR and set a state for
470 * flush in progress. Next time we come here if flush is in
471 * progress do nothing, once flush is complete the state will
472 * be cleared.
473 */
474 if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
475 return;
476
477 pf->fd_add_err++;
478 /* store the current atr filter count */
479 pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf);
480
481 if ((rx_desc->wb.qword0.hi_dword.fd_id == 0) &&
482 (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
483 pf->auto_disable_flags |= I40E_FLAG_FD_ATR_ENABLED;
484 set_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
485 }
486
487 /* filter programming failed most likely due to table full */
488 fcnt_prog = i40e_get_global_fd_count(pf);
489 fcnt_avail = pf->fdir_pf_filter_count;
490 /* If ATR is running fcnt_prog can quickly change,
491 * if we are very close to full, it makes sense to disable
492 * FD ATR/SB and then re-enable it when there is room.
493 */
494 if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) {
495 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
496 !(pf->auto_disable_flags &
497 I40E_FLAG_FD_SB_ENABLED)) {
498 if (I40E_DEBUG_FD & pf->hw.debug_mask)
499 dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n");
500 pf->auto_disable_flags |=
501 I40E_FLAG_FD_SB_ENABLED;
502 }
503 }
504 } else if (error == BIT(I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
505 if (I40E_DEBUG_FD & pf->hw.debug_mask)
506 dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n",
507 rx_desc->wb.qword0.hi_dword.fd_id);
508 }
509}
510
511/**
512 * i40e_unmap_and_free_tx_resource - Release a Tx buffer
513 * @ring: the ring that owns the buffer
514 * @tx_buffer: the buffer to free
515 **/
516static void i40e_unmap_and_free_tx_resource(struct i40e_ring *ring,
517 struct i40e_tx_buffer *tx_buffer)
518{
519 if (tx_buffer->skb) {
520 if (tx_buffer->tx_flags & I40E_TX_FLAGS_FD_SB)
521 kfree(tx_buffer->raw_buf);
522 else
523 dev_kfree_skb_any(tx_buffer->skb);
524 if (dma_unmap_len(tx_buffer, len))
525 dma_unmap_single(ring->dev,
526 dma_unmap_addr(tx_buffer, dma),
527 dma_unmap_len(tx_buffer, len),
528 DMA_TO_DEVICE);
529 } else if (dma_unmap_len(tx_buffer, len)) {
530 dma_unmap_page(ring->dev,
531 dma_unmap_addr(tx_buffer, dma),
532 dma_unmap_len(tx_buffer, len),
533 DMA_TO_DEVICE);
534 }
535
536 tx_buffer->next_to_watch = NULL;
537 tx_buffer->skb = NULL;
538 dma_unmap_len_set(tx_buffer, len, 0);
539 /* tx_buffer must be completely set up in the transmit path */
540}
541
542/**
543 * i40e_clean_tx_ring - Free any empty Tx buffers
544 * @tx_ring: ring to be cleaned
545 **/
546void i40e_clean_tx_ring(struct i40e_ring *tx_ring)
547{
548 unsigned long bi_size;
549 u16 i;
550
551 /* ring already cleared, nothing to do */
552 if (!tx_ring->tx_bi)
553 return;
554
555 /* Free all the Tx ring sk_buffs */
556 for (i = 0; i < tx_ring->count; i++)
557 i40e_unmap_and_free_tx_resource(tx_ring, &tx_ring->tx_bi[i]);
558
559 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
560 memset(tx_ring->tx_bi, 0, bi_size);
561
562 /* Zero out the descriptor ring */
563 memset(tx_ring->desc, 0, tx_ring->size);
564
565 tx_ring->next_to_use = 0;
566 tx_ring->next_to_clean = 0;
567
568 if (!tx_ring->netdev)
569 return;
570
571 /* cleanup Tx queue statistics */
572 netdev_tx_reset_queue(txring_txq(tx_ring));
573}
574
575/**
576 * i40e_free_tx_resources - Free Tx resources per queue
577 * @tx_ring: Tx descriptor ring for a specific queue
578 *
579 * Free all transmit software resources
580 **/
581void i40e_free_tx_resources(struct i40e_ring *tx_ring)
582{
583 i40e_clean_tx_ring(tx_ring);
584 kfree(tx_ring->tx_bi);
585 tx_ring->tx_bi = NULL;
586
587 if (tx_ring->desc) {
588 dma_free_coherent(tx_ring->dev, tx_ring->size,
589 tx_ring->desc, tx_ring->dma);
590 tx_ring->desc = NULL;
591 }
592}
593
594/**
595 * i40e_get_tx_pending - how many tx descriptors not processed
596 * @tx_ring: the ring of descriptors
597 * @in_sw: is tx_pending being checked in SW or HW
598 *
599 * Since there is no access to the ring head register
600 * in XL710, we need to use our local copies
601 **/
602u32 i40e_get_tx_pending(struct i40e_ring *ring, bool in_sw)
603{
604 u32 head, tail;
605
606 if (!in_sw)
607 head = i40e_get_head(ring);
608 else
609 head = ring->next_to_clean;
610 tail = readl(ring->tail);
611
612 if (head != tail)
613 return (head < tail) ?
614 tail - head : (tail + ring->count - head);
615
616 return 0;
617}
618
619#define WB_STRIDE 4
620
621/**
622 * i40e_clean_tx_irq - Reclaim resources after transmit completes
623 * @vsi: the VSI we care about
624 * @tx_ring: Tx ring to clean
625 * @napi_budget: Used to determine if we are in netpoll
626 *
627 * Returns true if there's any budget left (e.g. the clean is finished)
628 **/
629static bool i40e_clean_tx_irq(struct i40e_vsi *vsi,
630 struct i40e_ring *tx_ring, int napi_budget)
631{
632 u16 i = tx_ring->next_to_clean;
633 struct i40e_tx_buffer *tx_buf;
634 struct i40e_tx_desc *tx_head;
635 struct i40e_tx_desc *tx_desc;
636 unsigned int total_bytes = 0, total_packets = 0;
637 unsigned int budget = vsi->work_limit;
638
639 tx_buf = &tx_ring->tx_bi[i];
640 tx_desc = I40E_TX_DESC(tx_ring, i);
641 i -= tx_ring->count;
642
643 tx_head = I40E_TX_DESC(tx_ring, i40e_get_head(tx_ring));
644
645 do {
646 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
647
648 /* if next_to_watch is not set then there is no work pending */
649 if (!eop_desc)
650 break;
651
652 /* prevent any other reads prior to eop_desc */
653 read_barrier_depends();
654
655 /* we have caught up to head, no work left to do */
656 if (tx_head == tx_desc)
657 break;
658
659 /* clear next_to_watch to prevent false hangs */
660 tx_buf->next_to_watch = NULL;
661
662 /* update the statistics for this packet */
663 total_bytes += tx_buf->bytecount;
664 total_packets += tx_buf->gso_segs;
665
666 /* free the skb */
667 napi_consume_skb(tx_buf->skb, napi_budget);
668
669 /* unmap skb header data */
670 dma_unmap_single(tx_ring->dev,
671 dma_unmap_addr(tx_buf, dma),
672 dma_unmap_len(tx_buf, len),
673 DMA_TO_DEVICE);
674
675 /* clear tx_buffer data */
676 tx_buf->skb = NULL;
677 dma_unmap_len_set(tx_buf, len, 0);
678
679 /* unmap remaining buffers */
680 while (tx_desc != eop_desc) {
681
682 tx_buf++;
683 tx_desc++;
684 i++;
685 if (unlikely(!i)) {
686 i -= tx_ring->count;
687 tx_buf = tx_ring->tx_bi;
688 tx_desc = I40E_TX_DESC(tx_ring, 0);
689 }
690
691 /* unmap any remaining paged data */
692 if (dma_unmap_len(tx_buf, len)) {
693 dma_unmap_page(tx_ring->dev,
694 dma_unmap_addr(tx_buf, dma),
695 dma_unmap_len(tx_buf, len),
696 DMA_TO_DEVICE);
697 dma_unmap_len_set(tx_buf, len, 0);
698 }
699 }
700
701 /* move us one more past the eop_desc for start of next pkt */
702 tx_buf++;
703 tx_desc++;
704 i++;
705 if (unlikely(!i)) {
706 i -= tx_ring->count;
707 tx_buf = tx_ring->tx_bi;
708 tx_desc = I40E_TX_DESC(tx_ring, 0);
709 }
710
711 prefetch(tx_desc);
712
713 /* update budget accounting */
714 budget--;
715 } while (likely(budget));
716
717 i += tx_ring->count;
718 tx_ring->next_to_clean = i;
719 u64_stats_update_begin(&tx_ring->syncp);
720 tx_ring->stats.bytes += total_bytes;
721 tx_ring->stats.packets += total_packets;
722 u64_stats_update_end(&tx_ring->syncp);
723 tx_ring->q_vector->tx.total_bytes += total_bytes;
724 tx_ring->q_vector->tx.total_packets += total_packets;
725
726 if (tx_ring->flags & I40E_TXR_FLAGS_WB_ON_ITR) {
727 /* check to see if there are < 4 descriptors
728 * waiting to be written back, then kick the hardware to force
729 * them to be written back in case we stay in NAPI.
730 * In this mode on X722 we do not enable Interrupt.
731 */
732 unsigned int j = i40e_get_tx_pending(tx_ring, false);
733
734 if (budget &&
735 ((j / WB_STRIDE) == 0) && (j > 0) &&
736 !test_bit(__I40E_DOWN, &vsi->state) &&
737 (I40E_DESC_UNUSED(tx_ring) != tx_ring->count))
738 tx_ring->arm_wb = true;
739 }
740
741 /* notify netdev of completed buffers */
742 netdev_tx_completed_queue(txring_txq(tx_ring),
743 total_packets, total_bytes);
744
745#define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
746 if (unlikely(total_packets && netif_carrier_ok(tx_ring->netdev) &&
747 (I40E_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
748 /* Make sure that anybody stopping the queue after this
749 * sees the new next_to_clean.
750 */
751 smp_mb();
752 if (__netif_subqueue_stopped(tx_ring->netdev,
753 tx_ring->queue_index) &&
754 !test_bit(__I40E_DOWN, &vsi->state)) {
755 netif_wake_subqueue(tx_ring->netdev,
756 tx_ring->queue_index);
757 ++tx_ring->tx_stats.restart_queue;
758 }
759 }
760
761 return !!budget;
762}
763
764/**
765 * i40e_enable_wb_on_itr - Arm hardware to do a wb, interrupts are not enabled
766 * @vsi: the VSI we care about
767 * @q_vector: the vector on which to enable writeback
768 *
769 **/
770static void i40e_enable_wb_on_itr(struct i40e_vsi *vsi,
771 struct i40e_q_vector *q_vector)
772{
773 u16 flags = q_vector->tx.ring[0].flags;
774 u32 val;
775
776 if (!(flags & I40E_TXR_FLAGS_WB_ON_ITR))
777 return;
778
779 if (q_vector->arm_wb_state)
780 return;
781
782 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
783 val = I40E_PFINT_DYN_CTLN_WB_ON_ITR_MASK |
784 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK; /* set noitr */
785
786 wr32(&vsi->back->hw,
787 I40E_PFINT_DYN_CTLN(q_vector->v_idx + vsi->base_vector - 1),
788 val);
789 } else {
790 val = I40E_PFINT_DYN_CTL0_WB_ON_ITR_MASK |
791 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK; /* set noitr */
792
793 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val);
794 }
795 q_vector->arm_wb_state = true;
796}
797
798/**
799 * i40e_force_wb - Issue SW Interrupt so HW does a wb
800 * @vsi: the VSI we care about
801 * @q_vector: the vector on which to force writeback
802 *
803 **/
804void i40e_force_wb(struct i40e_vsi *vsi, struct i40e_q_vector *q_vector)
805{
806 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED) {
807 u32 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
808 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK | /* set noitr */
809 I40E_PFINT_DYN_CTLN_SWINT_TRIG_MASK |
810 I40E_PFINT_DYN_CTLN_SW_ITR_INDX_ENA_MASK;
811 /* allow 00 to be written to the index */
812
813 wr32(&vsi->back->hw,
814 I40E_PFINT_DYN_CTLN(q_vector->v_idx +
815 vsi->base_vector - 1), val);
816 } else {
817 u32 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
818 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK | /* set noitr */
819 I40E_PFINT_DYN_CTL0_SWINT_TRIG_MASK |
820 I40E_PFINT_DYN_CTL0_SW_ITR_INDX_ENA_MASK;
821 /* allow 00 to be written to the index */
822
823 wr32(&vsi->back->hw, I40E_PFINT_DYN_CTL0, val);
824 }
825}
826
827/**
828 * i40e_set_new_dynamic_itr - Find new ITR level
829 * @rc: structure containing ring performance data
830 *
831 * Returns true if ITR changed, false if not
832 *
833 * Stores a new ITR value based on packets and byte counts during
834 * the last interrupt. The advantage of per interrupt computation
835 * is faster updates and more accurate ITR for the current traffic
836 * pattern. Constants in this function were computed based on
837 * theoretical maximum wire speed and thresholds were set based on
838 * testing data as well as attempting to minimize response time
839 * while increasing bulk throughput.
840 **/
841static bool i40e_set_new_dynamic_itr(struct i40e_ring_container *rc)
842{
843 enum i40e_latency_range new_latency_range = rc->latency_range;
844 struct i40e_q_vector *qv = rc->ring->q_vector;
845 u32 new_itr = rc->itr;
846 int bytes_per_int;
847 int usecs;
848
849 if (rc->total_packets == 0 || !rc->itr)
850 return false;
851
852 /* simple throttlerate management
853 * 0-10MB/s lowest (50000 ints/s)
854 * 10-20MB/s low (20000 ints/s)
855 * 20-1249MB/s bulk (18000 ints/s)
856 * > 40000 Rx packets per second (8000 ints/s)
857 *
858 * The math works out because the divisor is in 10^(-6) which
859 * turns the bytes/us input value into MB/s values, but
860 * make sure to use usecs, as the register values written
861 * are in 2 usec increments in the ITR registers, and make sure
862 * to use the smoothed values that the countdown timer gives us.
863 */
864 usecs = (rc->itr << 1) * ITR_COUNTDOWN_START;
865 bytes_per_int = rc->total_bytes / usecs;
866
867 switch (new_latency_range) {
868 case I40E_LOWEST_LATENCY:
869 if (bytes_per_int > 10)
870 new_latency_range = I40E_LOW_LATENCY;
871 break;
872 case I40E_LOW_LATENCY:
873 if (bytes_per_int > 20)
874 new_latency_range = I40E_BULK_LATENCY;
875 else if (bytes_per_int <= 10)
876 new_latency_range = I40E_LOWEST_LATENCY;
877 break;
878 case I40E_BULK_LATENCY:
879 case I40E_ULTRA_LATENCY:
880 default:
881 if (bytes_per_int <= 20)
882 new_latency_range = I40E_LOW_LATENCY;
883 break;
884 }
885
886 /* this is to adjust RX more aggressively when streaming small
887 * packets. The value of 40000 was picked as it is just beyond
888 * what the hardware can receive per second if in low latency
889 * mode.
890 */
891#define RX_ULTRA_PACKET_RATE 40000
892
893 if ((((rc->total_packets * 1000000) / usecs) > RX_ULTRA_PACKET_RATE) &&
894 (&qv->rx == rc))
895 new_latency_range = I40E_ULTRA_LATENCY;
896
897 rc->latency_range = new_latency_range;
898
899 switch (new_latency_range) {
900 case I40E_LOWEST_LATENCY:
901 new_itr = I40E_ITR_50K;
902 break;
903 case I40E_LOW_LATENCY:
904 new_itr = I40E_ITR_20K;
905 break;
906 case I40E_BULK_LATENCY:
907 new_itr = I40E_ITR_18K;
908 break;
909 case I40E_ULTRA_LATENCY:
910 new_itr = I40E_ITR_8K;
911 break;
912 default:
913 break;
914 }
915
916 rc->total_bytes = 0;
917 rc->total_packets = 0;
918
919 if (new_itr != rc->itr) {
920 rc->itr = new_itr;
921 return true;
922 }
923
924 return false;
925}
926
927/**
928 * i40e_clean_programming_status - clean the programming status descriptor
929 * @rx_ring: the rx ring that has this descriptor
930 * @rx_desc: the rx descriptor written back by HW
931 *
932 * Flow director should handle FD_FILTER_STATUS to check its filter programming
933 * status being successful or not and take actions accordingly. FCoE should
934 * handle its context/filter programming/invalidation status and take actions.
935 *
936 **/
937static void i40e_clean_programming_status(struct i40e_ring *rx_ring,
938 union i40e_rx_desc *rx_desc)
939{
940 u64 qw;
941 u8 id;
942
943 qw = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
944 id = (qw & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
945 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
946
947 if (id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS)
948 i40e_fd_handle_status(rx_ring, rx_desc, id);
949#ifdef I40E_FCOE
950 else if ((id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS) ||
951 (id == I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS))
952 i40e_fcoe_handle_status(rx_ring, rx_desc, id);
953#endif
954}
955
956/**
957 * i40e_setup_tx_descriptors - Allocate the Tx descriptors
958 * @tx_ring: the tx ring to set up
959 *
960 * Return 0 on success, negative on error
961 **/
962int i40e_setup_tx_descriptors(struct i40e_ring *tx_ring)
963{
964 struct device *dev = tx_ring->dev;
965 int bi_size;
966
967 if (!dev)
968 return -ENOMEM;
969
970 /* warn if we are about to overwrite the pointer */
971 WARN_ON(tx_ring->tx_bi);
972 bi_size = sizeof(struct i40e_tx_buffer) * tx_ring->count;
973 tx_ring->tx_bi = kzalloc(bi_size, GFP_KERNEL);
974 if (!tx_ring->tx_bi)
975 goto err;
976
977 /* round up to nearest 4K */
978 tx_ring->size = tx_ring->count * sizeof(struct i40e_tx_desc);
979 /* add u32 for head writeback, align after this takes care of
980 * guaranteeing this is at least one cache line in size
981 */
982 tx_ring->size += sizeof(u32);
983 tx_ring->size = ALIGN(tx_ring->size, 4096);
984 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
985 &tx_ring->dma, GFP_KERNEL);
986 if (!tx_ring->desc) {
987 dev_info(dev, "Unable to allocate memory for the Tx descriptor ring, size=%d\n",
988 tx_ring->size);
989 goto err;
990 }
991
992 tx_ring->next_to_use = 0;
993 tx_ring->next_to_clean = 0;
994 return 0;
995
996err:
997 kfree(tx_ring->tx_bi);
998 tx_ring->tx_bi = NULL;
999 return -ENOMEM;
1000}
1001
1002/**
1003 * i40e_clean_rx_ring - Free Rx buffers
1004 * @rx_ring: ring to be cleaned
1005 **/
1006void i40e_clean_rx_ring(struct i40e_ring *rx_ring)
1007{
1008 struct device *dev = rx_ring->dev;
1009 unsigned long bi_size;
1010 u16 i;
1011
1012 /* ring already cleared, nothing to do */
1013 if (!rx_ring->rx_bi)
1014 return;
1015
1016 /* Free all the Rx ring sk_buffs */
1017 for (i = 0; i < rx_ring->count; i++) {
1018 struct i40e_rx_buffer *rx_bi = &rx_ring->rx_bi[i];
1019
1020 if (rx_bi->skb) {
1021 dev_kfree_skb(rx_bi->skb);
1022 rx_bi->skb = NULL;
1023 }
1024 if (!rx_bi->page)
1025 continue;
1026
1027 dma_unmap_page(dev, rx_bi->dma, PAGE_SIZE, DMA_FROM_DEVICE);
1028 __free_pages(rx_bi->page, 0);
1029
1030 rx_bi->page = NULL;
1031 rx_bi->page_offset = 0;
1032 }
1033
1034 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
1035 memset(rx_ring->rx_bi, 0, bi_size);
1036
1037 /* Zero out the descriptor ring */
1038 memset(rx_ring->desc, 0, rx_ring->size);
1039
1040 rx_ring->next_to_alloc = 0;
1041 rx_ring->next_to_clean = 0;
1042 rx_ring->next_to_use = 0;
1043}
1044
1045/**
1046 * i40e_free_rx_resources - Free Rx resources
1047 * @rx_ring: ring to clean the resources from
1048 *
1049 * Free all receive software resources
1050 **/
1051void i40e_free_rx_resources(struct i40e_ring *rx_ring)
1052{
1053 i40e_clean_rx_ring(rx_ring);
1054 kfree(rx_ring->rx_bi);
1055 rx_ring->rx_bi = NULL;
1056
1057 if (rx_ring->desc) {
1058 dma_free_coherent(rx_ring->dev, rx_ring->size,
1059 rx_ring->desc, rx_ring->dma);
1060 rx_ring->desc = NULL;
1061 }
1062}
1063
1064/**
1065 * i40e_setup_rx_descriptors - Allocate Rx descriptors
1066 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
1067 *
1068 * Returns 0 on success, negative on failure
1069 **/
1070int i40e_setup_rx_descriptors(struct i40e_ring *rx_ring)
1071{
1072 struct device *dev = rx_ring->dev;
1073 int bi_size;
1074
1075 /* warn if we are about to overwrite the pointer */
1076 WARN_ON(rx_ring->rx_bi);
1077 bi_size = sizeof(struct i40e_rx_buffer) * rx_ring->count;
1078 rx_ring->rx_bi = kzalloc(bi_size, GFP_KERNEL);
1079 if (!rx_ring->rx_bi)
1080 goto err;
1081
1082 u64_stats_init(&rx_ring->syncp);
1083
1084 /* Round up to nearest 4K */
1085 rx_ring->size = rx_ring->count * sizeof(union i40e_32byte_rx_desc);
1086 rx_ring->size = ALIGN(rx_ring->size, 4096);
1087 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
1088 &rx_ring->dma, GFP_KERNEL);
1089
1090 if (!rx_ring->desc) {
1091 dev_info(dev, "Unable to allocate memory for the Rx descriptor ring, size=%d\n",
1092 rx_ring->size);
1093 goto err;
1094 }
1095
1096 rx_ring->next_to_alloc = 0;
1097 rx_ring->next_to_clean = 0;
1098 rx_ring->next_to_use = 0;
1099
1100 return 0;
1101err:
1102 kfree(rx_ring->rx_bi);
1103 rx_ring->rx_bi = NULL;
1104 return -ENOMEM;
1105}
1106
1107/**
1108 * i40e_release_rx_desc - Store the new tail and head values
1109 * @rx_ring: ring to bump
1110 * @val: new head index
1111 **/
1112static inline void i40e_release_rx_desc(struct i40e_ring *rx_ring, u32 val)
1113{
1114 rx_ring->next_to_use = val;
1115
1116 /* update next to alloc since we have filled the ring */
1117 rx_ring->next_to_alloc = val;
1118
1119 /* Force memory writes to complete before letting h/w
1120 * know there are new descriptors to fetch. (Only
1121 * applicable for weak-ordered memory model archs,
1122 * such as IA-64).
1123 */
1124 wmb();
1125 writel(val, rx_ring->tail);
1126}
1127
1128/**
1129 * i40e_alloc_mapped_page - recycle or make a new page
1130 * @rx_ring: ring to use
1131 * @bi: rx_buffer struct to modify
1132 *
1133 * Returns true if the page was successfully allocated or
1134 * reused.
1135 **/
1136static bool i40e_alloc_mapped_page(struct i40e_ring *rx_ring,
1137 struct i40e_rx_buffer *bi)
1138{
1139 struct page *page = bi->page;
1140 dma_addr_t dma;
1141
1142 /* since we are recycling buffers we should seldom need to alloc */
1143 if (likely(page)) {
1144 rx_ring->rx_stats.page_reuse_count++;
1145 return true;
1146 }
1147
1148 /* alloc new page for storage */
1149 page = dev_alloc_page();
1150 if (unlikely(!page)) {
1151 rx_ring->rx_stats.alloc_page_failed++;
1152 return false;
1153 }
1154
1155 /* map page for use */
1156 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE, DMA_FROM_DEVICE);
1157
1158 /* if mapping failed free memory back to system since
1159 * there isn't much point in holding memory we can't use
1160 */
1161 if (dma_mapping_error(rx_ring->dev, dma)) {
1162 __free_pages(page, 0);
1163 rx_ring->rx_stats.alloc_page_failed++;
1164 return false;
1165 }
1166
1167 bi->dma = dma;
1168 bi->page = page;
1169 bi->page_offset = 0;
1170
1171 return true;
1172}
1173
1174/**
1175 * i40e_receive_skb - Send a completed packet up the stack
1176 * @rx_ring: rx ring in play
1177 * @skb: packet to send up
1178 * @vlan_tag: vlan tag for packet
1179 **/
1180static void i40e_receive_skb(struct i40e_ring *rx_ring,
1181 struct sk_buff *skb, u16 vlan_tag)
1182{
1183 struct i40e_q_vector *q_vector = rx_ring->q_vector;
1184
1185 if ((rx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1186 (vlan_tag & VLAN_VID_MASK))
1187 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
1188
1189 napi_gro_receive(&q_vector->napi, skb);
1190}
1191
1192/**
1193 * i40e_alloc_rx_buffers - Replace used receive buffers
1194 * @rx_ring: ring to place buffers on
1195 * @cleaned_count: number of buffers to replace
1196 *
1197 * Returns false if all allocations were successful, true if any fail
1198 **/
1199bool i40e_alloc_rx_buffers(struct i40e_ring *rx_ring, u16 cleaned_count)
1200{
1201 u16 ntu = rx_ring->next_to_use;
1202 union i40e_rx_desc *rx_desc;
1203 struct i40e_rx_buffer *bi;
1204
1205 /* do nothing if no valid netdev defined */
1206 if (!rx_ring->netdev || !cleaned_count)
1207 return false;
1208
1209 rx_desc = I40E_RX_DESC(rx_ring, ntu);
1210 bi = &rx_ring->rx_bi[ntu];
1211
1212 do {
1213 if (!i40e_alloc_mapped_page(rx_ring, bi))
1214 goto no_buffers;
1215
1216 /* Refresh the desc even if buffer_addrs didn't change
1217 * because each write-back erases this info.
1218 */
1219 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1220
1221 rx_desc++;
1222 bi++;
1223 ntu++;
1224 if (unlikely(ntu == rx_ring->count)) {
1225 rx_desc = I40E_RX_DESC(rx_ring, 0);
1226 bi = rx_ring->rx_bi;
1227 ntu = 0;
1228 }
1229
1230 /* clear the status bits for the next_to_use descriptor */
1231 rx_desc->wb.qword1.status_error_len = 0;
1232
1233 cleaned_count--;
1234 } while (cleaned_count);
1235
1236 if (rx_ring->next_to_use != ntu)
1237 i40e_release_rx_desc(rx_ring, ntu);
1238
1239 return false;
1240
1241no_buffers:
1242 if (rx_ring->next_to_use != ntu)
1243 i40e_release_rx_desc(rx_ring, ntu);
1244
1245 /* make sure to come back via polling to try again after
1246 * allocation failure
1247 */
1248 return true;
1249}
1250
1251/**
1252 * i40e_rx_checksum - Indicate in skb if hw indicated a good cksum
1253 * @vsi: the VSI we care about
1254 * @skb: skb currently being received and modified
1255 * @rx_desc: the receive descriptor
1256 *
1257 * skb->protocol must be set before this function is called
1258 **/
1259static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
1260 struct sk_buff *skb,
1261 union i40e_rx_desc *rx_desc)
1262{
1263 struct i40e_rx_ptype_decoded decoded;
1264 u32 rx_error, rx_status;
1265 bool ipv4, ipv6;
1266 u8 ptype;
1267 u64 qword;
1268
1269 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1270 ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT;
1271 rx_error = (qword & I40E_RXD_QW1_ERROR_MASK) >>
1272 I40E_RXD_QW1_ERROR_SHIFT;
1273 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1274 I40E_RXD_QW1_STATUS_SHIFT;
1275 decoded = decode_rx_desc_ptype(ptype);
1276
1277 skb->ip_summed = CHECKSUM_NONE;
1278
1279 skb_checksum_none_assert(skb);
1280
1281 /* Rx csum enabled and ip headers found? */
1282 if (!(vsi->netdev->features & NETIF_F_RXCSUM))
1283 return;
1284
1285 /* did the hardware decode the packet and checksum? */
1286 if (!(rx_status & BIT(I40E_RX_DESC_STATUS_L3L4P_SHIFT)))
1287 return;
1288
1289 /* both known and outer_ip must be set for the below code to work */
1290 if (!(decoded.known && decoded.outer_ip))
1291 return;
1292
1293 ipv4 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) &&
1294 (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV4);
1295 ipv6 = (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP) &&
1296 (decoded.outer_ip_ver == I40E_RX_PTYPE_OUTER_IPV6);
1297
1298 if (ipv4 &&
1299 (rx_error & (BIT(I40E_RX_DESC_ERROR_IPE_SHIFT) |
1300 BIT(I40E_RX_DESC_ERROR_EIPE_SHIFT))))
1301 goto checksum_fail;
1302
1303 /* likely incorrect csum if alternate IP extension headers found */
1304 if (ipv6 &&
1305 rx_status & BIT(I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT))
1306 /* don't increment checksum err here, non-fatal err */
1307 return;
1308
1309 /* there was some L4 error, count error and punt packet to the stack */
1310 if (rx_error & BIT(I40E_RX_DESC_ERROR_L4E_SHIFT))
1311 goto checksum_fail;
1312
1313 /* handle packets that were not able to be checksummed due
1314 * to arrival speed, in this case the stack can compute
1315 * the csum.
1316 */
1317 if (rx_error & BIT(I40E_RX_DESC_ERROR_PPRS_SHIFT))
1318 return;
1319
1320 /* If there is an outer header present that might contain a checksum
1321 * we need to bump the checksum level by 1 to reflect the fact that
1322 * we are indicating we validated the inner checksum.
1323 */
1324 if (decoded.tunnel_type >= I40E_RX_PTYPE_TUNNEL_IP_GRENAT)
1325 skb->csum_level = 1;
1326
1327 /* Only report checksum unnecessary for TCP, UDP, or SCTP */
1328 switch (decoded.inner_prot) {
1329 case I40E_RX_PTYPE_INNER_PROT_TCP:
1330 case I40E_RX_PTYPE_INNER_PROT_UDP:
1331 case I40E_RX_PTYPE_INNER_PROT_SCTP:
1332 skb->ip_summed = CHECKSUM_UNNECESSARY;
1333 /* fall though */
1334 default:
1335 break;
1336 }
1337
1338 return;
1339
1340checksum_fail:
1341 vsi->back->hw_csum_rx_error++;
1342}
1343
1344/**
1345 * i40e_ptype_to_htype - get a hash type
1346 * @ptype: the ptype value from the descriptor
1347 *
1348 * Returns a hash type to be used by skb_set_hash
1349 **/
1350static inline int i40e_ptype_to_htype(u8 ptype)
1351{
1352 struct i40e_rx_ptype_decoded decoded = decode_rx_desc_ptype(ptype);
1353
1354 if (!decoded.known)
1355 return PKT_HASH_TYPE_NONE;
1356
1357 if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1358 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4)
1359 return PKT_HASH_TYPE_L4;
1360 else if (decoded.outer_ip == I40E_RX_PTYPE_OUTER_IP &&
1361 decoded.payload_layer == I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3)
1362 return PKT_HASH_TYPE_L3;
1363 else
1364 return PKT_HASH_TYPE_L2;
1365}
1366
1367/**
1368 * i40e_rx_hash - set the hash value in the skb
1369 * @ring: descriptor ring
1370 * @rx_desc: specific descriptor
1371 **/
1372static inline void i40e_rx_hash(struct i40e_ring *ring,
1373 union i40e_rx_desc *rx_desc,
1374 struct sk_buff *skb,
1375 u8 rx_ptype)
1376{
1377 u32 hash;
1378 const __le64 rss_mask =
1379 cpu_to_le64((u64)I40E_RX_DESC_FLTSTAT_RSS_HASH <<
1380 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT);
1381
1382 if (!(ring->netdev->features & NETIF_F_RXHASH))
1383 return;
1384
1385 if ((rx_desc->wb.qword1.status_error_len & rss_mask) == rss_mask) {
1386 hash = le32_to_cpu(rx_desc->wb.qword0.hi_dword.rss);
1387 skb_set_hash(skb, hash, i40e_ptype_to_htype(rx_ptype));
1388 }
1389}
1390
1391/**
1392 * i40e_process_skb_fields - Populate skb header fields from Rx descriptor
1393 * @rx_ring: rx descriptor ring packet is being transacted on
1394 * @rx_desc: pointer to the EOP Rx descriptor
1395 * @skb: pointer to current skb being populated
1396 * @rx_ptype: the packet type decoded by hardware
1397 *
1398 * This function checks the ring, descriptor, and packet information in
1399 * order to populate the hash, checksum, VLAN, protocol, and
1400 * other fields within the skb.
1401 **/
1402static inline
1403void i40e_process_skb_fields(struct i40e_ring *rx_ring,
1404 union i40e_rx_desc *rx_desc, struct sk_buff *skb,
1405 u8 rx_ptype)
1406{
1407 u64 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1408 u32 rx_status = (qword & I40E_RXD_QW1_STATUS_MASK) >>
1409 I40E_RXD_QW1_STATUS_SHIFT;
1410 u32 tsynvalid = rx_status & I40E_RXD_QW1_STATUS_TSYNVALID_MASK;
1411 u32 tsyn = (rx_status & I40E_RXD_QW1_STATUS_TSYNINDX_MASK) >>
1412 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT;
1413
1414 if (unlikely(tsynvalid))
1415 i40e_ptp_rx_hwtstamp(rx_ring->vsi->back, skb, tsyn);
1416
1417 i40e_rx_hash(rx_ring, rx_desc, skb, rx_ptype);
1418
1419 /* modifies the skb - consumes the enet header */
1420 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1421
1422 i40e_rx_checksum(rx_ring->vsi, skb, rx_desc);
1423
1424 skb_record_rx_queue(skb, rx_ring->queue_index);
1425}
1426
1427/**
1428 * i40e_pull_tail - i40e specific version of skb_pull_tail
1429 * @rx_ring: rx descriptor ring packet is being transacted on
1430 * @skb: pointer to current skb being adjusted
1431 *
1432 * This function is an i40e specific version of __pskb_pull_tail. The
1433 * main difference between this version and the original function is that
1434 * this function can make several assumptions about the state of things
1435 * that allow for significant optimizations versus the standard function.
1436 * As a result we can do things like drop a frag and maintain an accurate
1437 * truesize for the skb.
1438 */
1439static void i40e_pull_tail(struct i40e_ring *rx_ring, struct sk_buff *skb)
1440{
1441 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[0];
1442 unsigned char *va;
1443 unsigned int pull_len;
1444
1445 /* it is valid to use page_address instead of kmap since we are
1446 * working with pages allocated out of the lomem pool per
1447 * alloc_page(GFP_ATOMIC)
1448 */
1449 va = skb_frag_address(frag);
1450
1451 /* we need the header to contain the greater of either ETH_HLEN or
1452 * 60 bytes if the skb->len is less than 60 for skb_pad.
1453 */
1454 pull_len = eth_get_headlen(va, I40E_RX_HDR_SIZE);
1455
1456 /* align pull length to size of long to optimize memcpy performance */
1457 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1458
1459 /* update all of the pointers */
1460 skb_frag_size_sub(frag, pull_len);
1461 frag->page_offset += pull_len;
1462 skb->data_len -= pull_len;
1463 skb->tail += pull_len;
1464}
1465
1466/**
1467 * i40e_cleanup_headers - Correct empty headers
1468 * @rx_ring: rx descriptor ring packet is being transacted on
1469 * @skb: pointer to current skb being fixed
1470 *
1471 * Also address the case where we are pulling data in on pages only
1472 * and as such no data is present in the skb header.
1473 *
1474 * In addition if skb is not at least 60 bytes we need to pad it so that
1475 * it is large enough to qualify as a valid Ethernet frame.
1476 *
1477 * Returns true if an error was encountered and skb was freed.
1478 **/
1479static bool i40e_cleanup_headers(struct i40e_ring *rx_ring, struct sk_buff *skb)
1480{
1481 /* place header in linear portion of buffer */
1482 if (skb_is_nonlinear(skb))
1483 i40e_pull_tail(rx_ring, skb);
1484
1485 /* if eth_skb_pad returns an error the skb was freed */
1486 if (eth_skb_pad(skb))
1487 return true;
1488
1489 return false;
1490}
1491
1492/**
1493 * i40e_reuse_rx_page - page flip buffer and store it back on the ring
1494 * @rx_ring: rx descriptor ring to store buffers on
1495 * @old_buff: donor buffer to have page reused
1496 *
1497 * Synchronizes page for reuse by the adapter
1498 **/
1499static void i40e_reuse_rx_page(struct i40e_ring *rx_ring,
1500 struct i40e_rx_buffer *old_buff)
1501{
1502 struct i40e_rx_buffer *new_buff;
1503 u16 nta = rx_ring->next_to_alloc;
1504
1505 new_buff = &rx_ring->rx_bi[nta];
1506
1507 /* update, and store next to alloc */
1508 nta++;
1509 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1510
1511 /* transfer page from old buffer to new buffer */
1512 *new_buff = *old_buff;
1513}
1514
1515/**
1516 * i40e_page_is_reserved - check if reuse is possible
1517 * @page: page struct to check
1518 */
1519static inline bool i40e_page_is_reserved(struct page *page)
1520{
1521 return (page_to_nid(page) != numa_mem_id()) || page_is_pfmemalloc(page);
1522}
1523
1524/**
1525 * i40e_add_rx_frag - Add contents of Rx buffer to sk_buff
1526 * @rx_ring: rx descriptor ring to transact packets on
1527 * @rx_buffer: buffer containing page to add
1528 * @rx_desc: descriptor containing length of buffer written by hardware
1529 * @skb: sk_buff to place the data into
1530 *
1531 * This function will add the data contained in rx_buffer->page to the skb.
1532 * This is done either through a direct copy if the data in the buffer is
1533 * less than the skb header size, otherwise it will just attach the page as
1534 * a frag to the skb.
1535 *
1536 * The function will then update the page offset if necessary and return
1537 * true if the buffer can be reused by the adapter.
1538 **/
1539static bool i40e_add_rx_frag(struct i40e_ring *rx_ring,
1540 struct i40e_rx_buffer *rx_buffer,
1541 union i40e_rx_desc *rx_desc,
1542 struct sk_buff *skb)
1543{
1544 struct page *page = rx_buffer->page;
1545 u64 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1546 unsigned int size = (qword & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1547 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1548#if (PAGE_SIZE < 8192)
1549 unsigned int truesize = I40E_RXBUFFER_2048;
1550#else
1551 unsigned int truesize = ALIGN(size, L1_CACHE_BYTES);
1552 unsigned int last_offset = PAGE_SIZE - I40E_RXBUFFER_2048;
1553#endif
1554
1555 /* will the data fit in the skb we allocated? if so, just
1556 * copy it as it is pretty small anyway
1557 */
1558 if ((size <= I40E_RX_HDR_SIZE) && !skb_is_nonlinear(skb)) {
1559 unsigned char *va = page_address(page) + rx_buffer->page_offset;
1560
1561 memcpy(__skb_put(skb, size), va, ALIGN(size, sizeof(long)));
1562
1563 /* page is not reserved, we can reuse buffer as-is */
1564 if (likely(!i40e_page_is_reserved(page)))
1565 return true;
1566
1567 /* this page cannot be reused so discard it */
1568 __free_pages(page, 0);
1569 return false;
1570 }
1571
1572 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, page,
1573 rx_buffer->page_offset, size, truesize);
1574
1575 /* avoid re-using remote pages */
1576 if (unlikely(i40e_page_is_reserved(page)))
1577 return false;
1578
1579#if (PAGE_SIZE < 8192)
1580 /* if we are only owner of page we can reuse it */
1581 if (unlikely(page_count(page) != 1))
1582 return false;
1583
1584 /* flip page offset to other buffer */
1585 rx_buffer->page_offset ^= truesize;
1586#else
1587 /* move offset up to the next cache line */
1588 rx_buffer->page_offset += truesize;
1589
1590 if (rx_buffer->page_offset > last_offset)
1591 return false;
1592#endif
1593
1594 /* Even if we own the page, we are not allowed to use atomic_set()
1595 * This would break get_page_unless_zero() users.
1596 */
1597 get_page(rx_buffer->page);
1598
1599 return true;
1600}
1601
1602/**
1603 * i40e_fetch_rx_buffer - Allocate skb and populate it
1604 * @rx_ring: rx descriptor ring to transact packets on
1605 * @rx_desc: descriptor containing info written by hardware
1606 *
1607 * This function allocates an skb on the fly, and populates it with the page
1608 * data from the current receive descriptor, taking care to set up the skb
1609 * correctly, as well as handling calling the page recycle function if
1610 * necessary.
1611 */
1612static inline
1613struct sk_buff *i40e_fetch_rx_buffer(struct i40e_ring *rx_ring,
1614 union i40e_rx_desc *rx_desc)
1615{
1616 struct i40e_rx_buffer *rx_buffer;
1617 struct sk_buff *skb;
1618 struct page *page;
1619
1620 rx_buffer = &rx_ring->rx_bi[rx_ring->next_to_clean];
1621 page = rx_buffer->page;
1622 prefetchw(page);
1623
1624 skb = rx_buffer->skb;
1625
1626 if (likely(!skb)) {
1627 void *page_addr = page_address(page) + rx_buffer->page_offset;
1628
1629 /* prefetch first cache line of first page */
1630 prefetch(page_addr);
1631#if L1_CACHE_BYTES < 128
1632 prefetch(page_addr + L1_CACHE_BYTES);
1633#endif
1634
1635 /* allocate a skb to store the frags */
1636 skb = __napi_alloc_skb(&rx_ring->q_vector->napi,
1637 I40E_RX_HDR_SIZE,
1638 GFP_ATOMIC | __GFP_NOWARN);
1639 if (unlikely(!skb)) {
1640 rx_ring->rx_stats.alloc_buff_failed++;
1641 return NULL;
1642 }
1643
1644 /* we will be copying header into skb->data in
1645 * pskb_may_pull so it is in our interest to prefetch
1646 * it now to avoid a possible cache miss
1647 */
1648 prefetchw(skb->data);
1649 } else {
1650 rx_buffer->skb = NULL;
1651 }
1652
1653 /* we are reusing so sync this buffer for CPU use */
1654 dma_sync_single_range_for_cpu(rx_ring->dev,
1655 rx_buffer->dma,
1656 rx_buffer->page_offset,
1657 I40E_RXBUFFER_2048,
1658 DMA_FROM_DEVICE);
1659
1660 /* pull page into skb */
1661 if (i40e_add_rx_frag(rx_ring, rx_buffer, rx_desc, skb)) {
1662 /* hand second half of page back to the ring */
1663 i40e_reuse_rx_page(rx_ring, rx_buffer);
1664 rx_ring->rx_stats.page_reuse_count++;
1665 } else {
1666 /* we are not reusing the buffer so unmap it */
1667 dma_unmap_page(rx_ring->dev, rx_buffer->dma, PAGE_SIZE,
1668 DMA_FROM_DEVICE);
1669 }
1670
1671 /* clear contents of buffer_info */
1672 rx_buffer->page = NULL;
1673
1674 return skb;
1675}
1676
1677/**
1678 * i40e_is_non_eop - process handling of non-EOP buffers
1679 * @rx_ring: Rx ring being processed
1680 * @rx_desc: Rx descriptor for current buffer
1681 * @skb: Current socket buffer containing buffer in progress
1682 *
1683 * This function updates next to clean. If the buffer is an EOP buffer
1684 * this function exits returning false, otherwise it will place the
1685 * sk_buff in the next buffer to be chained and return true indicating
1686 * that this is in fact a non-EOP buffer.
1687 **/
1688static bool i40e_is_non_eop(struct i40e_ring *rx_ring,
1689 union i40e_rx_desc *rx_desc,
1690 struct sk_buff *skb)
1691{
1692 u32 ntc = rx_ring->next_to_clean + 1;
1693
1694 /* fetch, update, and store next to clean */
1695 ntc = (ntc < rx_ring->count) ? ntc : 0;
1696 rx_ring->next_to_clean = ntc;
1697
1698 prefetch(I40E_RX_DESC(rx_ring, ntc));
1699
1700#define staterrlen rx_desc->wb.qword1.status_error_len
1701 if (unlikely(i40e_rx_is_programming_status(le64_to_cpu(staterrlen)))) {
1702 i40e_clean_programming_status(rx_ring, rx_desc);
1703 rx_ring->rx_bi[ntc].skb = skb;
1704 return true;
1705 }
1706 /* if we are the last buffer then there is nothing else to do */
1707#define I40E_RXD_EOF BIT(I40E_RX_DESC_STATUS_EOF_SHIFT)
1708 if (likely(i40e_test_staterr(rx_desc, I40E_RXD_EOF)))
1709 return false;
1710
1711 /* place skb in next buffer to be received */
1712 rx_ring->rx_bi[ntc].skb = skb;
1713 rx_ring->rx_stats.non_eop_descs++;
1714
1715 return true;
1716}
1717
1718/**
1719 * i40e_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
1720 * @rx_ring: rx descriptor ring to transact packets on
1721 * @budget: Total limit on number of packets to process
1722 *
1723 * This function provides a "bounce buffer" approach to Rx interrupt
1724 * processing. The advantage to this is that on systems that have
1725 * expensive overhead for IOMMU access this provides a means of avoiding
1726 * it by maintaining the mapping of the page to the system.
1727 *
1728 * Returns amount of work completed
1729 **/
1730static int i40e_clean_rx_irq(struct i40e_ring *rx_ring, int budget)
1731{
1732 unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1733 u16 cleaned_count = I40E_DESC_UNUSED(rx_ring);
1734 bool failure = false;
1735
1736 while (likely(total_rx_packets < budget)) {
1737 union i40e_rx_desc *rx_desc;
1738 struct sk_buff *skb;
1739 u16 vlan_tag;
1740 u8 rx_ptype;
1741 u64 qword;
1742
1743 /* return some buffers to hardware, one at a time is too slow */
1744 if (cleaned_count >= I40E_RX_BUFFER_WRITE) {
1745 failure = failure ||
1746 i40e_alloc_rx_buffers(rx_ring, cleaned_count);
1747 cleaned_count = 0;
1748 }
1749
1750 rx_desc = I40E_RX_DESC(rx_ring, rx_ring->next_to_clean);
1751
1752 /* status_error_len will always be zero for unused descriptors
1753 * because it's cleared in cleanup, and overlaps with hdr_addr
1754 * which is always zero because packet split isn't used, if the
1755 * hardware wrote DD then it will be non-zero
1756 */
1757 if (!i40e_test_staterr(rx_desc,
1758 BIT(I40E_RX_DESC_STATUS_DD_SHIFT)))
1759 break;
1760
1761 /* This memory barrier is needed to keep us from reading
1762 * any other fields out of the rx_desc until we know the
1763 * DD bit is set.
1764 */
1765 dma_rmb();
1766
1767 skb = i40e_fetch_rx_buffer(rx_ring, rx_desc);
1768 if (!skb)
1769 break;
1770
1771 cleaned_count++;
1772
1773 if (i40e_is_non_eop(rx_ring, rx_desc, skb))
1774 continue;
1775
1776 /* ERR_MASK will only have valid bits if EOP set, and
1777 * what we are doing here is actually checking
1778 * I40E_RX_DESC_ERROR_RXE_SHIFT, since it is the zeroth bit in
1779 * the error field
1780 */
1781 if (unlikely(i40e_test_staterr(rx_desc, BIT(I40E_RXD_QW1_ERROR_SHIFT)))) {
1782 dev_kfree_skb_any(skb);
1783 continue;
1784 }
1785
1786 if (i40e_cleanup_headers(rx_ring, skb))
1787 continue;
1788
1789 /* probably a little skewed due to removing CRC */
1790 total_rx_bytes += skb->len;
1791
1792 qword = le64_to_cpu(rx_desc->wb.qword1.status_error_len);
1793 rx_ptype = (qword & I40E_RXD_QW1_PTYPE_MASK) >>
1794 I40E_RXD_QW1_PTYPE_SHIFT;
1795
1796 /* populate checksum, VLAN, and protocol */
1797 i40e_process_skb_fields(rx_ring, rx_desc, skb, rx_ptype);
1798
1799#ifdef I40E_FCOE
1800 if (unlikely(
1801 i40e_rx_is_fcoe(rx_ptype) &&
1802 !i40e_fcoe_handle_offload(rx_ring, rx_desc, skb))) {
1803 dev_kfree_skb_any(skb);
1804 continue;
1805 }
1806#endif
1807
1808 vlan_tag = (qword & BIT(I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) ?
1809 le16_to_cpu(rx_desc->wb.qword0.lo_dword.l2tag1) : 0;
1810
1811 i40e_receive_skb(rx_ring, skb, vlan_tag);
1812
1813 /* update budget accounting */
1814 total_rx_packets++;
1815 }
1816
1817 u64_stats_update_begin(&rx_ring->syncp);
1818 rx_ring->stats.packets += total_rx_packets;
1819 rx_ring->stats.bytes += total_rx_bytes;
1820 u64_stats_update_end(&rx_ring->syncp);
1821 rx_ring->q_vector->rx.total_packets += total_rx_packets;
1822 rx_ring->q_vector->rx.total_bytes += total_rx_bytes;
1823
1824 /* guarantee a trip back through this routine if there was a failure */
1825 return failure ? budget : total_rx_packets;
1826}
1827
1828static u32 i40e_buildreg_itr(const int type, const u16 itr)
1829{
1830 u32 val;
1831
1832 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1833 /* Don't clear PBA because that can cause lost interrupts that
1834 * came in while we were cleaning/polling
1835 */
1836 (type << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
1837 (itr << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT);
1838
1839 return val;
1840}
1841
1842/* a small macro to shorten up some long lines */
1843#define INTREG I40E_PFINT_DYN_CTLN
1844static inline int get_rx_itr_enabled(struct i40e_vsi *vsi, int idx)
1845{
1846 return !!(vsi->rx_rings[idx]->rx_itr_setting);
1847}
1848
1849static inline int get_tx_itr_enabled(struct i40e_vsi *vsi, int idx)
1850{
1851 return !!(vsi->tx_rings[idx]->tx_itr_setting);
1852}
1853
1854/**
1855 * i40e_update_enable_itr - Update itr and re-enable MSIX interrupt
1856 * @vsi: the VSI we care about
1857 * @q_vector: q_vector for which itr is being updated and interrupt enabled
1858 *
1859 **/
1860static inline void i40e_update_enable_itr(struct i40e_vsi *vsi,
1861 struct i40e_q_vector *q_vector)
1862{
1863 struct i40e_hw *hw = &vsi->back->hw;
1864 bool rx = false, tx = false;
1865 u32 rxval, txval;
1866 int vector;
1867 int idx = q_vector->v_idx;
1868 int rx_itr_setting, tx_itr_setting;
1869
1870 vector = (q_vector->v_idx + vsi->base_vector);
1871
1872 /* avoid dynamic calculation if in countdown mode OR if
1873 * all dynamic is disabled
1874 */
1875 rxval = txval = i40e_buildreg_itr(I40E_ITR_NONE, 0);
1876
1877 rx_itr_setting = get_rx_itr_enabled(vsi, idx);
1878 tx_itr_setting = get_tx_itr_enabled(vsi, idx);
1879
1880 if (q_vector->itr_countdown > 0 ||
1881 (!ITR_IS_DYNAMIC(rx_itr_setting) &&
1882 !ITR_IS_DYNAMIC(tx_itr_setting))) {
1883 goto enable_int;
1884 }
1885
1886 if (ITR_IS_DYNAMIC(tx_itr_setting)) {
1887 rx = i40e_set_new_dynamic_itr(&q_vector->rx);
1888 rxval = i40e_buildreg_itr(I40E_RX_ITR, q_vector->rx.itr);
1889 }
1890
1891 if (ITR_IS_DYNAMIC(tx_itr_setting)) {
1892 tx = i40e_set_new_dynamic_itr(&q_vector->tx);
1893 txval = i40e_buildreg_itr(I40E_TX_ITR, q_vector->tx.itr);
1894 }
1895
1896 if (rx || tx) {
1897 /* get the higher of the two ITR adjustments and
1898 * use the same value for both ITR registers
1899 * when in adaptive mode (Rx and/or Tx)
1900 */
1901 u16 itr = max(q_vector->tx.itr, q_vector->rx.itr);
1902
1903 q_vector->tx.itr = q_vector->rx.itr = itr;
1904 txval = i40e_buildreg_itr(I40E_TX_ITR, itr);
1905 tx = true;
1906 rxval = i40e_buildreg_itr(I40E_RX_ITR, itr);
1907 rx = true;
1908 }
1909
1910 /* only need to enable the interrupt once, but need
1911 * to possibly update both ITR values
1912 */
1913 if (rx) {
1914 /* set the INTENA_MSK_MASK so that this first write
1915 * won't actually enable the interrupt, instead just
1916 * updating the ITR (it's bit 31 PF and VF)
1917 */
1918 rxval |= BIT(31);
1919 /* don't check _DOWN because interrupt isn't being enabled */
1920 wr32(hw, INTREG(vector - 1), rxval);
1921 }
1922
1923enable_int:
1924 if (!test_bit(__I40E_DOWN, &vsi->state))
1925 wr32(hw, INTREG(vector - 1), txval);
1926
1927 if (q_vector->itr_countdown)
1928 q_vector->itr_countdown--;
1929 else
1930 q_vector->itr_countdown = ITR_COUNTDOWN_START;
1931}
1932
1933/**
1934 * i40e_napi_poll - NAPI polling Rx/Tx cleanup routine
1935 * @napi: napi struct with our devices info in it
1936 * @budget: amount of work driver is allowed to do this pass, in packets
1937 *
1938 * This function will clean all queues associated with a q_vector.
1939 *
1940 * Returns the amount of work done
1941 **/
1942int i40e_napi_poll(struct napi_struct *napi, int budget)
1943{
1944 struct i40e_q_vector *q_vector =
1945 container_of(napi, struct i40e_q_vector, napi);
1946 struct i40e_vsi *vsi = q_vector->vsi;
1947 struct i40e_ring *ring;
1948 bool clean_complete = true;
1949 bool arm_wb = false;
1950 int budget_per_ring;
1951 int work_done = 0;
1952
1953 if (test_bit(__I40E_DOWN, &vsi->state)) {
1954 napi_complete(napi);
1955 return 0;
1956 }
1957
1958 /* Clear hung_detected bit */
1959 clear_bit(I40E_Q_VECTOR_HUNG_DETECT, &q_vector->hung_detected);
1960 /* Since the actual Tx work is minimal, we can give the Tx a larger
1961 * budget and be more aggressive about cleaning up the Tx descriptors.
1962 */
1963 i40e_for_each_ring(ring, q_vector->tx) {
1964 if (!i40e_clean_tx_irq(vsi, ring, budget)) {
1965 clean_complete = false;
1966 continue;
1967 }
1968 arm_wb |= ring->arm_wb;
1969 ring->arm_wb = false;
1970 }
1971
1972 /* Handle case where we are called by netpoll with a budget of 0 */
1973 if (budget <= 0)
1974 goto tx_only;
1975
1976 /* We attempt to distribute budget to each Rx queue fairly, but don't
1977 * allow the budget to go below 1 because that would exit polling early.
1978 */
1979 budget_per_ring = max(budget/q_vector->num_ringpairs, 1);
1980
1981 i40e_for_each_ring(ring, q_vector->rx) {
1982 int cleaned = i40e_clean_rx_irq(ring, budget_per_ring);
1983
1984 work_done += cleaned;
1985 /* if we clean as many as budgeted, we must not be done */
1986 if (cleaned >= budget_per_ring)
1987 clean_complete = false;
1988 }
1989
1990 /* If work not completed, return budget and polling will return */
1991 if (!clean_complete) {
1992 const cpumask_t *aff_mask = &q_vector->affinity_mask;
1993 int cpu_id = smp_processor_id();
1994
1995 /* It is possible that the interrupt affinity has changed but,
1996 * if the cpu is pegged at 100%, polling will never exit while
1997 * traffic continues and the interrupt will be stuck on this
1998 * cpu. We check to make sure affinity is correct before we
1999 * continue to poll, otherwise we must stop polling so the
2000 * interrupt can move to the correct cpu.
2001 */
2002 if (likely(cpumask_test_cpu(cpu_id, aff_mask) ||
2003 !(vsi->back->flags & I40E_FLAG_MSIX_ENABLED))) {
2004tx_only:
2005 if (arm_wb) {
2006 q_vector->tx.ring[0].tx_stats.tx_force_wb++;
2007 i40e_enable_wb_on_itr(vsi, q_vector);
2008 }
2009 return budget;
2010 }
2011 }
2012
2013 if (vsi->back->flags & I40E_TXR_FLAGS_WB_ON_ITR)
2014 q_vector->arm_wb_state = false;
2015
2016 /* Work is done so exit the polling mode and re-enable the interrupt */
2017 napi_complete_done(napi, work_done);
2018
2019 /* If we're prematurely stopping polling to fix the interrupt
2020 * affinity we want to make sure polling starts back up so we
2021 * issue a call to i40e_force_wb which triggers a SW interrupt.
2022 */
2023 if (!clean_complete)
2024 i40e_force_wb(vsi, q_vector);
2025 else if (!(vsi->back->flags & I40E_FLAG_MSIX_ENABLED))
2026 i40e_irq_dynamic_enable_icr0(vsi->back, false);
2027 else
2028 i40e_update_enable_itr(vsi, q_vector);
2029
2030 return min(work_done, budget - 1);
2031}
2032
2033/**
2034 * i40e_atr - Add a Flow Director ATR filter
2035 * @tx_ring: ring to add programming descriptor to
2036 * @skb: send buffer
2037 * @tx_flags: send tx flags
2038 **/
2039static void i40e_atr(struct i40e_ring *tx_ring, struct sk_buff *skb,
2040 u32 tx_flags)
2041{
2042 struct i40e_filter_program_desc *fdir_desc;
2043 struct i40e_pf *pf = tx_ring->vsi->back;
2044 union {
2045 unsigned char *network;
2046 struct iphdr *ipv4;
2047 struct ipv6hdr *ipv6;
2048 } hdr;
2049 struct tcphdr *th;
2050 unsigned int hlen;
2051 u32 flex_ptype, dtype_cmd;
2052 int l4_proto;
2053 u16 i;
2054
2055 /* make sure ATR is enabled */
2056 if (!(pf->flags & I40E_FLAG_FD_ATR_ENABLED))
2057 return;
2058
2059 if ((pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
2060 return;
2061
2062 /* if sampling is disabled do nothing */
2063 if (!tx_ring->atr_sample_rate)
2064 return;
2065
2066 /* Currently only IPv4/IPv6 with TCP is supported */
2067 if (!(tx_flags & (I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6)))
2068 return;
2069
2070 /* snag network header to get L4 type and address */
2071 hdr.network = (tx_flags & I40E_TX_FLAGS_UDP_TUNNEL) ?
2072 skb_inner_network_header(skb) : skb_network_header(skb);
2073
2074 /* Note: tx_flags gets modified to reflect inner protocols in
2075 * tx_enable_csum function if encap is enabled.
2076 */
2077 if (tx_flags & I40E_TX_FLAGS_IPV4) {
2078 /* access ihl as u8 to avoid unaligned access on ia64 */
2079 hlen = (hdr.network[0] & 0x0F) << 2;
2080 l4_proto = hdr.ipv4->protocol;
2081 } else {
2082 hlen = hdr.network - skb->data;
2083 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL);
2084 hlen -= hdr.network - skb->data;
2085 }
2086
2087 if (l4_proto != IPPROTO_TCP)
2088 return;
2089
2090 th = (struct tcphdr *)(hdr.network + hlen);
2091
2092 /* Due to lack of space, no more new filters can be programmed */
2093 if (th->syn && (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
2094 return;
2095 if ((pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE) &&
2096 (!(pf->auto_disable_flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE))) {
2097 /* HW ATR eviction will take care of removing filters on FIN
2098 * and RST packets.
2099 */
2100 if (th->fin || th->rst)
2101 return;
2102 }
2103
2104 tx_ring->atr_count++;
2105
2106 /* sample on all syn/fin/rst packets or once every atr sample rate */
2107 if (!th->fin &&
2108 !th->syn &&
2109 !th->rst &&
2110 (tx_ring->atr_count < tx_ring->atr_sample_rate))
2111 return;
2112
2113 tx_ring->atr_count = 0;
2114
2115 /* grab the next descriptor */
2116 i = tx_ring->next_to_use;
2117 fdir_desc = I40E_TX_FDIRDESC(tx_ring, i);
2118
2119 i++;
2120 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
2121
2122 flex_ptype = (tx_ring->queue_index << I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
2123 I40E_TXD_FLTR_QW0_QINDEX_MASK;
2124 flex_ptype |= (tx_flags & I40E_TX_FLAGS_IPV4) ?
2125 (I40E_FILTER_PCTYPE_NONF_IPV4_TCP <<
2126 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) :
2127 (I40E_FILTER_PCTYPE_NONF_IPV6_TCP <<
2128 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT);
2129
2130 flex_ptype |= tx_ring->vsi->id << I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT;
2131
2132 dtype_cmd = I40E_TX_DESC_DTYPE_FILTER_PROG;
2133
2134 dtype_cmd |= (th->fin || th->rst) ?
2135 (I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
2136 I40E_TXD_FLTR_QW1_PCMD_SHIFT) :
2137 (I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
2138 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
2139
2140 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX <<
2141 I40E_TXD_FLTR_QW1_DEST_SHIFT;
2142
2143 dtype_cmd |= I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID <<
2144 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT;
2145
2146 dtype_cmd |= I40E_TXD_FLTR_QW1_CNT_ENA_MASK;
2147 if (!(tx_flags & I40E_TX_FLAGS_UDP_TUNNEL))
2148 dtype_cmd |=
2149 ((u32)I40E_FD_ATR_STAT_IDX(pf->hw.pf_id) <<
2150 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2151 I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
2152 else
2153 dtype_cmd |=
2154 ((u32)I40E_FD_ATR_TUNNEL_STAT_IDX(pf->hw.pf_id) <<
2155 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
2156 I40E_TXD_FLTR_QW1_CNTINDEX_MASK;
2157
2158 if ((pf->flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE) &&
2159 (!(pf->auto_disable_flags & I40E_FLAG_HW_ATR_EVICT_CAPABLE)))
2160 dtype_cmd |= I40E_TXD_FLTR_QW1_ATR_MASK;
2161
2162 fdir_desc->qindex_flex_ptype_vsi = cpu_to_le32(flex_ptype);
2163 fdir_desc->rsvd = cpu_to_le32(0);
2164 fdir_desc->dtype_cmd_cntindex = cpu_to_le32(dtype_cmd);
2165 fdir_desc->fd_id = cpu_to_le32(0);
2166}
2167
2168/**
2169 * i40e_tx_prepare_vlan_flags - prepare generic TX VLAN tagging flags for HW
2170 * @skb: send buffer
2171 * @tx_ring: ring to send buffer on
2172 * @flags: the tx flags to be set
2173 *
2174 * Checks the skb and set up correspondingly several generic transmit flags
2175 * related to VLAN tagging for the HW, such as VLAN, DCB, etc.
2176 *
2177 * Returns error code indicate the frame should be dropped upon error and the
2178 * otherwise returns 0 to indicate the flags has been set properly.
2179 **/
2180#ifdef I40E_FCOE
2181inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
2182 struct i40e_ring *tx_ring,
2183 u32 *flags)
2184#else
2185static inline int i40e_tx_prepare_vlan_flags(struct sk_buff *skb,
2186 struct i40e_ring *tx_ring,
2187 u32 *flags)
2188#endif
2189{
2190 __be16 protocol = skb->protocol;
2191 u32 tx_flags = 0;
2192
2193 if (protocol == htons(ETH_P_8021Q) &&
2194 !(tx_ring->netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
2195 /* When HW VLAN acceleration is turned off by the user the
2196 * stack sets the protocol to 8021q so that the driver
2197 * can take any steps required to support the SW only
2198 * VLAN handling. In our case the driver doesn't need
2199 * to take any further steps so just set the protocol
2200 * to the encapsulated ethertype.
2201 */
2202 skb->protocol = vlan_get_protocol(skb);
2203 goto out;
2204 }
2205
2206 /* if we have a HW VLAN tag being added, default to the HW one */
2207 if (skb_vlan_tag_present(skb)) {
2208 tx_flags |= skb_vlan_tag_get(skb) << I40E_TX_FLAGS_VLAN_SHIFT;
2209 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
2210 /* else if it is a SW VLAN, check the next protocol and store the tag */
2211 } else if (protocol == htons(ETH_P_8021Q)) {
2212 struct vlan_hdr *vhdr, _vhdr;
2213
2214 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
2215 if (!vhdr)
2216 return -EINVAL;
2217
2218 protocol = vhdr->h_vlan_encapsulated_proto;
2219 tx_flags |= ntohs(vhdr->h_vlan_TCI) << I40E_TX_FLAGS_VLAN_SHIFT;
2220 tx_flags |= I40E_TX_FLAGS_SW_VLAN;
2221 }
2222
2223 if (!(tx_ring->vsi->back->flags & I40E_FLAG_DCB_ENABLED))
2224 goto out;
2225
2226 /* Insert 802.1p priority into VLAN header */
2227 if ((tx_flags & (I40E_TX_FLAGS_HW_VLAN | I40E_TX_FLAGS_SW_VLAN)) ||
2228 (skb->priority != TC_PRIO_CONTROL)) {
2229 tx_flags &= ~I40E_TX_FLAGS_VLAN_PRIO_MASK;
2230 tx_flags |= (skb->priority & 0x7) <<
2231 I40E_TX_FLAGS_VLAN_PRIO_SHIFT;
2232 if (tx_flags & I40E_TX_FLAGS_SW_VLAN) {
2233 struct vlan_ethhdr *vhdr;
2234 int rc;
2235
2236 rc = skb_cow_head(skb, 0);
2237 if (rc < 0)
2238 return rc;
2239 vhdr = (struct vlan_ethhdr *)skb->data;
2240 vhdr->h_vlan_TCI = htons(tx_flags >>
2241 I40E_TX_FLAGS_VLAN_SHIFT);
2242 } else {
2243 tx_flags |= I40E_TX_FLAGS_HW_VLAN;
2244 }
2245 }
2246
2247out:
2248 *flags = tx_flags;
2249 return 0;
2250}
2251
2252/**
2253 * i40e_tso - set up the tso context descriptor
2254 * @skb: ptr to the skb we're sending
2255 * @hdr_len: ptr to the size of the packet header
2256 * @cd_type_cmd_tso_mss: Quad Word 1
2257 *
2258 * Returns 0 if no TSO can happen, 1 if tso is going, or error
2259 **/
2260static int i40e_tso(struct sk_buff *skb, u8 *hdr_len, u64 *cd_type_cmd_tso_mss)
2261{
2262 u64 cd_cmd, cd_tso_len, cd_mss;
2263 union {
2264 struct iphdr *v4;
2265 struct ipv6hdr *v6;
2266 unsigned char *hdr;
2267 } ip;
2268 union {
2269 struct tcphdr *tcp;
2270 struct udphdr *udp;
2271 unsigned char *hdr;
2272 } l4;
2273 u32 paylen, l4_offset;
2274 int err;
2275
2276 if (skb->ip_summed != CHECKSUM_PARTIAL)
2277 return 0;
2278
2279 if (!skb_is_gso(skb))
2280 return 0;
2281
2282 err = skb_cow_head(skb, 0);
2283 if (err < 0)
2284 return err;
2285
2286 ip.hdr = skb_network_header(skb);
2287 l4.hdr = skb_transport_header(skb);
2288
2289 /* initialize outer IP header fields */
2290 if (ip.v4->version == 4) {
2291 ip.v4->tot_len = 0;
2292 ip.v4->check = 0;
2293 } else {
2294 ip.v6->payload_len = 0;
2295 }
2296
2297 if (skb_shinfo(skb)->gso_type & (SKB_GSO_GRE |
2298 SKB_GSO_GRE_CSUM |
2299 SKB_GSO_IPXIP4 |
2300 SKB_GSO_IPXIP6 |
2301 SKB_GSO_UDP_TUNNEL |
2302 SKB_GSO_UDP_TUNNEL_CSUM)) {
2303 if (!(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
2304 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM)) {
2305 l4.udp->len = 0;
2306
2307 /* determine offset of outer transport header */
2308 l4_offset = l4.hdr - skb->data;
2309
2310 /* remove payload length from outer checksum */
2311 paylen = skb->len - l4_offset;
2312 csum_replace_by_diff(&l4.udp->check, htonl(paylen));
2313 }
2314
2315 /* reset pointers to inner headers */
2316 ip.hdr = skb_inner_network_header(skb);
2317 l4.hdr = skb_inner_transport_header(skb);
2318
2319 /* initialize inner IP header fields */
2320 if (ip.v4->version == 4) {
2321 ip.v4->tot_len = 0;
2322 ip.v4->check = 0;
2323 } else {
2324 ip.v6->payload_len = 0;
2325 }
2326 }
2327
2328 /* determine offset of inner transport header */
2329 l4_offset = l4.hdr - skb->data;
2330
2331 /* remove payload length from inner checksum */
2332 paylen = skb->len - l4_offset;
2333 csum_replace_by_diff(&l4.tcp->check, htonl(paylen));
2334
2335 /* compute length of segmentation header */
2336 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
2337
2338 /* find the field values */
2339 cd_cmd = I40E_TX_CTX_DESC_TSO;
2340 cd_tso_len = skb->len - *hdr_len;
2341 cd_mss = skb_shinfo(skb)->gso_size;
2342 *cd_type_cmd_tso_mss |= (cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
2343 (cd_tso_len << I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
2344 (cd_mss << I40E_TXD_CTX_QW1_MSS_SHIFT);
2345 return 1;
2346}
2347
2348/**
2349 * i40e_tsyn - set up the tsyn context descriptor
2350 * @tx_ring: ptr to the ring to send
2351 * @skb: ptr to the skb we're sending
2352 * @tx_flags: the collected send information
2353 * @cd_type_cmd_tso_mss: Quad Word 1
2354 *
2355 * Returns 0 if no Tx timestamp can happen and 1 if the timestamp will happen
2356 **/
2357static int i40e_tsyn(struct i40e_ring *tx_ring, struct sk_buff *skb,
2358 u32 tx_flags, u64 *cd_type_cmd_tso_mss)
2359{
2360 struct i40e_pf *pf;
2361
2362 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)))
2363 return 0;
2364
2365 /* Tx timestamps cannot be sampled when doing TSO */
2366 if (tx_flags & I40E_TX_FLAGS_TSO)
2367 return 0;
2368
2369 /* only timestamp the outbound packet if the user has requested it and
2370 * we are not already transmitting a packet to be timestamped
2371 */
2372 pf = i40e_netdev_to_pf(tx_ring->netdev);
2373 if (!(pf->flags & I40E_FLAG_PTP))
2374 return 0;
2375
2376 if (pf->ptp_tx &&
2377 !test_and_set_bit_lock(__I40E_PTP_TX_IN_PROGRESS, &pf->state)) {
2378 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2379 pf->ptp_tx_skb = skb_get(skb);
2380 } else {
2381 return 0;
2382 }
2383
2384 *cd_type_cmd_tso_mss |= (u64)I40E_TX_CTX_DESC_TSYN <<
2385 I40E_TXD_CTX_QW1_CMD_SHIFT;
2386
2387 return 1;
2388}
2389
2390/**
2391 * i40e_tx_enable_csum - Enable Tx checksum offloads
2392 * @skb: send buffer
2393 * @tx_flags: pointer to Tx flags currently set
2394 * @td_cmd: Tx descriptor command bits to set
2395 * @td_offset: Tx descriptor header offsets to set
2396 * @tx_ring: Tx descriptor ring
2397 * @cd_tunneling: ptr to context desc bits
2398 **/
2399static int i40e_tx_enable_csum(struct sk_buff *skb, u32 *tx_flags,
2400 u32 *td_cmd, u32 *td_offset,
2401 struct i40e_ring *tx_ring,
2402 u32 *cd_tunneling)
2403{
2404 union {
2405 struct iphdr *v4;
2406 struct ipv6hdr *v6;
2407 unsigned char *hdr;
2408 } ip;
2409 union {
2410 struct tcphdr *tcp;
2411 struct udphdr *udp;
2412 unsigned char *hdr;
2413 } l4;
2414 unsigned char *exthdr;
2415 u32 offset, cmd = 0;
2416 __be16 frag_off;
2417 u8 l4_proto = 0;
2418
2419 if (skb->ip_summed != CHECKSUM_PARTIAL)
2420 return 0;
2421
2422 ip.hdr = skb_network_header(skb);
2423 l4.hdr = skb_transport_header(skb);
2424
2425 /* compute outer L2 header size */
2426 offset = ((ip.hdr - skb->data) / 2) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
2427
2428 if (skb->encapsulation) {
2429 u32 tunnel = 0;
2430 /* define outer network header type */
2431 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
2432 tunnel |= (*tx_flags & I40E_TX_FLAGS_TSO) ?
2433 I40E_TX_CTX_EXT_IP_IPV4 :
2434 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
2435
2436 l4_proto = ip.v4->protocol;
2437 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
2438 tunnel |= I40E_TX_CTX_EXT_IP_IPV6;
2439
2440 exthdr = ip.hdr + sizeof(*ip.v6);
2441 l4_proto = ip.v6->nexthdr;
2442 if (l4.hdr != exthdr)
2443 ipv6_skip_exthdr(skb, exthdr - skb->data,
2444 &l4_proto, &frag_off);
2445 }
2446
2447 /* define outer transport */
2448 switch (l4_proto) {
2449 case IPPROTO_UDP:
2450 tunnel |= I40E_TXD_CTX_UDP_TUNNELING;
2451 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
2452 break;
2453 case IPPROTO_GRE:
2454 tunnel |= I40E_TXD_CTX_GRE_TUNNELING;
2455 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
2456 break;
2457 case IPPROTO_IPIP:
2458 case IPPROTO_IPV6:
2459 *tx_flags |= I40E_TX_FLAGS_UDP_TUNNEL;
2460 l4.hdr = skb_inner_network_header(skb);
2461 break;
2462 default:
2463 if (*tx_flags & I40E_TX_FLAGS_TSO)
2464 return -1;
2465
2466 skb_checksum_help(skb);
2467 return 0;
2468 }
2469
2470 /* compute outer L3 header size */
2471 tunnel |= ((l4.hdr - ip.hdr) / 4) <<
2472 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
2473
2474 /* switch IP header pointer from outer to inner header */
2475 ip.hdr = skb_inner_network_header(skb);
2476
2477 /* compute tunnel header size */
2478 tunnel |= ((ip.hdr - l4.hdr) / 2) <<
2479 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
2480
2481 /* indicate if we need to offload outer UDP header */
2482 if ((*tx_flags & I40E_TX_FLAGS_TSO) &&
2483 !(skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) &&
2484 (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_TUNNEL_CSUM))
2485 tunnel |= I40E_TXD_CTX_QW0_L4T_CS_MASK;
2486
2487 /* record tunnel offload values */
2488 *cd_tunneling |= tunnel;
2489
2490 /* switch L4 header pointer from outer to inner */
2491 l4.hdr = skb_inner_transport_header(skb);
2492 l4_proto = 0;
2493
2494 /* reset type as we transition from outer to inner headers */
2495 *tx_flags &= ~(I40E_TX_FLAGS_IPV4 | I40E_TX_FLAGS_IPV6);
2496 if (ip.v4->version == 4)
2497 *tx_flags |= I40E_TX_FLAGS_IPV4;
2498 if (ip.v6->version == 6)
2499 *tx_flags |= I40E_TX_FLAGS_IPV6;
2500 }
2501
2502 /* Enable IP checksum offloads */
2503 if (*tx_flags & I40E_TX_FLAGS_IPV4) {
2504 l4_proto = ip.v4->protocol;
2505 /* the stack computes the IP header already, the only time we
2506 * need the hardware to recompute it is in the case of TSO.
2507 */
2508 cmd |= (*tx_flags & I40E_TX_FLAGS_TSO) ?
2509 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM :
2510 I40E_TX_DESC_CMD_IIPT_IPV4;
2511 } else if (*tx_flags & I40E_TX_FLAGS_IPV6) {
2512 cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
2513
2514 exthdr = ip.hdr + sizeof(*ip.v6);
2515 l4_proto = ip.v6->nexthdr;
2516 if (l4.hdr != exthdr)
2517 ipv6_skip_exthdr(skb, exthdr - skb->data,
2518 &l4_proto, &frag_off);
2519 }
2520
2521 /* compute inner L3 header size */
2522 offset |= ((l4.hdr - ip.hdr) / 4) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
2523
2524 /* Enable L4 checksum offloads */
2525 switch (l4_proto) {
2526 case IPPROTO_TCP:
2527 /* enable checksum offloads */
2528 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
2529 offset |= l4.tcp->doff << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2530 break;
2531 case IPPROTO_SCTP:
2532 /* enable SCTP checksum offload */
2533 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
2534 offset |= (sizeof(struct sctphdr) >> 2) <<
2535 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2536 break;
2537 case IPPROTO_UDP:
2538 /* enable UDP checksum offload */
2539 cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
2540 offset |= (sizeof(struct udphdr) >> 2) <<
2541 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
2542 break;
2543 default:
2544 if (*tx_flags & I40E_TX_FLAGS_TSO)
2545 return -1;
2546 skb_checksum_help(skb);
2547 return 0;
2548 }
2549
2550 *td_cmd |= cmd;
2551 *td_offset |= offset;
2552
2553 return 1;
2554}
2555
2556/**
2557 * i40e_create_tx_ctx Build the Tx context descriptor
2558 * @tx_ring: ring to create the descriptor on
2559 * @cd_type_cmd_tso_mss: Quad Word 1
2560 * @cd_tunneling: Quad Word 0 - bits 0-31
2561 * @cd_l2tag2: Quad Word 0 - bits 32-63
2562 **/
2563static void i40e_create_tx_ctx(struct i40e_ring *tx_ring,
2564 const u64 cd_type_cmd_tso_mss,
2565 const u32 cd_tunneling, const u32 cd_l2tag2)
2566{
2567 struct i40e_tx_context_desc *context_desc;
2568 int i = tx_ring->next_to_use;
2569
2570 if ((cd_type_cmd_tso_mss == I40E_TX_DESC_DTYPE_CONTEXT) &&
2571 !cd_tunneling && !cd_l2tag2)
2572 return;
2573
2574 /* grab the next descriptor */
2575 context_desc = I40E_TX_CTXTDESC(tx_ring, i);
2576
2577 i++;
2578 tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;
2579
2580 /* cpu_to_le32 and assign to struct fields */
2581 context_desc->tunneling_params = cpu_to_le32(cd_tunneling);
2582 context_desc->l2tag2 = cpu_to_le16(cd_l2tag2);
2583 context_desc->rsvd = cpu_to_le16(0);
2584 context_desc->type_cmd_tso_mss = cpu_to_le64(cd_type_cmd_tso_mss);
2585}
2586
2587/**
2588 * __i40e_maybe_stop_tx - 2nd level check for tx stop conditions
2589 * @tx_ring: the ring to be checked
2590 * @size: the size buffer we want to assure is available
2591 *
2592 * Returns -EBUSY if a stop is needed, else 0
2593 **/
2594int __i40e_maybe_stop_tx(struct i40e_ring *tx_ring, int size)
2595{
2596 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
2597 /* Memory barrier before checking head and tail */
2598 smp_mb();
2599
2600 /* Check again in a case another CPU has just made room available. */
2601 if (likely(I40E_DESC_UNUSED(tx_ring) < size))
2602 return -EBUSY;
2603
2604 /* A reprieve! - use start_queue because it doesn't call schedule */
2605 netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
2606 ++tx_ring->tx_stats.restart_queue;
2607 return 0;
2608}
2609
2610/**
2611 * __i40e_chk_linearize - Check if there are more than 8 buffers per packet
2612 * @skb: send buffer
2613 *
2614 * Note: Our HW can't DMA more than 8 buffers to build a packet on the wire
2615 * and so we need to figure out the cases where we need to linearize the skb.
2616 *
2617 * For TSO we need to count the TSO header and segment payload separately.
2618 * As such we need to check cases where we have 7 fragments or more as we
2619 * can potentially require 9 DMA transactions, 1 for the TSO header, 1 for
2620 * the segment payload in the first descriptor, and another 7 for the
2621 * fragments.
2622 **/
2623bool __i40e_chk_linearize(struct sk_buff *skb)
2624{
2625 const struct skb_frag_struct *frag, *stale;
2626 int nr_frags, sum;
2627
2628 /* no need to check if number of frags is less than 7 */
2629 nr_frags = skb_shinfo(skb)->nr_frags;
2630 if (nr_frags < (I40E_MAX_BUFFER_TXD - 1))
2631 return false;
2632
2633 /* We need to walk through the list and validate that each group
2634 * of 6 fragments totals at least gso_size.
2635 */
2636 nr_frags -= I40E_MAX_BUFFER_TXD - 2;
2637 frag = &skb_shinfo(skb)->frags[0];
2638
2639 /* Initialize size to the negative value of gso_size minus 1. We
2640 * use this as the worst case scenerio in which the frag ahead
2641 * of us only provides one byte which is why we are limited to 6
2642 * descriptors for a single transmit as the header and previous
2643 * fragment are already consuming 2 descriptors.
2644 */
2645 sum = 1 - skb_shinfo(skb)->gso_size;
2646
2647 /* Add size of frags 0 through 4 to create our initial sum */
2648 sum += skb_frag_size(frag++);
2649 sum += skb_frag_size(frag++);
2650 sum += skb_frag_size(frag++);
2651 sum += skb_frag_size(frag++);
2652 sum += skb_frag_size(frag++);
2653
2654 /* Walk through fragments adding latest fragment, testing it, and
2655 * then removing stale fragments from the sum.
2656 */
2657 stale = &skb_shinfo(skb)->frags[0];
2658 for (;;) {
2659 sum += skb_frag_size(frag++);
2660
2661 /* if sum is negative we failed to make sufficient progress */
2662 if (sum < 0)
2663 return true;
2664
2665 if (!nr_frags--)
2666 break;
2667
2668 sum -= skb_frag_size(stale++);
2669 }
2670
2671 return false;
2672}
2673
2674/**
2675 * i40e_tx_map - Build the Tx descriptor
2676 * @tx_ring: ring to send buffer on
2677 * @skb: send buffer
2678 * @first: first buffer info buffer to use
2679 * @tx_flags: collected send information
2680 * @hdr_len: size of the packet header
2681 * @td_cmd: the command field in the descriptor
2682 * @td_offset: offset for checksum or crc
2683 **/
2684#ifdef I40E_FCOE
2685inline void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
2686 struct i40e_tx_buffer *first, u32 tx_flags,
2687 const u8 hdr_len, u32 td_cmd, u32 td_offset)
2688#else
2689static inline void i40e_tx_map(struct i40e_ring *tx_ring, struct sk_buff *skb,
2690 struct i40e_tx_buffer *first, u32 tx_flags,
2691 const u8 hdr_len, u32 td_cmd, u32 td_offset)
2692#endif
2693{
2694 unsigned int data_len = skb->data_len;
2695 unsigned int size = skb_headlen(skb);
2696 struct skb_frag_struct *frag;
2697 struct i40e_tx_buffer *tx_bi;
2698 struct i40e_tx_desc *tx_desc;
2699 u16 i = tx_ring->next_to_use;
2700 u32 td_tag = 0;
2701 dma_addr_t dma;
2702 u16 gso_segs;
2703 u16 desc_count = 1;
2704
2705 if (tx_flags & I40E_TX_FLAGS_HW_VLAN) {
2706 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
2707 td_tag = (tx_flags & I40E_TX_FLAGS_VLAN_MASK) >>
2708 I40E_TX_FLAGS_VLAN_SHIFT;
2709 }
2710
2711 if (tx_flags & (I40E_TX_FLAGS_TSO | I40E_TX_FLAGS_FSO))
2712 gso_segs = skb_shinfo(skb)->gso_segs;
2713 else
2714 gso_segs = 1;
2715
2716 /* multiply data chunks by size of headers */
2717 first->bytecount = skb->len - hdr_len + (gso_segs * hdr_len);
2718 first->gso_segs = gso_segs;
2719 first->skb = skb;
2720 first->tx_flags = tx_flags;
2721
2722 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
2723
2724 tx_desc = I40E_TX_DESC(tx_ring, i);
2725 tx_bi = first;
2726
2727 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
2728 unsigned int max_data = I40E_MAX_DATA_PER_TXD_ALIGNED;
2729
2730 if (dma_mapping_error(tx_ring->dev, dma))
2731 goto dma_error;
2732
2733 /* record length, and DMA address */
2734 dma_unmap_len_set(tx_bi, len, size);
2735 dma_unmap_addr_set(tx_bi, dma, dma);
2736
2737 /* align size to end of page */
2738 max_data += -dma & (I40E_MAX_READ_REQ_SIZE - 1);
2739 tx_desc->buffer_addr = cpu_to_le64(dma);
2740
2741 while (unlikely(size > I40E_MAX_DATA_PER_TXD)) {
2742 tx_desc->cmd_type_offset_bsz =
2743 build_ctob(td_cmd, td_offset,
2744 max_data, td_tag);
2745
2746 tx_desc++;
2747 i++;
2748 desc_count++;
2749
2750 if (i == tx_ring->count) {
2751 tx_desc = I40E_TX_DESC(tx_ring, 0);
2752 i = 0;
2753 }
2754
2755 dma += max_data;
2756 size -= max_data;
2757
2758 max_data = I40E_MAX_DATA_PER_TXD_ALIGNED;
2759 tx_desc->buffer_addr = cpu_to_le64(dma);
2760 }
2761
2762 if (likely(!data_len))
2763 break;
2764
2765 tx_desc->cmd_type_offset_bsz = build_ctob(td_cmd, td_offset,
2766 size, td_tag);
2767
2768 tx_desc++;
2769 i++;
2770 desc_count++;
2771
2772 if (i == tx_ring->count) {
2773 tx_desc = I40E_TX_DESC(tx_ring, 0);
2774 i = 0;
2775 }
2776
2777 size = skb_frag_size(frag);
2778 data_len -= size;
2779
2780 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
2781 DMA_TO_DEVICE);
2782
2783 tx_bi = &tx_ring->tx_bi[i];
2784 }
2785
2786 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
2787
2788 i++;
2789 if (i == tx_ring->count)
2790 i = 0;
2791
2792 tx_ring->next_to_use = i;
2793
2794 i40e_maybe_stop_tx(tx_ring, DESC_NEEDED);
2795
2796 /* write last descriptor with EOP bit */
2797 td_cmd |= I40E_TX_DESC_CMD_EOP;
2798
2799 /* We can OR these values together as they both are checked against
2800 * 4 below and at this point desc_count will be used as a boolean value
2801 * after this if/else block.
2802 */
2803 desc_count |= ++tx_ring->packet_stride;
2804
2805 /* Algorithm to optimize tail and RS bit setting:
2806 * if queue is stopped
2807 * mark RS bit
2808 * reset packet counter
2809 * else if xmit_more is supported and is true
2810 * advance packet counter to 4
2811 * reset desc_count to 0
2812 *
2813 * if desc_count >= 4
2814 * mark RS bit
2815 * reset packet counter
2816 * if desc_count > 0
2817 * update tail
2818 *
2819 * Note: If there are less than 4 descriptors
2820 * pending and interrupts were disabled the service task will
2821 * trigger a force WB.
2822 */
2823 if (netif_xmit_stopped(txring_txq(tx_ring))) {
2824 goto do_rs;
2825 } else if (skb->xmit_more) {
2826 /* set stride to arm on next packet and reset desc_count */
2827 tx_ring->packet_stride = WB_STRIDE;
2828 desc_count = 0;
2829 } else if (desc_count >= WB_STRIDE) {
2830do_rs:
2831 /* write last descriptor with RS bit set */
2832 td_cmd |= I40E_TX_DESC_CMD_RS;
2833 tx_ring->packet_stride = 0;
2834 }
2835
2836 tx_desc->cmd_type_offset_bsz =
2837 build_ctob(td_cmd, td_offset, size, td_tag);
2838
2839 /* Force memory writes to complete before letting h/w know there
2840 * are new descriptors to fetch.
2841 *
2842 * We also use this memory barrier to make certain all of the
2843 * status bits have been updated before next_to_watch is written.
2844 */
2845 wmb();
2846
2847 /* set next_to_watch value indicating a packet is present */
2848 first->next_to_watch = tx_desc;
2849
2850 /* notify HW of packet */
2851 if (desc_count) {
2852 writel(i, tx_ring->tail);
2853
2854 /* we need this if more than one processor can write to our tail
2855 * at a time, it synchronizes IO on IA64/Altix systems
2856 */
2857 mmiowb();
2858 }
2859
2860 return;
2861
2862dma_error:
2863 dev_info(tx_ring->dev, "TX DMA map failed\n");
2864
2865 /* clear dma mappings for failed tx_bi map */
2866 for (;;) {
2867 tx_bi = &tx_ring->tx_bi[i];
2868 i40e_unmap_and_free_tx_resource(tx_ring, tx_bi);
2869 if (tx_bi == first)
2870 break;
2871 if (i == 0)
2872 i = tx_ring->count;
2873 i--;
2874 }
2875
2876 tx_ring->next_to_use = i;
2877}
2878
2879/**
2880 * i40e_xmit_frame_ring - Sends buffer on Tx ring
2881 * @skb: send buffer
2882 * @tx_ring: ring to send buffer on
2883 *
2884 * Returns NETDEV_TX_OK if sent, else an error code
2885 **/
2886static netdev_tx_t i40e_xmit_frame_ring(struct sk_buff *skb,
2887 struct i40e_ring *tx_ring)
2888{
2889 u64 cd_type_cmd_tso_mss = I40E_TX_DESC_DTYPE_CONTEXT;
2890 u32 cd_tunneling = 0, cd_l2tag2 = 0;
2891 struct i40e_tx_buffer *first;
2892 u32 td_offset = 0;
2893 u32 tx_flags = 0;
2894 __be16 protocol;
2895 u32 td_cmd = 0;
2896 u8 hdr_len = 0;
2897 int tso, count;
2898 int tsyn;
2899
2900 /* prefetch the data, we'll need it later */
2901 prefetch(skb->data);
2902
2903 count = i40e_xmit_descriptor_count(skb);
2904 if (i40e_chk_linearize(skb, count)) {
2905 if (__skb_linearize(skb))
2906 goto out_drop;
2907 count = i40e_txd_use_count(skb->len);
2908 tx_ring->tx_stats.tx_linearize++;
2909 }
2910
2911 /* need: 1 descriptor per page * PAGE_SIZE/I40E_MAX_DATA_PER_TXD,
2912 * + 1 desc for skb_head_len/I40E_MAX_DATA_PER_TXD,
2913 * + 4 desc gap to avoid the cache line where head is,
2914 * + 1 desc for context descriptor,
2915 * otherwise try next time
2916 */
2917 if (i40e_maybe_stop_tx(tx_ring, count + 4 + 1)) {
2918 tx_ring->tx_stats.tx_busy++;
2919 return NETDEV_TX_BUSY;
2920 }
2921
2922 /* prepare the xmit flags */
2923 if (i40e_tx_prepare_vlan_flags(skb, tx_ring, &tx_flags))
2924 goto out_drop;
2925
2926 /* obtain protocol of skb */
2927 protocol = vlan_get_protocol(skb);
2928
2929 /* record the location of the first descriptor for this packet */
2930 first = &tx_ring->tx_bi[tx_ring->next_to_use];
2931
2932 /* setup IPv4/IPv6 offloads */
2933 if (protocol == htons(ETH_P_IP))
2934 tx_flags |= I40E_TX_FLAGS_IPV4;
2935 else if (protocol == htons(ETH_P_IPV6))
2936 tx_flags |= I40E_TX_FLAGS_IPV6;
2937
2938 tso = i40e_tso(skb, &hdr_len, &cd_type_cmd_tso_mss);
2939
2940 if (tso < 0)
2941 goto out_drop;
2942 else if (tso)
2943 tx_flags |= I40E_TX_FLAGS_TSO;
2944
2945 /* Always offload the checksum, since it's in the data descriptor */
2946 tso = i40e_tx_enable_csum(skb, &tx_flags, &td_cmd, &td_offset,
2947 tx_ring, &cd_tunneling);
2948 if (tso < 0)
2949 goto out_drop;
2950
2951 tsyn = i40e_tsyn(tx_ring, skb, tx_flags, &cd_type_cmd_tso_mss);
2952
2953 if (tsyn)
2954 tx_flags |= I40E_TX_FLAGS_TSYN;
2955
2956 skb_tx_timestamp(skb);
2957
2958 /* always enable CRC insertion offload */
2959 td_cmd |= I40E_TX_DESC_CMD_ICRC;
2960
2961 i40e_create_tx_ctx(tx_ring, cd_type_cmd_tso_mss,
2962 cd_tunneling, cd_l2tag2);
2963
2964 /* Add Flow Director ATR if it's enabled.
2965 *
2966 * NOTE: this must always be directly before the data descriptor.
2967 */
2968 i40e_atr(tx_ring, skb, tx_flags);
2969
2970 i40e_tx_map(tx_ring, skb, first, tx_flags, hdr_len,
2971 td_cmd, td_offset);
2972
2973 return NETDEV_TX_OK;
2974
2975out_drop:
2976 dev_kfree_skb_any(skb);
2977 return NETDEV_TX_OK;
2978}
2979
2980/**
2981 * i40e_lan_xmit_frame - Selects the correct VSI and Tx queue to send buffer
2982 * @skb: send buffer
2983 * @netdev: network interface device structure
2984 *
2985 * Returns NETDEV_TX_OK if sent, else an error code
2986 **/
2987netdev_tx_t i40e_lan_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
2988{
2989 struct i40e_netdev_priv *np = netdev_priv(netdev);
2990 struct i40e_vsi *vsi = np->vsi;
2991 struct i40e_ring *tx_ring = vsi->tx_rings[skb->queue_mapping];
2992
2993 /* hardware can't handle really short frames, hardware padding works
2994 * beyond this point
2995 */
2996 if (skb_put_padto(skb, I40E_MIN_TX_LEN))
2997 return NETDEV_TX_OK;
2998
2999 return i40e_xmit_frame_ring(skb, tx_ring);
3000}