1// SPDX-License-Identifier: GPL-2.0
   2/* Copyright(c) 2013 - 2019 Intel Corporation. */
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
   3
   4#include "fm10k_pf.h"
   5#include "fm10k_vf.h"
   6
   7/**
   8 *  fm10k_reset_hw_pf - PF hardware reset
   9 *  @hw: pointer to hardware structure
  10 *
  11 *  This function should return the hardware to a state similar to the
  12 *  one it is in after being powered on.
  13 **/
  14static s32 fm10k_reset_hw_pf(struct fm10k_hw *hw)
  15{
  16	s32 err;
  17	u32 reg;
  18	u16 i;
  19
  20	/* Disable interrupts */
  21	fm10k_write_reg(hw, FM10K_EIMR, FM10K_EIMR_DISABLE(ALL));
  22
  23	/* Lock ITR2 reg 0 into itself and disable interrupt moderation */
  24	fm10k_write_reg(hw, FM10K_ITR2(0), 0);
  25	fm10k_write_reg(hw, FM10K_INT_CTRL, 0);
  26
  27	/* We assume here Tx and Rx queue 0 are owned by the PF */
  28
  29	/* Shut off VF access to their queues forcing them to queue 0 */
  30	for (i = 0; i < FM10K_TQMAP_TABLE_SIZE; i++) {
  31		fm10k_write_reg(hw, FM10K_TQMAP(i), 0);
  32		fm10k_write_reg(hw, FM10K_RQMAP(i), 0);
  33	}
  34
  35	/* shut down all rings */
  36	err = fm10k_disable_queues_generic(hw, FM10K_MAX_QUEUES);
  37	if (err == FM10K_ERR_REQUESTS_PENDING) {
  38		hw->mac.reset_while_pending++;
  39		goto force_reset;
  40	} else if (err) {
  41		return err;
  42	}
  43
  44	/* Verify that DMA is no longer active */
  45	reg = fm10k_read_reg(hw, FM10K_DMA_CTRL);
  46	if (reg & (FM10K_DMA_CTRL_TX_ACTIVE | FM10K_DMA_CTRL_RX_ACTIVE))
  47		return FM10K_ERR_DMA_PENDING;
  48
  49force_reset:
  50	/* Inititate data path reset */
  51	reg = FM10K_DMA_CTRL_DATAPATH_RESET;
  52	fm10k_write_reg(hw, FM10K_DMA_CTRL, reg);
  53
  54	/* Flush write and allow 100us for reset to complete */
  55	fm10k_write_flush(hw);
  56	udelay(FM10K_RESET_TIMEOUT);
  57
 
 
 
 
  58	/* Verify we made it out of reset */
  59	reg = fm10k_read_reg(hw, FM10K_IP);
  60	if (!(reg & FM10K_IP_NOTINRESET))
  61		return FM10K_ERR_RESET_FAILED;
  62
  63	return 0;
  64}
  65
  66/**
  67 *  fm10k_is_ari_hierarchy_pf - Indicate ARI hierarchy support
  68 *  @hw: pointer to hardware structure
  69 *
  70 *  Looks at the ARI hierarchy bit to determine whether ARI is supported or not.
  71 **/
  72static bool fm10k_is_ari_hierarchy_pf(struct fm10k_hw *hw)
  73{
  74	u16 sriov_ctrl = fm10k_read_pci_cfg_word(hw, FM10K_PCIE_SRIOV_CTRL);
  75
  76	return !!(sriov_ctrl & FM10K_PCIE_SRIOV_CTRL_VFARI);
  77}
  78
  79/**
  80 *  fm10k_init_hw_pf - PF hardware initialization
  81 *  @hw: pointer to hardware structure
  82 *
  83 **/
  84static s32 fm10k_init_hw_pf(struct fm10k_hw *hw)
  85{
  86	u32 dma_ctrl, txqctl;
  87	u16 i;
  88
  89	/* Establish default VSI as valid */
  90	fm10k_write_reg(hw, FM10K_DGLORTDEC(fm10k_dglort_default), 0);
  91	fm10k_write_reg(hw, FM10K_DGLORTMAP(fm10k_dglort_default),
  92			FM10K_DGLORTMAP_ANY);
  93
  94	/* Invalidate all other GLORT entries */
  95	for (i = 1; i < FM10K_DGLORT_COUNT; i++)
  96		fm10k_write_reg(hw, FM10K_DGLORTMAP(i), FM10K_DGLORTMAP_NONE);
  97
  98	/* reset ITR2(0) to point to itself */
  99	fm10k_write_reg(hw, FM10K_ITR2(0), 0);
 100
 101	/* reset VF ITR2(0) to point to 0 avoid PF registers */
 102	fm10k_write_reg(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), 0);
 103
 104	/* loop through all PF ITR2 registers pointing them to the previous */
 105	for (i = 1; i < FM10K_ITR_REG_COUNT_PF; i++)
 106		fm10k_write_reg(hw, FM10K_ITR2(i), i - 1);
 107
 108	/* Enable interrupt moderator if not already enabled */
 109	fm10k_write_reg(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR);
 110
 111	/* compute the default txqctl configuration */
 112	txqctl = FM10K_TXQCTL_PF | FM10K_TXQCTL_UNLIMITED_BW |
 113		 (hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT);
 114
 115	for (i = 0; i < FM10K_MAX_QUEUES; i++) {
 116		/* configure rings for 256 Queue / 32 Descriptor cache mode */
 117		fm10k_write_reg(hw, FM10K_TQDLOC(i),
 118				(i * FM10K_TQDLOC_BASE_32_DESC) |
 119				FM10K_TQDLOC_SIZE_32_DESC);
 120		fm10k_write_reg(hw, FM10K_TXQCTL(i), txqctl);
 121
 122		/* configure rings to provide TPH processing hints */
 123		fm10k_write_reg(hw, FM10K_TPH_TXCTRL(i),
 124				FM10K_TPH_TXCTRL_DESC_TPHEN |
 125				FM10K_TPH_TXCTRL_DESC_RROEN |
 126				FM10K_TPH_TXCTRL_DESC_WROEN |
 127				FM10K_TPH_TXCTRL_DATA_RROEN);
 128		fm10k_write_reg(hw, FM10K_TPH_RXCTRL(i),
 129				FM10K_TPH_RXCTRL_DESC_TPHEN |
 130				FM10K_TPH_RXCTRL_DESC_RROEN |
 131				FM10K_TPH_RXCTRL_DATA_WROEN |
 132				FM10K_TPH_RXCTRL_HDR_WROEN);
 133	}
 134
 135	/* set max hold interval to align with 1.024 usec in all modes and
 136	 * store ITR scale
 137	 */
 138	switch (hw->bus.speed) {
 139	case fm10k_bus_speed_2500:
 140		dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1;
 141		hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN1;
 142		break;
 143	case fm10k_bus_speed_5000:
 144		dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2;
 145		hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN2;
 146		break;
 147	case fm10k_bus_speed_8000:
 148		dma_ctrl = FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3;
 149		hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN3;
 150		break;
 151	default:
 152		dma_ctrl = 0;
 153		/* just in case, assume Gen3 ITR scale */
 154		hw->mac.itr_scale = FM10K_TDLEN_ITR_SCALE_GEN3;
 155		break;
 156	}
 157
 158	/* Configure TSO flags */
 159	fm10k_write_reg(hw, FM10K_DTXTCPFLGL, FM10K_TSO_FLAGS_LOW);
 160	fm10k_write_reg(hw, FM10K_DTXTCPFLGH, FM10K_TSO_FLAGS_HI);
 161
 162	/* Enable DMA engine
 163	 * Set Rx Descriptor size to 32
 164	 * Set Minimum MSS to 64
 165	 * Set Maximum number of Rx queues to 256 / 32 Descriptor
 166	 */
 167	dma_ctrl |= FM10K_DMA_CTRL_TX_ENABLE | FM10K_DMA_CTRL_RX_ENABLE |
 168		    FM10K_DMA_CTRL_RX_DESC_SIZE | FM10K_DMA_CTRL_MINMSS_64 |
 169		    FM10K_DMA_CTRL_32_DESC;
 170
 171	fm10k_write_reg(hw, FM10K_DMA_CTRL, dma_ctrl);
 172
 173	/* record maximum queue count, we limit ourselves to 128 */
 174	hw->mac.max_queues = FM10K_MAX_QUEUES_PF;
 175
 176	/* We support either 64 VFs or 7 VFs depending on if we have ARI */
 177	hw->iov.total_vfs = fm10k_is_ari_hierarchy_pf(hw) ? 64 : 7;
 178
 179	return 0;
 180}
 181
 182/**
 183 *  fm10k_update_vlan_pf - Update status of VLAN ID in VLAN filter table
 184 *  @hw: pointer to hardware structure
 185 *  @vid: VLAN ID to add to table
 186 *  @vsi: Index indicating VF ID or PF ID in table
 187 *  @set: Indicates if this is a set or clear operation
 188 *
 189 *  This function adds or removes the corresponding VLAN ID from the VLAN
 190 *  filter table for the corresponding function.  In addition to the
 191 *  standard set/clear that supports one bit a multi-bit write is
 192 *  supported to set 64 bits at a time.
 193 **/
 194static s32 fm10k_update_vlan_pf(struct fm10k_hw *hw, u32 vid, u8 vsi, bool set)
 195{
 196	u32 vlan_table, reg, mask, bit, len;
 197
 198	/* verify the VSI index is valid */
 199	if (vsi > FM10K_VLAN_TABLE_VSI_MAX)
 200		return FM10K_ERR_PARAM;
 201
 202	/* VLAN multi-bit write:
 203	 * The multi-bit write has several parts to it.
 204	 *               24              16               8               0
 205	 *  7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
 206	 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 207	 * | RSVD0 |         Length        |C|RSVD0|        VLAN ID        |
 208	 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 209	 *
 210	 * VLAN ID: Vlan Starting value
 211	 * RSVD0: Reserved section, must be 0
 212	 * C: Flag field, 0 is set, 1 is clear (Used in VF VLAN message)
 213	 * Length: Number of times to repeat the bit being set
 214	 */
 215	len = vid >> 16;
 216	vid = (vid << 17) >> 17;
 217
 218	/* verify the reserved 0 fields are 0 */
 219	if (len >= FM10K_VLAN_TABLE_VID_MAX || vid >= FM10K_VLAN_TABLE_VID_MAX)
 220		return FM10K_ERR_PARAM;
 221
 222	/* Loop through the table updating all required VLANs */
 223	for (reg = FM10K_VLAN_TABLE(vsi, vid / 32), bit = vid % 32;
 224	     len < FM10K_VLAN_TABLE_VID_MAX;
 225	     len -= 32 - bit, reg++, bit = 0) {
 226		/* record the initial state of the register */
 227		vlan_table = fm10k_read_reg(hw, reg);
 228
 229		/* truncate mask if we are at the start or end of the run */
 230		mask = (~(u32)0 >> ((len < 31) ? 31 - len : 0)) << bit;
 231
 232		/* make necessary modifications to the register */
 233		mask &= set ? ~vlan_table : vlan_table;
 234		if (mask)
 235			fm10k_write_reg(hw, reg, vlan_table ^ mask);
 236	}
 237
 238	return 0;
 239}
 240
 241/**
 242 *  fm10k_read_mac_addr_pf - Read device MAC address
 243 *  @hw: pointer to the HW structure
 244 *
 245 *  Reads the device MAC address from the SM_AREA and stores the value.
 246 **/
 247static s32 fm10k_read_mac_addr_pf(struct fm10k_hw *hw)
 248{
 249	u8 perm_addr[ETH_ALEN];
 250	u32 serial_num;
 251
 252	serial_num = fm10k_read_reg(hw, FM10K_SM_AREA(1));
 253
 254	/* last byte should be all 1's */
 255	if ((~serial_num) << 24)
 256		return  FM10K_ERR_INVALID_MAC_ADDR;
 257
 258	perm_addr[0] = (u8)(serial_num >> 24);
 259	perm_addr[1] = (u8)(serial_num >> 16);
 260	perm_addr[2] = (u8)(serial_num >> 8);
 261
 262	serial_num = fm10k_read_reg(hw, FM10K_SM_AREA(0));
 263
 264	/* first byte should be all 1's */
 265	if ((~serial_num) >> 24)
 266		return  FM10K_ERR_INVALID_MAC_ADDR;
 267
 268	perm_addr[3] = (u8)(serial_num >> 16);
 269	perm_addr[4] = (u8)(serial_num >> 8);
 270	perm_addr[5] = (u8)(serial_num);
 271
 272	ether_addr_copy(hw->mac.perm_addr, perm_addr);
 273	ether_addr_copy(hw->mac.addr, perm_addr);
 274
 275	return 0;
 276}
 277
 278/**
 279 *  fm10k_glort_valid_pf - Validate that the provided glort is valid
 280 *  @hw: pointer to the HW structure
 281 *  @glort: base glort to be validated
 282 *
 283 *  This function will return an error if the provided glort is invalid
 284 **/
 285bool fm10k_glort_valid_pf(struct fm10k_hw *hw, u16 glort)
 286{
 287	glort &= hw->mac.dglort_map >> FM10K_DGLORTMAP_MASK_SHIFT;
 288
 289	return glort == (hw->mac.dglort_map & FM10K_DGLORTMAP_NONE);
 290}
 291
 292/**
 293 *  fm10k_update_xc_addr_pf - Update device addresses
 294 *  @hw: pointer to the HW structure
 295 *  @glort: base resource tag for this request
 296 *  @mac: MAC address to add/remove from table
 297 *  @vid: VLAN ID to add/remove from table
 298 *  @add: Indicates if this is an add or remove operation
 299 *  @flags: flags field to indicate add and secure
 300 *
 301 *  This function generates a message to the Switch API requesting
 302 *  that the given logical port add/remove the given L2 MAC/VLAN address.
 303 **/
 304static s32 fm10k_update_xc_addr_pf(struct fm10k_hw *hw, u16 glort,
 305				   const u8 *mac, u16 vid, bool add, u8 flags)
 306{
 307	struct fm10k_mbx_info *mbx = &hw->mbx;
 308	struct fm10k_mac_update mac_update;
 309	u32 msg[5];
 310
 311	/* clear set bit from VLAN ID */
 312	vid &= ~FM10K_VLAN_CLEAR;
 313
 314	/* if glort or VLAN are not valid return error */
 315	if (!fm10k_glort_valid_pf(hw, glort) || vid >= FM10K_VLAN_TABLE_VID_MAX)
 316		return FM10K_ERR_PARAM;
 317
 318	/* record fields */
 319	mac_update.mac_lower = cpu_to_le32(((u32)mac[2] << 24) |
 320						 ((u32)mac[3] << 16) |
 321						 ((u32)mac[4] << 8) |
 322						 ((u32)mac[5]));
 323	mac_update.mac_upper = cpu_to_le16(((u16)mac[0] << 8) |
 324					   ((u16)mac[1]));
 325	mac_update.vlan = cpu_to_le16(vid);
 326	mac_update.glort = cpu_to_le16(glort);
 327	mac_update.action = add ? 0 : 1;
 328	mac_update.flags = flags;
 329
 330	/* populate mac_update fields */
 331	fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_UPDATE_MAC_FWD_RULE);
 332	fm10k_tlv_attr_put_le_struct(msg, FM10K_PF_ATTR_ID_MAC_UPDATE,
 333				     &mac_update, sizeof(mac_update));
 334
 335	/* load onto outgoing mailbox */
 336	return mbx->ops.enqueue_tx(hw, mbx, msg);
 337}
 338
 339/**
 340 *  fm10k_update_uc_addr_pf - Update device unicast addresses
 341 *  @hw: pointer to the HW structure
 342 *  @glort: base resource tag for this request
 343 *  @mac: MAC address to add/remove from table
 344 *  @vid: VLAN ID to add/remove from table
 345 *  @add: Indicates if this is an add or remove operation
 346 *  @flags: flags field to indicate add and secure
 347 *
 348 *  This function is used to add or remove unicast addresses for
 349 *  the PF.
 350 **/
 351static s32 fm10k_update_uc_addr_pf(struct fm10k_hw *hw, u16 glort,
 352				   const u8 *mac, u16 vid, bool add, u8 flags)
 353{
 354	/* verify MAC address is valid */
 355	if (!is_valid_ether_addr(mac))
 356		return FM10K_ERR_PARAM;
 357
 358	return fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, flags);
 359}
 360
 361/**
 362 *  fm10k_update_mc_addr_pf - Update device multicast addresses
 363 *  @hw: pointer to the HW structure
 364 *  @glort: base resource tag for this request
 365 *  @mac: MAC address to add/remove from table
 366 *  @vid: VLAN ID to add/remove from table
 367 *  @add: Indicates if this is an add or remove operation
 368 *
 369 *  This function is used to add or remove multicast MAC addresses for
 370 *  the PF.
 371 **/
 372static s32 fm10k_update_mc_addr_pf(struct fm10k_hw *hw, u16 glort,
 373				   const u8 *mac, u16 vid, bool add)
 374{
 375	/* verify multicast address is valid */
 376	if (!is_multicast_ether_addr(mac))
 377		return FM10K_ERR_PARAM;
 378
 379	return fm10k_update_xc_addr_pf(hw, glort, mac, vid, add, 0);
 380}
 381
 382/**
 383 *  fm10k_update_xcast_mode_pf - Request update of multicast mode
 384 *  @hw: pointer to hardware structure
 385 *  @glort: base resource tag for this request
 386 *  @mode: integer value indicating mode being requested
 387 *
 388 *  This function will attempt to request a higher mode for the port
 389 *  so that it can enable either multicast, multicast promiscuous, or
 390 *  promiscuous mode of operation.
 391 **/
 392static s32 fm10k_update_xcast_mode_pf(struct fm10k_hw *hw, u16 glort, u8 mode)
 393{
 394	struct fm10k_mbx_info *mbx = &hw->mbx;
 395	u32 msg[3], xcast_mode;
 396
 397	if (mode > FM10K_XCAST_MODE_NONE)
 398		return FM10K_ERR_PARAM;
 399
 400	/* if glort is not valid return error */
 401	if (!fm10k_glort_valid_pf(hw, glort))
 402		return FM10K_ERR_PARAM;
 403
 404	/* write xcast mode as a single u32 value,
 405	 * lower 16 bits: glort
 406	 * upper 16 bits: mode
 407	 */
 408	xcast_mode = ((u32)mode << 16) | glort;
 409
 410	/* generate message requesting to change xcast mode */
 411	fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_XCAST_MODES);
 412	fm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_XCAST_MODE, xcast_mode);
 413
 414	/* load onto outgoing mailbox */
 415	return mbx->ops.enqueue_tx(hw, mbx, msg);
 416}
 417
 418/**
 419 *  fm10k_update_int_moderator_pf - Update interrupt moderator linked list
 420 *  @hw: pointer to hardware structure
 421 *
 422 *  This function walks through the MSI-X vector table to determine the
 423 *  number of active interrupts and based on that information updates the
 424 *  interrupt moderator linked list.
 425 **/
 426static void fm10k_update_int_moderator_pf(struct fm10k_hw *hw)
 427{
 428	u32 i;
 429
 430	/* Disable interrupt moderator */
 431	fm10k_write_reg(hw, FM10K_INT_CTRL, 0);
 432
 433	/* loop through PF from last to first looking enabled vectors */
 434	for (i = FM10K_ITR_REG_COUNT_PF - 1; i; i--) {
 435		if (!fm10k_read_reg(hw, FM10K_MSIX_VECTOR_MASK(i)))
 436			break;
 437	}
 438
 439	/* always reset VFITR2[0] to point to last enabled PF vector */
 440	fm10k_write_reg(hw, FM10K_ITR2(FM10K_ITR_REG_COUNT_PF), i);
 441
 442	/* reset ITR2[0] to point to last enabled PF vector */
 443	if (!hw->iov.num_vfs)
 444		fm10k_write_reg(hw, FM10K_ITR2(0), i);
 445
 446	/* Enable interrupt moderator */
 447	fm10k_write_reg(hw, FM10K_INT_CTRL, FM10K_INT_CTRL_ENABLEMODERATOR);
 448}
 449
 450/**
 451 *  fm10k_update_lport_state_pf - Notify the switch of a change in port state
 452 *  @hw: pointer to the HW structure
 453 *  @glort: base resource tag for this request
 454 *  @count: number of logical ports being updated
 455 *  @enable: boolean value indicating enable or disable
 456 *
 457 *  This function is used to add/remove a logical port from the switch.
 458 **/
 459static s32 fm10k_update_lport_state_pf(struct fm10k_hw *hw, u16 glort,
 460				       u16 count, bool enable)
 461{
 462	struct fm10k_mbx_info *mbx = &hw->mbx;
 463	u32 msg[3], lport_msg;
 464
 465	/* do nothing if we are being asked to create or destroy 0 ports */
 466	if (!count)
 467		return 0;
 468
 469	/* if glort is not valid return error */
 470	if (!fm10k_glort_valid_pf(hw, glort))
 471		return FM10K_ERR_PARAM;
 472
 473	/* reset multicast mode if deleting lport */
 474	if (!enable)
 475		fm10k_update_xcast_mode_pf(hw, glort, FM10K_XCAST_MODE_NONE);
 476
 477	/* construct the lport message from the 2 pieces of data we have */
 478	lport_msg = ((u32)count << 16) | glort;
 479
 480	/* generate lport create/delete message */
 481	fm10k_tlv_msg_init(msg, enable ? FM10K_PF_MSG_ID_LPORT_CREATE :
 482					 FM10K_PF_MSG_ID_LPORT_DELETE);
 483	fm10k_tlv_attr_put_u32(msg, FM10K_PF_ATTR_ID_PORT, lport_msg);
 484
 485	/* load onto outgoing mailbox */
 486	return mbx->ops.enqueue_tx(hw, mbx, msg);
 487}
 488
 489/**
 490 *  fm10k_configure_dglort_map_pf - Configures GLORT entry and queues
 491 *  @hw: pointer to hardware structure
 492 *  @dglort: pointer to dglort configuration structure
 493 *
 494 *  Reads the configuration structure contained in dglort_cfg and uses
 495 *  that information to then populate a DGLORTMAP/DEC entry and the queues
 496 *  to which it has been assigned.
 497 **/
 498static s32 fm10k_configure_dglort_map_pf(struct fm10k_hw *hw,
 499					 struct fm10k_dglort_cfg *dglort)
 500{
 501	u16 glort, queue_count, vsi_count, pc_count;
 502	u16 vsi, queue, pc, q_idx;
 503	u32 txqctl, dglortdec, dglortmap;
 504
 505	/* verify the dglort pointer */
 506	if (!dglort)
 507		return FM10K_ERR_PARAM;
 508
 509	/* verify the dglort values */
 510	if ((dglort->idx > 7) || (dglort->rss_l > 7) || (dglort->pc_l > 3) ||
 511	    (dglort->vsi_l > 6) || (dglort->vsi_b > 64) ||
 512	    (dglort->queue_l > 8) || (dglort->queue_b >= 256))
 513		return FM10K_ERR_PARAM;
 514
 515	/* determine count of VSIs and queues */
 516	queue_count = BIT(dglort->rss_l + dglort->pc_l);
 517	vsi_count = BIT(dglort->vsi_l + dglort->queue_l);
 518	glort = dglort->glort;
 519	q_idx = dglort->queue_b;
 520
 521	/* configure SGLORT for queues */
 522	for (vsi = 0; vsi < vsi_count; vsi++, glort++) {
 523		for (queue = 0; queue < queue_count; queue++, q_idx++) {
 524			if (q_idx >= FM10K_MAX_QUEUES)
 525				break;
 526
 527			fm10k_write_reg(hw, FM10K_TX_SGLORT(q_idx), glort);
 528			fm10k_write_reg(hw, FM10K_RX_SGLORT(q_idx), glort);
 529		}
 530	}
 531
 532	/* determine count of PCs and queues */
 533	queue_count = BIT(dglort->queue_l + dglort->rss_l + dglort->vsi_l);
 534	pc_count = BIT(dglort->pc_l);
 535
 536	/* configure PC for Tx queues */
 537	for (pc = 0; pc < pc_count; pc++) {
 538		q_idx = pc + dglort->queue_b;
 539		for (queue = 0; queue < queue_count; queue++) {
 540			if (q_idx >= FM10K_MAX_QUEUES)
 541				break;
 542
 543			txqctl = fm10k_read_reg(hw, FM10K_TXQCTL(q_idx));
 544			txqctl &= ~FM10K_TXQCTL_PC_MASK;
 545			txqctl |= pc << FM10K_TXQCTL_PC_SHIFT;
 546			fm10k_write_reg(hw, FM10K_TXQCTL(q_idx), txqctl);
 547
 548			q_idx += pc_count;
 549		}
 550	}
 551
 552	/* configure DGLORTDEC */
 553	dglortdec = ((u32)(dglort->rss_l) << FM10K_DGLORTDEC_RSSLENGTH_SHIFT) |
 554		    ((u32)(dglort->queue_b) << FM10K_DGLORTDEC_QBASE_SHIFT) |
 555		    ((u32)(dglort->pc_l) << FM10K_DGLORTDEC_PCLENGTH_SHIFT) |
 556		    ((u32)(dglort->vsi_b) << FM10K_DGLORTDEC_VSIBASE_SHIFT) |
 557		    ((u32)(dglort->vsi_l) << FM10K_DGLORTDEC_VSILENGTH_SHIFT) |
 558		    ((u32)(dglort->queue_l));
 559	if (dglort->inner_rss)
 560		dglortdec |=  FM10K_DGLORTDEC_INNERRSS_ENABLE;
 561
 562	/* configure DGLORTMAP */
 563	dglortmap = (dglort->idx == fm10k_dglort_default) ?
 564			FM10K_DGLORTMAP_ANY : FM10K_DGLORTMAP_ZERO;
 565	dglortmap <<= dglort->vsi_l + dglort->queue_l + dglort->shared_l;
 566	dglortmap |= dglort->glort;
 567
 568	/* write values to hardware */
 569	fm10k_write_reg(hw, FM10K_DGLORTDEC(dglort->idx), dglortdec);
 570	fm10k_write_reg(hw, FM10K_DGLORTMAP(dglort->idx), dglortmap);
 571
 572	return 0;
 573}
 574
 575u16 fm10k_queues_per_pool(struct fm10k_hw *hw)
 576{
 577	u16 num_pools = hw->iov.num_pools;
 578
 579	return (num_pools > 32) ? 2 : (num_pools > 16) ? 4 : (num_pools > 8) ?
 580	       8 : FM10K_MAX_QUEUES_POOL;
 581}
 582
 583u16 fm10k_vf_queue_index(struct fm10k_hw *hw, u16 vf_idx)
 584{
 585	u16 num_vfs = hw->iov.num_vfs;
 586	u16 vf_q_idx = FM10K_MAX_QUEUES;
 587
 588	vf_q_idx -= fm10k_queues_per_pool(hw) * (num_vfs - vf_idx);
 589
 590	return vf_q_idx;
 591}
 592
 593static u16 fm10k_vectors_per_pool(struct fm10k_hw *hw)
 594{
 595	u16 num_pools = hw->iov.num_pools;
 596
 597	return (num_pools > 32) ? 8 : (num_pools > 16) ? 16 :
 598	       FM10K_MAX_VECTORS_POOL;
 599}
 600
 601static u16 fm10k_vf_vector_index(struct fm10k_hw *hw, u16 vf_idx)
 602{
 603	u16 vf_v_idx = FM10K_MAX_VECTORS_PF;
 604
 605	vf_v_idx += fm10k_vectors_per_pool(hw) * vf_idx;
 606
 607	return vf_v_idx;
 608}
 609
 610/**
 611 *  fm10k_iov_assign_resources_pf - Assign pool resources for virtualization
 612 *  @hw: pointer to the HW structure
 613 *  @num_vfs: number of VFs to be allocated
 614 *  @num_pools: number of virtualization pools to be allocated
 615 *
 616 *  Allocates queues and traffic classes to virtualization entities to prepare
 617 *  the PF for SR-IOV and VMDq
 618 **/
 619static s32 fm10k_iov_assign_resources_pf(struct fm10k_hw *hw, u16 num_vfs,
 620					 u16 num_pools)
 621{
 622	u16 qmap_stride, qpp, vpp, vf_q_idx, vf_q_idx0, qmap_idx;
 623	u32 vid = hw->mac.default_vid << FM10K_TXQCTL_VID_SHIFT;
 624	int i, j;
 625
 626	/* hardware only supports up to 64 pools */
 627	if (num_pools > 64)
 628		return FM10K_ERR_PARAM;
 629
 630	/* the number of VFs cannot exceed the number of pools */
 631	if ((num_vfs > num_pools) || (num_vfs > hw->iov.total_vfs))
 632		return FM10K_ERR_PARAM;
 633
 634	/* record number of virtualization entities */
 635	hw->iov.num_vfs = num_vfs;
 636	hw->iov.num_pools = num_pools;
 637
 638	/* determine qmap offsets and counts */
 639	qmap_stride = (num_vfs > 8) ? 32 : 256;
 640	qpp = fm10k_queues_per_pool(hw);
 641	vpp = fm10k_vectors_per_pool(hw);
 642
 643	/* calculate starting index for queues */
 644	vf_q_idx = fm10k_vf_queue_index(hw, 0);
 645	qmap_idx = 0;
 646
 647	/* establish TCs with -1 credits and no quanta to prevent transmit */
 648	for (i = 0; i < num_vfs; i++) {
 649		fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(i), 0);
 650		fm10k_write_reg(hw, FM10K_TC_RATE(i), 0);
 651		fm10k_write_reg(hw, FM10K_TC_CREDIT(i),
 652				FM10K_TC_CREDIT_CREDIT_MASK);
 653	}
 654
 655	/* zero out all mbmem registers */
 656	for (i = FM10K_VFMBMEM_LEN * num_vfs; i--;)
 657		fm10k_write_reg(hw, FM10K_MBMEM(i), 0);
 658
 659	/* clear event notification of VF FLR */
 660	fm10k_write_reg(hw, FM10K_PFVFLREC(0), ~0);
 661	fm10k_write_reg(hw, FM10K_PFVFLREC(1), ~0);
 662
 663	/* loop through unallocated rings assigning them back to PF */
 664	for (i = FM10K_MAX_QUEUES_PF; i < vf_q_idx; i++) {
 665		fm10k_write_reg(hw, FM10K_TXDCTL(i), 0);
 666		fm10k_write_reg(hw, FM10K_TXQCTL(i), FM10K_TXQCTL_PF |
 667				FM10K_TXQCTL_UNLIMITED_BW | vid);
 668		fm10k_write_reg(hw, FM10K_RXQCTL(i), FM10K_RXQCTL_PF);
 669	}
 670
 671	/* PF should have already updated VFITR2[0] */
 672
 673	/* update all ITR registers to flow to VFITR2[0] */
 674	for (i = FM10K_ITR_REG_COUNT_PF + 1; i < FM10K_ITR_REG_COUNT; i++) {
 675		if (!(i & (vpp - 1)))
 676			fm10k_write_reg(hw, FM10K_ITR2(i), i - vpp);
 677		else
 678			fm10k_write_reg(hw, FM10K_ITR2(i), i - 1);
 679	}
 680
 681	/* update PF ITR2[0] to reference the last vector */
 682	fm10k_write_reg(hw, FM10K_ITR2(0),
 683			fm10k_vf_vector_index(hw, num_vfs - 1));
 684
 685	/* loop through rings populating rings and TCs */
 686	for (i = 0; i < num_vfs; i++) {
 687		/* record index for VF queue 0 for use in end of loop */
 688		vf_q_idx0 = vf_q_idx;
 689
 690		for (j = 0; j < qpp; j++, qmap_idx++, vf_q_idx++) {
 691			/* assign VF and locked TC to queues */
 692			fm10k_write_reg(hw, FM10K_TXDCTL(vf_q_idx), 0);
 693			fm10k_write_reg(hw, FM10K_TXQCTL(vf_q_idx),
 694					(i << FM10K_TXQCTL_TC_SHIFT) | i |
 695					FM10K_TXQCTL_VF | vid);
 696			fm10k_write_reg(hw, FM10K_RXDCTL(vf_q_idx),
 697					FM10K_RXDCTL_WRITE_BACK_MIN_DELAY |
 698					FM10K_RXDCTL_DROP_ON_EMPTY);
 699			fm10k_write_reg(hw, FM10K_RXQCTL(vf_q_idx),
 700					(i << FM10K_RXQCTL_VF_SHIFT) |
 701					FM10K_RXQCTL_VF);
 702
 703			/* map queue pair to VF */
 704			fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx);
 705			fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), vf_q_idx);
 706		}
 707
 708		/* repeat the first ring for all of the remaining VF rings */
 709		for (; j < qmap_stride; j++, qmap_idx++) {
 710			fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx0);
 711			fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), vf_q_idx0);
 712		}
 713	}
 714
 715	/* loop through remaining indexes assigning all to queue 0 */
 716	while (qmap_idx < FM10K_TQMAP_TABLE_SIZE) {
 717		fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), 0);
 718		fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx), 0);
 719		qmap_idx++;
 720	}
 721
 722	return 0;
 723}
 724
 725/**
 726 *  fm10k_iov_configure_tc_pf - Configure the shaping group for VF
 727 *  @hw: pointer to the HW structure
 728 *  @vf_idx: index of VF receiving GLORT
 729 *  @rate: Rate indicated in Mb/s
 730 *
 731 *  Configured the TC for a given VF to allow only up to a given number
 732 *  of Mb/s of outgoing Tx throughput.
 733 **/
 734static s32 fm10k_iov_configure_tc_pf(struct fm10k_hw *hw, u16 vf_idx, int rate)
 735{
 736	/* configure defaults */
 737	u32 interval = FM10K_TC_RATE_INTERVAL_4US_GEN3;
 738	u32 tc_rate = FM10K_TC_RATE_QUANTA_MASK;
 739
 740	/* verify vf is in range */
 741	if (vf_idx >= hw->iov.num_vfs)
 742		return FM10K_ERR_PARAM;
 743
 744	/* set interval to align with 4.096 usec in all modes */
 745	switch (hw->bus.speed) {
 746	case fm10k_bus_speed_2500:
 747		interval = FM10K_TC_RATE_INTERVAL_4US_GEN1;
 748		break;
 749	case fm10k_bus_speed_5000:
 750		interval = FM10K_TC_RATE_INTERVAL_4US_GEN2;
 751		break;
 752	default:
 753		break;
 754	}
 755
 756	if (rate) {
 757		if (rate > FM10K_VF_TC_MAX || rate < FM10K_VF_TC_MIN)
 758			return FM10K_ERR_PARAM;
 759
 760		/* The quanta is measured in Bytes per 4.096 or 8.192 usec
 761		 * The rate is provided in Mbits per second
 762		 * To tralslate from rate to quanta we need to multiply the
 763		 * rate by 8.192 usec and divide by 8 bits/byte.  To avoid
 764		 * dealing with floating point we can round the values up
 765		 * to the nearest whole number ratio which gives us 128 / 125.
 766		 */
 767		tc_rate = (rate * 128) / 125;
 768
 769		/* try to keep the rate limiting accurate by increasing
 770		 * the number of credits and interval for rates less than 4Gb/s
 771		 */
 772		if (rate < 4000)
 773			interval <<= 1;
 774		else
 775			tc_rate >>= 1;
 776	}
 777
 778	/* update rate limiter with new values */
 779	fm10k_write_reg(hw, FM10K_TC_RATE(vf_idx), tc_rate | interval);
 780	fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K);
 781	fm10k_write_reg(hw, FM10K_TC_CREDIT(vf_idx), FM10K_TC_MAXCREDIT_64K);
 782
 783	return 0;
 784}
 785
 786/**
 787 *  fm10k_iov_assign_int_moderator_pf - Add VF interrupts to moderator list
 788 *  @hw: pointer to the HW structure
 789 *  @vf_idx: index of VF receiving GLORT
 790 *
 791 *  Update the interrupt moderator linked list to include any MSI-X
 792 *  interrupts which the VF has enabled in the MSI-X vector table.
 793 **/
 794static s32 fm10k_iov_assign_int_moderator_pf(struct fm10k_hw *hw, u16 vf_idx)
 795{
 796	u16 vf_v_idx, vf_v_limit, i;
 797
 798	/* verify vf is in range */
 799	if (vf_idx >= hw->iov.num_vfs)
 800		return FM10K_ERR_PARAM;
 801
 802	/* determine vector offset and count */
 803	vf_v_idx = fm10k_vf_vector_index(hw, vf_idx);
 804	vf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw);
 805
 806	/* search for first vector that is not masked */
 807	for (i = vf_v_limit - 1; i > vf_v_idx; i--) {
 808		if (!fm10k_read_reg(hw, FM10K_MSIX_VECTOR_MASK(i)))
 809			break;
 810	}
 811
 812	/* reset linked list so it now includes our active vectors */
 813	if (vf_idx == (hw->iov.num_vfs - 1))
 814		fm10k_write_reg(hw, FM10K_ITR2(0), i);
 815	else
 816		fm10k_write_reg(hw, FM10K_ITR2(vf_v_limit), i);
 817
 818	return 0;
 819}
 820
 821/**
 822 *  fm10k_iov_assign_default_mac_vlan_pf - Assign a MAC and VLAN to VF
 823 *  @hw: pointer to the HW structure
 824 *  @vf_info: pointer to VF information structure
 825 *
 826 *  Assign a MAC address and default VLAN to a VF and notify it of the update
 827 **/
 828static s32 fm10k_iov_assign_default_mac_vlan_pf(struct fm10k_hw *hw,
 829						struct fm10k_vf_info *vf_info)
 830{
 831	u16 qmap_stride, queues_per_pool, vf_q_idx, timeout, qmap_idx, i;
 832	u32 msg[4], txdctl, txqctl, tdbal = 0, tdbah = 0;
 833	s32 err = 0;
 834	u16 vf_idx, vf_vid;
 835
 836	/* verify vf is in range */
 837	if (!vf_info || vf_info->vf_idx >= hw->iov.num_vfs)
 838		return FM10K_ERR_PARAM;
 839
 840	/* determine qmap offsets and counts */
 841	qmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256;
 842	queues_per_pool = fm10k_queues_per_pool(hw);
 843
 844	/* calculate starting index for queues */
 845	vf_idx = vf_info->vf_idx;
 846	vf_q_idx = fm10k_vf_queue_index(hw, vf_idx);
 847	qmap_idx = qmap_stride * vf_idx;
 848
 849	/* Determine correct default VLAN ID. The FM10K_VLAN_OVERRIDE bit is
 850	 * used here to indicate to the VF that it will not have privilege to
 851	 * write VLAN_TABLE. All policy is enforced on the PF but this allows
 852	 * the VF to correctly report errors to userspace requests.
 853	 */
 854	if (vf_info->pf_vid)
 855		vf_vid = vf_info->pf_vid | FM10K_VLAN_OVERRIDE;
 856	else
 857		vf_vid = vf_info->sw_vid;
 858
 859	/* generate MAC_ADDR request */
 860	fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_MAC_VLAN);
 861	fm10k_tlv_attr_put_mac_vlan(msg, FM10K_MAC_VLAN_MSG_DEFAULT_MAC,
 862				    vf_info->mac, vf_vid);
 863
 864	/* Configure Queue control register with new VLAN ID. The TXQCTL
 865	 * register is RO from the VF, so the PF must do this even in the
 866	 * case of notifying the VF of a new VID via the mailbox.
 867	 */
 868	txqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) &
 869		 FM10K_TXQCTL_VID_MASK;
 870	txqctl |= (vf_idx << FM10K_TXQCTL_TC_SHIFT) |
 871		  FM10K_TXQCTL_VF | vf_idx;
 872
 873	for (i = 0; i < queues_per_pool; i++)
 874		fm10k_write_reg(hw, FM10K_TXQCTL(vf_q_idx + i), txqctl);
 875
 876	/* try loading a message onto outgoing mailbox first */
 877	if (vf_info->mbx.ops.enqueue_tx) {
 878		err = vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg);
 879		if (err != FM10K_MBX_ERR_NO_MBX)
 880			return err;
 881		err = 0;
 882	}
 883
 884	/* If we aren't connected to a mailbox, this is most likely because
 885	 * the VF driver is not running. It should thus be safe to re-map
 886	 * queues and use the registers to pass the MAC address so that the VF
 887	 * driver gets correct information during its initialization.
 888	 */
 889
 890	/* MAP Tx queue back to 0 temporarily, and disable it */
 891	fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), 0);
 892	fm10k_write_reg(hw, FM10K_TXDCTL(vf_q_idx), 0);
 893
 894	/* verify ring has disabled before modifying base address registers */
 895	txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(vf_q_idx));
 896	for (timeout = 0; txdctl & FM10K_TXDCTL_ENABLE; timeout++) {
 897		/* limit ourselves to a 1ms timeout */
 898		if (timeout == 10) {
 899			err = FM10K_ERR_DMA_PENDING;
 900			goto err_out;
 901		}
 902
 903		usleep_range(100, 200);
 904		txdctl = fm10k_read_reg(hw, FM10K_TXDCTL(vf_q_idx));
 905	}
 906
 907	/* Update base address registers to contain MAC address */
 908	if (is_valid_ether_addr(vf_info->mac)) {
 909		tdbal = (((u32)vf_info->mac[3]) << 24) |
 910			(((u32)vf_info->mac[4]) << 16) |
 911			(((u32)vf_info->mac[5]) << 8);
 912
 913		tdbah = (((u32)0xFF)	        << 24) |
 914			(((u32)vf_info->mac[0]) << 16) |
 915			(((u32)vf_info->mac[1]) << 8) |
 916			((u32)vf_info->mac[2]);
 917	}
 918
 919	/* Record the base address into queue 0 */
 920	fm10k_write_reg(hw, FM10K_TDBAL(vf_q_idx), tdbal);
 921	fm10k_write_reg(hw, FM10K_TDBAH(vf_q_idx), tdbah);
 922
 923	/* Provide the VF the ITR scale, using software-defined fields in TDLEN
 924	 * to pass the information during VF initialization. See definition of
 925	 * FM10K_TDLEN_ITR_SCALE_SHIFT for more details.
 926	 */
 927	fm10k_write_reg(hw, FM10K_TDLEN(vf_q_idx), hw->mac.itr_scale <<
 928						   FM10K_TDLEN_ITR_SCALE_SHIFT);
 929
 930err_out:
 931	/* restore the queue back to VF ownership */
 932	fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx), vf_q_idx);
 933	return err;
 934}
 935
 936/**
 937 *  fm10k_iov_reset_resources_pf - Reassign queues and interrupts to a VF
 938 *  @hw: pointer to the HW structure
 939 *  @vf_info: pointer to VF information structure
 940 *
 941 *  Reassign the interrupts and queues to a VF following an FLR
 942 **/
 943static s32 fm10k_iov_reset_resources_pf(struct fm10k_hw *hw,
 944					struct fm10k_vf_info *vf_info)
 945{
 946	u16 qmap_stride, queues_per_pool, vf_q_idx, qmap_idx;
 947	u32 tdbal = 0, tdbah = 0, txqctl, rxqctl;
 948	u16 vf_v_idx, vf_v_limit, vf_vid;
 949	u8 vf_idx = vf_info->vf_idx;
 950	int i;
 951
 952	/* verify vf is in range */
 953	if (vf_idx >= hw->iov.num_vfs)
 954		return FM10K_ERR_PARAM;
 955
 956	/* clear event notification of VF FLR */
 957	fm10k_write_reg(hw, FM10K_PFVFLREC(vf_idx / 32), BIT(vf_idx % 32));
 958
 959	/* force timeout and then disconnect the mailbox */
 960	vf_info->mbx.timeout = 0;
 961	if (vf_info->mbx.ops.disconnect)
 962		vf_info->mbx.ops.disconnect(hw, &vf_info->mbx);
 963
 964	/* determine vector offset and count */
 965	vf_v_idx = fm10k_vf_vector_index(hw, vf_idx);
 966	vf_v_limit = vf_v_idx + fm10k_vectors_per_pool(hw);
 967
 968	/* determine qmap offsets and counts */
 969	qmap_stride = (hw->iov.num_vfs > 8) ? 32 : 256;
 970	queues_per_pool = fm10k_queues_per_pool(hw);
 971	qmap_idx = qmap_stride * vf_idx;
 972
 973	/* make all the queues inaccessible to the VF */
 974	for (i = qmap_idx; i < (qmap_idx + qmap_stride); i++) {
 975		fm10k_write_reg(hw, FM10K_TQMAP(i), 0);
 976		fm10k_write_reg(hw, FM10K_RQMAP(i), 0);
 977	}
 978
 979	/* calculate starting index for queues */
 980	vf_q_idx = fm10k_vf_queue_index(hw, vf_idx);
 981
 982	/* determine correct default VLAN ID */
 983	if (vf_info->pf_vid)
 984		vf_vid = vf_info->pf_vid;
 985	else
 986		vf_vid = vf_info->sw_vid;
 987
 988	/* configure Queue control register */
 989	txqctl = ((u32)vf_vid << FM10K_TXQCTL_VID_SHIFT) |
 990		 (vf_idx << FM10K_TXQCTL_TC_SHIFT) |
 991		 FM10K_TXQCTL_VF | vf_idx;
 992	rxqctl = (vf_idx << FM10K_RXQCTL_VF_SHIFT) | FM10K_RXQCTL_VF;
 993
 994	/* stop further DMA and reset queue ownership back to VF */
 995	for (i = vf_q_idx; i < (queues_per_pool + vf_q_idx); i++) {
 996		fm10k_write_reg(hw, FM10K_TXDCTL(i), 0);
 997		fm10k_write_reg(hw, FM10K_TXQCTL(i), txqctl);
 998		fm10k_write_reg(hw, FM10K_RXDCTL(i),
 999				FM10K_RXDCTL_WRITE_BACK_MIN_DELAY |
1000				FM10K_RXDCTL_DROP_ON_EMPTY);
1001		fm10k_write_reg(hw, FM10K_RXQCTL(i), rxqctl);
1002	}
1003
1004	/* reset TC with -1 credits and no quanta to prevent transmit */
1005	fm10k_write_reg(hw, FM10K_TC_MAXCREDIT(vf_idx), 0);
1006	fm10k_write_reg(hw, FM10K_TC_RATE(vf_idx), 0);
1007	fm10k_write_reg(hw, FM10K_TC_CREDIT(vf_idx),
1008			FM10K_TC_CREDIT_CREDIT_MASK);
1009
1010	/* update our first entry in the table based on previous VF */
1011	if (!vf_idx)
1012		hw->mac.ops.update_int_moderator(hw);
1013	else
1014		hw->iov.ops.assign_int_moderator(hw, vf_idx - 1);
1015
1016	/* reset linked list so it now includes our active vectors */
1017	if (vf_idx == (hw->iov.num_vfs - 1))
1018		fm10k_write_reg(hw, FM10K_ITR2(0), vf_v_idx);
1019	else
1020		fm10k_write_reg(hw, FM10K_ITR2(vf_v_limit), vf_v_idx);
1021
1022	/* link remaining vectors so that next points to previous */
1023	for (vf_v_idx++; vf_v_idx < vf_v_limit; vf_v_idx++)
1024		fm10k_write_reg(hw, FM10K_ITR2(vf_v_idx), vf_v_idx - 1);
1025
1026	/* zero out MBMEM, VLAN_TABLE, RETA, RSSRK, and MRQC registers */
1027	for (i = FM10K_VFMBMEM_LEN; i--;)
1028		fm10k_write_reg(hw, FM10K_MBMEM_VF(vf_idx, i), 0);
1029	for (i = FM10K_VLAN_TABLE_SIZE; i--;)
1030		fm10k_write_reg(hw, FM10K_VLAN_TABLE(vf_info->vsi, i), 0);
1031	for (i = FM10K_RETA_SIZE; i--;)
1032		fm10k_write_reg(hw, FM10K_RETA(vf_info->vsi, i), 0);
1033	for (i = FM10K_RSSRK_SIZE; i--;)
1034		fm10k_write_reg(hw, FM10K_RSSRK(vf_info->vsi, i), 0);
1035	fm10k_write_reg(hw, FM10K_MRQC(vf_info->vsi), 0);
1036
1037	/* Update base address registers to contain MAC address */
1038	if (is_valid_ether_addr(vf_info->mac)) {
1039		tdbal = (((u32)vf_info->mac[3]) << 24) |
1040			(((u32)vf_info->mac[4]) << 16) |
1041			(((u32)vf_info->mac[5]) << 8);
1042		tdbah = (((u32)0xFF)	   << 24) |
1043			(((u32)vf_info->mac[0]) << 16) |
1044			(((u32)vf_info->mac[1]) << 8) |
1045			((u32)vf_info->mac[2]);
1046	}
1047
1048	/* map queue pairs back to VF from last to first */
1049	for (i = queues_per_pool; i--;) {
1050		fm10k_write_reg(hw, FM10K_TDBAL(vf_q_idx + i), tdbal);
1051		fm10k_write_reg(hw, FM10K_TDBAH(vf_q_idx + i), tdbah);
1052		/* See definition of FM10K_TDLEN_ITR_SCALE_SHIFT for an
1053		 * explanation of how TDLEN is used.
1054		 */
1055		fm10k_write_reg(hw, FM10K_TDLEN(vf_q_idx + i),
1056				hw->mac.itr_scale <<
1057				FM10K_TDLEN_ITR_SCALE_SHIFT);
1058		fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx + i);
1059		fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx + i);
1060	}
1061
1062	/* repeat the first ring for all the remaining VF rings */
1063	for (i = queues_per_pool; i < qmap_stride; i++) {
1064		fm10k_write_reg(hw, FM10K_TQMAP(qmap_idx + i), vf_q_idx);
1065		fm10k_write_reg(hw, FM10K_RQMAP(qmap_idx + i), vf_q_idx);
1066	}
1067
1068	return 0;
1069}
1070
1071/**
1072 *  fm10k_iov_set_lport_pf - Assign and enable a logical port for a given VF
1073 *  @hw: pointer to hardware structure
1074 *  @vf_info: pointer to VF information structure
1075 *  @lport_idx: Logical port offset from the hardware glort
1076 *  @flags: Set of capability flags to extend port beyond basic functionality
1077 *
1078 *  This function allows enabling a VF port by assigning it a GLORT and
1079 *  setting the flags so that it can enable an Rx mode.
1080 **/
1081static s32 fm10k_iov_set_lport_pf(struct fm10k_hw *hw,
1082				  struct fm10k_vf_info *vf_info,
1083				  u16 lport_idx, u8 flags)
1084{
1085	u16 glort = (hw->mac.dglort_map + lport_idx) & FM10K_DGLORTMAP_NONE;
1086
1087	/* if glort is not valid return error */
1088	if (!fm10k_glort_valid_pf(hw, glort))
1089		return FM10K_ERR_PARAM;
1090
1091	vf_info->vf_flags = flags | FM10K_VF_FLAG_NONE_CAPABLE;
1092	vf_info->glort = glort;
1093
1094	return 0;
1095}
1096
1097/**
1098 *  fm10k_iov_reset_lport_pf - Disable a logical port for a given VF
1099 *  @hw: pointer to hardware structure
1100 *  @vf_info: pointer to VF information structure
1101 *
1102 *  This function disables a VF port by stripping it of a GLORT and
1103 *  setting the flags so that it cannot enable any Rx mode.
1104 **/
1105static void fm10k_iov_reset_lport_pf(struct fm10k_hw *hw,
1106				     struct fm10k_vf_info *vf_info)
1107{
1108	u32 msg[1];
1109
1110	/* need to disable the port if it is already enabled */
1111	if (FM10K_VF_FLAG_ENABLED(vf_info)) {
1112		/* notify switch that this port has been disabled */
1113		fm10k_update_lport_state_pf(hw, vf_info->glort, 1, false);
1114
1115		/* generate port state response to notify VF it is not ready */
1116		fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE);
1117		vf_info->mbx.ops.enqueue_tx(hw, &vf_info->mbx, msg);
1118	}
1119
1120	/* clear flags and glort if it exists */
1121	vf_info->vf_flags = 0;
1122	vf_info->glort = 0;
1123}
1124
1125/**
1126 *  fm10k_iov_update_stats_pf - Updates hardware related statistics for VFs
1127 *  @hw: pointer to hardware structure
1128 *  @q: stats for all queues of a VF
1129 *  @vf_idx: index of VF
1130 *
1131 *  This function collects queue stats for VFs.
1132 **/
1133static void fm10k_iov_update_stats_pf(struct fm10k_hw *hw,
1134				      struct fm10k_hw_stats_q *q,
1135				      u16 vf_idx)
1136{
1137	u32 idx, qpp;
1138
1139	/* get stats for all of the queues */
1140	qpp = fm10k_queues_per_pool(hw);
1141	idx = fm10k_vf_queue_index(hw, vf_idx);
1142	fm10k_update_hw_stats_q(hw, q, idx, qpp);
1143}
1144
1145/**
1146 *  fm10k_iov_msg_msix_pf - Message handler for MSI-X request from VF
1147 *  @hw: Pointer to hardware structure
1148 *  @results: Pointer array to message, results[0] is pointer to message
1149 *  @mbx: Pointer to mailbox information structure
1150 *
1151 *  This function is a default handler for MSI-X requests from the VF. The
1152 *  assumption is that in this case it is acceptable to just directly
1153 *  hand off the message from the VF to the underlying shared code.
1154 **/
1155s32 fm10k_iov_msg_msix_pf(struct fm10k_hw *hw, u32 __always_unused **results,
1156			  struct fm10k_mbx_info *mbx)
1157{
1158	struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx;
1159	u8 vf_idx = vf_info->vf_idx;
1160
1161	return hw->iov.ops.assign_int_moderator(hw, vf_idx);
1162}
1163
1164/**
1165 * fm10k_iov_select_vid - Select correct default VLAN ID
1166 * @vf_info: pointer to VF information structure
1167 * @vid: VLAN ID to correct
1168 *
1169 * Will report an error if the VLAN ID is out of range. For VID = 0, it will
1170 * return either the pf_vid or sw_vid depending on which one is set.
1171 */
1172s32 fm10k_iov_select_vid(struct fm10k_vf_info *vf_info, u16 vid)
1173{
1174	if (!vid)
1175		return vf_info->pf_vid ? vf_info->pf_vid : vf_info->sw_vid;
1176	else if (vf_info->pf_vid && vid != vf_info->pf_vid)
1177		return FM10K_ERR_PARAM;
1178	else
1179		return vid;
1180}
1181
1182/**
1183 *  fm10k_iov_msg_mac_vlan_pf - Message handler for MAC/VLAN request from VF
1184 *  @hw: Pointer to hardware structure
1185 *  @results: Pointer array to message, results[0] is pointer to message
1186 *  @mbx: Pointer to mailbox information structure
1187 *
1188 *  This function is a default handler for MAC/VLAN requests from the VF.
1189 *  The assumption is that in this case it is acceptable to just directly
1190 *  hand off the message from the VF to the underlying shared code.
1191 **/
1192s32 fm10k_iov_msg_mac_vlan_pf(struct fm10k_hw *hw, u32 **results,
1193			      struct fm10k_mbx_info *mbx)
1194{
1195	struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx;
1196	u8 mac[ETH_ALEN];
1197	u32 *result;
1198	int err = 0;
1199	bool set;
1200	u16 vlan;
1201	u32 vid;
1202
1203	/* we shouldn't be updating rules on a disabled interface */
1204	if (!FM10K_VF_FLAG_ENABLED(vf_info))
1205		err = FM10K_ERR_PARAM;
1206
1207	if (!err && !!results[FM10K_MAC_VLAN_MSG_VLAN]) {
1208		result = results[FM10K_MAC_VLAN_MSG_VLAN];
1209
1210		/* record VLAN id requested */
1211		err = fm10k_tlv_attr_get_u32(result, &vid);
1212		if (err)
1213			return err;
1214
1215		set = !(vid & FM10K_VLAN_CLEAR);
1216		vid &= ~FM10K_VLAN_CLEAR;
1217
1218		/* if the length field has been set, this is a multi-bit
1219		 * update request. For multi-bit requests, simply disallow
1220		 * them when the pf_vid has been set. In this case, the PF
1221		 * should have already cleared the VLAN_TABLE, and if we
1222		 * allowed them, it could allow a rogue VF to receive traffic
1223		 * on a VLAN it was not assigned. In the single-bit case, we
1224		 * need to modify requests for VLAN 0 to use the default PF or
1225		 * SW vid when assigned.
1226		 */
1227
1228		if (vid >> 16) {
1229			/* prevent multi-bit requests when PF has
1230			 * administratively set the VLAN for this VF
1231			 */
1232			if (vf_info->pf_vid)
1233				return FM10K_ERR_PARAM;
1234		} else {
1235			err = fm10k_iov_select_vid(vf_info, (u16)vid);
1236			if (err < 0)
1237				return err;
1238
1239			vid = err;
1240		}
1241
1242		/* update VSI info for VF in regards to VLAN table */
1243		err = hw->mac.ops.update_vlan(hw, vid, vf_info->vsi, set);
1244	}
1245
1246	if (!err && !!results[FM10K_MAC_VLAN_MSG_MAC]) {
1247		result = results[FM10K_MAC_VLAN_MSG_MAC];
1248
1249		/* record unicast MAC address requested */
1250		err = fm10k_tlv_attr_get_mac_vlan(result, mac, &vlan);
1251		if (err)
1252			return err;
1253
1254		/* block attempts to set MAC for a locked device */
1255		if (is_valid_ether_addr(vf_info->mac) &&
1256		    !ether_addr_equal(mac, vf_info->mac))
1257			return FM10K_ERR_PARAM;
1258
1259		set = !(vlan & FM10K_VLAN_CLEAR);
1260		vlan &= ~FM10K_VLAN_CLEAR;
1261
1262		err = fm10k_iov_select_vid(vf_info, vlan);
1263		if (err < 0)
1264			return err;
1265
1266		vlan = (u16)err;
1267
1268		/* notify switch of request for new unicast address */
1269		err = hw->mac.ops.update_uc_addr(hw, vf_info->glort,
1270						 mac, vlan, set, 0);
1271	}
1272
1273	if (!err && !!results[FM10K_MAC_VLAN_MSG_MULTICAST]) {
1274		result = results[FM10K_MAC_VLAN_MSG_MULTICAST];
1275
1276		/* record multicast MAC address requested */
1277		err = fm10k_tlv_attr_get_mac_vlan(result, mac, &vlan);
1278		if (err)
1279			return err;
1280
1281		/* verify that the VF is allowed to request multicast */
1282		if (!(vf_info->vf_flags & FM10K_VF_FLAG_MULTI_ENABLED))
1283			return FM10K_ERR_PARAM;
1284
1285		set = !(vlan & FM10K_VLAN_CLEAR);
1286		vlan &= ~FM10K_VLAN_CLEAR;
1287
1288		err = fm10k_iov_select_vid(vf_info, vlan);
1289		if (err < 0)
1290			return err;
1291
1292		vlan = (u16)err;
1293
1294		/* notify switch of request for new multicast address */
1295		err = hw->mac.ops.update_mc_addr(hw, vf_info->glort,
1296						 mac, vlan, set);
1297	}
1298
1299	return err;
1300}
1301
1302/**
1303 *  fm10k_iov_supported_xcast_mode_pf - Determine best match for xcast mode
1304 *  @vf_info: VF info structure containing capability flags
1305 *  @mode: Requested xcast mode
1306 *
1307 *  This function outputs the mode that most closely matches the requested
1308 *  mode.  If not modes match it will request we disable the port
1309 **/
1310static u8 fm10k_iov_supported_xcast_mode_pf(struct fm10k_vf_info *vf_info,
1311					    u8 mode)
1312{
1313	u8 vf_flags = vf_info->vf_flags;
1314
1315	/* match up mode to capabilities as best as possible */
1316	switch (mode) {
1317	case FM10K_XCAST_MODE_PROMISC:
1318		if (vf_flags & FM10K_VF_FLAG_PROMISC_CAPABLE)
1319			return FM10K_XCAST_MODE_PROMISC;
1320		/* fall through */
1321	case FM10K_XCAST_MODE_ALLMULTI:
1322		if (vf_flags & FM10K_VF_FLAG_ALLMULTI_CAPABLE)
1323			return FM10K_XCAST_MODE_ALLMULTI;
1324		/* fall through */
1325	case FM10K_XCAST_MODE_MULTI:
1326		if (vf_flags & FM10K_VF_FLAG_MULTI_CAPABLE)
1327			return FM10K_XCAST_MODE_MULTI;
1328		/* fall through */
1329	case FM10K_XCAST_MODE_NONE:
1330		if (vf_flags & FM10K_VF_FLAG_NONE_CAPABLE)
1331			return FM10K_XCAST_MODE_NONE;
1332		/* fall through */
1333	default:
1334		break;
1335	}
1336
1337	/* disable interface as it should not be able to request any */
1338	return FM10K_XCAST_MODE_DISABLE;
1339}
1340
1341/**
1342 *  fm10k_iov_msg_lport_state_pf - Message handler for port state requests
1343 *  @hw: Pointer to hardware structure
1344 *  @results: Pointer array to message, results[0] is pointer to message
1345 *  @mbx: Pointer to mailbox information structure
1346 *
1347 *  This function is a default handler for port state requests.  The port
1348 *  state requests for now are basic and consist of enabling or disabling
1349 *  the port.
1350 **/
1351s32 fm10k_iov_msg_lport_state_pf(struct fm10k_hw *hw, u32 **results,
1352				 struct fm10k_mbx_info *mbx)
1353{
1354	struct fm10k_vf_info *vf_info = (struct fm10k_vf_info *)mbx;
 
1355	s32 err = 0;
1356	u32 msg[2];
1357	u8 mode = 0;
1358
1359	/* verify VF is allowed to enable even minimal mode */
1360	if (!(vf_info->vf_flags & FM10K_VF_FLAG_NONE_CAPABLE))
1361		return FM10K_ERR_PARAM;
1362
1363	if (!!results[FM10K_LPORT_STATE_MSG_XCAST_MODE]) {
1364		u32 *result = results[FM10K_LPORT_STATE_MSG_XCAST_MODE];
1365
1366		/* XCAST mode update requested */
1367		err = fm10k_tlv_attr_get_u8(result, &mode);
1368		if (err)
1369			return FM10K_ERR_PARAM;
1370
1371		/* prep for possible demotion depending on capabilities */
1372		mode = fm10k_iov_supported_xcast_mode_pf(vf_info, mode);
1373
1374		/* if mode is not currently enabled, enable it */
1375		if (!(FM10K_VF_FLAG_ENABLED(vf_info) & BIT(mode)))
1376			fm10k_update_xcast_mode_pf(hw, vf_info->glort, mode);
1377
1378		/* swap mode back to a bit flag */
1379		mode = FM10K_VF_FLAG_SET_MODE(mode);
1380	} else if (!results[FM10K_LPORT_STATE_MSG_DISABLE]) {
1381		/* need to disable the port if it is already enabled */
1382		if (FM10K_VF_FLAG_ENABLED(vf_info))
1383			err = fm10k_update_lport_state_pf(hw, vf_info->glort,
1384							  1, false);
1385
1386		/* we need to clear VF_FLAG_ENABLED flags in order to ensure
1387		 * that we actually re-enable the LPORT state below. Note that
1388		 * this has no impact if the VF is already disabled, as the
1389		 * flags are already cleared.
1390		 */
1391		if (!err)
1392			vf_info->vf_flags = FM10K_VF_FLAG_CAPABLE(vf_info);
1393
1394		/* when enabling the port we should reset the rate limiters */
1395		hw->iov.ops.configure_tc(hw, vf_info->vf_idx, vf_info->rate);
1396
1397		/* set mode for minimal functionality */
1398		mode = FM10K_VF_FLAG_SET_MODE_NONE;
1399
1400		/* generate port state response to notify VF it is ready */
1401		fm10k_tlv_msg_init(msg, FM10K_VF_MSG_ID_LPORT_STATE);
1402		fm10k_tlv_attr_put_bool(msg, FM10K_LPORT_STATE_MSG_READY);
1403		mbx->ops.enqueue_tx(hw, mbx, msg);
1404	}
1405
1406	/* if enable state toggled note the update */
1407	if (!err && (!FM10K_VF_FLAG_ENABLED(vf_info) != !mode))
1408		err = fm10k_update_lport_state_pf(hw, vf_info->glort, 1,
1409						  !!mode);
1410
1411	/* if state change succeeded, then update our stored state */
1412	mode |= FM10K_VF_FLAG_CAPABLE(vf_info);
1413	if (!err)
1414		vf_info->vf_flags = mode;
1415
1416	return err;
1417}
1418
1419/**
1420 *  fm10k_update_stats_hw_pf - Updates hardware related statistics of PF
1421 *  @hw: pointer to hardware structure
1422 *  @stats: pointer to the stats structure to update
1423 *
1424 *  This function collects and aggregates global and per queue hardware
1425 *  statistics.
1426 **/
1427static void fm10k_update_hw_stats_pf(struct fm10k_hw *hw,
1428				     struct fm10k_hw_stats *stats)
1429{
1430	u32 timeout, ur, ca, um, xec, vlan_drop, loopback_drop, nodesc_drop;
1431	u32 id, id_prev;
1432
1433	/* Use Tx queue 0 as a canary to detect a reset */
1434	id = fm10k_read_reg(hw, FM10K_TXQCTL(0));
1435
1436	/* Read Global Statistics */
1437	do {
1438		timeout = fm10k_read_hw_stats_32b(hw, FM10K_STATS_TIMEOUT,
1439						  &stats->timeout);
1440		ur = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UR, &stats->ur);
1441		ca = fm10k_read_hw_stats_32b(hw, FM10K_STATS_CA, &stats->ca);
1442		um = fm10k_read_hw_stats_32b(hw, FM10K_STATS_UM, &stats->um);
1443		xec = fm10k_read_hw_stats_32b(hw, FM10K_STATS_XEC, &stats->xec);
1444		vlan_drop = fm10k_read_hw_stats_32b(hw, FM10K_STATS_VLAN_DROP,
1445						    &stats->vlan_drop);
1446		loopback_drop =
1447			fm10k_read_hw_stats_32b(hw,
1448						FM10K_STATS_LOOPBACK_DROP,
1449						&stats->loopback_drop);
1450		nodesc_drop = fm10k_read_hw_stats_32b(hw,
1451						      FM10K_STATS_NODESC_DROP,
1452						      &stats->nodesc_drop);
1453
1454		/* if value has not changed then we have consistent data */
1455		id_prev = id;
1456		id = fm10k_read_reg(hw, FM10K_TXQCTL(0));
1457	} while ((id ^ id_prev) & FM10K_TXQCTL_ID_MASK);
1458
1459	/* drop non-ID bits and set VALID ID bit */
1460	id &= FM10K_TXQCTL_ID_MASK;
1461	id |= FM10K_STAT_VALID;
1462
1463	/* Update Global Statistics */
1464	if (stats->stats_idx == id) {
1465		stats->timeout.count += timeout;
1466		stats->ur.count += ur;
1467		stats->ca.count += ca;
1468		stats->um.count += um;
1469		stats->xec.count += xec;
1470		stats->vlan_drop.count += vlan_drop;
1471		stats->loopback_drop.count += loopback_drop;
1472		stats->nodesc_drop.count += nodesc_drop;
1473	}
1474
1475	/* Update bases and record current PF id */
1476	fm10k_update_hw_base_32b(&stats->timeout, timeout);
1477	fm10k_update_hw_base_32b(&stats->ur, ur);
1478	fm10k_update_hw_base_32b(&stats->ca, ca);
1479	fm10k_update_hw_base_32b(&stats->um, um);
1480	fm10k_update_hw_base_32b(&stats->xec, xec);
1481	fm10k_update_hw_base_32b(&stats->vlan_drop, vlan_drop);
1482	fm10k_update_hw_base_32b(&stats->loopback_drop, loopback_drop);
1483	fm10k_update_hw_base_32b(&stats->nodesc_drop, nodesc_drop);
1484	stats->stats_idx = id;
1485
1486	/* Update Queue Statistics */
1487	fm10k_update_hw_stats_q(hw, stats->q, 0, hw->mac.max_queues);
1488}
1489
1490/**
1491 *  fm10k_rebind_hw_stats_pf - Resets base for hardware statistics of PF
1492 *  @hw: pointer to hardware structure
1493 *  @stats: pointer to the stats structure to update
1494 *
1495 *  This function resets the base for global and per queue hardware
1496 *  statistics.
1497 **/
1498static void fm10k_rebind_hw_stats_pf(struct fm10k_hw *hw,
1499				     struct fm10k_hw_stats *stats)
1500{
1501	/* Unbind Global Statistics */
1502	fm10k_unbind_hw_stats_32b(&stats->timeout);
1503	fm10k_unbind_hw_stats_32b(&stats->ur);
1504	fm10k_unbind_hw_stats_32b(&stats->ca);
1505	fm10k_unbind_hw_stats_32b(&stats->um);
1506	fm10k_unbind_hw_stats_32b(&stats->xec);
1507	fm10k_unbind_hw_stats_32b(&stats->vlan_drop);
1508	fm10k_unbind_hw_stats_32b(&stats->loopback_drop);
1509	fm10k_unbind_hw_stats_32b(&stats->nodesc_drop);
1510
1511	/* Unbind Queue Statistics */
1512	fm10k_unbind_hw_stats_q(stats->q, 0, hw->mac.max_queues);
1513
1514	/* Reinitialize bases for all stats */
1515	fm10k_update_hw_stats_pf(hw, stats);
1516}
1517
1518/**
1519 *  fm10k_set_dma_mask_pf - Configures PhyAddrSpace to limit DMA to system
1520 *  @hw: pointer to hardware structure
1521 *  @dma_mask: 64 bit DMA mask required for platform
1522 *
1523 *  This function sets the PHYADDR.PhyAddrSpace bits for the endpoint in order
1524 *  to limit the access to memory beyond what is physically in the system.
1525 **/
1526static void fm10k_set_dma_mask_pf(struct fm10k_hw *hw, u64 dma_mask)
1527{
1528	/* we need to write the upper 32 bits of DMA mask to PhyAddrSpace */
1529	u32 phyaddr = (u32)(dma_mask >> 32);
1530
1531	fm10k_write_reg(hw, FM10K_PHYADDR, phyaddr);
1532}
1533
1534/**
1535 *  fm10k_get_fault_pf - Record a fault in one of the interface units
1536 *  @hw: pointer to hardware structure
1537 *  @type: pointer to fault type register offset
1538 *  @fault: pointer to memory location to record the fault
1539 *
1540 *  Record the fault register contents to the fault data structure and
1541 *  clear the entry from the register.
1542 *
1543 *  Returns ERR_PARAM if invalid register is specified or no error is present.
1544 **/
1545static s32 fm10k_get_fault_pf(struct fm10k_hw *hw, int type,
1546			      struct fm10k_fault *fault)
1547{
1548	u32 func;
1549
1550	/* verify the fault register is in range and is aligned */
1551	switch (type) {
1552	case FM10K_PCA_FAULT:
1553	case FM10K_THI_FAULT:
1554	case FM10K_FUM_FAULT:
1555		break;
1556	default:
1557		return FM10K_ERR_PARAM;
1558	}
1559
1560	/* only service faults that are valid */
1561	func = fm10k_read_reg(hw, type + FM10K_FAULT_FUNC);
1562	if (!(func & FM10K_FAULT_FUNC_VALID))
1563		return FM10K_ERR_PARAM;
1564
1565	/* read remaining fields */
1566	fault->address = fm10k_read_reg(hw, type + FM10K_FAULT_ADDR_HI);
1567	fault->address <<= 32;
1568	fault->address |= fm10k_read_reg(hw, type + FM10K_FAULT_ADDR_LO);
1569	fault->specinfo = fm10k_read_reg(hw, type + FM10K_FAULT_SPECINFO);
1570
1571	/* clear valid bit to allow for next error */
1572	fm10k_write_reg(hw, type + FM10K_FAULT_FUNC, FM10K_FAULT_FUNC_VALID);
1573
1574	/* Record which function triggered the error */
1575	if (func & FM10K_FAULT_FUNC_PF)
1576		fault->func = 0;
1577	else
1578		fault->func = 1 + ((func & FM10K_FAULT_FUNC_VF_MASK) >>
1579				   FM10K_FAULT_FUNC_VF_SHIFT);
1580
1581	/* record fault type */
1582	fault->type = func & FM10K_FAULT_FUNC_TYPE_MASK;
1583
1584	return 0;
1585}
1586
1587/**
1588 *  fm10k_request_lport_map_pf - Request LPORT map from the switch API
1589 *  @hw: pointer to hardware structure
1590 *
1591 **/
1592static s32 fm10k_request_lport_map_pf(struct fm10k_hw *hw)
1593{
1594	struct fm10k_mbx_info *mbx = &hw->mbx;
1595	u32 msg[1];
1596
1597	/* issue request asking for LPORT map */
1598	fm10k_tlv_msg_init(msg, FM10K_PF_MSG_ID_LPORT_MAP);
1599
1600	/* load onto outgoing mailbox */
1601	return mbx->ops.enqueue_tx(hw, mbx, msg);
1602}
1603
1604/**
1605 *  fm10k_get_host_state_pf - Returns the state of the switch and mailbox
1606 *  @hw: pointer to hardware structure
1607 *  @switch_ready: pointer to boolean value that will record switch state
1608 *
1609 *  This function will check the DMA_CTRL2 register and mailbox in order
1610 *  to determine if the switch is ready for the PF to begin requesting
1611 *  addresses and mapping traffic to the local interface.
1612 **/
1613static s32 fm10k_get_host_state_pf(struct fm10k_hw *hw, bool *switch_ready)
1614{
1615	u32 dma_ctrl2;
1616
1617	/* verify the switch is ready for interaction */
1618	dma_ctrl2 = fm10k_read_reg(hw, FM10K_DMA_CTRL2);
1619	if (!(dma_ctrl2 & FM10K_DMA_CTRL2_SWITCH_READY))
1620		return 0;
1621
1622	/* retrieve generic host state info */
1623	return fm10k_get_host_state_generic(hw, switch_ready);
1624}
1625
1626/* This structure defines the attibutes to be parsed below */
1627const struct fm10k_tlv_attr fm10k_lport_map_msg_attr[] = {
1628	FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_ERR,
1629				 sizeof(struct fm10k_swapi_error)),
1630	FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_LPORT_MAP),
1631	FM10K_TLV_ATTR_LAST
1632};
1633
1634/**
1635 *  fm10k_msg_lport_map_pf - Message handler for lport_map message from SM
1636 *  @hw: Pointer to hardware structure
1637 *  @results: pointer array containing parsed data
1638 *  @mbx: Pointer to mailbox information structure
1639 *
1640 *  This handler configures the lport mapping based on the reply from the
1641 *  switch API.
1642 **/
1643s32 fm10k_msg_lport_map_pf(struct fm10k_hw *hw, u32 **results,
1644			   struct fm10k_mbx_info __always_unused *mbx)
1645{
1646	u16 glort, mask;
1647	u32 dglort_map;
1648	s32 err;
1649
1650	err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_LPORT_MAP],
1651				     &dglort_map);
1652	if (err)
1653		return err;
1654
1655	/* extract values out of the header */
1656	glort = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_GLORT);
1657	mask = FM10K_MSG_HDR_FIELD_GET(dglort_map, LPORT_MAP_MASK);
1658
1659	/* verify mask is set and none of the masked bits in glort are set */
1660	if (!mask || (glort & ~mask))
1661		return FM10K_ERR_PARAM;
1662
1663	/* verify the mask is contiguous, and that it is 1's followed by 0's */
1664	if (((~(mask - 1) & mask) + mask) & FM10K_DGLORTMAP_NONE)
1665		return FM10K_ERR_PARAM;
1666
1667	/* record the glort, mask, and port count */
1668	hw->mac.dglort_map = dglort_map;
1669
1670	return 0;
1671}
1672
1673const struct fm10k_tlv_attr fm10k_update_pvid_msg_attr[] = {
1674	FM10K_TLV_ATTR_U32(FM10K_PF_ATTR_ID_UPDATE_PVID),
1675	FM10K_TLV_ATTR_LAST
1676};
1677
1678/**
1679 *  fm10k_msg_update_pvid_pf - Message handler for port VLAN message from SM
1680 *  @hw: Pointer to hardware structure
1681 *  @results: pointer array containing parsed data
1682 *  @mbx: Pointer to mailbox information structure
1683 *
1684 *  This handler configures the default VLAN for the PF
1685 **/
1686static s32 fm10k_msg_update_pvid_pf(struct fm10k_hw *hw, u32 **results,
1687				    struct fm10k_mbx_info __always_unused *mbx)
1688{
1689	u16 glort, pvid;
1690	u32 pvid_update;
1691	s32 err;
1692
1693	err = fm10k_tlv_attr_get_u32(results[FM10K_PF_ATTR_ID_UPDATE_PVID],
1694				     &pvid_update);
1695	if (err)
1696		return err;
1697
1698	/* extract values from the pvid update */
1699	glort = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_GLORT);
1700	pvid = FM10K_MSG_HDR_FIELD_GET(pvid_update, UPDATE_PVID_PVID);
1701
1702	/* if glort is not valid return error */
1703	if (!fm10k_glort_valid_pf(hw, glort))
1704		return FM10K_ERR_PARAM;
1705
1706	/* verify VLAN ID is valid */
1707	if (pvid >= FM10K_VLAN_TABLE_VID_MAX)
1708		return FM10K_ERR_PARAM;
1709
1710	/* record the port VLAN ID value */
1711	hw->mac.default_vid = pvid;
1712
1713	return 0;
1714}
1715
1716/**
1717 *  fm10k_record_global_table_data - Move global table data to swapi table info
1718 *  @from: pointer to source table data structure
1719 *  @to: pointer to destination table info structure
1720 *
1721 *  This function is will copy table_data to the table_info contained in
1722 *  the hw struct.
1723 **/
1724static void fm10k_record_global_table_data(struct fm10k_global_table_data *from,
1725					   struct fm10k_swapi_table_info *to)
1726{
1727	/* convert from le32 struct to CPU byte ordered values */
1728	to->used = le32_to_cpu(from->used);
1729	to->avail = le32_to_cpu(from->avail);
1730}
1731
1732const struct fm10k_tlv_attr fm10k_err_msg_attr[] = {
1733	FM10K_TLV_ATTR_LE_STRUCT(FM10K_PF_ATTR_ID_ERR,
1734				 sizeof(struct fm10k_swapi_error)),
1735	FM10K_TLV_ATTR_LAST
1736};
1737
1738/**
1739 *  fm10k_msg_err_pf - Message handler for error reply
1740 *  @hw: Pointer to hardware structure
1741 *  @results: pointer array containing parsed data
1742 *  @mbx: Pointer to mailbox information structure
1743 *
1744 *  This handler will capture the data for any error replies to previous
1745 *  messages that the PF has sent.
1746 **/
1747s32 fm10k_msg_err_pf(struct fm10k_hw *hw, u32 **results,
1748		     struct fm10k_mbx_info __always_unused *mbx)
1749{
1750	struct fm10k_swapi_error err_msg;
1751	s32 err;
1752
1753	/* extract structure from message */
1754	err = fm10k_tlv_attr_get_le_struct(results[FM10K_PF_ATTR_ID_ERR],
1755					   &err_msg, sizeof(err_msg));
1756	if (err)
1757		return err;
1758
1759	/* record table status */
1760	fm10k_record_global_table_data(&err_msg.mac, &hw->swapi.mac);
1761	fm10k_record_global_table_data(&err_msg.nexthop, &hw->swapi.nexthop);
1762	fm10k_record_global_table_data(&err_msg.ffu, &hw->swapi.ffu);
1763
1764	/* record SW API status value */
1765	hw->swapi.status = le32_to_cpu(err_msg.status);
1766
1767	return 0;
1768}
1769
1770static const struct fm10k_msg_data fm10k_msg_data_pf[] = {
1771	FM10K_PF_MSG_ERR_HANDLER(XCAST_MODES, fm10k_msg_err_pf),
1772	FM10K_PF_MSG_ERR_HANDLER(UPDATE_MAC_FWD_RULE, fm10k_msg_err_pf),
1773	FM10K_PF_MSG_LPORT_MAP_HANDLER(fm10k_msg_lport_map_pf),
1774	FM10K_PF_MSG_ERR_HANDLER(LPORT_CREATE, fm10k_msg_err_pf),
1775	FM10K_PF_MSG_ERR_HANDLER(LPORT_DELETE, fm10k_msg_err_pf),
1776	FM10K_PF_MSG_UPDATE_PVID_HANDLER(fm10k_msg_update_pvid_pf),
1777	FM10K_TLV_MSG_ERROR_HANDLER(fm10k_tlv_msg_error),
1778};
1779
1780static const struct fm10k_mac_ops mac_ops_pf = {
1781	.get_bus_info		= fm10k_get_bus_info_generic,
1782	.reset_hw		= fm10k_reset_hw_pf,
1783	.init_hw		= fm10k_init_hw_pf,
1784	.start_hw		= fm10k_start_hw_generic,
1785	.stop_hw		= fm10k_stop_hw_generic,
1786	.update_vlan		= fm10k_update_vlan_pf,
1787	.read_mac_addr		= fm10k_read_mac_addr_pf,
1788	.update_uc_addr		= fm10k_update_uc_addr_pf,
1789	.update_mc_addr		= fm10k_update_mc_addr_pf,
1790	.update_xcast_mode	= fm10k_update_xcast_mode_pf,
1791	.update_int_moderator	= fm10k_update_int_moderator_pf,
1792	.update_lport_state	= fm10k_update_lport_state_pf,
1793	.update_hw_stats	= fm10k_update_hw_stats_pf,
1794	.rebind_hw_stats	= fm10k_rebind_hw_stats_pf,
1795	.configure_dglort_map	= fm10k_configure_dglort_map_pf,
1796	.set_dma_mask		= fm10k_set_dma_mask_pf,
1797	.get_fault		= fm10k_get_fault_pf,
1798	.get_host_state		= fm10k_get_host_state_pf,
1799	.request_lport_map	= fm10k_request_lport_map_pf,
1800};
1801
1802static const struct fm10k_iov_ops iov_ops_pf = {
1803	.assign_resources		= fm10k_iov_assign_resources_pf,
1804	.configure_tc			= fm10k_iov_configure_tc_pf,
1805	.assign_int_moderator		= fm10k_iov_assign_int_moderator_pf,
1806	.assign_default_mac_vlan	= fm10k_iov_assign_default_mac_vlan_pf,
1807	.reset_resources		= fm10k_iov_reset_resources_pf,
1808	.set_lport			= fm10k_iov_set_lport_pf,
1809	.reset_lport			= fm10k_iov_reset_lport_pf,
1810	.update_stats			= fm10k_iov_update_stats_pf,
1811};
1812
1813static s32 fm10k_get_invariants_pf(struct fm10k_hw *hw)
1814{
1815	fm10k_get_invariants_generic(hw);
1816
1817	return fm10k_sm_mbx_init(hw, &hw->mbx, fm10k_msg_data_pf);
1818}
1819
1820const struct fm10k_info fm10k_pf_info = {
1821	.mac		= fm10k_mac_pf,
1822	.get_invariants	= fm10k_get_invariants_pf,
1823	.mac_ops	= &mac_ops_pf,
1824	.iov_ops	= &iov_ops_pf,
1825};