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1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Freescale MPC85xx, MPC83xx DMA Engine support
4 *
5 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
6 *
7 * Author:
8 * Zhang Wei <wei.zhang@freescale.com>, Jul 2007
9 * Ebony Zhu <ebony.zhu@freescale.com>, May 2007
10 *
11 * Description:
12 * DMA engine driver for Freescale MPC8540 DMA controller, which is
13 * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc.
14 * The support for MPC8349 DMA controller is also added.
15 *
16 * This driver instructs the DMA controller to issue the PCI Read Multiple
17 * command for PCI read operations, instead of using the default PCI Read Line
18 * command. Please be aware that this setting may result in read pre-fetching
19 * on some platforms.
20 */
21
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/pci.h>
25#include <linux/slab.h>
26#include <linux/interrupt.h>
27#include <linux/dmaengine.h>
28#include <linux/delay.h>
29#include <linux/dma-mapping.h>
30#include <linux/dmapool.h>
31#include <linux/of_address.h>
32#include <linux/of_irq.h>
33#include <linux/of_platform.h>
34#include <linux/fsldma.h>
35#include "dmaengine.h"
36#include "fsldma.h"
37
38#define chan_dbg(chan, fmt, arg...) \
39 dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
40#define chan_err(chan, fmt, arg...) \
41 dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
42
43static const char msg_ld_oom[] = "No free memory for link descriptor";
44
45/*
46 * Register Helpers
47 */
48
49static void set_sr(struct fsldma_chan *chan, u32 val)
50{
51 FSL_DMA_OUT(chan, &chan->regs->sr, val, 32);
52}
53
54static u32 get_sr(struct fsldma_chan *chan)
55{
56 return FSL_DMA_IN(chan, &chan->regs->sr, 32);
57}
58
59static void set_mr(struct fsldma_chan *chan, u32 val)
60{
61 FSL_DMA_OUT(chan, &chan->regs->mr, val, 32);
62}
63
64static u32 get_mr(struct fsldma_chan *chan)
65{
66 return FSL_DMA_IN(chan, &chan->regs->mr, 32);
67}
68
69static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr)
70{
71 FSL_DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
72}
73
74static dma_addr_t get_cdar(struct fsldma_chan *chan)
75{
76 return FSL_DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
77}
78
79static void set_bcr(struct fsldma_chan *chan, u32 val)
80{
81 FSL_DMA_OUT(chan, &chan->regs->bcr, val, 32);
82}
83
84static u32 get_bcr(struct fsldma_chan *chan)
85{
86 return FSL_DMA_IN(chan, &chan->regs->bcr, 32);
87}
88
89/*
90 * Descriptor Helpers
91 */
92
93static void set_desc_cnt(struct fsldma_chan *chan,
94 struct fsl_dma_ld_hw *hw, u32 count)
95{
96 hw->count = CPU_TO_DMA(chan, count, 32);
97}
98
99static void set_desc_src(struct fsldma_chan *chan,
100 struct fsl_dma_ld_hw *hw, dma_addr_t src)
101{
102 u64 snoop_bits;
103
104 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
105 ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0;
106 hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64);
107}
108
109static void set_desc_dst(struct fsldma_chan *chan,
110 struct fsl_dma_ld_hw *hw, dma_addr_t dst)
111{
112 u64 snoop_bits;
113
114 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
115 ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
116 hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64);
117}
118
119static void set_desc_next(struct fsldma_chan *chan,
120 struct fsl_dma_ld_hw *hw, dma_addr_t next)
121{
122 u64 snoop_bits;
123
124 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
125 ? FSL_DMA_SNEN : 0;
126 hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64);
127}
128
129static void set_ld_eol(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
130{
131 u64 snoop_bits;
132
133 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
134 ? FSL_DMA_SNEN : 0;
135
136 desc->hw.next_ln_addr = CPU_TO_DMA(chan,
137 DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
138 | snoop_bits, 64);
139}
140
141/*
142 * DMA Engine Hardware Control Helpers
143 */
144
145static void dma_init(struct fsldma_chan *chan)
146{
147 /* Reset the channel */
148 set_mr(chan, 0);
149
150 switch (chan->feature & FSL_DMA_IP_MASK) {
151 case FSL_DMA_IP_85XX:
152 /* Set the channel to below modes:
153 * EIE - Error interrupt enable
154 * EOLNIE - End of links interrupt enable
155 * BWC - Bandwidth sharing among channels
156 */
157 set_mr(chan, FSL_DMA_MR_BWC | FSL_DMA_MR_EIE
158 | FSL_DMA_MR_EOLNIE);
159 break;
160 case FSL_DMA_IP_83XX:
161 /* Set the channel to below modes:
162 * EOTIE - End-of-transfer interrupt enable
163 * PRC_RM - PCI read multiple
164 */
165 set_mr(chan, FSL_DMA_MR_EOTIE | FSL_DMA_MR_PRC_RM);
166 break;
167 }
168}
169
170static int dma_is_idle(struct fsldma_chan *chan)
171{
172 u32 sr = get_sr(chan);
173 return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH);
174}
175
176/*
177 * Start the DMA controller
178 *
179 * Preconditions:
180 * - the CDAR register must point to the start descriptor
181 * - the MRn[CS] bit must be cleared
182 */
183static void dma_start(struct fsldma_chan *chan)
184{
185 u32 mode;
186
187 mode = get_mr(chan);
188
189 if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
190 set_bcr(chan, 0);
191 mode |= FSL_DMA_MR_EMP_EN;
192 } else {
193 mode &= ~FSL_DMA_MR_EMP_EN;
194 }
195
196 if (chan->feature & FSL_DMA_CHAN_START_EXT) {
197 mode |= FSL_DMA_MR_EMS_EN;
198 } else {
199 mode &= ~FSL_DMA_MR_EMS_EN;
200 mode |= FSL_DMA_MR_CS;
201 }
202
203 set_mr(chan, mode);
204}
205
206static void dma_halt(struct fsldma_chan *chan)
207{
208 u32 mode;
209 int i;
210
211 /* read the mode register */
212 mode = get_mr(chan);
213
214 /*
215 * The 85xx controller supports channel abort, which will stop
216 * the current transfer. On 83xx, this bit is the transfer error
217 * mask bit, which should not be changed.
218 */
219 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
220 mode |= FSL_DMA_MR_CA;
221 set_mr(chan, mode);
222
223 mode &= ~FSL_DMA_MR_CA;
224 }
225
226 /* stop the DMA controller */
227 mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN);
228 set_mr(chan, mode);
229
230 /* wait for the DMA controller to become idle */
231 for (i = 0; i < 100; i++) {
232 if (dma_is_idle(chan))
233 return;
234
235 udelay(10);
236 }
237
238 if (!dma_is_idle(chan))
239 chan_err(chan, "DMA halt timeout!\n");
240}
241
242/**
243 * fsl_chan_set_src_loop_size - Set source address hold transfer size
244 * @chan : Freescale DMA channel
245 * @size : Address loop size, 0 for disable loop
246 *
247 * The set source address hold transfer size. The source
248 * address hold or loop transfer size is when the DMA transfer
249 * data from source address (SA), if the loop size is 4, the DMA will
250 * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA,
251 * SA + 1 ... and so on.
252 */
253static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size)
254{
255 u32 mode;
256
257 mode = get_mr(chan);
258
259 switch (size) {
260 case 0:
261 mode &= ~FSL_DMA_MR_SAHE;
262 break;
263 case 1:
264 case 2:
265 case 4:
266 case 8:
267 mode &= ~FSL_DMA_MR_SAHTS_MASK;
268 mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14);
269 break;
270 }
271
272 set_mr(chan, mode);
273}
274
275/**
276 * fsl_chan_set_dst_loop_size - Set destination address hold transfer size
277 * @chan : Freescale DMA channel
278 * @size : Address loop size, 0 for disable loop
279 *
280 * The set destination address hold transfer size. The destination
281 * address hold or loop transfer size is when the DMA transfer
282 * data to destination address (TA), if the loop size is 4, the DMA will
283 * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA,
284 * TA + 1 ... and so on.
285 */
286static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size)
287{
288 u32 mode;
289
290 mode = get_mr(chan);
291
292 switch (size) {
293 case 0:
294 mode &= ~FSL_DMA_MR_DAHE;
295 break;
296 case 1:
297 case 2:
298 case 4:
299 case 8:
300 mode &= ~FSL_DMA_MR_DAHTS_MASK;
301 mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16);
302 break;
303 }
304
305 set_mr(chan, mode);
306}
307
308/**
309 * fsl_chan_set_request_count - Set DMA Request Count for external control
310 * @chan : Freescale DMA channel
311 * @size : Number of bytes to transfer in a single request
312 *
313 * The Freescale DMA channel can be controlled by the external signal DREQ#.
314 * The DMA request count is how many bytes are allowed to transfer before
315 * pausing the channel, after which a new assertion of DREQ# resumes channel
316 * operation.
317 *
318 * A size of 0 disables external pause control. The maximum size is 1024.
319 */
320static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size)
321{
322 u32 mode;
323
324 BUG_ON(size > 1024);
325
326 mode = get_mr(chan);
327 mode &= ~FSL_DMA_MR_BWC_MASK;
328 mode |= (__ilog2(size) << 24) & FSL_DMA_MR_BWC_MASK;
329
330 set_mr(chan, mode);
331}
332
333/**
334 * fsl_chan_toggle_ext_pause - Toggle channel external pause status
335 * @chan : Freescale DMA channel
336 * @enable : 0 is disabled, 1 is enabled.
337 *
338 * The Freescale DMA channel can be controlled by the external signal DREQ#.
339 * The DMA Request Count feature should be used in addition to this feature
340 * to set the number of bytes to transfer before pausing the channel.
341 */
342static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable)
343{
344 if (enable)
345 chan->feature |= FSL_DMA_CHAN_PAUSE_EXT;
346 else
347 chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT;
348}
349
350/**
351 * fsl_chan_toggle_ext_start - Toggle channel external start status
352 * @chan : Freescale DMA channel
353 * @enable : 0 is disabled, 1 is enabled.
354 *
355 * If enable the external start, the channel can be started by an
356 * external DMA start pin. So the dma_start() does not start the
357 * transfer immediately. The DMA channel will wait for the
358 * control pin asserted.
359 */
360static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable)
361{
362 if (enable)
363 chan->feature |= FSL_DMA_CHAN_START_EXT;
364 else
365 chan->feature &= ~FSL_DMA_CHAN_START_EXT;
366}
367
368int fsl_dma_external_start(struct dma_chan *dchan, int enable)
369{
370 struct fsldma_chan *chan;
371
372 if (!dchan)
373 return -EINVAL;
374
375 chan = to_fsl_chan(dchan);
376
377 fsl_chan_toggle_ext_start(chan, enable);
378 return 0;
379}
380EXPORT_SYMBOL_GPL(fsl_dma_external_start);
381
382static void append_ld_queue(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
383{
384 struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev);
385
386 if (list_empty(&chan->ld_pending))
387 goto out_splice;
388
389 /*
390 * Add the hardware descriptor to the chain of hardware descriptors
391 * that already exists in memory.
392 *
393 * This will un-set the EOL bit of the existing transaction, and the
394 * last link in this transaction will become the EOL descriptor.
395 */
396 set_desc_next(chan, &tail->hw, desc->async_tx.phys);
397
398 /*
399 * Add the software descriptor and all children to the list
400 * of pending transactions
401 */
402out_splice:
403 list_splice_tail_init(&desc->tx_list, &chan->ld_pending);
404}
405
406static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
407{
408 struct fsldma_chan *chan = to_fsl_chan(tx->chan);
409 struct fsl_desc_sw *desc = tx_to_fsl_desc(tx);
410 struct fsl_desc_sw *child;
411 dma_cookie_t cookie = -EINVAL;
412
413 spin_lock_bh(&chan->desc_lock);
414
415#ifdef CONFIG_PM
416 if (unlikely(chan->pm_state != RUNNING)) {
417 chan_dbg(chan, "cannot submit due to suspend\n");
418 spin_unlock_bh(&chan->desc_lock);
419 return -1;
420 }
421#endif
422
423 /*
424 * assign cookies to all of the software descriptors
425 * that make up this transaction
426 */
427 list_for_each_entry(child, &desc->tx_list, node) {
428 cookie = dma_cookie_assign(&child->async_tx);
429 }
430
431 /* put this transaction onto the tail of the pending queue */
432 append_ld_queue(chan, desc);
433
434 spin_unlock_bh(&chan->desc_lock);
435
436 return cookie;
437}
438
439/**
440 * fsl_dma_free_descriptor - Free descriptor from channel's DMA pool.
441 * @chan : Freescale DMA channel
442 * @desc: descriptor to be freed
443 */
444static void fsl_dma_free_descriptor(struct fsldma_chan *chan,
445 struct fsl_desc_sw *desc)
446{
447 list_del(&desc->node);
448 chan_dbg(chan, "LD %p free\n", desc);
449 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
450}
451
452/**
453 * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
454 * @chan : Freescale DMA channel
455 *
456 * Return - The descriptor allocated. NULL for failed.
457 */
458static struct fsl_desc_sw *fsl_dma_alloc_descriptor(struct fsldma_chan *chan)
459{
460 struct fsl_desc_sw *desc;
461 dma_addr_t pdesc;
462
463 desc = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &pdesc);
464 if (!desc) {
465 chan_dbg(chan, "out of memory for link descriptor\n");
466 return NULL;
467 }
468
469 INIT_LIST_HEAD(&desc->tx_list);
470 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
471 desc->async_tx.tx_submit = fsl_dma_tx_submit;
472 desc->async_tx.phys = pdesc;
473
474 chan_dbg(chan, "LD %p allocated\n", desc);
475
476 return desc;
477}
478
479/**
480 * fsldma_clean_completed_descriptor - free all descriptors which
481 * has been completed and acked
482 * @chan: Freescale DMA channel
483 *
484 * This function is used on all completed and acked descriptors.
485 * All descriptors should only be freed in this function.
486 */
487static void fsldma_clean_completed_descriptor(struct fsldma_chan *chan)
488{
489 struct fsl_desc_sw *desc, *_desc;
490
491 /* Run the callback for each descriptor, in order */
492 list_for_each_entry_safe(desc, _desc, &chan->ld_completed, node)
493 if (async_tx_test_ack(&desc->async_tx))
494 fsl_dma_free_descriptor(chan, desc);
495}
496
497/**
498 * fsldma_run_tx_complete_actions - cleanup a single link descriptor
499 * @chan: Freescale DMA channel
500 * @desc: descriptor to cleanup and free
501 * @cookie: Freescale DMA transaction identifier
502 *
503 * This function is used on a descriptor which has been executed by the DMA
504 * controller. It will run any callbacks, submit any dependencies.
505 */
506static dma_cookie_t fsldma_run_tx_complete_actions(struct fsldma_chan *chan,
507 struct fsl_desc_sw *desc, dma_cookie_t cookie)
508{
509 struct dma_async_tx_descriptor *txd = &desc->async_tx;
510 dma_cookie_t ret = cookie;
511
512 BUG_ON(txd->cookie < 0);
513
514 if (txd->cookie > 0) {
515 ret = txd->cookie;
516
517 dma_descriptor_unmap(txd);
518 /* Run the link descriptor callback function */
519 dmaengine_desc_get_callback_invoke(txd, NULL);
520 }
521
522 /* Run any dependencies */
523 dma_run_dependencies(txd);
524
525 return ret;
526}
527
528/**
529 * fsldma_clean_running_descriptor - move the completed descriptor from
530 * ld_running to ld_completed
531 * @chan: Freescale DMA channel
532 * @desc: the descriptor which is completed
533 *
534 * Free the descriptor directly if acked by async_tx api, or move it to
535 * queue ld_completed.
536 */
537static void fsldma_clean_running_descriptor(struct fsldma_chan *chan,
538 struct fsl_desc_sw *desc)
539{
540 /* Remove from the list of transactions */
541 list_del(&desc->node);
542
543 /*
544 * the client is allowed to attach dependent operations
545 * until 'ack' is set
546 */
547 if (!async_tx_test_ack(&desc->async_tx)) {
548 /*
549 * Move this descriptor to the list of descriptors which is
550 * completed, but still awaiting the 'ack' bit to be set.
551 */
552 list_add_tail(&desc->node, &chan->ld_completed);
553 return;
554 }
555
556 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
557}
558
559/**
560 * fsl_chan_xfer_ld_queue - transfer any pending transactions
561 * @chan : Freescale DMA channel
562 *
563 * HARDWARE STATE: idle
564 * LOCKING: must hold chan->desc_lock
565 */
566static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan)
567{
568 struct fsl_desc_sw *desc;
569
570 /*
571 * If the list of pending descriptors is empty, then we
572 * don't need to do any work at all
573 */
574 if (list_empty(&chan->ld_pending)) {
575 chan_dbg(chan, "no pending LDs\n");
576 return;
577 }
578
579 /*
580 * The DMA controller is not idle, which means that the interrupt
581 * handler will start any queued transactions when it runs after
582 * this transaction finishes
583 */
584 if (!chan->idle) {
585 chan_dbg(chan, "DMA controller still busy\n");
586 return;
587 }
588
589 /*
590 * If there are some link descriptors which have not been
591 * transferred, we need to start the controller
592 */
593
594 /*
595 * Move all elements from the queue of pending transactions
596 * onto the list of running transactions
597 */
598 chan_dbg(chan, "idle, starting controller\n");
599 desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node);
600 list_splice_tail_init(&chan->ld_pending, &chan->ld_running);
601
602 /*
603 * The 85xx DMA controller doesn't clear the channel start bit
604 * automatically at the end of a transfer. Therefore we must clear
605 * it in software before starting the transfer.
606 */
607 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
608 u32 mode;
609
610 mode = get_mr(chan);
611 mode &= ~FSL_DMA_MR_CS;
612 set_mr(chan, mode);
613 }
614
615 /*
616 * Program the descriptor's address into the DMA controller,
617 * then start the DMA transaction
618 */
619 set_cdar(chan, desc->async_tx.phys);
620 get_cdar(chan);
621
622 dma_start(chan);
623 chan->idle = false;
624}
625
626/**
627 * fsldma_cleanup_descriptors - cleanup link descriptors which are completed
628 * and move them to ld_completed to free until flag 'ack' is set
629 * @chan: Freescale DMA channel
630 *
631 * This function is used on descriptors which have been executed by the DMA
632 * controller. It will run any callbacks, submit any dependencies, then
633 * free these descriptors if flag 'ack' is set.
634 */
635static void fsldma_cleanup_descriptors(struct fsldma_chan *chan)
636{
637 struct fsl_desc_sw *desc, *_desc;
638 dma_cookie_t cookie = 0;
639 dma_addr_t curr_phys = get_cdar(chan);
640 int seen_current = 0;
641
642 fsldma_clean_completed_descriptor(chan);
643
644 /* Run the callback for each descriptor, in order */
645 list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) {
646 /*
647 * do not advance past the current descriptor loaded into the
648 * hardware channel, subsequent descriptors are either in
649 * process or have not been submitted
650 */
651 if (seen_current)
652 break;
653
654 /*
655 * stop the search if we reach the current descriptor and the
656 * channel is busy
657 */
658 if (desc->async_tx.phys == curr_phys) {
659 seen_current = 1;
660 if (!dma_is_idle(chan))
661 break;
662 }
663
664 cookie = fsldma_run_tx_complete_actions(chan, desc, cookie);
665
666 fsldma_clean_running_descriptor(chan, desc);
667 }
668
669 /*
670 * Start any pending transactions automatically
671 *
672 * In the ideal case, we keep the DMA controller busy while we go
673 * ahead and free the descriptors below.
674 */
675 fsl_chan_xfer_ld_queue(chan);
676
677 if (cookie > 0)
678 chan->common.completed_cookie = cookie;
679}
680
681/**
682 * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
683 * @chan : Freescale DMA channel
684 *
685 * This function will create a dma pool for descriptor allocation.
686 *
687 * Return - The number of descriptors allocated.
688 */
689static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan)
690{
691 struct fsldma_chan *chan = to_fsl_chan(dchan);
692
693 /* Has this channel already been allocated? */
694 if (chan->desc_pool)
695 return 1;
696
697 /*
698 * We need the descriptor to be aligned to 32bytes
699 * for meeting FSL DMA specification requirement.
700 */
701 chan->desc_pool = dma_pool_create(chan->name, chan->dev,
702 sizeof(struct fsl_desc_sw),
703 __alignof__(struct fsl_desc_sw), 0);
704 if (!chan->desc_pool) {
705 chan_err(chan, "unable to allocate descriptor pool\n");
706 return -ENOMEM;
707 }
708
709 /* there is at least one descriptor free to be allocated */
710 return 1;
711}
712
713/**
714 * fsldma_free_desc_list - Free all descriptors in a queue
715 * @chan: Freescae DMA channel
716 * @list: the list to free
717 *
718 * LOCKING: must hold chan->desc_lock
719 */
720static void fsldma_free_desc_list(struct fsldma_chan *chan,
721 struct list_head *list)
722{
723 struct fsl_desc_sw *desc, *_desc;
724
725 list_for_each_entry_safe(desc, _desc, list, node)
726 fsl_dma_free_descriptor(chan, desc);
727}
728
729static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan,
730 struct list_head *list)
731{
732 struct fsl_desc_sw *desc, *_desc;
733
734 list_for_each_entry_safe_reverse(desc, _desc, list, node)
735 fsl_dma_free_descriptor(chan, desc);
736}
737
738/**
739 * fsl_dma_free_chan_resources - Free all resources of the channel.
740 * @chan : Freescale DMA channel
741 */
742static void fsl_dma_free_chan_resources(struct dma_chan *dchan)
743{
744 struct fsldma_chan *chan = to_fsl_chan(dchan);
745
746 chan_dbg(chan, "free all channel resources\n");
747 spin_lock_bh(&chan->desc_lock);
748 fsldma_cleanup_descriptors(chan);
749 fsldma_free_desc_list(chan, &chan->ld_pending);
750 fsldma_free_desc_list(chan, &chan->ld_running);
751 fsldma_free_desc_list(chan, &chan->ld_completed);
752 spin_unlock_bh(&chan->desc_lock);
753
754 dma_pool_destroy(chan->desc_pool);
755 chan->desc_pool = NULL;
756}
757
758static struct dma_async_tx_descriptor *
759fsl_dma_prep_memcpy(struct dma_chan *dchan,
760 dma_addr_t dma_dst, dma_addr_t dma_src,
761 size_t len, unsigned long flags)
762{
763 struct fsldma_chan *chan;
764 struct fsl_desc_sw *first = NULL, *prev = NULL, *new;
765 size_t copy;
766
767 if (!dchan)
768 return NULL;
769
770 if (!len)
771 return NULL;
772
773 chan = to_fsl_chan(dchan);
774
775 do {
776
777 /* Allocate the link descriptor from DMA pool */
778 new = fsl_dma_alloc_descriptor(chan);
779 if (!new) {
780 chan_err(chan, "%s\n", msg_ld_oom);
781 goto fail;
782 }
783
784 copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT);
785
786 set_desc_cnt(chan, &new->hw, copy);
787 set_desc_src(chan, &new->hw, dma_src);
788 set_desc_dst(chan, &new->hw, dma_dst);
789
790 if (!first)
791 first = new;
792 else
793 set_desc_next(chan, &prev->hw, new->async_tx.phys);
794
795 new->async_tx.cookie = 0;
796 async_tx_ack(&new->async_tx);
797
798 prev = new;
799 len -= copy;
800 dma_src += copy;
801 dma_dst += copy;
802
803 /* Insert the link descriptor to the LD ring */
804 list_add_tail(&new->node, &first->tx_list);
805 } while (len);
806
807 new->async_tx.flags = flags; /* client is in control of this ack */
808 new->async_tx.cookie = -EBUSY;
809
810 /* Set End-of-link to the last link descriptor of new list */
811 set_ld_eol(chan, new);
812
813 return &first->async_tx;
814
815fail:
816 if (!first)
817 return NULL;
818
819 fsldma_free_desc_list_reverse(chan, &first->tx_list);
820 return NULL;
821}
822
823static int fsl_dma_device_terminate_all(struct dma_chan *dchan)
824{
825 struct fsldma_chan *chan;
826
827 if (!dchan)
828 return -EINVAL;
829
830 chan = to_fsl_chan(dchan);
831
832 spin_lock_bh(&chan->desc_lock);
833
834 /* Halt the DMA engine */
835 dma_halt(chan);
836
837 /* Remove and free all of the descriptors in the LD queue */
838 fsldma_free_desc_list(chan, &chan->ld_pending);
839 fsldma_free_desc_list(chan, &chan->ld_running);
840 fsldma_free_desc_list(chan, &chan->ld_completed);
841 chan->idle = true;
842
843 spin_unlock_bh(&chan->desc_lock);
844 return 0;
845}
846
847static int fsl_dma_device_config(struct dma_chan *dchan,
848 struct dma_slave_config *config)
849{
850 struct fsldma_chan *chan;
851 int size;
852
853 if (!dchan)
854 return -EINVAL;
855
856 chan = to_fsl_chan(dchan);
857
858 /* make sure the channel supports setting burst size */
859 if (!chan->set_request_count)
860 return -ENXIO;
861
862 /* we set the controller burst size depending on direction */
863 if (config->direction == DMA_MEM_TO_DEV)
864 size = config->dst_addr_width * config->dst_maxburst;
865 else
866 size = config->src_addr_width * config->src_maxburst;
867
868 chan->set_request_count(chan, size);
869 return 0;
870}
871
872
873/**
874 * fsl_dma_memcpy_issue_pending - Issue the DMA start command
875 * @chan : Freescale DMA channel
876 */
877static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan)
878{
879 struct fsldma_chan *chan = to_fsl_chan(dchan);
880
881 spin_lock_bh(&chan->desc_lock);
882 fsl_chan_xfer_ld_queue(chan);
883 spin_unlock_bh(&chan->desc_lock);
884}
885
886/**
887 * fsl_tx_status - Determine the DMA status
888 * @chan : Freescale DMA channel
889 */
890static enum dma_status fsl_tx_status(struct dma_chan *dchan,
891 dma_cookie_t cookie,
892 struct dma_tx_state *txstate)
893{
894 struct fsldma_chan *chan = to_fsl_chan(dchan);
895 enum dma_status ret;
896
897 ret = dma_cookie_status(dchan, cookie, txstate);
898 if (ret == DMA_COMPLETE)
899 return ret;
900
901 spin_lock_bh(&chan->desc_lock);
902 fsldma_cleanup_descriptors(chan);
903 spin_unlock_bh(&chan->desc_lock);
904
905 return dma_cookie_status(dchan, cookie, txstate);
906}
907
908/*----------------------------------------------------------------------------*/
909/* Interrupt Handling */
910/*----------------------------------------------------------------------------*/
911
912static irqreturn_t fsldma_chan_irq(int irq, void *data)
913{
914 struct fsldma_chan *chan = data;
915 u32 stat;
916
917 /* save and clear the status register */
918 stat = get_sr(chan);
919 set_sr(chan, stat);
920 chan_dbg(chan, "irq: stat = 0x%x\n", stat);
921
922 /* check that this was really our device */
923 stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH);
924 if (!stat)
925 return IRQ_NONE;
926
927 if (stat & FSL_DMA_SR_TE)
928 chan_err(chan, "Transfer Error!\n");
929
930 /*
931 * Programming Error
932 * The DMA_INTERRUPT async_tx is a NULL transfer, which will
933 * trigger a PE interrupt.
934 */
935 if (stat & FSL_DMA_SR_PE) {
936 chan_dbg(chan, "irq: Programming Error INT\n");
937 stat &= ~FSL_DMA_SR_PE;
938 if (get_bcr(chan) != 0)
939 chan_err(chan, "Programming Error!\n");
940 }
941
942 /*
943 * For MPC8349, EOCDI event need to update cookie
944 * and start the next transfer if it exist.
945 */
946 if (stat & FSL_DMA_SR_EOCDI) {
947 chan_dbg(chan, "irq: End-of-Chain link INT\n");
948 stat &= ~FSL_DMA_SR_EOCDI;
949 }
950
951 /*
952 * If it current transfer is the end-of-transfer,
953 * we should clear the Channel Start bit for
954 * prepare next transfer.
955 */
956 if (stat & FSL_DMA_SR_EOLNI) {
957 chan_dbg(chan, "irq: End-of-link INT\n");
958 stat &= ~FSL_DMA_SR_EOLNI;
959 }
960
961 /* check that the DMA controller is really idle */
962 if (!dma_is_idle(chan))
963 chan_err(chan, "irq: controller not idle!\n");
964
965 /* check that we handled all of the bits */
966 if (stat)
967 chan_err(chan, "irq: unhandled sr 0x%08x\n", stat);
968
969 /*
970 * Schedule the tasklet to handle all cleanup of the current
971 * transaction. It will start a new transaction if there is
972 * one pending.
973 */
974 tasklet_schedule(&chan->tasklet);
975 chan_dbg(chan, "irq: Exit\n");
976 return IRQ_HANDLED;
977}
978
979static void dma_do_tasklet(unsigned long data)
980{
981 struct fsldma_chan *chan = (struct fsldma_chan *)data;
982
983 chan_dbg(chan, "tasklet entry\n");
984
985 spin_lock(&chan->desc_lock);
986
987 /* the hardware is now idle and ready for more */
988 chan->idle = true;
989
990 /* Run all cleanup for descriptors which have been completed */
991 fsldma_cleanup_descriptors(chan);
992
993 spin_unlock(&chan->desc_lock);
994
995 chan_dbg(chan, "tasklet exit\n");
996}
997
998static irqreturn_t fsldma_ctrl_irq(int irq, void *data)
999{
1000 struct fsldma_device *fdev = data;
1001 struct fsldma_chan *chan;
1002 unsigned int handled = 0;
1003 u32 gsr, mask;
1004 int i;
1005
1006 gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs)
1007 : in_le32(fdev->regs);
1008 mask = 0xff000000;
1009 dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr);
1010
1011 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1012 chan = fdev->chan[i];
1013 if (!chan)
1014 continue;
1015
1016 if (gsr & mask) {
1017 dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id);
1018 fsldma_chan_irq(irq, chan);
1019 handled++;
1020 }
1021
1022 gsr &= ~mask;
1023 mask >>= 8;
1024 }
1025
1026 return IRQ_RETVAL(handled);
1027}
1028
1029static void fsldma_free_irqs(struct fsldma_device *fdev)
1030{
1031 struct fsldma_chan *chan;
1032 int i;
1033
1034 if (fdev->irq) {
1035 dev_dbg(fdev->dev, "free per-controller IRQ\n");
1036 free_irq(fdev->irq, fdev);
1037 return;
1038 }
1039
1040 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1041 chan = fdev->chan[i];
1042 if (chan && chan->irq) {
1043 chan_dbg(chan, "free per-channel IRQ\n");
1044 free_irq(chan->irq, chan);
1045 }
1046 }
1047}
1048
1049static int fsldma_request_irqs(struct fsldma_device *fdev)
1050{
1051 struct fsldma_chan *chan;
1052 int ret;
1053 int i;
1054
1055 /* if we have a per-controller IRQ, use that */
1056 if (fdev->irq) {
1057 dev_dbg(fdev->dev, "request per-controller IRQ\n");
1058 ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED,
1059 "fsldma-controller", fdev);
1060 return ret;
1061 }
1062
1063 /* no per-controller IRQ, use the per-channel IRQs */
1064 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1065 chan = fdev->chan[i];
1066 if (!chan)
1067 continue;
1068
1069 if (!chan->irq) {
1070 chan_err(chan, "interrupts property missing in device tree\n");
1071 ret = -ENODEV;
1072 goto out_unwind;
1073 }
1074
1075 chan_dbg(chan, "request per-channel IRQ\n");
1076 ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED,
1077 "fsldma-chan", chan);
1078 if (ret) {
1079 chan_err(chan, "unable to request per-channel IRQ\n");
1080 goto out_unwind;
1081 }
1082 }
1083
1084 return 0;
1085
1086out_unwind:
1087 for (/* none */; i >= 0; i--) {
1088 chan = fdev->chan[i];
1089 if (!chan)
1090 continue;
1091
1092 if (!chan->irq)
1093 continue;
1094
1095 free_irq(chan->irq, chan);
1096 }
1097
1098 return ret;
1099}
1100
1101/*----------------------------------------------------------------------------*/
1102/* OpenFirmware Subsystem */
1103/*----------------------------------------------------------------------------*/
1104
1105static int fsl_dma_chan_probe(struct fsldma_device *fdev,
1106 struct device_node *node, u32 feature, const char *compatible)
1107{
1108 struct fsldma_chan *chan;
1109 struct resource res;
1110 int err;
1111
1112 /* alloc channel */
1113 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
1114 if (!chan) {
1115 err = -ENOMEM;
1116 goto out_return;
1117 }
1118
1119 /* ioremap registers for use */
1120 chan->regs = of_iomap(node, 0);
1121 if (!chan->regs) {
1122 dev_err(fdev->dev, "unable to ioremap registers\n");
1123 err = -ENOMEM;
1124 goto out_free_chan;
1125 }
1126
1127 err = of_address_to_resource(node, 0, &res);
1128 if (err) {
1129 dev_err(fdev->dev, "unable to find 'reg' property\n");
1130 goto out_iounmap_regs;
1131 }
1132
1133 chan->feature = feature;
1134 if (!fdev->feature)
1135 fdev->feature = chan->feature;
1136
1137 /*
1138 * If the DMA device's feature is different than the feature
1139 * of its channels, report the bug
1140 */
1141 WARN_ON(fdev->feature != chan->feature);
1142
1143 chan->dev = fdev->dev;
1144 chan->id = (res.start & 0xfff) < 0x300 ?
1145 ((res.start - 0x100) & 0xfff) >> 7 :
1146 ((res.start - 0x200) & 0xfff) >> 7;
1147 if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) {
1148 dev_err(fdev->dev, "too many channels for device\n");
1149 err = -EINVAL;
1150 goto out_iounmap_regs;
1151 }
1152
1153 fdev->chan[chan->id] = chan;
1154 tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan);
1155 snprintf(chan->name, sizeof(chan->name), "chan%d", chan->id);
1156
1157 /* Initialize the channel */
1158 dma_init(chan);
1159
1160 /* Clear cdar registers */
1161 set_cdar(chan, 0);
1162
1163 switch (chan->feature & FSL_DMA_IP_MASK) {
1164 case FSL_DMA_IP_85XX:
1165 chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
1166 /* Fall through */
1167 case FSL_DMA_IP_83XX:
1168 chan->toggle_ext_start = fsl_chan_toggle_ext_start;
1169 chan->set_src_loop_size = fsl_chan_set_src_loop_size;
1170 chan->set_dst_loop_size = fsl_chan_set_dst_loop_size;
1171 chan->set_request_count = fsl_chan_set_request_count;
1172 }
1173
1174 spin_lock_init(&chan->desc_lock);
1175 INIT_LIST_HEAD(&chan->ld_pending);
1176 INIT_LIST_HEAD(&chan->ld_running);
1177 INIT_LIST_HEAD(&chan->ld_completed);
1178 chan->idle = true;
1179#ifdef CONFIG_PM
1180 chan->pm_state = RUNNING;
1181#endif
1182
1183 chan->common.device = &fdev->common;
1184 dma_cookie_init(&chan->common);
1185
1186 /* find the IRQ line, if it exists in the device tree */
1187 chan->irq = irq_of_parse_and_map(node, 0);
1188
1189 /* Add the channel to DMA device channel list */
1190 list_add_tail(&chan->common.device_node, &fdev->common.channels);
1191
1192 dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible,
1193 chan->irq ? chan->irq : fdev->irq);
1194
1195 return 0;
1196
1197out_iounmap_regs:
1198 iounmap(chan->regs);
1199out_free_chan:
1200 kfree(chan);
1201out_return:
1202 return err;
1203}
1204
1205static void fsl_dma_chan_remove(struct fsldma_chan *chan)
1206{
1207 irq_dispose_mapping(chan->irq);
1208 list_del(&chan->common.device_node);
1209 iounmap(chan->regs);
1210 kfree(chan);
1211}
1212
1213static int fsldma_of_probe(struct platform_device *op)
1214{
1215 struct fsldma_device *fdev;
1216 struct device_node *child;
1217 int err;
1218
1219 fdev = kzalloc(sizeof(*fdev), GFP_KERNEL);
1220 if (!fdev) {
1221 err = -ENOMEM;
1222 goto out_return;
1223 }
1224
1225 fdev->dev = &op->dev;
1226 INIT_LIST_HEAD(&fdev->common.channels);
1227
1228 /* ioremap the registers for use */
1229 fdev->regs = of_iomap(op->dev.of_node, 0);
1230 if (!fdev->regs) {
1231 dev_err(&op->dev, "unable to ioremap registers\n");
1232 err = -ENOMEM;
1233 goto out_free;
1234 }
1235
1236 /* map the channel IRQ if it exists, but don't hookup the handler yet */
1237 fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0);
1238
1239 dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
1240 dma_cap_set(DMA_SLAVE, fdev->common.cap_mask);
1241 fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources;
1242 fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources;
1243 fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy;
1244 fdev->common.device_tx_status = fsl_tx_status;
1245 fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending;
1246 fdev->common.device_config = fsl_dma_device_config;
1247 fdev->common.device_terminate_all = fsl_dma_device_terminate_all;
1248 fdev->common.dev = &op->dev;
1249
1250 fdev->common.src_addr_widths = FSL_DMA_BUSWIDTHS;
1251 fdev->common.dst_addr_widths = FSL_DMA_BUSWIDTHS;
1252 fdev->common.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1253 fdev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
1254
1255 dma_set_mask(&(op->dev), DMA_BIT_MASK(36));
1256
1257 platform_set_drvdata(op, fdev);
1258
1259 /*
1260 * We cannot use of_platform_bus_probe() because there is no
1261 * of_platform_bus_remove(). Instead, we manually instantiate every DMA
1262 * channel object.
1263 */
1264 for_each_child_of_node(op->dev.of_node, child) {
1265 if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) {
1266 fsl_dma_chan_probe(fdev, child,
1267 FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN,
1268 "fsl,eloplus-dma-channel");
1269 }
1270
1271 if (of_device_is_compatible(child, "fsl,elo-dma-channel")) {
1272 fsl_dma_chan_probe(fdev, child,
1273 FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN,
1274 "fsl,elo-dma-channel");
1275 }
1276 }
1277
1278 /*
1279 * Hookup the IRQ handler(s)
1280 *
1281 * If we have a per-controller interrupt, we prefer that to the
1282 * per-channel interrupts to reduce the number of shared interrupt
1283 * handlers on the same IRQ line
1284 */
1285 err = fsldma_request_irqs(fdev);
1286 if (err) {
1287 dev_err(fdev->dev, "unable to request IRQs\n");
1288 goto out_free_fdev;
1289 }
1290
1291 dma_async_device_register(&fdev->common);
1292 return 0;
1293
1294out_free_fdev:
1295 irq_dispose_mapping(fdev->irq);
1296 iounmap(fdev->regs);
1297out_free:
1298 kfree(fdev);
1299out_return:
1300 return err;
1301}
1302
1303static int fsldma_of_remove(struct platform_device *op)
1304{
1305 struct fsldma_device *fdev;
1306 unsigned int i;
1307
1308 fdev = platform_get_drvdata(op);
1309 dma_async_device_unregister(&fdev->common);
1310
1311 fsldma_free_irqs(fdev);
1312
1313 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1314 if (fdev->chan[i])
1315 fsl_dma_chan_remove(fdev->chan[i]);
1316 }
1317
1318 iounmap(fdev->regs);
1319 kfree(fdev);
1320
1321 return 0;
1322}
1323
1324#ifdef CONFIG_PM
1325static int fsldma_suspend_late(struct device *dev)
1326{
1327 struct fsldma_device *fdev = dev_get_drvdata(dev);
1328 struct fsldma_chan *chan;
1329 int i;
1330
1331 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1332 chan = fdev->chan[i];
1333 if (!chan)
1334 continue;
1335
1336 spin_lock_bh(&chan->desc_lock);
1337 if (unlikely(!chan->idle))
1338 goto out;
1339 chan->regs_save.mr = get_mr(chan);
1340 chan->pm_state = SUSPENDED;
1341 spin_unlock_bh(&chan->desc_lock);
1342 }
1343 return 0;
1344
1345out:
1346 for (; i >= 0; i--) {
1347 chan = fdev->chan[i];
1348 if (!chan)
1349 continue;
1350 chan->pm_state = RUNNING;
1351 spin_unlock_bh(&chan->desc_lock);
1352 }
1353 return -EBUSY;
1354}
1355
1356static int fsldma_resume_early(struct device *dev)
1357{
1358 struct fsldma_device *fdev = dev_get_drvdata(dev);
1359 struct fsldma_chan *chan;
1360 u32 mode;
1361 int i;
1362
1363 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1364 chan = fdev->chan[i];
1365 if (!chan)
1366 continue;
1367
1368 spin_lock_bh(&chan->desc_lock);
1369 mode = chan->regs_save.mr
1370 & ~FSL_DMA_MR_CS & ~FSL_DMA_MR_CC & ~FSL_DMA_MR_CA;
1371 set_mr(chan, mode);
1372 chan->pm_state = RUNNING;
1373 spin_unlock_bh(&chan->desc_lock);
1374 }
1375
1376 return 0;
1377}
1378
1379static const struct dev_pm_ops fsldma_pm_ops = {
1380 .suspend_late = fsldma_suspend_late,
1381 .resume_early = fsldma_resume_early,
1382};
1383#endif
1384
1385static const struct of_device_id fsldma_of_ids[] = {
1386 { .compatible = "fsl,elo3-dma", },
1387 { .compatible = "fsl,eloplus-dma", },
1388 { .compatible = "fsl,elo-dma", },
1389 {}
1390};
1391MODULE_DEVICE_TABLE(of, fsldma_of_ids);
1392
1393static struct platform_driver fsldma_of_driver = {
1394 .driver = {
1395 .name = "fsl-elo-dma",
1396 .of_match_table = fsldma_of_ids,
1397#ifdef CONFIG_PM
1398 .pm = &fsldma_pm_ops,
1399#endif
1400 },
1401 .probe = fsldma_of_probe,
1402 .remove = fsldma_of_remove,
1403};
1404
1405/*----------------------------------------------------------------------------*/
1406/* Module Init / Exit */
1407/*----------------------------------------------------------------------------*/
1408
1409static __init int fsldma_init(void)
1410{
1411 pr_info("Freescale Elo series DMA driver\n");
1412 return platform_driver_register(&fsldma_of_driver);
1413}
1414
1415static void __exit fsldma_exit(void)
1416{
1417 platform_driver_unregister(&fsldma_of_driver);
1418}
1419
1420subsys_initcall(fsldma_init);
1421module_exit(fsldma_exit);
1422
1423MODULE_DESCRIPTION("Freescale Elo series DMA driver");
1424MODULE_LICENSE("GPL");
1/*
2 * Freescale MPC85xx, MPC83xx DMA Engine support
3 *
4 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
5 *
6 * Author:
7 * Zhang Wei <wei.zhang@freescale.com>, Jul 2007
8 * Ebony Zhu <ebony.zhu@freescale.com>, May 2007
9 *
10 * Description:
11 * DMA engine driver for Freescale MPC8540 DMA controller, which is
12 * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc.
13 * The support for MPC8349 DMA controller is also added.
14 *
15 * This driver instructs the DMA controller to issue the PCI Read Multiple
16 * command for PCI read operations, instead of using the default PCI Read Line
17 * command. Please be aware that this setting may result in read pre-fetching
18 * on some platforms.
19 *
20 * This is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 */
26
27#include <linux/init.h>
28#include <linux/module.h>
29#include <linux/pci.h>
30#include <linux/slab.h>
31#include <linux/interrupt.h>
32#include <linux/dmaengine.h>
33#include <linux/delay.h>
34#include <linux/dma-mapping.h>
35#include <linux/dmapool.h>
36#include <linux/of_address.h>
37#include <linux/of_irq.h>
38#include <linux/of_platform.h>
39#include <linux/fsldma.h>
40#include "dmaengine.h"
41#include "fsldma.h"
42
43#define chan_dbg(chan, fmt, arg...) \
44 dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
45#define chan_err(chan, fmt, arg...) \
46 dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
47
48static const char msg_ld_oom[] = "No free memory for link descriptor";
49
50/*
51 * Register Helpers
52 */
53
54static void set_sr(struct fsldma_chan *chan, u32 val)
55{
56 DMA_OUT(chan, &chan->regs->sr, val, 32);
57}
58
59static u32 get_sr(struct fsldma_chan *chan)
60{
61 return DMA_IN(chan, &chan->regs->sr, 32);
62}
63
64static void set_mr(struct fsldma_chan *chan, u32 val)
65{
66 DMA_OUT(chan, &chan->regs->mr, val, 32);
67}
68
69static u32 get_mr(struct fsldma_chan *chan)
70{
71 return DMA_IN(chan, &chan->regs->mr, 32);
72}
73
74static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr)
75{
76 DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
77}
78
79static dma_addr_t get_cdar(struct fsldma_chan *chan)
80{
81 return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
82}
83
84static void set_bcr(struct fsldma_chan *chan, u32 val)
85{
86 DMA_OUT(chan, &chan->regs->bcr, val, 32);
87}
88
89static u32 get_bcr(struct fsldma_chan *chan)
90{
91 return DMA_IN(chan, &chan->regs->bcr, 32);
92}
93
94/*
95 * Descriptor Helpers
96 */
97
98static void set_desc_cnt(struct fsldma_chan *chan,
99 struct fsl_dma_ld_hw *hw, u32 count)
100{
101 hw->count = CPU_TO_DMA(chan, count, 32);
102}
103
104static void set_desc_src(struct fsldma_chan *chan,
105 struct fsl_dma_ld_hw *hw, dma_addr_t src)
106{
107 u64 snoop_bits;
108
109 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
110 ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0;
111 hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64);
112}
113
114static void set_desc_dst(struct fsldma_chan *chan,
115 struct fsl_dma_ld_hw *hw, dma_addr_t dst)
116{
117 u64 snoop_bits;
118
119 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
120 ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
121 hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64);
122}
123
124static void set_desc_next(struct fsldma_chan *chan,
125 struct fsl_dma_ld_hw *hw, dma_addr_t next)
126{
127 u64 snoop_bits;
128
129 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
130 ? FSL_DMA_SNEN : 0;
131 hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64);
132}
133
134static void set_ld_eol(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
135{
136 u64 snoop_bits;
137
138 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
139 ? FSL_DMA_SNEN : 0;
140
141 desc->hw.next_ln_addr = CPU_TO_DMA(chan,
142 DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
143 | snoop_bits, 64);
144}
145
146/*
147 * DMA Engine Hardware Control Helpers
148 */
149
150static void dma_init(struct fsldma_chan *chan)
151{
152 /* Reset the channel */
153 set_mr(chan, 0);
154
155 switch (chan->feature & FSL_DMA_IP_MASK) {
156 case FSL_DMA_IP_85XX:
157 /* Set the channel to below modes:
158 * EIE - Error interrupt enable
159 * EOLNIE - End of links interrupt enable
160 * BWC - Bandwidth sharing among channels
161 */
162 set_mr(chan, FSL_DMA_MR_BWC | FSL_DMA_MR_EIE
163 | FSL_DMA_MR_EOLNIE);
164 break;
165 case FSL_DMA_IP_83XX:
166 /* Set the channel to below modes:
167 * EOTIE - End-of-transfer interrupt enable
168 * PRC_RM - PCI read multiple
169 */
170 set_mr(chan, FSL_DMA_MR_EOTIE | FSL_DMA_MR_PRC_RM);
171 break;
172 }
173}
174
175static int dma_is_idle(struct fsldma_chan *chan)
176{
177 u32 sr = get_sr(chan);
178 return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH);
179}
180
181/*
182 * Start the DMA controller
183 *
184 * Preconditions:
185 * - the CDAR register must point to the start descriptor
186 * - the MRn[CS] bit must be cleared
187 */
188static void dma_start(struct fsldma_chan *chan)
189{
190 u32 mode;
191
192 mode = get_mr(chan);
193
194 if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
195 set_bcr(chan, 0);
196 mode |= FSL_DMA_MR_EMP_EN;
197 } else {
198 mode &= ~FSL_DMA_MR_EMP_EN;
199 }
200
201 if (chan->feature & FSL_DMA_CHAN_START_EXT) {
202 mode |= FSL_DMA_MR_EMS_EN;
203 } else {
204 mode &= ~FSL_DMA_MR_EMS_EN;
205 mode |= FSL_DMA_MR_CS;
206 }
207
208 set_mr(chan, mode);
209}
210
211static void dma_halt(struct fsldma_chan *chan)
212{
213 u32 mode;
214 int i;
215
216 /* read the mode register */
217 mode = get_mr(chan);
218
219 /*
220 * The 85xx controller supports channel abort, which will stop
221 * the current transfer. On 83xx, this bit is the transfer error
222 * mask bit, which should not be changed.
223 */
224 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
225 mode |= FSL_DMA_MR_CA;
226 set_mr(chan, mode);
227
228 mode &= ~FSL_DMA_MR_CA;
229 }
230
231 /* stop the DMA controller */
232 mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN);
233 set_mr(chan, mode);
234
235 /* wait for the DMA controller to become idle */
236 for (i = 0; i < 100; i++) {
237 if (dma_is_idle(chan))
238 return;
239
240 udelay(10);
241 }
242
243 if (!dma_is_idle(chan))
244 chan_err(chan, "DMA halt timeout!\n");
245}
246
247/**
248 * fsl_chan_set_src_loop_size - Set source address hold transfer size
249 * @chan : Freescale DMA channel
250 * @size : Address loop size, 0 for disable loop
251 *
252 * The set source address hold transfer size. The source
253 * address hold or loop transfer size is when the DMA transfer
254 * data from source address (SA), if the loop size is 4, the DMA will
255 * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA,
256 * SA + 1 ... and so on.
257 */
258static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size)
259{
260 u32 mode;
261
262 mode = get_mr(chan);
263
264 switch (size) {
265 case 0:
266 mode &= ~FSL_DMA_MR_SAHE;
267 break;
268 case 1:
269 case 2:
270 case 4:
271 case 8:
272 mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14);
273 break;
274 }
275
276 set_mr(chan, mode);
277}
278
279/**
280 * fsl_chan_set_dst_loop_size - Set destination address hold transfer size
281 * @chan : Freescale DMA channel
282 * @size : Address loop size, 0 for disable loop
283 *
284 * The set destination address hold transfer size. The destination
285 * address hold or loop transfer size is when the DMA transfer
286 * data to destination address (TA), if the loop size is 4, the DMA will
287 * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA,
288 * TA + 1 ... and so on.
289 */
290static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size)
291{
292 u32 mode;
293
294 mode = get_mr(chan);
295
296 switch (size) {
297 case 0:
298 mode &= ~FSL_DMA_MR_DAHE;
299 break;
300 case 1:
301 case 2:
302 case 4:
303 case 8:
304 mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16);
305 break;
306 }
307
308 set_mr(chan, mode);
309}
310
311/**
312 * fsl_chan_set_request_count - Set DMA Request Count for external control
313 * @chan : Freescale DMA channel
314 * @size : Number of bytes to transfer in a single request
315 *
316 * The Freescale DMA channel can be controlled by the external signal DREQ#.
317 * The DMA request count is how many bytes are allowed to transfer before
318 * pausing the channel, after which a new assertion of DREQ# resumes channel
319 * operation.
320 *
321 * A size of 0 disables external pause control. The maximum size is 1024.
322 */
323static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size)
324{
325 u32 mode;
326
327 BUG_ON(size > 1024);
328
329 mode = get_mr(chan);
330 mode |= (__ilog2(size) << 24) & 0x0f000000;
331
332 set_mr(chan, mode);
333}
334
335/**
336 * fsl_chan_toggle_ext_pause - Toggle channel external pause status
337 * @chan : Freescale DMA channel
338 * @enable : 0 is disabled, 1 is enabled.
339 *
340 * The Freescale DMA channel can be controlled by the external signal DREQ#.
341 * The DMA Request Count feature should be used in addition to this feature
342 * to set the number of bytes to transfer before pausing the channel.
343 */
344static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable)
345{
346 if (enable)
347 chan->feature |= FSL_DMA_CHAN_PAUSE_EXT;
348 else
349 chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT;
350}
351
352/**
353 * fsl_chan_toggle_ext_start - Toggle channel external start status
354 * @chan : Freescale DMA channel
355 * @enable : 0 is disabled, 1 is enabled.
356 *
357 * If enable the external start, the channel can be started by an
358 * external DMA start pin. So the dma_start() does not start the
359 * transfer immediately. The DMA channel will wait for the
360 * control pin asserted.
361 */
362static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable)
363{
364 if (enable)
365 chan->feature |= FSL_DMA_CHAN_START_EXT;
366 else
367 chan->feature &= ~FSL_DMA_CHAN_START_EXT;
368}
369
370int fsl_dma_external_start(struct dma_chan *dchan, int enable)
371{
372 struct fsldma_chan *chan;
373
374 if (!dchan)
375 return -EINVAL;
376
377 chan = to_fsl_chan(dchan);
378
379 fsl_chan_toggle_ext_start(chan, enable);
380 return 0;
381}
382EXPORT_SYMBOL_GPL(fsl_dma_external_start);
383
384static void append_ld_queue(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
385{
386 struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev);
387
388 if (list_empty(&chan->ld_pending))
389 goto out_splice;
390
391 /*
392 * Add the hardware descriptor to the chain of hardware descriptors
393 * that already exists in memory.
394 *
395 * This will un-set the EOL bit of the existing transaction, and the
396 * last link in this transaction will become the EOL descriptor.
397 */
398 set_desc_next(chan, &tail->hw, desc->async_tx.phys);
399
400 /*
401 * Add the software descriptor and all children to the list
402 * of pending transactions
403 */
404out_splice:
405 list_splice_tail_init(&desc->tx_list, &chan->ld_pending);
406}
407
408static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
409{
410 struct fsldma_chan *chan = to_fsl_chan(tx->chan);
411 struct fsl_desc_sw *desc = tx_to_fsl_desc(tx);
412 struct fsl_desc_sw *child;
413 dma_cookie_t cookie = -EINVAL;
414
415 spin_lock_bh(&chan->desc_lock);
416
417#ifdef CONFIG_PM
418 if (unlikely(chan->pm_state != RUNNING)) {
419 chan_dbg(chan, "cannot submit due to suspend\n");
420 spin_unlock_bh(&chan->desc_lock);
421 return -1;
422 }
423#endif
424
425 /*
426 * assign cookies to all of the software descriptors
427 * that make up this transaction
428 */
429 list_for_each_entry(child, &desc->tx_list, node) {
430 cookie = dma_cookie_assign(&child->async_tx);
431 }
432
433 /* put this transaction onto the tail of the pending queue */
434 append_ld_queue(chan, desc);
435
436 spin_unlock_bh(&chan->desc_lock);
437
438 return cookie;
439}
440
441/**
442 * fsl_dma_free_descriptor - Free descriptor from channel's DMA pool.
443 * @chan : Freescale DMA channel
444 * @desc: descriptor to be freed
445 */
446static void fsl_dma_free_descriptor(struct fsldma_chan *chan,
447 struct fsl_desc_sw *desc)
448{
449 list_del(&desc->node);
450 chan_dbg(chan, "LD %p free\n", desc);
451 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
452}
453
454/**
455 * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
456 * @chan : Freescale DMA channel
457 *
458 * Return - The descriptor allocated. NULL for failed.
459 */
460static struct fsl_desc_sw *fsl_dma_alloc_descriptor(struct fsldma_chan *chan)
461{
462 struct fsl_desc_sw *desc;
463 dma_addr_t pdesc;
464
465 desc = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &pdesc);
466 if (!desc) {
467 chan_dbg(chan, "out of memory for link descriptor\n");
468 return NULL;
469 }
470
471 INIT_LIST_HEAD(&desc->tx_list);
472 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
473 desc->async_tx.tx_submit = fsl_dma_tx_submit;
474 desc->async_tx.phys = pdesc;
475
476 chan_dbg(chan, "LD %p allocated\n", desc);
477
478 return desc;
479}
480
481/**
482 * fsldma_clean_completed_descriptor - free all descriptors which
483 * has been completed and acked
484 * @chan: Freescale DMA channel
485 *
486 * This function is used on all completed and acked descriptors.
487 * All descriptors should only be freed in this function.
488 */
489static void fsldma_clean_completed_descriptor(struct fsldma_chan *chan)
490{
491 struct fsl_desc_sw *desc, *_desc;
492
493 /* Run the callback for each descriptor, in order */
494 list_for_each_entry_safe(desc, _desc, &chan->ld_completed, node)
495 if (async_tx_test_ack(&desc->async_tx))
496 fsl_dma_free_descriptor(chan, desc);
497}
498
499/**
500 * fsldma_run_tx_complete_actions - cleanup a single link descriptor
501 * @chan: Freescale DMA channel
502 * @desc: descriptor to cleanup and free
503 * @cookie: Freescale DMA transaction identifier
504 *
505 * This function is used on a descriptor which has been executed by the DMA
506 * controller. It will run any callbacks, submit any dependencies.
507 */
508static dma_cookie_t fsldma_run_tx_complete_actions(struct fsldma_chan *chan,
509 struct fsl_desc_sw *desc, dma_cookie_t cookie)
510{
511 struct dma_async_tx_descriptor *txd = &desc->async_tx;
512 dma_cookie_t ret = cookie;
513
514 BUG_ON(txd->cookie < 0);
515
516 if (txd->cookie > 0) {
517 ret = txd->cookie;
518
519 dma_descriptor_unmap(txd);
520 /* Run the link descriptor callback function */
521 dmaengine_desc_get_callback_invoke(txd, NULL);
522 }
523
524 /* Run any dependencies */
525 dma_run_dependencies(txd);
526
527 return ret;
528}
529
530/**
531 * fsldma_clean_running_descriptor - move the completed descriptor from
532 * ld_running to ld_completed
533 * @chan: Freescale DMA channel
534 * @desc: the descriptor which is completed
535 *
536 * Free the descriptor directly if acked by async_tx api, or move it to
537 * queue ld_completed.
538 */
539static void fsldma_clean_running_descriptor(struct fsldma_chan *chan,
540 struct fsl_desc_sw *desc)
541{
542 /* Remove from the list of transactions */
543 list_del(&desc->node);
544
545 /*
546 * the client is allowed to attach dependent operations
547 * until 'ack' is set
548 */
549 if (!async_tx_test_ack(&desc->async_tx)) {
550 /*
551 * Move this descriptor to the list of descriptors which is
552 * completed, but still awaiting the 'ack' bit to be set.
553 */
554 list_add_tail(&desc->node, &chan->ld_completed);
555 return;
556 }
557
558 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
559}
560
561/**
562 * fsl_chan_xfer_ld_queue - transfer any pending transactions
563 * @chan : Freescale DMA channel
564 *
565 * HARDWARE STATE: idle
566 * LOCKING: must hold chan->desc_lock
567 */
568static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan)
569{
570 struct fsl_desc_sw *desc;
571
572 /*
573 * If the list of pending descriptors is empty, then we
574 * don't need to do any work at all
575 */
576 if (list_empty(&chan->ld_pending)) {
577 chan_dbg(chan, "no pending LDs\n");
578 return;
579 }
580
581 /*
582 * The DMA controller is not idle, which means that the interrupt
583 * handler will start any queued transactions when it runs after
584 * this transaction finishes
585 */
586 if (!chan->idle) {
587 chan_dbg(chan, "DMA controller still busy\n");
588 return;
589 }
590
591 /*
592 * If there are some link descriptors which have not been
593 * transferred, we need to start the controller
594 */
595
596 /*
597 * Move all elements from the queue of pending transactions
598 * onto the list of running transactions
599 */
600 chan_dbg(chan, "idle, starting controller\n");
601 desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node);
602 list_splice_tail_init(&chan->ld_pending, &chan->ld_running);
603
604 /*
605 * The 85xx DMA controller doesn't clear the channel start bit
606 * automatically at the end of a transfer. Therefore we must clear
607 * it in software before starting the transfer.
608 */
609 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
610 u32 mode;
611
612 mode = get_mr(chan);
613 mode &= ~FSL_DMA_MR_CS;
614 set_mr(chan, mode);
615 }
616
617 /*
618 * Program the descriptor's address into the DMA controller,
619 * then start the DMA transaction
620 */
621 set_cdar(chan, desc->async_tx.phys);
622 get_cdar(chan);
623
624 dma_start(chan);
625 chan->idle = false;
626}
627
628/**
629 * fsldma_cleanup_descriptors - cleanup link descriptors which are completed
630 * and move them to ld_completed to free until flag 'ack' is set
631 * @chan: Freescale DMA channel
632 *
633 * This function is used on descriptors which have been executed by the DMA
634 * controller. It will run any callbacks, submit any dependencies, then
635 * free these descriptors if flag 'ack' is set.
636 */
637static void fsldma_cleanup_descriptors(struct fsldma_chan *chan)
638{
639 struct fsl_desc_sw *desc, *_desc;
640 dma_cookie_t cookie = 0;
641 dma_addr_t curr_phys = get_cdar(chan);
642 int seen_current = 0;
643
644 fsldma_clean_completed_descriptor(chan);
645
646 /* Run the callback for each descriptor, in order */
647 list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) {
648 /*
649 * do not advance past the current descriptor loaded into the
650 * hardware channel, subsequent descriptors are either in
651 * process or have not been submitted
652 */
653 if (seen_current)
654 break;
655
656 /*
657 * stop the search if we reach the current descriptor and the
658 * channel is busy
659 */
660 if (desc->async_tx.phys == curr_phys) {
661 seen_current = 1;
662 if (!dma_is_idle(chan))
663 break;
664 }
665
666 cookie = fsldma_run_tx_complete_actions(chan, desc, cookie);
667
668 fsldma_clean_running_descriptor(chan, desc);
669 }
670
671 /*
672 * Start any pending transactions automatically
673 *
674 * In the ideal case, we keep the DMA controller busy while we go
675 * ahead and free the descriptors below.
676 */
677 fsl_chan_xfer_ld_queue(chan);
678
679 if (cookie > 0)
680 chan->common.completed_cookie = cookie;
681}
682
683/**
684 * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
685 * @chan : Freescale DMA channel
686 *
687 * This function will create a dma pool for descriptor allocation.
688 *
689 * Return - The number of descriptors allocated.
690 */
691static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan)
692{
693 struct fsldma_chan *chan = to_fsl_chan(dchan);
694
695 /* Has this channel already been allocated? */
696 if (chan->desc_pool)
697 return 1;
698
699 /*
700 * We need the descriptor to be aligned to 32bytes
701 * for meeting FSL DMA specification requirement.
702 */
703 chan->desc_pool = dma_pool_create(chan->name, chan->dev,
704 sizeof(struct fsl_desc_sw),
705 __alignof__(struct fsl_desc_sw), 0);
706 if (!chan->desc_pool) {
707 chan_err(chan, "unable to allocate descriptor pool\n");
708 return -ENOMEM;
709 }
710
711 /* there is at least one descriptor free to be allocated */
712 return 1;
713}
714
715/**
716 * fsldma_free_desc_list - Free all descriptors in a queue
717 * @chan: Freescae DMA channel
718 * @list: the list to free
719 *
720 * LOCKING: must hold chan->desc_lock
721 */
722static void fsldma_free_desc_list(struct fsldma_chan *chan,
723 struct list_head *list)
724{
725 struct fsl_desc_sw *desc, *_desc;
726
727 list_for_each_entry_safe(desc, _desc, list, node)
728 fsl_dma_free_descriptor(chan, desc);
729}
730
731static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan,
732 struct list_head *list)
733{
734 struct fsl_desc_sw *desc, *_desc;
735
736 list_for_each_entry_safe_reverse(desc, _desc, list, node)
737 fsl_dma_free_descriptor(chan, desc);
738}
739
740/**
741 * fsl_dma_free_chan_resources - Free all resources of the channel.
742 * @chan : Freescale DMA channel
743 */
744static void fsl_dma_free_chan_resources(struct dma_chan *dchan)
745{
746 struct fsldma_chan *chan = to_fsl_chan(dchan);
747
748 chan_dbg(chan, "free all channel resources\n");
749 spin_lock_bh(&chan->desc_lock);
750 fsldma_cleanup_descriptors(chan);
751 fsldma_free_desc_list(chan, &chan->ld_pending);
752 fsldma_free_desc_list(chan, &chan->ld_running);
753 fsldma_free_desc_list(chan, &chan->ld_completed);
754 spin_unlock_bh(&chan->desc_lock);
755
756 dma_pool_destroy(chan->desc_pool);
757 chan->desc_pool = NULL;
758}
759
760static struct dma_async_tx_descriptor *
761fsl_dma_prep_memcpy(struct dma_chan *dchan,
762 dma_addr_t dma_dst, dma_addr_t dma_src,
763 size_t len, unsigned long flags)
764{
765 struct fsldma_chan *chan;
766 struct fsl_desc_sw *first = NULL, *prev = NULL, *new;
767 size_t copy;
768
769 if (!dchan)
770 return NULL;
771
772 if (!len)
773 return NULL;
774
775 chan = to_fsl_chan(dchan);
776
777 do {
778
779 /* Allocate the link descriptor from DMA pool */
780 new = fsl_dma_alloc_descriptor(chan);
781 if (!new) {
782 chan_err(chan, "%s\n", msg_ld_oom);
783 goto fail;
784 }
785
786 copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT);
787
788 set_desc_cnt(chan, &new->hw, copy);
789 set_desc_src(chan, &new->hw, dma_src);
790 set_desc_dst(chan, &new->hw, dma_dst);
791
792 if (!first)
793 first = new;
794 else
795 set_desc_next(chan, &prev->hw, new->async_tx.phys);
796
797 new->async_tx.cookie = 0;
798 async_tx_ack(&new->async_tx);
799
800 prev = new;
801 len -= copy;
802 dma_src += copy;
803 dma_dst += copy;
804
805 /* Insert the link descriptor to the LD ring */
806 list_add_tail(&new->node, &first->tx_list);
807 } while (len);
808
809 new->async_tx.flags = flags; /* client is in control of this ack */
810 new->async_tx.cookie = -EBUSY;
811
812 /* Set End-of-link to the last link descriptor of new list */
813 set_ld_eol(chan, new);
814
815 return &first->async_tx;
816
817fail:
818 if (!first)
819 return NULL;
820
821 fsldma_free_desc_list_reverse(chan, &first->tx_list);
822 return NULL;
823}
824
825static struct dma_async_tx_descriptor *fsl_dma_prep_sg(struct dma_chan *dchan,
826 struct scatterlist *dst_sg, unsigned int dst_nents,
827 struct scatterlist *src_sg, unsigned int src_nents,
828 unsigned long flags)
829{
830 struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL;
831 struct fsldma_chan *chan = to_fsl_chan(dchan);
832 size_t dst_avail, src_avail;
833 dma_addr_t dst, src;
834 size_t len;
835
836 /* basic sanity checks */
837 if (dst_nents == 0 || src_nents == 0)
838 return NULL;
839
840 if (dst_sg == NULL || src_sg == NULL)
841 return NULL;
842
843 /*
844 * TODO: should we check that both scatterlists have the same
845 * TODO: number of bytes in total? Is that really an error?
846 */
847
848 /* get prepared for the loop */
849 dst_avail = sg_dma_len(dst_sg);
850 src_avail = sg_dma_len(src_sg);
851
852 /* run until we are out of scatterlist entries */
853 while (true) {
854
855 /* create the largest transaction possible */
856 len = min_t(size_t, src_avail, dst_avail);
857 len = min_t(size_t, len, FSL_DMA_BCR_MAX_CNT);
858 if (len == 0)
859 goto fetch;
860
861 dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_avail;
862 src = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_avail;
863
864 /* allocate and populate the descriptor */
865 new = fsl_dma_alloc_descriptor(chan);
866 if (!new) {
867 chan_err(chan, "%s\n", msg_ld_oom);
868 goto fail;
869 }
870
871 set_desc_cnt(chan, &new->hw, len);
872 set_desc_src(chan, &new->hw, src);
873 set_desc_dst(chan, &new->hw, dst);
874
875 if (!first)
876 first = new;
877 else
878 set_desc_next(chan, &prev->hw, new->async_tx.phys);
879
880 new->async_tx.cookie = 0;
881 async_tx_ack(&new->async_tx);
882 prev = new;
883
884 /* Insert the link descriptor to the LD ring */
885 list_add_tail(&new->node, &first->tx_list);
886
887 /* update metadata */
888 dst_avail -= len;
889 src_avail -= len;
890
891fetch:
892 /* fetch the next dst scatterlist entry */
893 if (dst_avail == 0) {
894
895 /* no more entries: we're done */
896 if (dst_nents == 0)
897 break;
898
899 /* fetch the next entry: if there are no more: done */
900 dst_sg = sg_next(dst_sg);
901 if (dst_sg == NULL)
902 break;
903
904 dst_nents--;
905 dst_avail = sg_dma_len(dst_sg);
906 }
907
908 /* fetch the next src scatterlist entry */
909 if (src_avail == 0) {
910
911 /* no more entries: we're done */
912 if (src_nents == 0)
913 break;
914
915 /* fetch the next entry: if there are no more: done */
916 src_sg = sg_next(src_sg);
917 if (src_sg == NULL)
918 break;
919
920 src_nents--;
921 src_avail = sg_dma_len(src_sg);
922 }
923 }
924
925 new->async_tx.flags = flags; /* client is in control of this ack */
926 new->async_tx.cookie = -EBUSY;
927
928 /* Set End-of-link to the last link descriptor of new list */
929 set_ld_eol(chan, new);
930
931 return &first->async_tx;
932
933fail:
934 if (!first)
935 return NULL;
936
937 fsldma_free_desc_list_reverse(chan, &first->tx_list);
938 return NULL;
939}
940
941static int fsl_dma_device_terminate_all(struct dma_chan *dchan)
942{
943 struct fsldma_chan *chan;
944
945 if (!dchan)
946 return -EINVAL;
947
948 chan = to_fsl_chan(dchan);
949
950 spin_lock_bh(&chan->desc_lock);
951
952 /* Halt the DMA engine */
953 dma_halt(chan);
954
955 /* Remove and free all of the descriptors in the LD queue */
956 fsldma_free_desc_list(chan, &chan->ld_pending);
957 fsldma_free_desc_list(chan, &chan->ld_running);
958 fsldma_free_desc_list(chan, &chan->ld_completed);
959 chan->idle = true;
960
961 spin_unlock_bh(&chan->desc_lock);
962 return 0;
963}
964
965static int fsl_dma_device_config(struct dma_chan *dchan,
966 struct dma_slave_config *config)
967{
968 struct fsldma_chan *chan;
969 int size;
970
971 if (!dchan)
972 return -EINVAL;
973
974 chan = to_fsl_chan(dchan);
975
976 /* make sure the channel supports setting burst size */
977 if (!chan->set_request_count)
978 return -ENXIO;
979
980 /* we set the controller burst size depending on direction */
981 if (config->direction == DMA_MEM_TO_DEV)
982 size = config->dst_addr_width * config->dst_maxburst;
983 else
984 size = config->src_addr_width * config->src_maxburst;
985
986 chan->set_request_count(chan, size);
987 return 0;
988}
989
990
991/**
992 * fsl_dma_memcpy_issue_pending - Issue the DMA start command
993 * @chan : Freescale DMA channel
994 */
995static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan)
996{
997 struct fsldma_chan *chan = to_fsl_chan(dchan);
998
999 spin_lock_bh(&chan->desc_lock);
1000 fsl_chan_xfer_ld_queue(chan);
1001 spin_unlock_bh(&chan->desc_lock);
1002}
1003
1004/**
1005 * fsl_tx_status - Determine the DMA status
1006 * @chan : Freescale DMA channel
1007 */
1008static enum dma_status fsl_tx_status(struct dma_chan *dchan,
1009 dma_cookie_t cookie,
1010 struct dma_tx_state *txstate)
1011{
1012 struct fsldma_chan *chan = to_fsl_chan(dchan);
1013 enum dma_status ret;
1014
1015 ret = dma_cookie_status(dchan, cookie, txstate);
1016 if (ret == DMA_COMPLETE)
1017 return ret;
1018
1019 spin_lock_bh(&chan->desc_lock);
1020 fsldma_cleanup_descriptors(chan);
1021 spin_unlock_bh(&chan->desc_lock);
1022
1023 return dma_cookie_status(dchan, cookie, txstate);
1024}
1025
1026/*----------------------------------------------------------------------------*/
1027/* Interrupt Handling */
1028/*----------------------------------------------------------------------------*/
1029
1030static irqreturn_t fsldma_chan_irq(int irq, void *data)
1031{
1032 struct fsldma_chan *chan = data;
1033 u32 stat;
1034
1035 /* save and clear the status register */
1036 stat = get_sr(chan);
1037 set_sr(chan, stat);
1038 chan_dbg(chan, "irq: stat = 0x%x\n", stat);
1039
1040 /* check that this was really our device */
1041 stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH);
1042 if (!stat)
1043 return IRQ_NONE;
1044
1045 if (stat & FSL_DMA_SR_TE)
1046 chan_err(chan, "Transfer Error!\n");
1047
1048 /*
1049 * Programming Error
1050 * The DMA_INTERRUPT async_tx is a NULL transfer, which will
1051 * trigger a PE interrupt.
1052 */
1053 if (stat & FSL_DMA_SR_PE) {
1054 chan_dbg(chan, "irq: Programming Error INT\n");
1055 stat &= ~FSL_DMA_SR_PE;
1056 if (get_bcr(chan) != 0)
1057 chan_err(chan, "Programming Error!\n");
1058 }
1059
1060 /*
1061 * For MPC8349, EOCDI event need to update cookie
1062 * and start the next transfer if it exist.
1063 */
1064 if (stat & FSL_DMA_SR_EOCDI) {
1065 chan_dbg(chan, "irq: End-of-Chain link INT\n");
1066 stat &= ~FSL_DMA_SR_EOCDI;
1067 }
1068
1069 /*
1070 * If it current transfer is the end-of-transfer,
1071 * we should clear the Channel Start bit for
1072 * prepare next transfer.
1073 */
1074 if (stat & FSL_DMA_SR_EOLNI) {
1075 chan_dbg(chan, "irq: End-of-link INT\n");
1076 stat &= ~FSL_DMA_SR_EOLNI;
1077 }
1078
1079 /* check that the DMA controller is really idle */
1080 if (!dma_is_idle(chan))
1081 chan_err(chan, "irq: controller not idle!\n");
1082
1083 /* check that we handled all of the bits */
1084 if (stat)
1085 chan_err(chan, "irq: unhandled sr 0x%08x\n", stat);
1086
1087 /*
1088 * Schedule the tasklet to handle all cleanup of the current
1089 * transaction. It will start a new transaction if there is
1090 * one pending.
1091 */
1092 tasklet_schedule(&chan->tasklet);
1093 chan_dbg(chan, "irq: Exit\n");
1094 return IRQ_HANDLED;
1095}
1096
1097static void dma_do_tasklet(unsigned long data)
1098{
1099 struct fsldma_chan *chan = (struct fsldma_chan *)data;
1100
1101 chan_dbg(chan, "tasklet entry\n");
1102
1103 spin_lock_bh(&chan->desc_lock);
1104
1105 /* the hardware is now idle and ready for more */
1106 chan->idle = true;
1107
1108 /* Run all cleanup for descriptors which have been completed */
1109 fsldma_cleanup_descriptors(chan);
1110
1111 spin_unlock_bh(&chan->desc_lock);
1112
1113 chan_dbg(chan, "tasklet exit\n");
1114}
1115
1116static irqreturn_t fsldma_ctrl_irq(int irq, void *data)
1117{
1118 struct fsldma_device *fdev = data;
1119 struct fsldma_chan *chan;
1120 unsigned int handled = 0;
1121 u32 gsr, mask;
1122 int i;
1123
1124 gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs)
1125 : in_le32(fdev->regs);
1126 mask = 0xff000000;
1127 dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr);
1128
1129 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1130 chan = fdev->chan[i];
1131 if (!chan)
1132 continue;
1133
1134 if (gsr & mask) {
1135 dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id);
1136 fsldma_chan_irq(irq, chan);
1137 handled++;
1138 }
1139
1140 gsr &= ~mask;
1141 mask >>= 8;
1142 }
1143
1144 return IRQ_RETVAL(handled);
1145}
1146
1147static void fsldma_free_irqs(struct fsldma_device *fdev)
1148{
1149 struct fsldma_chan *chan;
1150 int i;
1151
1152 if (fdev->irq) {
1153 dev_dbg(fdev->dev, "free per-controller IRQ\n");
1154 free_irq(fdev->irq, fdev);
1155 return;
1156 }
1157
1158 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1159 chan = fdev->chan[i];
1160 if (chan && chan->irq) {
1161 chan_dbg(chan, "free per-channel IRQ\n");
1162 free_irq(chan->irq, chan);
1163 }
1164 }
1165}
1166
1167static int fsldma_request_irqs(struct fsldma_device *fdev)
1168{
1169 struct fsldma_chan *chan;
1170 int ret;
1171 int i;
1172
1173 /* if we have a per-controller IRQ, use that */
1174 if (fdev->irq) {
1175 dev_dbg(fdev->dev, "request per-controller IRQ\n");
1176 ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED,
1177 "fsldma-controller", fdev);
1178 return ret;
1179 }
1180
1181 /* no per-controller IRQ, use the per-channel IRQs */
1182 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1183 chan = fdev->chan[i];
1184 if (!chan)
1185 continue;
1186
1187 if (!chan->irq) {
1188 chan_err(chan, "interrupts property missing in device tree\n");
1189 ret = -ENODEV;
1190 goto out_unwind;
1191 }
1192
1193 chan_dbg(chan, "request per-channel IRQ\n");
1194 ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED,
1195 "fsldma-chan", chan);
1196 if (ret) {
1197 chan_err(chan, "unable to request per-channel IRQ\n");
1198 goto out_unwind;
1199 }
1200 }
1201
1202 return 0;
1203
1204out_unwind:
1205 for (/* none */; i >= 0; i--) {
1206 chan = fdev->chan[i];
1207 if (!chan)
1208 continue;
1209
1210 if (!chan->irq)
1211 continue;
1212
1213 free_irq(chan->irq, chan);
1214 }
1215
1216 return ret;
1217}
1218
1219/*----------------------------------------------------------------------------*/
1220/* OpenFirmware Subsystem */
1221/*----------------------------------------------------------------------------*/
1222
1223static int fsl_dma_chan_probe(struct fsldma_device *fdev,
1224 struct device_node *node, u32 feature, const char *compatible)
1225{
1226 struct fsldma_chan *chan;
1227 struct resource res;
1228 int err;
1229
1230 /* alloc channel */
1231 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
1232 if (!chan) {
1233 err = -ENOMEM;
1234 goto out_return;
1235 }
1236
1237 /* ioremap registers for use */
1238 chan->regs = of_iomap(node, 0);
1239 if (!chan->regs) {
1240 dev_err(fdev->dev, "unable to ioremap registers\n");
1241 err = -ENOMEM;
1242 goto out_free_chan;
1243 }
1244
1245 err = of_address_to_resource(node, 0, &res);
1246 if (err) {
1247 dev_err(fdev->dev, "unable to find 'reg' property\n");
1248 goto out_iounmap_regs;
1249 }
1250
1251 chan->feature = feature;
1252 if (!fdev->feature)
1253 fdev->feature = chan->feature;
1254
1255 /*
1256 * If the DMA device's feature is different than the feature
1257 * of its channels, report the bug
1258 */
1259 WARN_ON(fdev->feature != chan->feature);
1260
1261 chan->dev = fdev->dev;
1262 chan->id = (res.start & 0xfff) < 0x300 ?
1263 ((res.start - 0x100) & 0xfff) >> 7 :
1264 ((res.start - 0x200) & 0xfff) >> 7;
1265 if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) {
1266 dev_err(fdev->dev, "too many channels for device\n");
1267 err = -EINVAL;
1268 goto out_iounmap_regs;
1269 }
1270
1271 fdev->chan[chan->id] = chan;
1272 tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan);
1273 snprintf(chan->name, sizeof(chan->name), "chan%d", chan->id);
1274
1275 /* Initialize the channel */
1276 dma_init(chan);
1277
1278 /* Clear cdar registers */
1279 set_cdar(chan, 0);
1280
1281 switch (chan->feature & FSL_DMA_IP_MASK) {
1282 case FSL_DMA_IP_85XX:
1283 chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
1284 case FSL_DMA_IP_83XX:
1285 chan->toggle_ext_start = fsl_chan_toggle_ext_start;
1286 chan->set_src_loop_size = fsl_chan_set_src_loop_size;
1287 chan->set_dst_loop_size = fsl_chan_set_dst_loop_size;
1288 chan->set_request_count = fsl_chan_set_request_count;
1289 }
1290
1291 spin_lock_init(&chan->desc_lock);
1292 INIT_LIST_HEAD(&chan->ld_pending);
1293 INIT_LIST_HEAD(&chan->ld_running);
1294 INIT_LIST_HEAD(&chan->ld_completed);
1295 chan->idle = true;
1296#ifdef CONFIG_PM
1297 chan->pm_state = RUNNING;
1298#endif
1299
1300 chan->common.device = &fdev->common;
1301 dma_cookie_init(&chan->common);
1302
1303 /* find the IRQ line, if it exists in the device tree */
1304 chan->irq = irq_of_parse_and_map(node, 0);
1305
1306 /* Add the channel to DMA device channel list */
1307 list_add_tail(&chan->common.device_node, &fdev->common.channels);
1308
1309 dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible,
1310 chan->irq ? chan->irq : fdev->irq);
1311
1312 return 0;
1313
1314out_iounmap_regs:
1315 iounmap(chan->regs);
1316out_free_chan:
1317 kfree(chan);
1318out_return:
1319 return err;
1320}
1321
1322static void fsl_dma_chan_remove(struct fsldma_chan *chan)
1323{
1324 irq_dispose_mapping(chan->irq);
1325 list_del(&chan->common.device_node);
1326 iounmap(chan->regs);
1327 kfree(chan);
1328}
1329
1330static int fsldma_of_probe(struct platform_device *op)
1331{
1332 struct fsldma_device *fdev;
1333 struct device_node *child;
1334 int err;
1335
1336 fdev = kzalloc(sizeof(*fdev), GFP_KERNEL);
1337 if (!fdev) {
1338 err = -ENOMEM;
1339 goto out_return;
1340 }
1341
1342 fdev->dev = &op->dev;
1343 INIT_LIST_HEAD(&fdev->common.channels);
1344
1345 /* ioremap the registers for use */
1346 fdev->regs = of_iomap(op->dev.of_node, 0);
1347 if (!fdev->regs) {
1348 dev_err(&op->dev, "unable to ioremap registers\n");
1349 err = -ENOMEM;
1350 goto out_free;
1351 }
1352
1353 /* map the channel IRQ if it exists, but don't hookup the handler yet */
1354 fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0);
1355
1356 dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
1357 dma_cap_set(DMA_SG, fdev->common.cap_mask);
1358 dma_cap_set(DMA_SLAVE, fdev->common.cap_mask);
1359 fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources;
1360 fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources;
1361 fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy;
1362 fdev->common.device_prep_dma_sg = fsl_dma_prep_sg;
1363 fdev->common.device_tx_status = fsl_tx_status;
1364 fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending;
1365 fdev->common.device_config = fsl_dma_device_config;
1366 fdev->common.device_terminate_all = fsl_dma_device_terminate_all;
1367 fdev->common.dev = &op->dev;
1368
1369 fdev->common.src_addr_widths = FSL_DMA_BUSWIDTHS;
1370 fdev->common.dst_addr_widths = FSL_DMA_BUSWIDTHS;
1371 fdev->common.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
1372 fdev->common.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
1373
1374 dma_set_mask(&(op->dev), DMA_BIT_MASK(36));
1375
1376 platform_set_drvdata(op, fdev);
1377
1378 /*
1379 * We cannot use of_platform_bus_probe() because there is no
1380 * of_platform_bus_remove(). Instead, we manually instantiate every DMA
1381 * channel object.
1382 */
1383 for_each_child_of_node(op->dev.of_node, child) {
1384 if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) {
1385 fsl_dma_chan_probe(fdev, child,
1386 FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN,
1387 "fsl,eloplus-dma-channel");
1388 }
1389
1390 if (of_device_is_compatible(child, "fsl,elo-dma-channel")) {
1391 fsl_dma_chan_probe(fdev, child,
1392 FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN,
1393 "fsl,elo-dma-channel");
1394 }
1395 }
1396
1397 /*
1398 * Hookup the IRQ handler(s)
1399 *
1400 * If we have a per-controller interrupt, we prefer that to the
1401 * per-channel interrupts to reduce the number of shared interrupt
1402 * handlers on the same IRQ line
1403 */
1404 err = fsldma_request_irqs(fdev);
1405 if (err) {
1406 dev_err(fdev->dev, "unable to request IRQs\n");
1407 goto out_free_fdev;
1408 }
1409
1410 dma_async_device_register(&fdev->common);
1411 return 0;
1412
1413out_free_fdev:
1414 irq_dispose_mapping(fdev->irq);
1415 iounmap(fdev->regs);
1416out_free:
1417 kfree(fdev);
1418out_return:
1419 return err;
1420}
1421
1422static int fsldma_of_remove(struct platform_device *op)
1423{
1424 struct fsldma_device *fdev;
1425 unsigned int i;
1426
1427 fdev = platform_get_drvdata(op);
1428 dma_async_device_unregister(&fdev->common);
1429
1430 fsldma_free_irqs(fdev);
1431
1432 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1433 if (fdev->chan[i])
1434 fsl_dma_chan_remove(fdev->chan[i]);
1435 }
1436
1437 iounmap(fdev->regs);
1438 kfree(fdev);
1439
1440 return 0;
1441}
1442
1443#ifdef CONFIG_PM
1444static int fsldma_suspend_late(struct device *dev)
1445{
1446 struct platform_device *pdev = to_platform_device(dev);
1447 struct fsldma_device *fdev = platform_get_drvdata(pdev);
1448 struct fsldma_chan *chan;
1449 int i;
1450
1451 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1452 chan = fdev->chan[i];
1453 if (!chan)
1454 continue;
1455
1456 spin_lock_bh(&chan->desc_lock);
1457 if (unlikely(!chan->idle))
1458 goto out;
1459 chan->regs_save.mr = get_mr(chan);
1460 chan->pm_state = SUSPENDED;
1461 spin_unlock_bh(&chan->desc_lock);
1462 }
1463 return 0;
1464
1465out:
1466 for (; i >= 0; i--) {
1467 chan = fdev->chan[i];
1468 if (!chan)
1469 continue;
1470 chan->pm_state = RUNNING;
1471 spin_unlock_bh(&chan->desc_lock);
1472 }
1473 return -EBUSY;
1474}
1475
1476static int fsldma_resume_early(struct device *dev)
1477{
1478 struct platform_device *pdev = to_platform_device(dev);
1479 struct fsldma_device *fdev = platform_get_drvdata(pdev);
1480 struct fsldma_chan *chan;
1481 u32 mode;
1482 int i;
1483
1484 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1485 chan = fdev->chan[i];
1486 if (!chan)
1487 continue;
1488
1489 spin_lock_bh(&chan->desc_lock);
1490 mode = chan->regs_save.mr
1491 & ~FSL_DMA_MR_CS & ~FSL_DMA_MR_CC & ~FSL_DMA_MR_CA;
1492 set_mr(chan, mode);
1493 chan->pm_state = RUNNING;
1494 spin_unlock_bh(&chan->desc_lock);
1495 }
1496
1497 return 0;
1498}
1499
1500static const struct dev_pm_ops fsldma_pm_ops = {
1501 .suspend_late = fsldma_suspend_late,
1502 .resume_early = fsldma_resume_early,
1503};
1504#endif
1505
1506static const struct of_device_id fsldma_of_ids[] = {
1507 { .compatible = "fsl,elo3-dma", },
1508 { .compatible = "fsl,eloplus-dma", },
1509 { .compatible = "fsl,elo-dma", },
1510 {}
1511};
1512MODULE_DEVICE_TABLE(of, fsldma_of_ids);
1513
1514static struct platform_driver fsldma_of_driver = {
1515 .driver = {
1516 .name = "fsl-elo-dma",
1517 .of_match_table = fsldma_of_ids,
1518#ifdef CONFIG_PM
1519 .pm = &fsldma_pm_ops,
1520#endif
1521 },
1522 .probe = fsldma_of_probe,
1523 .remove = fsldma_of_remove,
1524};
1525
1526/*----------------------------------------------------------------------------*/
1527/* Module Init / Exit */
1528/*----------------------------------------------------------------------------*/
1529
1530static __init int fsldma_init(void)
1531{
1532 pr_info("Freescale Elo series DMA driver\n");
1533 return platform_driver_register(&fsldma_of_driver);
1534}
1535
1536static void __exit fsldma_exit(void)
1537{
1538 platform_driver_unregister(&fsldma_of_driver);
1539}
1540
1541subsys_initcall(fsldma_init);
1542module_exit(fsldma_exit);
1543
1544MODULE_DESCRIPTION("Freescale Elo series DMA driver");
1545MODULE_LICENSE("GPL");