Loading...
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2016 Broadcom
4 * Author: Jayachandran C <jchandra@broadcom.com>
5 * Copyright (C) 2016 Semihalf
6 * Author: Tomasz Nowicki <tn@semihalf.com>
7 */
8
9#define pr_fmt(fmt) "ACPI: " fmt
10
11#include <linux/kernel.h>
12#include <linux/pci.h>
13#include <linux/pci-acpi.h>
14#include <linux/pci-ecam.h>
15
16/* Structure to hold entries from the MCFG table */
17struct mcfg_entry {
18 struct list_head list;
19 phys_addr_t addr;
20 u16 segment;
21 u8 bus_start;
22 u8 bus_end;
23};
24
25#ifdef CONFIG_PCI_QUIRKS
26struct mcfg_fixup {
27 char oem_id[ACPI_OEM_ID_SIZE + 1];
28 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
29 u32 oem_revision;
30 u16 segment;
31 struct resource bus_range;
32 struct pci_ecam_ops *ops;
33 struct resource cfgres;
34};
35
36#define MCFG_BUS_RANGE(start, end) DEFINE_RES_NAMED((start), \
37 ((end) - (start) + 1), \
38 NULL, IORESOURCE_BUS)
39#define MCFG_BUS_ANY MCFG_BUS_RANGE(0x0, 0xff)
40
41static struct mcfg_fixup mcfg_quirks[] = {
42/* { OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, ops, cfgres }, */
43
44#define AL_ECAM(table_id, rev, seg, ops) \
45 { "AMAZON", table_id, rev, seg, MCFG_BUS_ANY, ops }
46
47 AL_ECAM("GRAVITON", 0, 0, &al_pcie_ops),
48 AL_ECAM("GRAVITON", 0, 1, &al_pcie_ops),
49 AL_ECAM("GRAVITON", 0, 2, &al_pcie_ops),
50 AL_ECAM("GRAVITON", 0, 3, &al_pcie_ops),
51 AL_ECAM("GRAVITON", 0, 4, &al_pcie_ops),
52 AL_ECAM("GRAVITON", 0, 5, &al_pcie_ops),
53 AL_ECAM("GRAVITON", 0, 6, &al_pcie_ops),
54 AL_ECAM("GRAVITON", 0, 7, &al_pcie_ops),
55
56#define QCOM_ECAM32(seg) \
57 { "QCOM ", "QDF2432 ", 1, seg, MCFG_BUS_ANY, &pci_32b_ops }
58
59 QCOM_ECAM32(0),
60 QCOM_ECAM32(1),
61 QCOM_ECAM32(2),
62 QCOM_ECAM32(3),
63 QCOM_ECAM32(4),
64 QCOM_ECAM32(5),
65 QCOM_ECAM32(6),
66 QCOM_ECAM32(7),
67
68#define HISI_QUAD_DOM(table_id, seg, ops) \
69 { "HISI ", table_id, 0, (seg) + 0, MCFG_BUS_ANY, ops }, \
70 { "HISI ", table_id, 0, (seg) + 1, MCFG_BUS_ANY, ops }, \
71 { "HISI ", table_id, 0, (seg) + 2, MCFG_BUS_ANY, ops }, \
72 { "HISI ", table_id, 0, (seg) + 3, MCFG_BUS_ANY, ops }
73
74 HISI_QUAD_DOM("HIP05 ", 0, &hisi_pcie_ops),
75 HISI_QUAD_DOM("HIP06 ", 0, &hisi_pcie_ops),
76 HISI_QUAD_DOM("HIP07 ", 0, &hisi_pcie_ops),
77 HISI_QUAD_DOM("HIP07 ", 4, &hisi_pcie_ops),
78 HISI_QUAD_DOM("HIP07 ", 8, &hisi_pcie_ops),
79 HISI_QUAD_DOM("HIP07 ", 12, &hisi_pcie_ops),
80
81#define THUNDER_PEM_RES(addr, node) \
82 DEFINE_RES_MEM((addr) + ((u64) (node) << 44), 0x39 * SZ_16M)
83
84#define THUNDER_PEM_QUIRK(rev, node) \
85 { "CAVIUM", "THUNDERX", rev, 4 + (10 * (node)), MCFG_BUS_ANY, \
86 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88001f000000UL, node) }, \
87 { "CAVIUM", "THUNDERX", rev, 5 + (10 * (node)), MCFG_BUS_ANY, \
88 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x884057000000UL, node) }, \
89 { "CAVIUM", "THUNDERX", rev, 6 + (10 * (node)), MCFG_BUS_ANY, \
90 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88808f000000UL, node) }, \
91 { "CAVIUM", "THUNDERX", rev, 7 + (10 * (node)), MCFG_BUS_ANY, \
92 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89001f000000UL, node) }, \
93 { "CAVIUM", "THUNDERX", rev, 8 + (10 * (node)), MCFG_BUS_ANY, \
94 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x894057000000UL, node) }, \
95 { "CAVIUM", "THUNDERX", rev, 9 + (10 * (node)), MCFG_BUS_ANY, \
96 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89808f000000UL, node) }
97
98#define THUNDER_ECAM_QUIRK(rev, seg) \
99 { "CAVIUM", "THUNDERX", rev, seg, MCFG_BUS_ANY, \
100 &pci_thunder_ecam_ops }
101
102 /* SoC pass2.x */
103 THUNDER_PEM_QUIRK(1, 0),
104 THUNDER_PEM_QUIRK(1, 1),
105 THUNDER_ECAM_QUIRK(1, 10),
106
107 /* SoC pass1.x */
108 THUNDER_PEM_QUIRK(2, 0), /* off-chip devices */
109 THUNDER_PEM_QUIRK(2, 1), /* off-chip devices */
110 THUNDER_ECAM_QUIRK(2, 0),
111 THUNDER_ECAM_QUIRK(2, 1),
112 THUNDER_ECAM_QUIRK(2, 2),
113 THUNDER_ECAM_QUIRK(2, 3),
114 THUNDER_ECAM_QUIRK(2, 10),
115 THUNDER_ECAM_QUIRK(2, 11),
116 THUNDER_ECAM_QUIRK(2, 12),
117 THUNDER_ECAM_QUIRK(2, 13),
118
119#define XGENE_V1_ECAM_MCFG(rev, seg) \
120 {"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \
121 &xgene_v1_pcie_ecam_ops }
122
123#define XGENE_V2_ECAM_MCFG(rev, seg) \
124 {"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \
125 &xgene_v2_pcie_ecam_ops }
126
127 /* X-Gene SoC with v1 PCIe controller */
128 XGENE_V1_ECAM_MCFG(1, 0),
129 XGENE_V1_ECAM_MCFG(1, 1),
130 XGENE_V1_ECAM_MCFG(1, 2),
131 XGENE_V1_ECAM_MCFG(1, 3),
132 XGENE_V1_ECAM_MCFG(1, 4),
133 XGENE_V1_ECAM_MCFG(2, 0),
134 XGENE_V1_ECAM_MCFG(2, 1),
135 XGENE_V1_ECAM_MCFG(2, 2),
136 XGENE_V1_ECAM_MCFG(2, 3),
137 XGENE_V1_ECAM_MCFG(2, 4),
138 /* X-Gene SoC with v2.1 PCIe controller */
139 XGENE_V2_ECAM_MCFG(3, 0),
140 XGENE_V2_ECAM_MCFG(3, 1),
141 /* X-Gene SoC with v2.2 PCIe controller */
142 XGENE_V2_ECAM_MCFG(4, 0),
143 XGENE_V2_ECAM_MCFG(4, 1),
144 XGENE_V2_ECAM_MCFG(4, 2),
145};
146
147static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
148static char mcfg_oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
149static u32 mcfg_oem_revision;
150
151static int pci_mcfg_quirk_matches(struct mcfg_fixup *f, u16 segment,
152 struct resource *bus_range)
153{
154 if (!memcmp(f->oem_id, mcfg_oem_id, ACPI_OEM_ID_SIZE) &&
155 !memcmp(f->oem_table_id, mcfg_oem_table_id,
156 ACPI_OEM_TABLE_ID_SIZE) &&
157 f->oem_revision == mcfg_oem_revision &&
158 f->segment == segment &&
159 resource_contains(&f->bus_range, bus_range))
160 return 1;
161
162 return 0;
163}
164#endif
165
166static void pci_mcfg_apply_quirks(struct acpi_pci_root *root,
167 struct resource *cfgres,
168 struct pci_ecam_ops **ecam_ops)
169{
170#ifdef CONFIG_PCI_QUIRKS
171 u16 segment = root->segment;
172 struct resource *bus_range = &root->secondary;
173 struct mcfg_fixup *f;
174 int i;
175
176 for (i = 0, f = mcfg_quirks; i < ARRAY_SIZE(mcfg_quirks); i++, f++) {
177 if (pci_mcfg_quirk_matches(f, segment, bus_range)) {
178 if (f->cfgres.start)
179 *cfgres = f->cfgres;
180 if (f->ops)
181 *ecam_ops = f->ops;
182 dev_info(&root->device->dev, "MCFG quirk: ECAM at %pR for %pR with %ps\n",
183 cfgres, bus_range, *ecam_ops);
184 return;
185 }
186 }
187#endif
188}
189
190/* List to save MCFG entries */
191static LIST_HEAD(pci_mcfg_list);
192
193int pci_mcfg_lookup(struct acpi_pci_root *root, struct resource *cfgres,
194 struct pci_ecam_ops **ecam_ops)
195{
196 struct pci_ecam_ops *ops = &pci_generic_ecam_ops;
197 struct resource *bus_res = &root->secondary;
198 u16 seg = root->segment;
199 struct mcfg_entry *e;
200 struct resource res;
201
202 /* Use address from _CBA if present, otherwise lookup MCFG */
203 if (root->mcfg_addr)
204 goto skip_lookup;
205
206 /*
207 * We expect the range in bus_res in the coverage of MCFG bus range.
208 */
209 list_for_each_entry(e, &pci_mcfg_list, list) {
210 if (e->segment == seg && e->bus_start <= bus_res->start &&
211 e->bus_end >= bus_res->end) {
212 root->mcfg_addr = e->addr;
213 }
214
215 }
216
217skip_lookup:
218 memset(&res, 0, sizeof(res));
219 if (root->mcfg_addr) {
220 res.start = root->mcfg_addr + (bus_res->start << 20);
221 res.end = res.start + (resource_size(bus_res) << 20) - 1;
222 res.flags = IORESOURCE_MEM;
223 }
224
225 /*
226 * Allow quirks to override default ECAM ops and CFG resource
227 * range. This may even fabricate a CFG resource range in case
228 * MCFG does not have it. Invalid CFG start address means MCFG
229 * firmware bug or we need another quirk in array.
230 */
231 pci_mcfg_apply_quirks(root, &res, &ops);
232 if (!res.start)
233 return -ENXIO;
234
235 *cfgres = res;
236 *ecam_ops = ops;
237 return 0;
238}
239
240static __init int pci_mcfg_parse(struct acpi_table_header *header)
241{
242 struct acpi_table_mcfg *mcfg;
243 struct acpi_mcfg_allocation *mptr;
244 struct mcfg_entry *e, *arr;
245 int i, n;
246
247 if (header->length < sizeof(struct acpi_table_mcfg))
248 return -EINVAL;
249
250 n = (header->length - sizeof(struct acpi_table_mcfg)) /
251 sizeof(struct acpi_mcfg_allocation);
252 mcfg = (struct acpi_table_mcfg *)header;
253 mptr = (struct acpi_mcfg_allocation *) &mcfg[1];
254
255 arr = kcalloc(n, sizeof(*arr), GFP_KERNEL);
256 if (!arr)
257 return -ENOMEM;
258
259 for (i = 0, e = arr; i < n; i++, mptr++, e++) {
260 e->segment = mptr->pci_segment;
261 e->addr = mptr->address;
262 e->bus_start = mptr->start_bus_number;
263 e->bus_end = mptr->end_bus_number;
264 list_add(&e->list, &pci_mcfg_list);
265 }
266
267#ifdef CONFIG_PCI_QUIRKS
268 /* Save MCFG IDs and revision for quirks matching */
269 memcpy(mcfg_oem_id, header->oem_id, ACPI_OEM_ID_SIZE);
270 memcpy(mcfg_oem_table_id, header->oem_table_id, ACPI_OEM_TABLE_ID_SIZE);
271 mcfg_oem_revision = header->oem_revision;
272#endif
273
274 pr_info("MCFG table detected, %d entries\n", n);
275 return 0;
276}
277
278/* Interface called by ACPI - parse and save MCFG table */
279void __init pci_mmcfg_late_init(void)
280{
281 int err = acpi_table_parse(ACPI_SIG_MCFG, pci_mcfg_parse);
282 if (err)
283 pr_err("Failed to parse MCFG (%d)\n", err);
284}
1/*
2 * Copyright (C) 2016 Broadcom
3 * Author: Jayachandran C <jchandra@broadcom.com>
4 * Copyright (C) 2016 Semihalf
5 * Author: Tomasz Nowicki <tn@semihalf.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License, version 2, as
9 * published by the Free Software Foundation (the "GPL").
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License version 2 (GPLv2) for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * version 2 (GPLv2) along with this source code.
18 */
19
20#define pr_fmt(fmt) "ACPI: " fmt
21
22#include <linux/kernel.h>
23#include <linux/pci.h>
24#include <linux/pci-acpi.h>
25#include <linux/pci-ecam.h>
26
27/* Structure to hold entries from the MCFG table */
28struct mcfg_entry {
29 struct list_head list;
30 phys_addr_t addr;
31 u16 segment;
32 u8 bus_start;
33 u8 bus_end;
34};
35
36#ifdef CONFIG_PCI_QUIRKS
37struct mcfg_fixup {
38 char oem_id[ACPI_OEM_ID_SIZE + 1];
39 char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
40 u32 oem_revision;
41 u16 segment;
42 struct resource bus_range;
43 struct pci_ecam_ops *ops;
44 struct resource cfgres;
45};
46
47#define MCFG_BUS_RANGE(start, end) DEFINE_RES_NAMED((start), \
48 ((end) - (start) + 1), \
49 NULL, IORESOURCE_BUS)
50#define MCFG_BUS_ANY MCFG_BUS_RANGE(0x0, 0xff)
51
52static struct mcfg_fixup mcfg_quirks[] = {
53/* { OEM_ID, OEM_TABLE_ID, REV, SEGMENT, BUS_RANGE, ops, cfgres }, */
54
55#define QCOM_ECAM32(seg) \
56 { "QCOM ", "QDF2432 ", 1, seg, MCFG_BUS_ANY, &pci_32b_ops }
57 QCOM_ECAM32(0),
58 QCOM_ECAM32(1),
59 QCOM_ECAM32(2),
60 QCOM_ECAM32(3),
61 QCOM_ECAM32(4),
62 QCOM_ECAM32(5),
63 QCOM_ECAM32(6),
64 QCOM_ECAM32(7),
65
66#define HISI_QUAD_DOM(table_id, seg, ops) \
67 { "HISI ", table_id, 0, (seg) + 0, MCFG_BUS_ANY, ops }, \
68 { "HISI ", table_id, 0, (seg) + 1, MCFG_BUS_ANY, ops }, \
69 { "HISI ", table_id, 0, (seg) + 2, MCFG_BUS_ANY, ops }, \
70 { "HISI ", table_id, 0, (seg) + 3, MCFG_BUS_ANY, ops }
71 HISI_QUAD_DOM("HIP05 ", 0, &hisi_pcie_ops),
72 HISI_QUAD_DOM("HIP06 ", 0, &hisi_pcie_ops),
73 HISI_QUAD_DOM("HIP07 ", 0, &hisi_pcie_ops),
74 HISI_QUAD_DOM("HIP07 ", 4, &hisi_pcie_ops),
75 HISI_QUAD_DOM("HIP07 ", 8, &hisi_pcie_ops),
76 HISI_QUAD_DOM("HIP07 ", 12, &hisi_pcie_ops),
77
78#define THUNDER_PEM_RES(addr, node) \
79 DEFINE_RES_MEM((addr) + ((u64) (node) << 44), 0x39 * SZ_16M)
80#define THUNDER_PEM_QUIRK(rev, node) \
81 { "CAVIUM", "THUNDERX", rev, 4 + (10 * (node)), MCFG_BUS_ANY, \
82 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88001f000000UL, node) }, \
83 { "CAVIUM", "THUNDERX", rev, 5 + (10 * (node)), MCFG_BUS_ANY, \
84 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x884057000000UL, node) }, \
85 { "CAVIUM", "THUNDERX", rev, 6 + (10 * (node)), MCFG_BUS_ANY, \
86 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88808f000000UL, node) }, \
87 { "CAVIUM", "THUNDERX", rev, 7 + (10 * (node)), MCFG_BUS_ANY, \
88 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89001f000000UL, node) }, \
89 { "CAVIUM", "THUNDERX", rev, 8 + (10 * (node)), MCFG_BUS_ANY, \
90 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x894057000000UL, node) }, \
91 { "CAVIUM", "THUNDERX", rev, 9 + (10 * (node)), MCFG_BUS_ANY, \
92 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89808f000000UL, node) }
93 /* SoC pass2.x */
94 THUNDER_PEM_QUIRK(1, 0),
95 THUNDER_PEM_QUIRK(1, 1),
96
97#define THUNDER_ECAM_QUIRK(rev, seg) \
98 { "CAVIUM", "THUNDERX", rev, seg, MCFG_BUS_ANY, \
99 &pci_thunder_ecam_ops }
100 /* SoC pass1.x */
101 THUNDER_PEM_QUIRK(2, 0), /* off-chip devices */
102 THUNDER_PEM_QUIRK(2, 1), /* off-chip devices */
103 THUNDER_ECAM_QUIRK(2, 0),
104 THUNDER_ECAM_QUIRK(2, 1),
105 THUNDER_ECAM_QUIRK(2, 2),
106 THUNDER_ECAM_QUIRK(2, 3),
107 THUNDER_ECAM_QUIRK(2, 10),
108 THUNDER_ECAM_QUIRK(2, 11),
109 THUNDER_ECAM_QUIRK(2, 12),
110 THUNDER_ECAM_QUIRK(2, 13),
111
112#define XGENE_V1_ECAM_MCFG(rev, seg) \
113 {"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \
114 &xgene_v1_pcie_ecam_ops }
115#define XGENE_V2_ECAM_MCFG(rev, seg) \
116 {"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \
117 &xgene_v2_pcie_ecam_ops }
118 /* X-Gene SoC with v1 PCIe controller */
119 XGENE_V1_ECAM_MCFG(1, 0),
120 XGENE_V1_ECAM_MCFG(1, 1),
121 XGENE_V1_ECAM_MCFG(1, 2),
122 XGENE_V1_ECAM_MCFG(1, 3),
123 XGENE_V1_ECAM_MCFG(1, 4),
124 XGENE_V1_ECAM_MCFG(2, 0),
125 XGENE_V1_ECAM_MCFG(2, 1),
126 XGENE_V1_ECAM_MCFG(2, 2),
127 XGENE_V1_ECAM_MCFG(2, 3),
128 XGENE_V1_ECAM_MCFG(2, 4),
129 /* X-Gene SoC with v2.1 PCIe controller */
130 XGENE_V2_ECAM_MCFG(3, 0),
131 XGENE_V2_ECAM_MCFG(3, 1),
132 /* X-Gene SoC with v2.2 PCIe controller */
133 XGENE_V2_ECAM_MCFG(4, 0),
134 XGENE_V2_ECAM_MCFG(4, 1),
135 XGENE_V2_ECAM_MCFG(4, 2),
136};
137
138static char mcfg_oem_id[ACPI_OEM_ID_SIZE];
139static char mcfg_oem_table_id[ACPI_OEM_TABLE_ID_SIZE];
140static u32 mcfg_oem_revision;
141
142static int pci_mcfg_quirk_matches(struct mcfg_fixup *f, u16 segment,
143 struct resource *bus_range)
144{
145 if (!memcmp(f->oem_id, mcfg_oem_id, ACPI_OEM_ID_SIZE) &&
146 !memcmp(f->oem_table_id, mcfg_oem_table_id,
147 ACPI_OEM_TABLE_ID_SIZE) &&
148 f->oem_revision == mcfg_oem_revision &&
149 f->segment == segment &&
150 resource_contains(&f->bus_range, bus_range))
151 return 1;
152
153 return 0;
154}
155#endif
156
157static void pci_mcfg_apply_quirks(struct acpi_pci_root *root,
158 struct resource *cfgres,
159 struct pci_ecam_ops **ecam_ops)
160{
161#ifdef CONFIG_PCI_QUIRKS
162 u16 segment = root->segment;
163 struct resource *bus_range = &root->secondary;
164 struct mcfg_fixup *f;
165 int i;
166
167 for (i = 0, f = mcfg_quirks; i < ARRAY_SIZE(mcfg_quirks); i++, f++) {
168 if (pci_mcfg_quirk_matches(f, segment, bus_range)) {
169 if (f->cfgres.start)
170 *cfgres = f->cfgres;
171 if (f->ops)
172 *ecam_ops = f->ops;
173 dev_info(&root->device->dev, "MCFG quirk: ECAM at %pR for %pR with %ps\n",
174 cfgres, bus_range, *ecam_ops);
175 return;
176 }
177 }
178#endif
179}
180
181/* List to save MCFG entries */
182static LIST_HEAD(pci_mcfg_list);
183
184int pci_mcfg_lookup(struct acpi_pci_root *root, struct resource *cfgres,
185 struct pci_ecam_ops **ecam_ops)
186{
187 struct pci_ecam_ops *ops = &pci_generic_ecam_ops;
188 struct resource *bus_res = &root->secondary;
189 u16 seg = root->segment;
190 struct mcfg_entry *e;
191 struct resource res;
192
193 /* Use address from _CBA if present, otherwise lookup MCFG */
194 if (root->mcfg_addr)
195 goto skip_lookup;
196
197 /*
198 * We expect exact match, unless MCFG entry end bus covers more than
199 * specified by caller.
200 */
201 list_for_each_entry(e, &pci_mcfg_list, list) {
202 if (e->segment == seg && e->bus_start == bus_res->start &&
203 e->bus_end >= bus_res->end) {
204 root->mcfg_addr = e->addr;
205 }
206
207 }
208
209skip_lookup:
210 memset(&res, 0, sizeof(res));
211 if (root->mcfg_addr) {
212 res.start = root->mcfg_addr + (bus_res->start << 20);
213 res.end = res.start + (resource_size(bus_res) << 20) - 1;
214 res.flags = IORESOURCE_MEM;
215 }
216
217 /*
218 * Allow quirks to override default ECAM ops and CFG resource
219 * range. This may even fabricate a CFG resource range in case
220 * MCFG does not have it. Invalid CFG start address means MCFG
221 * firmware bug or we need another quirk in array.
222 */
223 pci_mcfg_apply_quirks(root, &res, &ops);
224 if (!res.start)
225 return -ENXIO;
226
227 *cfgres = res;
228 *ecam_ops = ops;
229 return 0;
230}
231
232static __init int pci_mcfg_parse(struct acpi_table_header *header)
233{
234 struct acpi_table_mcfg *mcfg;
235 struct acpi_mcfg_allocation *mptr;
236 struct mcfg_entry *e, *arr;
237 int i, n;
238
239 if (header->length < sizeof(struct acpi_table_mcfg))
240 return -EINVAL;
241
242 n = (header->length - sizeof(struct acpi_table_mcfg)) /
243 sizeof(struct acpi_mcfg_allocation);
244 mcfg = (struct acpi_table_mcfg *)header;
245 mptr = (struct acpi_mcfg_allocation *) &mcfg[1];
246
247 arr = kcalloc(n, sizeof(*arr), GFP_KERNEL);
248 if (!arr)
249 return -ENOMEM;
250
251 for (i = 0, e = arr; i < n; i++, mptr++, e++) {
252 e->segment = mptr->pci_segment;
253 e->addr = mptr->address;
254 e->bus_start = mptr->start_bus_number;
255 e->bus_end = mptr->end_bus_number;
256 list_add(&e->list, &pci_mcfg_list);
257 }
258
259#ifdef CONFIG_PCI_QUIRKS
260 /* Save MCFG IDs and revision for quirks matching */
261 memcpy(mcfg_oem_id, header->oem_id, ACPI_OEM_ID_SIZE);
262 memcpy(mcfg_oem_table_id, header->oem_table_id, ACPI_OEM_TABLE_ID_SIZE);
263 mcfg_oem_revision = header->oem_revision;
264#endif
265
266 pr_info("MCFG table detected, %d entries\n", n);
267 return 0;
268}
269
270/* Interface called by ACPI - parse and save MCFG table */
271void __init pci_mmcfg_late_init(void)
272{
273 int err = acpi_table_parse(ACPI_SIG_MCFG, pci_mcfg_parse);
274 if (err)
275 pr_err("Failed to parse MCFG (%d)\n", err);
276}