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1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2012 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_AGL_DEFS_H__
29#define __CVMX_AGL_DEFS_H__
30
31#define CVMX_AGL_GMX_BAD_REG (CVMX_ADD_IO_SEG(0x00011800E0000518ull))
32#define CVMX_AGL_GMX_BIST (CVMX_ADD_IO_SEG(0x00011800E0000400ull))
33#define CVMX_AGL_GMX_DRV_CTL (CVMX_ADD_IO_SEG(0x00011800E00007F0ull))
34#define CVMX_AGL_GMX_INF_MODE (CVMX_ADD_IO_SEG(0x00011800E00007F8ull))
35#define CVMX_AGL_GMX_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000010ull) + ((offset) & 1) * 2048)
36#define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) (CVMX_ADD_IO_SEG(0x00011800E0000180ull) + ((offset) & 1) * 2048)
37#define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) (CVMX_ADD_IO_SEG(0x00011800E0000188ull) + ((offset) & 1) * 2048)
38#define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) (CVMX_ADD_IO_SEG(0x00011800E0000190ull) + ((offset) & 1) * 2048)
39#define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) (CVMX_ADD_IO_SEG(0x00011800E0000198ull) + ((offset) & 1) * 2048)
40#define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) (CVMX_ADD_IO_SEG(0x00011800E00001A0ull) + ((offset) & 1) * 2048)
41#define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) (CVMX_ADD_IO_SEG(0x00011800E00001A8ull) + ((offset) & 1) * 2048)
42#define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000108ull) + ((offset) & 1) * 2048)
43#define CVMX_AGL_GMX_RXX_ADR_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000100ull) + ((offset) & 1) * 2048)
44#define CVMX_AGL_GMX_RXX_DECISION(offset) (CVMX_ADD_IO_SEG(0x00011800E0000040ull) + ((offset) & 1) * 2048)
45#define CVMX_AGL_GMX_RXX_FRM_CHK(offset) (CVMX_ADD_IO_SEG(0x00011800E0000020ull) + ((offset) & 1) * 2048)
46#define CVMX_AGL_GMX_RXX_FRM_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000018ull) + ((offset) & 1) * 2048)
47#define CVMX_AGL_GMX_RXX_FRM_MAX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000030ull) + ((offset) & 1) * 2048)
48#define CVMX_AGL_GMX_RXX_FRM_MIN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000028ull) + ((offset) & 1) * 2048)
49#define CVMX_AGL_GMX_RXX_IFG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000058ull) + ((offset) & 1) * 2048)
50#define CVMX_AGL_GMX_RXX_INT_EN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000008ull) + ((offset) & 1) * 2048)
51#define CVMX_AGL_GMX_RXX_INT_REG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000000ull) + ((offset) & 1) * 2048)
52#define CVMX_AGL_GMX_RXX_JABBER(offset) (CVMX_ADD_IO_SEG(0x00011800E0000038ull) + ((offset) & 1) * 2048)
53#define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) (CVMX_ADD_IO_SEG(0x00011800E0000068ull) + ((offset) & 1) * 2048)
54#define CVMX_AGL_GMX_RXX_RX_INBND(offset) (CVMX_ADD_IO_SEG(0x00011800E0000060ull) + ((offset) & 1) * 2048)
55#define CVMX_AGL_GMX_RXX_STATS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000050ull) + ((offset) & 1) * 2048)
56#define CVMX_AGL_GMX_RXX_STATS_OCTS(offset) (CVMX_ADD_IO_SEG(0x00011800E0000088ull) + ((offset) & 1) * 2048)
57#define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000098ull) + ((offset) & 1) * 2048)
58#define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) (CVMX_ADD_IO_SEG(0x00011800E00000A8ull) + ((offset) & 1) * 2048)
59#define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) (CVMX_ADD_IO_SEG(0x00011800E00000B8ull) + ((offset) & 1) * 2048)
60#define CVMX_AGL_GMX_RXX_STATS_PKTS(offset) (CVMX_ADD_IO_SEG(0x00011800E0000080ull) + ((offset) & 1) * 2048)
61#define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) (CVMX_ADD_IO_SEG(0x00011800E00000C0ull) + ((offset) & 1) * 2048)
62#define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000090ull) + ((offset) & 1) * 2048)
63#define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) (CVMX_ADD_IO_SEG(0x00011800E00000A0ull) + ((offset) & 1) * 2048)
64#define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) (CVMX_ADD_IO_SEG(0x00011800E00000B0ull) + ((offset) & 1) * 2048)
65#define CVMX_AGL_GMX_RXX_UDD_SKP(offset) (CVMX_ADD_IO_SEG(0x00011800E0000048ull) + ((offset) & 1) * 2048)
66#define CVMX_AGL_GMX_RX_BP_DROPX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000420ull) + ((offset) & 1) * 8)
67#define CVMX_AGL_GMX_RX_BP_OFFX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000460ull) + ((offset) & 1) * 8)
68#define CVMX_AGL_GMX_RX_BP_ONX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000440ull) + ((offset) & 1) * 8)
69#define CVMX_AGL_GMX_RX_PRT_INFO (CVMX_ADD_IO_SEG(0x00011800E00004E8ull))
70#define CVMX_AGL_GMX_RX_TX_STATUS (CVMX_ADD_IO_SEG(0x00011800E00007E8ull))
71#define CVMX_AGL_GMX_SMACX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000230ull) + ((offset) & 1) * 2048)
72#define CVMX_AGL_GMX_STAT_BP (CVMX_ADD_IO_SEG(0x00011800E0000520ull))
73#define CVMX_AGL_GMX_TXX_APPEND(offset) (CVMX_ADD_IO_SEG(0x00011800E0000218ull) + ((offset) & 1) * 2048)
74#define CVMX_AGL_GMX_TXX_CLK(offset) (CVMX_ADD_IO_SEG(0x00011800E0000208ull) + ((offset) & 1) * 2048)
75#define CVMX_AGL_GMX_TXX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000270ull) + ((offset) & 1) * 2048)
76#define CVMX_AGL_GMX_TXX_MIN_PKT(offset) (CVMX_ADD_IO_SEG(0x00011800E0000240ull) + ((offset) & 1) * 2048)
77#define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000248ull) + ((offset) & 1) * 2048)
78#define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset) (CVMX_ADD_IO_SEG(0x00011800E0000238ull) + ((offset) & 1) * 2048)
79#define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset) (CVMX_ADD_IO_SEG(0x00011800E0000258ull) + ((offset) & 1) * 2048)
80#define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset) (CVMX_ADD_IO_SEG(0x00011800E0000260ull) + ((offset) & 1) * 2048)
81#define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset) (CVMX_ADD_IO_SEG(0x00011800E0000250ull) + ((offset) & 1) * 2048)
82#define CVMX_AGL_GMX_TXX_STAT0(offset) (CVMX_ADD_IO_SEG(0x00011800E0000280ull) + ((offset) & 1) * 2048)
83#define CVMX_AGL_GMX_TXX_STAT1(offset) (CVMX_ADD_IO_SEG(0x00011800E0000288ull) + ((offset) & 1) * 2048)
84#define CVMX_AGL_GMX_TXX_STAT2(offset) (CVMX_ADD_IO_SEG(0x00011800E0000290ull) + ((offset) & 1) * 2048)
85#define CVMX_AGL_GMX_TXX_STAT3(offset) (CVMX_ADD_IO_SEG(0x00011800E0000298ull) + ((offset) & 1) * 2048)
86#define CVMX_AGL_GMX_TXX_STAT4(offset) (CVMX_ADD_IO_SEG(0x00011800E00002A0ull) + ((offset) & 1) * 2048)
87#define CVMX_AGL_GMX_TXX_STAT5(offset) (CVMX_ADD_IO_SEG(0x00011800E00002A8ull) + ((offset) & 1) * 2048)
88#define CVMX_AGL_GMX_TXX_STAT6(offset) (CVMX_ADD_IO_SEG(0x00011800E00002B0ull) + ((offset) & 1) * 2048)
89#define CVMX_AGL_GMX_TXX_STAT7(offset) (CVMX_ADD_IO_SEG(0x00011800E00002B8ull) + ((offset) & 1) * 2048)
90#define CVMX_AGL_GMX_TXX_STAT8(offset) (CVMX_ADD_IO_SEG(0x00011800E00002C0ull) + ((offset) & 1) * 2048)
91#define CVMX_AGL_GMX_TXX_STAT9(offset) (CVMX_ADD_IO_SEG(0x00011800E00002C8ull) + ((offset) & 1) * 2048)
92#define CVMX_AGL_GMX_TXX_STATS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000268ull) + ((offset) & 1) * 2048)
93#define CVMX_AGL_GMX_TXX_THRESH(offset) (CVMX_ADD_IO_SEG(0x00011800E0000210ull) + ((offset) & 1) * 2048)
94#define CVMX_AGL_GMX_TX_BP (CVMX_ADD_IO_SEG(0x00011800E00004D0ull))
95#define CVMX_AGL_GMX_TX_COL_ATTEMPT (CVMX_ADD_IO_SEG(0x00011800E0000498ull))
96#define CVMX_AGL_GMX_TX_IFG (CVMX_ADD_IO_SEG(0x00011800E0000488ull))
97#define CVMX_AGL_GMX_TX_INT_EN (CVMX_ADD_IO_SEG(0x00011800E0000508ull))
98#define CVMX_AGL_GMX_TX_INT_REG (CVMX_ADD_IO_SEG(0x00011800E0000500ull))
99#define CVMX_AGL_GMX_TX_JAM (CVMX_ADD_IO_SEG(0x00011800E0000490ull))
100#define CVMX_AGL_GMX_TX_LFSR (CVMX_ADD_IO_SEG(0x00011800E00004F8ull))
101#define CVMX_AGL_GMX_TX_OVR_BP (CVMX_ADD_IO_SEG(0x00011800E00004C8ull))
102#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC (CVMX_ADD_IO_SEG(0x00011800E00004A0ull))
103#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE (CVMX_ADD_IO_SEG(0x00011800E00004A8ull))
104#define CVMX_AGL_PRTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0002000ull) + ((offset) & 1) * 8)
105
106union cvmx_agl_gmx_bad_reg {
107 uint64_t u64;
108 struct cvmx_agl_gmx_bad_reg_s {
109#ifdef __BIG_ENDIAN_BITFIELD
110 uint64_t reserved_38_63:26;
111 uint64_t txpsh1:1;
112 uint64_t txpop1:1;
113 uint64_t ovrflw1:1;
114 uint64_t txpsh:1;
115 uint64_t txpop:1;
116 uint64_t ovrflw:1;
117 uint64_t reserved_27_31:5;
118 uint64_t statovr:1;
119 uint64_t reserved_24_25:2;
120 uint64_t loststat:2;
121 uint64_t reserved_4_21:18;
122 uint64_t out_ovr:2;
123 uint64_t reserved_0_1:2;
124#else
125 uint64_t reserved_0_1:2;
126 uint64_t out_ovr:2;
127 uint64_t reserved_4_21:18;
128 uint64_t loststat:2;
129 uint64_t reserved_24_25:2;
130 uint64_t statovr:1;
131 uint64_t reserved_27_31:5;
132 uint64_t ovrflw:1;
133 uint64_t txpop:1;
134 uint64_t txpsh:1;
135 uint64_t ovrflw1:1;
136 uint64_t txpop1:1;
137 uint64_t txpsh1:1;
138 uint64_t reserved_38_63:26;
139#endif
140 } s;
141 struct cvmx_agl_gmx_bad_reg_cn52xx {
142#ifdef __BIG_ENDIAN_BITFIELD
143 uint64_t reserved_38_63:26;
144 uint64_t txpsh1:1;
145 uint64_t txpop1:1;
146 uint64_t ovrflw1:1;
147 uint64_t txpsh:1;
148 uint64_t txpop:1;
149 uint64_t ovrflw:1;
150 uint64_t reserved_27_31:5;
151 uint64_t statovr:1;
152 uint64_t reserved_23_25:3;
153 uint64_t loststat:1;
154 uint64_t reserved_4_21:18;
155 uint64_t out_ovr:2;
156 uint64_t reserved_0_1:2;
157#else
158 uint64_t reserved_0_1:2;
159 uint64_t out_ovr:2;
160 uint64_t reserved_4_21:18;
161 uint64_t loststat:1;
162 uint64_t reserved_23_25:3;
163 uint64_t statovr:1;
164 uint64_t reserved_27_31:5;
165 uint64_t ovrflw:1;
166 uint64_t txpop:1;
167 uint64_t txpsh:1;
168 uint64_t ovrflw1:1;
169 uint64_t txpop1:1;
170 uint64_t txpsh1:1;
171 uint64_t reserved_38_63:26;
172#endif
173 } cn52xx;
174 struct cvmx_agl_gmx_bad_reg_cn56xx {
175#ifdef __BIG_ENDIAN_BITFIELD
176 uint64_t reserved_35_63:29;
177 uint64_t txpsh:1;
178 uint64_t txpop:1;
179 uint64_t ovrflw:1;
180 uint64_t reserved_27_31:5;
181 uint64_t statovr:1;
182 uint64_t reserved_23_25:3;
183 uint64_t loststat:1;
184 uint64_t reserved_3_21:19;
185 uint64_t out_ovr:1;
186 uint64_t reserved_0_1:2;
187#else
188 uint64_t reserved_0_1:2;
189 uint64_t out_ovr:1;
190 uint64_t reserved_3_21:19;
191 uint64_t loststat:1;
192 uint64_t reserved_23_25:3;
193 uint64_t statovr:1;
194 uint64_t reserved_27_31:5;
195 uint64_t ovrflw:1;
196 uint64_t txpop:1;
197 uint64_t txpsh:1;
198 uint64_t reserved_35_63:29;
199#endif
200 } cn56xx;
201};
202
203union cvmx_agl_gmx_bist {
204 uint64_t u64;
205 struct cvmx_agl_gmx_bist_s {
206#ifdef __BIG_ENDIAN_BITFIELD
207 uint64_t reserved_25_63:39;
208 uint64_t status:25;
209#else
210 uint64_t status:25;
211 uint64_t reserved_25_63:39;
212#endif
213 } s;
214 struct cvmx_agl_gmx_bist_cn52xx {
215#ifdef __BIG_ENDIAN_BITFIELD
216 uint64_t reserved_10_63:54;
217 uint64_t status:10;
218#else
219 uint64_t status:10;
220 uint64_t reserved_10_63:54;
221#endif
222 } cn52xx;
223};
224
225union cvmx_agl_gmx_drv_ctl {
226 uint64_t u64;
227 struct cvmx_agl_gmx_drv_ctl_s {
228#ifdef __BIG_ENDIAN_BITFIELD
229 uint64_t reserved_49_63:15;
230 uint64_t byp_en1:1;
231 uint64_t reserved_45_47:3;
232 uint64_t pctl1:5;
233 uint64_t reserved_37_39:3;
234 uint64_t nctl1:5;
235 uint64_t reserved_17_31:15;
236 uint64_t byp_en:1;
237 uint64_t reserved_13_15:3;
238 uint64_t pctl:5;
239 uint64_t reserved_5_7:3;
240 uint64_t nctl:5;
241#else
242 uint64_t nctl:5;
243 uint64_t reserved_5_7:3;
244 uint64_t pctl:5;
245 uint64_t reserved_13_15:3;
246 uint64_t byp_en:1;
247 uint64_t reserved_17_31:15;
248 uint64_t nctl1:5;
249 uint64_t reserved_37_39:3;
250 uint64_t pctl1:5;
251 uint64_t reserved_45_47:3;
252 uint64_t byp_en1:1;
253 uint64_t reserved_49_63:15;
254#endif
255 } s;
256 struct cvmx_agl_gmx_drv_ctl_cn56xx {
257#ifdef __BIG_ENDIAN_BITFIELD
258 uint64_t reserved_17_63:47;
259 uint64_t byp_en:1;
260 uint64_t reserved_13_15:3;
261 uint64_t pctl:5;
262 uint64_t reserved_5_7:3;
263 uint64_t nctl:5;
264#else
265 uint64_t nctl:5;
266 uint64_t reserved_5_7:3;
267 uint64_t pctl:5;
268 uint64_t reserved_13_15:3;
269 uint64_t byp_en:1;
270 uint64_t reserved_17_63:47;
271#endif
272 } cn56xx;
273};
274
275union cvmx_agl_gmx_inf_mode {
276 uint64_t u64;
277 struct cvmx_agl_gmx_inf_mode_s {
278#ifdef __BIG_ENDIAN_BITFIELD
279 uint64_t reserved_2_63:62;
280 uint64_t en:1;
281 uint64_t reserved_0_0:1;
282#else
283 uint64_t reserved_0_0:1;
284 uint64_t en:1;
285 uint64_t reserved_2_63:62;
286#endif
287 } s;
288};
289
290union cvmx_agl_gmx_prtx_cfg {
291 uint64_t u64;
292 struct cvmx_agl_gmx_prtx_cfg_s {
293#ifdef __BIG_ENDIAN_BITFIELD
294 uint64_t reserved_14_63:50;
295 uint64_t tx_idle:1;
296 uint64_t rx_idle:1;
297 uint64_t reserved_9_11:3;
298 uint64_t speed_msb:1;
299 uint64_t reserved_7_7:1;
300 uint64_t burst:1;
301 uint64_t tx_en:1;
302 uint64_t rx_en:1;
303 uint64_t slottime:1;
304 uint64_t duplex:1;
305 uint64_t speed:1;
306 uint64_t en:1;
307#else
308 uint64_t en:1;
309 uint64_t speed:1;
310 uint64_t duplex:1;
311 uint64_t slottime:1;
312 uint64_t rx_en:1;
313 uint64_t tx_en:1;
314 uint64_t burst:1;
315 uint64_t reserved_7_7:1;
316 uint64_t speed_msb:1;
317 uint64_t reserved_9_11:3;
318 uint64_t rx_idle:1;
319 uint64_t tx_idle:1;
320 uint64_t reserved_14_63:50;
321#endif
322 } s;
323 struct cvmx_agl_gmx_prtx_cfg_cn52xx {
324#ifdef __BIG_ENDIAN_BITFIELD
325 uint64_t reserved_6_63:58;
326 uint64_t tx_en:1;
327 uint64_t rx_en:1;
328 uint64_t slottime:1;
329 uint64_t duplex:1;
330 uint64_t speed:1;
331 uint64_t en:1;
332#else
333 uint64_t en:1;
334 uint64_t speed:1;
335 uint64_t duplex:1;
336 uint64_t slottime:1;
337 uint64_t rx_en:1;
338 uint64_t tx_en:1;
339 uint64_t reserved_6_63:58;
340#endif
341 } cn52xx;
342};
343
344union cvmx_agl_gmx_rxx_adr_cam0 {
345 uint64_t u64;
346 struct cvmx_agl_gmx_rxx_adr_cam0_s {
347#ifdef __BIG_ENDIAN_BITFIELD
348 uint64_t adr:64;
349#else
350 uint64_t adr:64;
351#endif
352 } s;
353};
354
355union cvmx_agl_gmx_rxx_adr_cam1 {
356 uint64_t u64;
357 struct cvmx_agl_gmx_rxx_adr_cam1_s {
358#ifdef __BIG_ENDIAN_BITFIELD
359 uint64_t adr:64;
360#else
361 uint64_t adr:64;
362#endif
363 } s;
364};
365
366union cvmx_agl_gmx_rxx_adr_cam2 {
367 uint64_t u64;
368 struct cvmx_agl_gmx_rxx_adr_cam2_s {
369#ifdef __BIG_ENDIAN_BITFIELD
370 uint64_t adr:64;
371#else
372 uint64_t adr:64;
373#endif
374 } s;
375};
376
377union cvmx_agl_gmx_rxx_adr_cam3 {
378 uint64_t u64;
379 struct cvmx_agl_gmx_rxx_adr_cam3_s {
380#ifdef __BIG_ENDIAN_BITFIELD
381 uint64_t adr:64;
382#else
383 uint64_t adr:64;
384#endif
385 } s;
386};
387
388union cvmx_agl_gmx_rxx_adr_cam4 {
389 uint64_t u64;
390 struct cvmx_agl_gmx_rxx_adr_cam4_s {
391#ifdef __BIG_ENDIAN_BITFIELD
392 uint64_t adr:64;
393#else
394 uint64_t adr:64;
395#endif
396 } s;
397};
398
399union cvmx_agl_gmx_rxx_adr_cam5 {
400 uint64_t u64;
401 struct cvmx_agl_gmx_rxx_adr_cam5_s {
402#ifdef __BIG_ENDIAN_BITFIELD
403 uint64_t adr:64;
404#else
405 uint64_t adr:64;
406#endif
407 } s;
408};
409
410union cvmx_agl_gmx_rxx_adr_cam_en {
411 uint64_t u64;
412 struct cvmx_agl_gmx_rxx_adr_cam_en_s {
413#ifdef __BIG_ENDIAN_BITFIELD
414 uint64_t reserved_8_63:56;
415 uint64_t en:8;
416#else
417 uint64_t en:8;
418 uint64_t reserved_8_63:56;
419#endif
420 } s;
421};
422
423union cvmx_agl_gmx_rxx_adr_ctl {
424 uint64_t u64;
425 struct cvmx_agl_gmx_rxx_adr_ctl_s {
426#ifdef __BIG_ENDIAN_BITFIELD
427 uint64_t reserved_4_63:60;
428 uint64_t cam_mode:1;
429 uint64_t mcst:2;
430 uint64_t bcst:1;
431#else
432 uint64_t bcst:1;
433 uint64_t mcst:2;
434 uint64_t cam_mode:1;
435 uint64_t reserved_4_63:60;
436#endif
437 } s;
438};
439
440union cvmx_agl_gmx_rxx_decision {
441 uint64_t u64;
442 struct cvmx_agl_gmx_rxx_decision_s {
443#ifdef __BIG_ENDIAN_BITFIELD
444 uint64_t reserved_5_63:59;
445 uint64_t cnt:5;
446#else
447 uint64_t cnt:5;
448 uint64_t reserved_5_63:59;
449#endif
450 } s;
451};
452
453union cvmx_agl_gmx_rxx_frm_chk {
454 uint64_t u64;
455 struct cvmx_agl_gmx_rxx_frm_chk_s {
456#ifdef __BIG_ENDIAN_BITFIELD
457 uint64_t reserved_10_63:54;
458 uint64_t niberr:1;
459 uint64_t skperr:1;
460 uint64_t rcverr:1;
461 uint64_t lenerr:1;
462 uint64_t alnerr:1;
463 uint64_t fcserr:1;
464 uint64_t jabber:1;
465 uint64_t maxerr:1;
466 uint64_t carext:1;
467 uint64_t minerr:1;
468#else
469 uint64_t minerr:1;
470 uint64_t carext:1;
471 uint64_t maxerr:1;
472 uint64_t jabber:1;
473 uint64_t fcserr:1;
474 uint64_t alnerr:1;
475 uint64_t lenerr:1;
476 uint64_t rcverr:1;
477 uint64_t skperr:1;
478 uint64_t niberr:1;
479 uint64_t reserved_10_63:54;
480#endif
481 } s;
482 struct cvmx_agl_gmx_rxx_frm_chk_cn52xx {
483#ifdef __BIG_ENDIAN_BITFIELD
484 uint64_t reserved_9_63:55;
485 uint64_t skperr:1;
486 uint64_t rcverr:1;
487 uint64_t lenerr:1;
488 uint64_t alnerr:1;
489 uint64_t fcserr:1;
490 uint64_t jabber:1;
491 uint64_t maxerr:1;
492 uint64_t reserved_1_1:1;
493 uint64_t minerr:1;
494#else
495 uint64_t minerr:1;
496 uint64_t reserved_1_1:1;
497 uint64_t maxerr:1;
498 uint64_t jabber:1;
499 uint64_t fcserr:1;
500 uint64_t alnerr:1;
501 uint64_t lenerr:1;
502 uint64_t rcverr:1;
503 uint64_t skperr:1;
504 uint64_t reserved_9_63:55;
505#endif
506 } cn52xx;
507};
508
509union cvmx_agl_gmx_rxx_frm_ctl {
510 uint64_t u64;
511 struct cvmx_agl_gmx_rxx_frm_ctl_s {
512#ifdef __BIG_ENDIAN_BITFIELD
513 uint64_t reserved_13_63:51;
514 uint64_t ptp_mode:1;
515 uint64_t reserved_11_11:1;
516 uint64_t null_dis:1;
517 uint64_t pre_align:1;
518 uint64_t pad_len:1;
519 uint64_t vlan_len:1;
520 uint64_t pre_free:1;
521 uint64_t ctl_smac:1;
522 uint64_t ctl_mcst:1;
523 uint64_t ctl_bck:1;
524 uint64_t ctl_drp:1;
525 uint64_t pre_strp:1;
526 uint64_t pre_chk:1;
527#else
528 uint64_t pre_chk:1;
529 uint64_t pre_strp:1;
530 uint64_t ctl_drp:1;
531 uint64_t ctl_bck:1;
532 uint64_t ctl_mcst:1;
533 uint64_t ctl_smac:1;
534 uint64_t pre_free:1;
535 uint64_t vlan_len:1;
536 uint64_t pad_len:1;
537 uint64_t pre_align:1;
538 uint64_t null_dis:1;
539 uint64_t reserved_11_11:1;
540 uint64_t ptp_mode:1;
541 uint64_t reserved_13_63:51;
542#endif
543 } s;
544 struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx {
545#ifdef __BIG_ENDIAN_BITFIELD
546 uint64_t reserved_10_63:54;
547 uint64_t pre_align:1;
548 uint64_t pad_len:1;
549 uint64_t vlan_len:1;
550 uint64_t pre_free:1;
551 uint64_t ctl_smac:1;
552 uint64_t ctl_mcst:1;
553 uint64_t ctl_bck:1;
554 uint64_t ctl_drp:1;
555 uint64_t pre_strp:1;
556 uint64_t pre_chk:1;
557#else
558 uint64_t pre_chk:1;
559 uint64_t pre_strp:1;
560 uint64_t ctl_drp:1;
561 uint64_t ctl_bck:1;
562 uint64_t ctl_mcst:1;
563 uint64_t ctl_smac:1;
564 uint64_t pre_free:1;
565 uint64_t vlan_len:1;
566 uint64_t pad_len:1;
567 uint64_t pre_align:1;
568 uint64_t reserved_10_63:54;
569#endif
570 } cn52xx;
571};
572
573union cvmx_agl_gmx_rxx_frm_max {
574 uint64_t u64;
575 struct cvmx_agl_gmx_rxx_frm_max_s {
576#ifdef __BIG_ENDIAN_BITFIELD
577 uint64_t reserved_16_63:48;
578 uint64_t len:16;
579#else
580 uint64_t len:16;
581 uint64_t reserved_16_63:48;
582#endif
583 } s;
584};
585
586union cvmx_agl_gmx_rxx_frm_min {
587 uint64_t u64;
588 struct cvmx_agl_gmx_rxx_frm_min_s {
589#ifdef __BIG_ENDIAN_BITFIELD
590 uint64_t reserved_16_63:48;
591 uint64_t len:16;
592#else
593 uint64_t len:16;
594 uint64_t reserved_16_63:48;
595#endif
596 } s;
597};
598
599union cvmx_agl_gmx_rxx_ifg {
600 uint64_t u64;
601 struct cvmx_agl_gmx_rxx_ifg_s {
602#ifdef __BIG_ENDIAN_BITFIELD
603 uint64_t reserved_4_63:60;
604 uint64_t ifg:4;
605#else
606 uint64_t ifg:4;
607 uint64_t reserved_4_63:60;
608#endif
609 } s;
610};
611
612union cvmx_agl_gmx_rxx_int_en {
613 uint64_t u64;
614 struct cvmx_agl_gmx_rxx_int_en_s {
615#ifdef __BIG_ENDIAN_BITFIELD
616 uint64_t reserved_20_63:44;
617 uint64_t pause_drp:1;
618 uint64_t phy_dupx:1;
619 uint64_t phy_spd:1;
620 uint64_t phy_link:1;
621 uint64_t ifgerr:1;
622 uint64_t coldet:1;
623 uint64_t falerr:1;
624 uint64_t rsverr:1;
625 uint64_t pcterr:1;
626 uint64_t ovrerr:1;
627 uint64_t niberr:1;
628 uint64_t skperr:1;
629 uint64_t rcverr:1;
630 uint64_t lenerr:1;
631 uint64_t alnerr:1;
632 uint64_t fcserr:1;
633 uint64_t jabber:1;
634 uint64_t maxerr:1;
635 uint64_t carext:1;
636 uint64_t minerr:1;
637#else
638 uint64_t minerr:1;
639 uint64_t carext:1;
640 uint64_t maxerr:1;
641 uint64_t jabber:1;
642 uint64_t fcserr:1;
643 uint64_t alnerr:1;
644 uint64_t lenerr:1;
645 uint64_t rcverr:1;
646 uint64_t skperr:1;
647 uint64_t niberr:1;
648 uint64_t ovrerr:1;
649 uint64_t pcterr:1;
650 uint64_t rsverr:1;
651 uint64_t falerr:1;
652 uint64_t coldet:1;
653 uint64_t ifgerr:1;
654 uint64_t phy_link:1;
655 uint64_t phy_spd:1;
656 uint64_t phy_dupx:1;
657 uint64_t pause_drp:1;
658 uint64_t reserved_20_63:44;
659#endif
660 } s;
661 struct cvmx_agl_gmx_rxx_int_en_cn52xx {
662#ifdef __BIG_ENDIAN_BITFIELD
663 uint64_t reserved_20_63:44;
664 uint64_t pause_drp:1;
665 uint64_t reserved_16_18:3;
666 uint64_t ifgerr:1;
667 uint64_t coldet:1;
668 uint64_t falerr:1;
669 uint64_t rsverr:1;
670 uint64_t pcterr:1;
671 uint64_t ovrerr:1;
672 uint64_t reserved_9_9:1;
673 uint64_t skperr:1;
674 uint64_t rcverr:1;
675 uint64_t lenerr:1;
676 uint64_t alnerr:1;
677 uint64_t fcserr:1;
678 uint64_t jabber:1;
679 uint64_t maxerr:1;
680 uint64_t reserved_1_1:1;
681 uint64_t minerr:1;
682#else
683 uint64_t minerr:1;
684 uint64_t reserved_1_1:1;
685 uint64_t maxerr:1;
686 uint64_t jabber:1;
687 uint64_t fcserr:1;
688 uint64_t alnerr:1;
689 uint64_t lenerr:1;
690 uint64_t rcverr:1;
691 uint64_t skperr:1;
692 uint64_t reserved_9_9:1;
693 uint64_t ovrerr:1;
694 uint64_t pcterr:1;
695 uint64_t rsverr:1;
696 uint64_t falerr:1;
697 uint64_t coldet:1;
698 uint64_t ifgerr:1;
699 uint64_t reserved_16_18:3;
700 uint64_t pause_drp:1;
701 uint64_t reserved_20_63:44;
702#endif
703 } cn52xx;
704};
705
706union cvmx_agl_gmx_rxx_int_reg {
707 uint64_t u64;
708 struct cvmx_agl_gmx_rxx_int_reg_s {
709#ifdef __BIG_ENDIAN_BITFIELD
710 uint64_t reserved_20_63:44;
711 uint64_t pause_drp:1;
712 uint64_t phy_dupx:1;
713 uint64_t phy_spd:1;
714 uint64_t phy_link:1;
715 uint64_t ifgerr:1;
716 uint64_t coldet:1;
717 uint64_t falerr:1;
718 uint64_t rsverr:1;
719 uint64_t pcterr:1;
720 uint64_t ovrerr:1;
721 uint64_t niberr:1;
722 uint64_t skperr:1;
723 uint64_t rcverr:1;
724 uint64_t lenerr:1;
725 uint64_t alnerr:1;
726 uint64_t fcserr:1;
727 uint64_t jabber:1;
728 uint64_t maxerr:1;
729 uint64_t carext:1;
730 uint64_t minerr:1;
731#else
732 uint64_t minerr:1;
733 uint64_t carext:1;
734 uint64_t maxerr:1;
735 uint64_t jabber:1;
736 uint64_t fcserr:1;
737 uint64_t alnerr:1;
738 uint64_t lenerr:1;
739 uint64_t rcverr:1;
740 uint64_t skperr:1;
741 uint64_t niberr:1;
742 uint64_t ovrerr:1;
743 uint64_t pcterr:1;
744 uint64_t rsverr:1;
745 uint64_t falerr:1;
746 uint64_t coldet:1;
747 uint64_t ifgerr:1;
748 uint64_t phy_link:1;
749 uint64_t phy_spd:1;
750 uint64_t phy_dupx:1;
751 uint64_t pause_drp:1;
752 uint64_t reserved_20_63:44;
753#endif
754 } s;
755 struct cvmx_agl_gmx_rxx_int_reg_cn52xx {
756#ifdef __BIG_ENDIAN_BITFIELD
757 uint64_t reserved_20_63:44;
758 uint64_t pause_drp:1;
759 uint64_t reserved_16_18:3;
760 uint64_t ifgerr:1;
761 uint64_t coldet:1;
762 uint64_t falerr:1;
763 uint64_t rsverr:1;
764 uint64_t pcterr:1;
765 uint64_t ovrerr:1;
766 uint64_t reserved_9_9:1;
767 uint64_t skperr:1;
768 uint64_t rcverr:1;
769 uint64_t lenerr:1;
770 uint64_t alnerr:1;
771 uint64_t fcserr:1;
772 uint64_t jabber:1;
773 uint64_t maxerr:1;
774 uint64_t reserved_1_1:1;
775 uint64_t minerr:1;
776#else
777 uint64_t minerr:1;
778 uint64_t reserved_1_1:1;
779 uint64_t maxerr:1;
780 uint64_t jabber:1;
781 uint64_t fcserr:1;
782 uint64_t alnerr:1;
783 uint64_t lenerr:1;
784 uint64_t rcverr:1;
785 uint64_t skperr:1;
786 uint64_t reserved_9_9:1;
787 uint64_t ovrerr:1;
788 uint64_t pcterr:1;
789 uint64_t rsverr:1;
790 uint64_t falerr:1;
791 uint64_t coldet:1;
792 uint64_t ifgerr:1;
793 uint64_t reserved_16_18:3;
794 uint64_t pause_drp:1;
795 uint64_t reserved_20_63:44;
796#endif
797 } cn52xx;
798};
799
800union cvmx_agl_gmx_rxx_jabber {
801 uint64_t u64;
802 struct cvmx_agl_gmx_rxx_jabber_s {
803#ifdef __BIG_ENDIAN_BITFIELD
804 uint64_t reserved_16_63:48;
805 uint64_t cnt:16;
806#else
807 uint64_t cnt:16;
808 uint64_t reserved_16_63:48;
809#endif
810 } s;
811};
812
813union cvmx_agl_gmx_rxx_pause_drop_time {
814 uint64_t u64;
815 struct cvmx_agl_gmx_rxx_pause_drop_time_s {
816#ifdef __BIG_ENDIAN_BITFIELD
817 uint64_t reserved_16_63:48;
818 uint64_t status:16;
819#else
820 uint64_t status:16;
821 uint64_t reserved_16_63:48;
822#endif
823 } s;
824};
825
826union cvmx_agl_gmx_rxx_rx_inbnd {
827 uint64_t u64;
828 struct cvmx_agl_gmx_rxx_rx_inbnd_s {
829#ifdef __BIG_ENDIAN_BITFIELD
830 uint64_t reserved_4_63:60;
831 uint64_t duplex:1;
832 uint64_t speed:2;
833 uint64_t status:1;
834#else
835 uint64_t status:1;
836 uint64_t speed:2;
837 uint64_t duplex:1;
838 uint64_t reserved_4_63:60;
839#endif
840 } s;
841};
842
843union cvmx_agl_gmx_rxx_stats_ctl {
844 uint64_t u64;
845 struct cvmx_agl_gmx_rxx_stats_ctl_s {
846#ifdef __BIG_ENDIAN_BITFIELD
847 uint64_t reserved_1_63:63;
848 uint64_t rd_clr:1;
849#else
850 uint64_t rd_clr:1;
851 uint64_t reserved_1_63:63;
852#endif
853 } s;
854};
855
856union cvmx_agl_gmx_rxx_stats_octs {
857 uint64_t u64;
858 struct cvmx_agl_gmx_rxx_stats_octs_s {
859#ifdef __BIG_ENDIAN_BITFIELD
860 uint64_t reserved_48_63:16;
861 uint64_t cnt:48;
862#else
863 uint64_t cnt:48;
864 uint64_t reserved_48_63:16;
865#endif
866 } s;
867};
868
869union cvmx_agl_gmx_rxx_stats_octs_ctl {
870 uint64_t u64;
871 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s {
872#ifdef __BIG_ENDIAN_BITFIELD
873 uint64_t reserved_48_63:16;
874 uint64_t cnt:48;
875#else
876 uint64_t cnt:48;
877 uint64_t reserved_48_63:16;
878#endif
879 } s;
880};
881
882union cvmx_agl_gmx_rxx_stats_octs_dmac {
883 uint64_t u64;
884 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s {
885#ifdef __BIG_ENDIAN_BITFIELD
886 uint64_t reserved_48_63:16;
887 uint64_t cnt:48;
888#else
889 uint64_t cnt:48;
890 uint64_t reserved_48_63:16;
891#endif
892 } s;
893};
894
895union cvmx_agl_gmx_rxx_stats_octs_drp {
896 uint64_t u64;
897 struct cvmx_agl_gmx_rxx_stats_octs_drp_s {
898#ifdef __BIG_ENDIAN_BITFIELD
899 uint64_t reserved_48_63:16;
900 uint64_t cnt:48;
901#else
902 uint64_t cnt:48;
903 uint64_t reserved_48_63:16;
904#endif
905 } s;
906};
907
908union cvmx_agl_gmx_rxx_stats_pkts {
909 uint64_t u64;
910 struct cvmx_agl_gmx_rxx_stats_pkts_s {
911#ifdef __BIG_ENDIAN_BITFIELD
912 uint64_t reserved_32_63:32;
913 uint64_t cnt:32;
914#else
915 uint64_t cnt:32;
916 uint64_t reserved_32_63:32;
917#endif
918 } s;
919};
920
921union cvmx_agl_gmx_rxx_stats_pkts_bad {
922 uint64_t u64;
923 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s {
924#ifdef __BIG_ENDIAN_BITFIELD
925 uint64_t reserved_32_63:32;
926 uint64_t cnt:32;
927#else
928 uint64_t cnt:32;
929 uint64_t reserved_32_63:32;
930#endif
931 } s;
932};
933
934union cvmx_agl_gmx_rxx_stats_pkts_ctl {
935 uint64_t u64;
936 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s {
937#ifdef __BIG_ENDIAN_BITFIELD
938 uint64_t reserved_32_63:32;
939 uint64_t cnt:32;
940#else
941 uint64_t cnt:32;
942 uint64_t reserved_32_63:32;
943#endif
944 } s;
945};
946
947union cvmx_agl_gmx_rxx_stats_pkts_dmac {
948 uint64_t u64;
949 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s {
950#ifdef __BIG_ENDIAN_BITFIELD
951 uint64_t reserved_32_63:32;
952 uint64_t cnt:32;
953#else
954 uint64_t cnt:32;
955 uint64_t reserved_32_63:32;
956#endif
957 } s;
958};
959
960union cvmx_agl_gmx_rxx_stats_pkts_drp {
961 uint64_t u64;
962 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s {
963#ifdef __BIG_ENDIAN_BITFIELD
964 uint64_t reserved_32_63:32;
965 uint64_t cnt:32;
966#else
967 uint64_t cnt:32;
968 uint64_t reserved_32_63:32;
969#endif
970 } s;
971};
972
973union cvmx_agl_gmx_rxx_udd_skp {
974 uint64_t u64;
975 struct cvmx_agl_gmx_rxx_udd_skp_s {
976#ifdef __BIG_ENDIAN_BITFIELD
977 uint64_t reserved_9_63:55;
978 uint64_t fcssel:1;
979 uint64_t reserved_7_7:1;
980 uint64_t len:7;
981#else
982 uint64_t len:7;
983 uint64_t reserved_7_7:1;
984 uint64_t fcssel:1;
985 uint64_t reserved_9_63:55;
986#endif
987 } s;
988};
989
990union cvmx_agl_gmx_rx_bp_dropx {
991 uint64_t u64;
992 struct cvmx_agl_gmx_rx_bp_dropx_s {
993#ifdef __BIG_ENDIAN_BITFIELD
994 uint64_t reserved_6_63:58;
995 uint64_t mark:6;
996#else
997 uint64_t mark:6;
998 uint64_t reserved_6_63:58;
999#endif
1000 } s;
1001};
1002
1003union cvmx_agl_gmx_rx_bp_offx {
1004 uint64_t u64;
1005 struct cvmx_agl_gmx_rx_bp_offx_s {
1006#ifdef __BIG_ENDIAN_BITFIELD
1007 uint64_t reserved_6_63:58;
1008 uint64_t mark:6;
1009#else
1010 uint64_t mark:6;
1011 uint64_t reserved_6_63:58;
1012#endif
1013 } s;
1014};
1015
1016union cvmx_agl_gmx_rx_bp_onx {
1017 uint64_t u64;
1018 struct cvmx_agl_gmx_rx_bp_onx_s {
1019#ifdef __BIG_ENDIAN_BITFIELD
1020 uint64_t reserved_9_63:55;
1021 uint64_t mark:9;
1022#else
1023 uint64_t mark:9;
1024 uint64_t reserved_9_63:55;
1025#endif
1026 } s;
1027};
1028
1029union cvmx_agl_gmx_rx_prt_info {
1030 uint64_t u64;
1031 struct cvmx_agl_gmx_rx_prt_info_s {
1032#ifdef __BIG_ENDIAN_BITFIELD
1033 uint64_t reserved_18_63:46;
1034 uint64_t drop:2;
1035 uint64_t reserved_2_15:14;
1036 uint64_t commit:2;
1037#else
1038 uint64_t commit:2;
1039 uint64_t reserved_2_15:14;
1040 uint64_t drop:2;
1041 uint64_t reserved_18_63:46;
1042#endif
1043 } s;
1044 struct cvmx_agl_gmx_rx_prt_info_cn56xx {
1045#ifdef __BIG_ENDIAN_BITFIELD
1046 uint64_t reserved_17_63:47;
1047 uint64_t drop:1;
1048 uint64_t reserved_1_15:15;
1049 uint64_t commit:1;
1050#else
1051 uint64_t commit:1;
1052 uint64_t reserved_1_15:15;
1053 uint64_t drop:1;
1054 uint64_t reserved_17_63:47;
1055#endif
1056 } cn56xx;
1057};
1058
1059union cvmx_agl_gmx_rx_tx_status {
1060 uint64_t u64;
1061 struct cvmx_agl_gmx_rx_tx_status_s {
1062#ifdef __BIG_ENDIAN_BITFIELD
1063 uint64_t reserved_6_63:58;
1064 uint64_t tx:2;
1065 uint64_t reserved_2_3:2;
1066 uint64_t rx:2;
1067#else
1068 uint64_t rx:2;
1069 uint64_t reserved_2_3:2;
1070 uint64_t tx:2;
1071 uint64_t reserved_6_63:58;
1072#endif
1073 } s;
1074 struct cvmx_agl_gmx_rx_tx_status_cn56xx {
1075#ifdef __BIG_ENDIAN_BITFIELD
1076 uint64_t reserved_5_63:59;
1077 uint64_t tx:1;
1078 uint64_t reserved_1_3:3;
1079 uint64_t rx:1;
1080#else
1081 uint64_t rx:1;
1082 uint64_t reserved_1_3:3;
1083 uint64_t tx:1;
1084 uint64_t reserved_5_63:59;
1085#endif
1086 } cn56xx;
1087};
1088
1089union cvmx_agl_gmx_smacx {
1090 uint64_t u64;
1091 struct cvmx_agl_gmx_smacx_s {
1092#ifdef __BIG_ENDIAN_BITFIELD
1093 uint64_t reserved_48_63:16;
1094 uint64_t smac:48;
1095#else
1096 uint64_t smac:48;
1097 uint64_t reserved_48_63:16;
1098#endif
1099 } s;
1100};
1101
1102union cvmx_agl_gmx_stat_bp {
1103 uint64_t u64;
1104 struct cvmx_agl_gmx_stat_bp_s {
1105#ifdef __BIG_ENDIAN_BITFIELD
1106 uint64_t reserved_17_63:47;
1107 uint64_t bp:1;
1108 uint64_t cnt:16;
1109#else
1110 uint64_t cnt:16;
1111 uint64_t bp:1;
1112 uint64_t reserved_17_63:47;
1113#endif
1114 } s;
1115};
1116
1117union cvmx_agl_gmx_txx_append {
1118 uint64_t u64;
1119 struct cvmx_agl_gmx_txx_append_s {
1120#ifdef __BIG_ENDIAN_BITFIELD
1121 uint64_t reserved_4_63:60;
1122 uint64_t force_fcs:1;
1123 uint64_t fcs:1;
1124 uint64_t pad:1;
1125 uint64_t preamble:1;
1126#else
1127 uint64_t preamble:1;
1128 uint64_t pad:1;
1129 uint64_t fcs:1;
1130 uint64_t force_fcs:1;
1131 uint64_t reserved_4_63:60;
1132#endif
1133 } s;
1134};
1135
1136union cvmx_agl_gmx_txx_clk {
1137 uint64_t u64;
1138 struct cvmx_agl_gmx_txx_clk_s {
1139#ifdef __BIG_ENDIAN_BITFIELD
1140 uint64_t reserved_6_63:58;
1141 uint64_t clk_cnt:6;
1142#else
1143 uint64_t clk_cnt:6;
1144 uint64_t reserved_6_63:58;
1145#endif
1146 } s;
1147};
1148
1149union cvmx_agl_gmx_txx_ctl {
1150 uint64_t u64;
1151 struct cvmx_agl_gmx_txx_ctl_s {
1152#ifdef __BIG_ENDIAN_BITFIELD
1153 uint64_t reserved_2_63:62;
1154 uint64_t xsdef_en:1;
1155 uint64_t xscol_en:1;
1156#else
1157 uint64_t xscol_en:1;
1158 uint64_t xsdef_en:1;
1159 uint64_t reserved_2_63:62;
1160#endif
1161 } s;
1162};
1163
1164union cvmx_agl_gmx_txx_min_pkt {
1165 uint64_t u64;
1166 struct cvmx_agl_gmx_txx_min_pkt_s {
1167#ifdef __BIG_ENDIAN_BITFIELD
1168 uint64_t reserved_8_63:56;
1169 uint64_t min_size:8;
1170#else
1171 uint64_t min_size:8;
1172 uint64_t reserved_8_63:56;
1173#endif
1174 } s;
1175};
1176
1177union cvmx_agl_gmx_txx_pause_pkt_interval {
1178 uint64_t u64;
1179 struct cvmx_agl_gmx_txx_pause_pkt_interval_s {
1180#ifdef __BIG_ENDIAN_BITFIELD
1181 uint64_t reserved_16_63:48;
1182 uint64_t interval:16;
1183#else
1184 uint64_t interval:16;
1185 uint64_t reserved_16_63:48;
1186#endif
1187 } s;
1188};
1189
1190union cvmx_agl_gmx_txx_pause_pkt_time {
1191 uint64_t u64;
1192 struct cvmx_agl_gmx_txx_pause_pkt_time_s {
1193#ifdef __BIG_ENDIAN_BITFIELD
1194 uint64_t reserved_16_63:48;
1195 uint64_t time:16;
1196#else
1197 uint64_t time:16;
1198 uint64_t reserved_16_63:48;
1199#endif
1200 } s;
1201};
1202
1203union cvmx_agl_gmx_txx_pause_togo {
1204 uint64_t u64;
1205 struct cvmx_agl_gmx_txx_pause_togo_s {
1206#ifdef __BIG_ENDIAN_BITFIELD
1207 uint64_t reserved_16_63:48;
1208 uint64_t time:16;
1209#else
1210 uint64_t time:16;
1211 uint64_t reserved_16_63:48;
1212#endif
1213 } s;
1214};
1215
1216union cvmx_agl_gmx_txx_pause_zero {
1217 uint64_t u64;
1218 struct cvmx_agl_gmx_txx_pause_zero_s {
1219#ifdef __BIG_ENDIAN_BITFIELD
1220 uint64_t reserved_1_63:63;
1221 uint64_t send:1;
1222#else
1223 uint64_t send:1;
1224 uint64_t reserved_1_63:63;
1225#endif
1226 } s;
1227};
1228
1229union cvmx_agl_gmx_txx_soft_pause {
1230 uint64_t u64;
1231 struct cvmx_agl_gmx_txx_soft_pause_s {
1232#ifdef __BIG_ENDIAN_BITFIELD
1233 uint64_t reserved_16_63:48;
1234 uint64_t time:16;
1235#else
1236 uint64_t time:16;
1237 uint64_t reserved_16_63:48;
1238#endif
1239 } s;
1240};
1241
1242union cvmx_agl_gmx_txx_stat0 {
1243 uint64_t u64;
1244 struct cvmx_agl_gmx_txx_stat0_s {
1245#ifdef __BIG_ENDIAN_BITFIELD
1246 uint64_t xsdef:32;
1247 uint64_t xscol:32;
1248#else
1249 uint64_t xscol:32;
1250 uint64_t xsdef:32;
1251#endif
1252 } s;
1253};
1254
1255union cvmx_agl_gmx_txx_stat1 {
1256 uint64_t u64;
1257 struct cvmx_agl_gmx_txx_stat1_s {
1258#ifdef __BIG_ENDIAN_BITFIELD
1259 uint64_t scol:32;
1260 uint64_t mcol:32;
1261#else
1262 uint64_t mcol:32;
1263 uint64_t scol:32;
1264#endif
1265 } s;
1266};
1267
1268union cvmx_agl_gmx_txx_stat2 {
1269 uint64_t u64;
1270 struct cvmx_agl_gmx_txx_stat2_s {
1271#ifdef __BIG_ENDIAN_BITFIELD
1272 uint64_t reserved_48_63:16;
1273 uint64_t octs:48;
1274#else
1275 uint64_t octs:48;
1276 uint64_t reserved_48_63:16;
1277#endif
1278 } s;
1279};
1280
1281union cvmx_agl_gmx_txx_stat3 {
1282 uint64_t u64;
1283 struct cvmx_agl_gmx_txx_stat3_s {
1284#ifdef __BIG_ENDIAN_BITFIELD
1285 uint64_t reserved_32_63:32;
1286 uint64_t pkts:32;
1287#else
1288 uint64_t pkts:32;
1289 uint64_t reserved_32_63:32;
1290#endif
1291 } s;
1292};
1293
1294union cvmx_agl_gmx_txx_stat4 {
1295 uint64_t u64;
1296 struct cvmx_agl_gmx_txx_stat4_s {
1297#ifdef __BIG_ENDIAN_BITFIELD
1298 uint64_t hist1:32;
1299 uint64_t hist0:32;
1300#else
1301 uint64_t hist0:32;
1302 uint64_t hist1:32;
1303#endif
1304 } s;
1305};
1306
1307union cvmx_agl_gmx_txx_stat5 {
1308 uint64_t u64;
1309 struct cvmx_agl_gmx_txx_stat5_s {
1310#ifdef __BIG_ENDIAN_BITFIELD
1311 uint64_t hist3:32;
1312 uint64_t hist2:32;
1313#else
1314 uint64_t hist2:32;
1315 uint64_t hist3:32;
1316#endif
1317 } s;
1318};
1319
1320union cvmx_agl_gmx_txx_stat6 {
1321 uint64_t u64;
1322 struct cvmx_agl_gmx_txx_stat6_s {
1323#ifdef __BIG_ENDIAN_BITFIELD
1324 uint64_t hist5:32;
1325 uint64_t hist4:32;
1326#else
1327 uint64_t hist4:32;
1328 uint64_t hist5:32;
1329#endif
1330 } s;
1331};
1332
1333union cvmx_agl_gmx_txx_stat7 {
1334 uint64_t u64;
1335 struct cvmx_agl_gmx_txx_stat7_s {
1336#ifdef __BIG_ENDIAN_BITFIELD
1337 uint64_t hist7:32;
1338 uint64_t hist6:32;
1339#else
1340 uint64_t hist6:32;
1341 uint64_t hist7:32;
1342#endif
1343 } s;
1344};
1345
1346union cvmx_agl_gmx_txx_stat8 {
1347 uint64_t u64;
1348 struct cvmx_agl_gmx_txx_stat8_s {
1349#ifdef __BIG_ENDIAN_BITFIELD
1350 uint64_t mcst:32;
1351 uint64_t bcst:32;
1352#else
1353 uint64_t bcst:32;
1354 uint64_t mcst:32;
1355#endif
1356 } s;
1357};
1358
1359union cvmx_agl_gmx_txx_stat9 {
1360 uint64_t u64;
1361 struct cvmx_agl_gmx_txx_stat9_s {
1362#ifdef __BIG_ENDIAN_BITFIELD
1363 uint64_t undflw:32;
1364 uint64_t ctl:32;
1365#else
1366 uint64_t ctl:32;
1367 uint64_t undflw:32;
1368#endif
1369 } s;
1370};
1371
1372union cvmx_agl_gmx_txx_stats_ctl {
1373 uint64_t u64;
1374 struct cvmx_agl_gmx_txx_stats_ctl_s {
1375#ifdef __BIG_ENDIAN_BITFIELD
1376 uint64_t reserved_1_63:63;
1377 uint64_t rd_clr:1;
1378#else
1379 uint64_t rd_clr:1;
1380 uint64_t reserved_1_63:63;
1381#endif
1382 } s;
1383};
1384
1385union cvmx_agl_gmx_txx_thresh {
1386 uint64_t u64;
1387 struct cvmx_agl_gmx_txx_thresh_s {
1388#ifdef __BIG_ENDIAN_BITFIELD
1389 uint64_t reserved_6_63:58;
1390 uint64_t cnt:6;
1391#else
1392 uint64_t cnt:6;
1393 uint64_t reserved_6_63:58;
1394#endif
1395 } s;
1396};
1397
1398union cvmx_agl_gmx_tx_bp {
1399 uint64_t u64;
1400 struct cvmx_agl_gmx_tx_bp_s {
1401#ifdef __BIG_ENDIAN_BITFIELD
1402 uint64_t reserved_2_63:62;
1403 uint64_t bp:2;
1404#else
1405 uint64_t bp:2;
1406 uint64_t reserved_2_63:62;
1407#endif
1408 } s;
1409 struct cvmx_agl_gmx_tx_bp_cn56xx {
1410#ifdef __BIG_ENDIAN_BITFIELD
1411 uint64_t reserved_1_63:63;
1412 uint64_t bp:1;
1413#else
1414 uint64_t bp:1;
1415 uint64_t reserved_1_63:63;
1416#endif
1417 } cn56xx;
1418};
1419
1420union cvmx_agl_gmx_tx_col_attempt {
1421 uint64_t u64;
1422 struct cvmx_agl_gmx_tx_col_attempt_s {
1423#ifdef __BIG_ENDIAN_BITFIELD
1424 uint64_t reserved_5_63:59;
1425 uint64_t limit:5;
1426#else
1427 uint64_t limit:5;
1428 uint64_t reserved_5_63:59;
1429#endif
1430 } s;
1431};
1432
1433union cvmx_agl_gmx_tx_ifg {
1434 uint64_t u64;
1435 struct cvmx_agl_gmx_tx_ifg_s {
1436#ifdef __BIG_ENDIAN_BITFIELD
1437 uint64_t reserved_8_63:56;
1438 uint64_t ifg2:4;
1439 uint64_t ifg1:4;
1440#else
1441 uint64_t ifg1:4;
1442 uint64_t ifg2:4;
1443 uint64_t reserved_8_63:56;
1444#endif
1445 } s;
1446};
1447
1448union cvmx_agl_gmx_tx_int_en {
1449 uint64_t u64;
1450 struct cvmx_agl_gmx_tx_int_en_s {
1451#ifdef __BIG_ENDIAN_BITFIELD
1452 uint64_t reserved_22_63:42;
1453 uint64_t ptp_lost:2;
1454 uint64_t reserved_18_19:2;
1455 uint64_t late_col:2;
1456 uint64_t reserved_14_15:2;
1457 uint64_t xsdef:2;
1458 uint64_t reserved_10_11:2;
1459 uint64_t xscol:2;
1460 uint64_t reserved_4_7:4;
1461 uint64_t undflw:2;
1462 uint64_t reserved_1_1:1;
1463 uint64_t pko_nxa:1;
1464#else
1465 uint64_t pko_nxa:1;
1466 uint64_t reserved_1_1:1;
1467 uint64_t undflw:2;
1468 uint64_t reserved_4_7:4;
1469 uint64_t xscol:2;
1470 uint64_t reserved_10_11:2;
1471 uint64_t xsdef:2;
1472 uint64_t reserved_14_15:2;
1473 uint64_t late_col:2;
1474 uint64_t reserved_18_19:2;
1475 uint64_t ptp_lost:2;
1476 uint64_t reserved_22_63:42;
1477#endif
1478 } s;
1479 struct cvmx_agl_gmx_tx_int_en_cn52xx {
1480#ifdef __BIG_ENDIAN_BITFIELD
1481 uint64_t reserved_18_63:46;
1482 uint64_t late_col:2;
1483 uint64_t reserved_14_15:2;
1484 uint64_t xsdef:2;
1485 uint64_t reserved_10_11:2;
1486 uint64_t xscol:2;
1487 uint64_t reserved_4_7:4;
1488 uint64_t undflw:2;
1489 uint64_t reserved_1_1:1;
1490 uint64_t pko_nxa:1;
1491#else
1492 uint64_t pko_nxa:1;
1493 uint64_t reserved_1_1:1;
1494 uint64_t undflw:2;
1495 uint64_t reserved_4_7:4;
1496 uint64_t xscol:2;
1497 uint64_t reserved_10_11:2;
1498 uint64_t xsdef:2;
1499 uint64_t reserved_14_15:2;
1500 uint64_t late_col:2;
1501 uint64_t reserved_18_63:46;
1502#endif
1503 } cn52xx;
1504 struct cvmx_agl_gmx_tx_int_en_cn56xx {
1505#ifdef __BIG_ENDIAN_BITFIELD
1506 uint64_t reserved_17_63:47;
1507 uint64_t late_col:1;
1508 uint64_t reserved_13_15:3;
1509 uint64_t xsdef:1;
1510 uint64_t reserved_9_11:3;
1511 uint64_t xscol:1;
1512 uint64_t reserved_3_7:5;
1513 uint64_t undflw:1;
1514 uint64_t reserved_1_1:1;
1515 uint64_t pko_nxa:1;
1516#else
1517 uint64_t pko_nxa:1;
1518 uint64_t reserved_1_1:1;
1519 uint64_t undflw:1;
1520 uint64_t reserved_3_7:5;
1521 uint64_t xscol:1;
1522 uint64_t reserved_9_11:3;
1523 uint64_t xsdef:1;
1524 uint64_t reserved_13_15:3;
1525 uint64_t late_col:1;
1526 uint64_t reserved_17_63:47;
1527#endif
1528 } cn56xx;
1529};
1530
1531union cvmx_agl_gmx_tx_int_reg {
1532 uint64_t u64;
1533 struct cvmx_agl_gmx_tx_int_reg_s {
1534#ifdef __BIG_ENDIAN_BITFIELD
1535 uint64_t reserved_22_63:42;
1536 uint64_t ptp_lost:2;
1537 uint64_t reserved_18_19:2;
1538 uint64_t late_col:2;
1539 uint64_t reserved_14_15:2;
1540 uint64_t xsdef:2;
1541 uint64_t reserved_10_11:2;
1542 uint64_t xscol:2;
1543 uint64_t reserved_4_7:4;
1544 uint64_t undflw:2;
1545 uint64_t reserved_1_1:1;
1546 uint64_t pko_nxa:1;
1547#else
1548 uint64_t pko_nxa:1;
1549 uint64_t reserved_1_1:1;
1550 uint64_t undflw:2;
1551 uint64_t reserved_4_7:4;
1552 uint64_t xscol:2;
1553 uint64_t reserved_10_11:2;
1554 uint64_t xsdef:2;
1555 uint64_t reserved_14_15:2;
1556 uint64_t late_col:2;
1557 uint64_t reserved_18_19:2;
1558 uint64_t ptp_lost:2;
1559 uint64_t reserved_22_63:42;
1560#endif
1561 } s;
1562 struct cvmx_agl_gmx_tx_int_reg_cn52xx {
1563#ifdef __BIG_ENDIAN_BITFIELD
1564 uint64_t reserved_18_63:46;
1565 uint64_t late_col:2;
1566 uint64_t reserved_14_15:2;
1567 uint64_t xsdef:2;
1568 uint64_t reserved_10_11:2;
1569 uint64_t xscol:2;
1570 uint64_t reserved_4_7:4;
1571 uint64_t undflw:2;
1572 uint64_t reserved_1_1:1;
1573 uint64_t pko_nxa:1;
1574#else
1575 uint64_t pko_nxa:1;
1576 uint64_t reserved_1_1:1;
1577 uint64_t undflw:2;
1578 uint64_t reserved_4_7:4;
1579 uint64_t xscol:2;
1580 uint64_t reserved_10_11:2;
1581 uint64_t xsdef:2;
1582 uint64_t reserved_14_15:2;
1583 uint64_t late_col:2;
1584 uint64_t reserved_18_63:46;
1585#endif
1586 } cn52xx;
1587 struct cvmx_agl_gmx_tx_int_reg_cn56xx {
1588#ifdef __BIG_ENDIAN_BITFIELD
1589 uint64_t reserved_17_63:47;
1590 uint64_t late_col:1;
1591 uint64_t reserved_13_15:3;
1592 uint64_t xsdef:1;
1593 uint64_t reserved_9_11:3;
1594 uint64_t xscol:1;
1595 uint64_t reserved_3_7:5;
1596 uint64_t undflw:1;
1597 uint64_t reserved_1_1:1;
1598 uint64_t pko_nxa:1;
1599#else
1600 uint64_t pko_nxa:1;
1601 uint64_t reserved_1_1:1;
1602 uint64_t undflw:1;
1603 uint64_t reserved_3_7:5;
1604 uint64_t xscol:1;
1605 uint64_t reserved_9_11:3;
1606 uint64_t xsdef:1;
1607 uint64_t reserved_13_15:3;
1608 uint64_t late_col:1;
1609 uint64_t reserved_17_63:47;
1610#endif
1611 } cn56xx;
1612};
1613
1614union cvmx_agl_gmx_tx_jam {
1615 uint64_t u64;
1616 struct cvmx_agl_gmx_tx_jam_s {
1617#ifdef __BIG_ENDIAN_BITFIELD
1618 uint64_t reserved_8_63:56;
1619 uint64_t jam:8;
1620#else
1621 uint64_t jam:8;
1622 uint64_t reserved_8_63:56;
1623#endif
1624 } s;
1625};
1626
1627union cvmx_agl_gmx_tx_lfsr {
1628 uint64_t u64;
1629 struct cvmx_agl_gmx_tx_lfsr_s {
1630#ifdef __BIG_ENDIAN_BITFIELD
1631 uint64_t reserved_16_63:48;
1632 uint64_t lfsr:16;
1633#else
1634 uint64_t lfsr:16;
1635 uint64_t reserved_16_63:48;
1636#endif
1637 } s;
1638};
1639
1640union cvmx_agl_gmx_tx_ovr_bp {
1641 uint64_t u64;
1642 struct cvmx_agl_gmx_tx_ovr_bp_s {
1643#ifdef __BIG_ENDIAN_BITFIELD
1644 uint64_t reserved_10_63:54;
1645 uint64_t en:2;
1646 uint64_t reserved_6_7:2;
1647 uint64_t bp:2;
1648 uint64_t reserved_2_3:2;
1649 uint64_t ign_full:2;
1650#else
1651 uint64_t ign_full:2;
1652 uint64_t reserved_2_3:2;
1653 uint64_t bp:2;
1654 uint64_t reserved_6_7:2;
1655 uint64_t en:2;
1656 uint64_t reserved_10_63:54;
1657#endif
1658 } s;
1659 struct cvmx_agl_gmx_tx_ovr_bp_cn56xx {
1660#ifdef __BIG_ENDIAN_BITFIELD
1661 uint64_t reserved_9_63:55;
1662 uint64_t en:1;
1663 uint64_t reserved_5_7:3;
1664 uint64_t bp:1;
1665 uint64_t reserved_1_3:3;
1666 uint64_t ign_full:1;
1667#else
1668 uint64_t ign_full:1;
1669 uint64_t reserved_1_3:3;
1670 uint64_t bp:1;
1671 uint64_t reserved_5_7:3;
1672 uint64_t en:1;
1673 uint64_t reserved_9_63:55;
1674#endif
1675 } cn56xx;
1676};
1677
1678union cvmx_agl_gmx_tx_pause_pkt_dmac {
1679 uint64_t u64;
1680 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s {
1681#ifdef __BIG_ENDIAN_BITFIELD
1682 uint64_t reserved_48_63:16;
1683 uint64_t dmac:48;
1684#else
1685 uint64_t dmac:48;
1686 uint64_t reserved_48_63:16;
1687#endif
1688 } s;
1689};
1690
1691union cvmx_agl_gmx_tx_pause_pkt_type {
1692 uint64_t u64;
1693 struct cvmx_agl_gmx_tx_pause_pkt_type_s {
1694#ifdef __BIG_ENDIAN_BITFIELD
1695 uint64_t reserved_16_63:48;
1696 uint64_t type:16;
1697#else
1698 uint64_t type:16;
1699 uint64_t reserved_16_63:48;
1700#endif
1701 } s;
1702};
1703
1704union cvmx_agl_prtx_ctl {
1705 uint64_t u64;
1706 struct cvmx_agl_prtx_ctl_s {
1707#ifdef __BIG_ENDIAN_BITFIELD
1708 uint64_t drv_byp:1;
1709 uint64_t reserved_62_62:1;
1710 uint64_t cmp_pctl:6;
1711 uint64_t reserved_54_55:2;
1712 uint64_t cmp_nctl:6;
1713 uint64_t reserved_46_47:2;
1714 uint64_t drv_pctl:6;
1715 uint64_t reserved_38_39:2;
1716 uint64_t drv_nctl:6;
1717 uint64_t reserved_29_31:3;
1718 uint64_t clk_set:5;
1719 uint64_t clkrx_byp:1;
1720 uint64_t reserved_21_22:2;
1721 uint64_t clkrx_set:5;
1722 uint64_t clktx_byp:1;
1723 uint64_t reserved_13_14:2;
1724 uint64_t clktx_set:5;
1725 uint64_t reserved_5_7:3;
1726 uint64_t dllrst:1;
1727 uint64_t comp:1;
1728 uint64_t enable:1;
1729 uint64_t clkrst:1;
1730 uint64_t mode:1;
1731#else
1732 uint64_t mode:1;
1733 uint64_t clkrst:1;
1734 uint64_t enable:1;
1735 uint64_t comp:1;
1736 uint64_t dllrst:1;
1737 uint64_t reserved_5_7:3;
1738 uint64_t clktx_set:5;
1739 uint64_t reserved_13_14:2;
1740 uint64_t clktx_byp:1;
1741 uint64_t clkrx_set:5;
1742 uint64_t reserved_21_22:2;
1743 uint64_t clkrx_byp:1;
1744 uint64_t clk_set:5;
1745 uint64_t reserved_29_31:3;
1746 uint64_t drv_nctl:6;
1747 uint64_t reserved_38_39:2;
1748 uint64_t drv_pctl:6;
1749 uint64_t reserved_46_47:2;
1750 uint64_t cmp_nctl:6;
1751 uint64_t reserved_54_55:2;
1752 uint64_t cmp_pctl:6;
1753 uint64_t reserved_62_62:1;
1754 uint64_t drv_byp:1;
1755#endif
1756 } s;
1757};
1758
1759#endif
1/***********************license start***************
2 * Author: Cavium Networks
3 *
4 * Contact: support@caviumnetworks.com
5 * This file is part of the OCTEON SDK
6 *
7 * Copyright (c) 2003-2012 Cavium Networks
8 *
9 * This file is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License, Version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful, but
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
16 * NONINFRINGEMENT. See the GNU General Public License for more
17 * details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this file; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 * or visit http://www.gnu.org/licenses/.
23 *
24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information
26 ***********************license end**************************************/
27
28#ifndef __CVMX_AGL_DEFS_H__
29#define __CVMX_AGL_DEFS_H__
30
31#define CVMX_AGL_GMX_BAD_REG (CVMX_ADD_IO_SEG(0x00011800E0000518ull))
32#define CVMX_AGL_GMX_BIST (CVMX_ADD_IO_SEG(0x00011800E0000400ull))
33#define CVMX_AGL_GMX_DRV_CTL (CVMX_ADD_IO_SEG(0x00011800E00007F0ull))
34#define CVMX_AGL_GMX_INF_MODE (CVMX_ADD_IO_SEG(0x00011800E00007F8ull))
35#define CVMX_AGL_GMX_PRTX_CFG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000010ull) + ((offset) & 1) * 2048)
36#define CVMX_AGL_GMX_RXX_ADR_CAM0(offset) (CVMX_ADD_IO_SEG(0x00011800E0000180ull) + ((offset) & 1) * 2048)
37#define CVMX_AGL_GMX_RXX_ADR_CAM1(offset) (CVMX_ADD_IO_SEG(0x00011800E0000188ull) + ((offset) & 1) * 2048)
38#define CVMX_AGL_GMX_RXX_ADR_CAM2(offset) (CVMX_ADD_IO_SEG(0x00011800E0000190ull) + ((offset) & 1) * 2048)
39#define CVMX_AGL_GMX_RXX_ADR_CAM3(offset) (CVMX_ADD_IO_SEG(0x00011800E0000198ull) + ((offset) & 1) * 2048)
40#define CVMX_AGL_GMX_RXX_ADR_CAM4(offset) (CVMX_ADD_IO_SEG(0x00011800E00001A0ull) + ((offset) & 1) * 2048)
41#define CVMX_AGL_GMX_RXX_ADR_CAM5(offset) (CVMX_ADD_IO_SEG(0x00011800E00001A8ull) + ((offset) & 1) * 2048)
42#define CVMX_AGL_GMX_RXX_ADR_CAM_EN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000108ull) + ((offset) & 1) * 2048)
43#define CVMX_AGL_GMX_RXX_ADR_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000100ull) + ((offset) & 1) * 2048)
44#define CVMX_AGL_GMX_RXX_DECISION(offset) (CVMX_ADD_IO_SEG(0x00011800E0000040ull) + ((offset) & 1) * 2048)
45#define CVMX_AGL_GMX_RXX_FRM_CHK(offset) (CVMX_ADD_IO_SEG(0x00011800E0000020ull) + ((offset) & 1) * 2048)
46#define CVMX_AGL_GMX_RXX_FRM_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000018ull) + ((offset) & 1) * 2048)
47#define CVMX_AGL_GMX_RXX_FRM_MAX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000030ull) + ((offset) & 1) * 2048)
48#define CVMX_AGL_GMX_RXX_FRM_MIN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000028ull) + ((offset) & 1) * 2048)
49#define CVMX_AGL_GMX_RXX_IFG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000058ull) + ((offset) & 1) * 2048)
50#define CVMX_AGL_GMX_RXX_INT_EN(offset) (CVMX_ADD_IO_SEG(0x00011800E0000008ull) + ((offset) & 1) * 2048)
51#define CVMX_AGL_GMX_RXX_INT_REG(offset) (CVMX_ADD_IO_SEG(0x00011800E0000000ull) + ((offset) & 1) * 2048)
52#define CVMX_AGL_GMX_RXX_JABBER(offset) (CVMX_ADD_IO_SEG(0x00011800E0000038ull) + ((offset) & 1) * 2048)
53#define CVMX_AGL_GMX_RXX_PAUSE_DROP_TIME(offset) (CVMX_ADD_IO_SEG(0x00011800E0000068ull) + ((offset) & 1) * 2048)
54#define CVMX_AGL_GMX_RXX_RX_INBND(offset) (CVMX_ADD_IO_SEG(0x00011800E0000060ull) + ((offset) & 1) * 2048)
55#define CVMX_AGL_GMX_RXX_STATS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000050ull) + ((offset) & 1) * 2048)
56#define CVMX_AGL_GMX_RXX_STATS_OCTS(offset) (CVMX_ADD_IO_SEG(0x00011800E0000088ull) + ((offset) & 1) * 2048)
57#define CVMX_AGL_GMX_RXX_STATS_OCTS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000098ull) + ((offset) & 1) * 2048)
58#define CVMX_AGL_GMX_RXX_STATS_OCTS_DMAC(offset) (CVMX_ADD_IO_SEG(0x00011800E00000A8ull) + ((offset) & 1) * 2048)
59#define CVMX_AGL_GMX_RXX_STATS_OCTS_DRP(offset) (CVMX_ADD_IO_SEG(0x00011800E00000B8ull) + ((offset) & 1) * 2048)
60#define CVMX_AGL_GMX_RXX_STATS_PKTS(offset) (CVMX_ADD_IO_SEG(0x00011800E0000080ull) + ((offset) & 1) * 2048)
61#define CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(offset) (CVMX_ADD_IO_SEG(0x00011800E00000C0ull) + ((offset) & 1) * 2048)
62#define CVMX_AGL_GMX_RXX_STATS_PKTS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000090ull) + ((offset) & 1) * 2048)
63#define CVMX_AGL_GMX_RXX_STATS_PKTS_DMAC(offset) (CVMX_ADD_IO_SEG(0x00011800E00000A0ull) + ((offset) & 1) * 2048)
64#define CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(offset) (CVMX_ADD_IO_SEG(0x00011800E00000B0ull) + ((offset) & 1) * 2048)
65#define CVMX_AGL_GMX_RXX_UDD_SKP(offset) (CVMX_ADD_IO_SEG(0x00011800E0000048ull) + ((offset) & 1) * 2048)
66#define CVMX_AGL_GMX_RX_BP_DROPX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000420ull) + ((offset) & 1) * 8)
67#define CVMX_AGL_GMX_RX_BP_OFFX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000460ull) + ((offset) & 1) * 8)
68#define CVMX_AGL_GMX_RX_BP_ONX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000440ull) + ((offset) & 1) * 8)
69#define CVMX_AGL_GMX_RX_PRT_INFO (CVMX_ADD_IO_SEG(0x00011800E00004E8ull))
70#define CVMX_AGL_GMX_RX_TX_STATUS (CVMX_ADD_IO_SEG(0x00011800E00007E8ull))
71#define CVMX_AGL_GMX_SMACX(offset) (CVMX_ADD_IO_SEG(0x00011800E0000230ull) + ((offset) & 1) * 2048)
72#define CVMX_AGL_GMX_STAT_BP (CVMX_ADD_IO_SEG(0x00011800E0000520ull))
73#define CVMX_AGL_GMX_TXX_APPEND(offset) (CVMX_ADD_IO_SEG(0x00011800E0000218ull) + ((offset) & 1) * 2048)
74#define CVMX_AGL_GMX_TXX_CLK(offset) (CVMX_ADD_IO_SEG(0x00011800E0000208ull) + ((offset) & 1) * 2048)
75#define CVMX_AGL_GMX_TXX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000270ull) + ((offset) & 1) * 2048)
76#define CVMX_AGL_GMX_TXX_MIN_PKT(offset) (CVMX_ADD_IO_SEG(0x00011800E0000240ull) + ((offset) & 1) * 2048)
77#define CVMX_AGL_GMX_TXX_PAUSE_PKT_INTERVAL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000248ull) + ((offset) & 1) * 2048)
78#define CVMX_AGL_GMX_TXX_PAUSE_PKT_TIME(offset) (CVMX_ADD_IO_SEG(0x00011800E0000238ull) + ((offset) & 1) * 2048)
79#define CVMX_AGL_GMX_TXX_PAUSE_TOGO(offset) (CVMX_ADD_IO_SEG(0x00011800E0000258ull) + ((offset) & 1) * 2048)
80#define CVMX_AGL_GMX_TXX_PAUSE_ZERO(offset) (CVMX_ADD_IO_SEG(0x00011800E0000260ull) + ((offset) & 1) * 2048)
81#define CVMX_AGL_GMX_TXX_SOFT_PAUSE(offset) (CVMX_ADD_IO_SEG(0x00011800E0000250ull) + ((offset) & 1) * 2048)
82#define CVMX_AGL_GMX_TXX_STAT0(offset) (CVMX_ADD_IO_SEG(0x00011800E0000280ull) + ((offset) & 1) * 2048)
83#define CVMX_AGL_GMX_TXX_STAT1(offset) (CVMX_ADD_IO_SEG(0x00011800E0000288ull) + ((offset) & 1) * 2048)
84#define CVMX_AGL_GMX_TXX_STAT2(offset) (CVMX_ADD_IO_SEG(0x00011800E0000290ull) + ((offset) & 1) * 2048)
85#define CVMX_AGL_GMX_TXX_STAT3(offset) (CVMX_ADD_IO_SEG(0x00011800E0000298ull) + ((offset) & 1) * 2048)
86#define CVMX_AGL_GMX_TXX_STAT4(offset) (CVMX_ADD_IO_SEG(0x00011800E00002A0ull) + ((offset) & 1) * 2048)
87#define CVMX_AGL_GMX_TXX_STAT5(offset) (CVMX_ADD_IO_SEG(0x00011800E00002A8ull) + ((offset) & 1) * 2048)
88#define CVMX_AGL_GMX_TXX_STAT6(offset) (CVMX_ADD_IO_SEG(0x00011800E00002B0ull) + ((offset) & 1) * 2048)
89#define CVMX_AGL_GMX_TXX_STAT7(offset) (CVMX_ADD_IO_SEG(0x00011800E00002B8ull) + ((offset) & 1) * 2048)
90#define CVMX_AGL_GMX_TXX_STAT8(offset) (CVMX_ADD_IO_SEG(0x00011800E00002C0ull) + ((offset) & 1) * 2048)
91#define CVMX_AGL_GMX_TXX_STAT9(offset) (CVMX_ADD_IO_SEG(0x00011800E00002C8ull) + ((offset) & 1) * 2048)
92#define CVMX_AGL_GMX_TXX_STATS_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0000268ull) + ((offset) & 1) * 2048)
93#define CVMX_AGL_GMX_TXX_THRESH(offset) (CVMX_ADD_IO_SEG(0x00011800E0000210ull) + ((offset) & 1) * 2048)
94#define CVMX_AGL_GMX_TX_BP (CVMX_ADD_IO_SEG(0x00011800E00004D0ull))
95#define CVMX_AGL_GMX_TX_COL_ATTEMPT (CVMX_ADD_IO_SEG(0x00011800E0000498ull))
96#define CVMX_AGL_GMX_TX_IFG (CVMX_ADD_IO_SEG(0x00011800E0000488ull))
97#define CVMX_AGL_GMX_TX_INT_EN (CVMX_ADD_IO_SEG(0x00011800E0000508ull))
98#define CVMX_AGL_GMX_TX_INT_REG (CVMX_ADD_IO_SEG(0x00011800E0000500ull))
99#define CVMX_AGL_GMX_TX_JAM (CVMX_ADD_IO_SEG(0x00011800E0000490ull))
100#define CVMX_AGL_GMX_TX_LFSR (CVMX_ADD_IO_SEG(0x00011800E00004F8ull))
101#define CVMX_AGL_GMX_TX_OVR_BP (CVMX_ADD_IO_SEG(0x00011800E00004C8ull))
102#define CVMX_AGL_GMX_TX_PAUSE_PKT_DMAC (CVMX_ADD_IO_SEG(0x00011800E00004A0ull))
103#define CVMX_AGL_GMX_TX_PAUSE_PKT_TYPE (CVMX_ADD_IO_SEG(0x00011800E00004A8ull))
104#define CVMX_AGL_PRTX_CTL(offset) (CVMX_ADD_IO_SEG(0x00011800E0002000ull) + ((offset) & 1) * 8)
105
106union cvmx_agl_gmx_bad_reg {
107 uint64_t u64;
108 struct cvmx_agl_gmx_bad_reg_s {
109#ifdef __BIG_ENDIAN_BITFIELD
110 uint64_t reserved_38_63:26;
111 uint64_t txpsh1:1;
112 uint64_t txpop1:1;
113 uint64_t ovrflw1:1;
114 uint64_t txpsh:1;
115 uint64_t txpop:1;
116 uint64_t ovrflw:1;
117 uint64_t reserved_27_31:5;
118 uint64_t statovr:1;
119 uint64_t reserved_24_25:2;
120 uint64_t loststat:2;
121 uint64_t reserved_4_21:18;
122 uint64_t out_ovr:2;
123 uint64_t reserved_0_1:2;
124#else
125 uint64_t reserved_0_1:2;
126 uint64_t out_ovr:2;
127 uint64_t reserved_4_21:18;
128 uint64_t loststat:2;
129 uint64_t reserved_24_25:2;
130 uint64_t statovr:1;
131 uint64_t reserved_27_31:5;
132 uint64_t ovrflw:1;
133 uint64_t txpop:1;
134 uint64_t txpsh:1;
135 uint64_t ovrflw1:1;
136 uint64_t txpop1:1;
137 uint64_t txpsh1:1;
138 uint64_t reserved_38_63:26;
139#endif
140 } s;
141 struct cvmx_agl_gmx_bad_reg_cn52xx {
142#ifdef __BIG_ENDIAN_BITFIELD
143 uint64_t reserved_38_63:26;
144 uint64_t txpsh1:1;
145 uint64_t txpop1:1;
146 uint64_t ovrflw1:1;
147 uint64_t txpsh:1;
148 uint64_t txpop:1;
149 uint64_t ovrflw:1;
150 uint64_t reserved_27_31:5;
151 uint64_t statovr:1;
152 uint64_t reserved_23_25:3;
153 uint64_t loststat:1;
154 uint64_t reserved_4_21:18;
155 uint64_t out_ovr:2;
156 uint64_t reserved_0_1:2;
157#else
158 uint64_t reserved_0_1:2;
159 uint64_t out_ovr:2;
160 uint64_t reserved_4_21:18;
161 uint64_t loststat:1;
162 uint64_t reserved_23_25:3;
163 uint64_t statovr:1;
164 uint64_t reserved_27_31:5;
165 uint64_t ovrflw:1;
166 uint64_t txpop:1;
167 uint64_t txpsh:1;
168 uint64_t ovrflw1:1;
169 uint64_t txpop1:1;
170 uint64_t txpsh1:1;
171 uint64_t reserved_38_63:26;
172#endif
173 } cn52xx;
174 struct cvmx_agl_gmx_bad_reg_cn52xx cn52xxp1;
175 struct cvmx_agl_gmx_bad_reg_cn56xx {
176#ifdef __BIG_ENDIAN_BITFIELD
177 uint64_t reserved_35_63:29;
178 uint64_t txpsh:1;
179 uint64_t txpop:1;
180 uint64_t ovrflw:1;
181 uint64_t reserved_27_31:5;
182 uint64_t statovr:1;
183 uint64_t reserved_23_25:3;
184 uint64_t loststat:1;
185 uint64_t reserved_3_21:19;
186 uint64_t out_ovr:1;
187 uint64_t reserved_0_1:2;
188#else
189 uint64_t reserved_0_1:2;
190 uint64_t out_ovr:1;
191 uint64_t reserved_3_21:19;
192 uint64_t loststat:1;
193 uint64_t reserved_23_25:3;
194 uint64_t statovr:1;
195 uint64_t reserved_27_31:5;
196 uint64_t ovrflw:1;
197 uint64_t txpop:1;
198 uint64_t txpsh:1;
199 uint64_t reserved_35_63:29;
200#endif
201 } cn56xx;
202 struct cvmx_agl_gmx_bad_reg_cn56xx cn56xxp1;
203 struct cvmx_agl_gmx_bad_reg_s cn61xx;
204 struct cvmx_agl_gmx_bad_reg_s cn63xx;
205 struct cvmx_agl_gmx_bad_reg_s cn63xxp1;
206 struct cvmx_agl_gmx_bad_reg_s cn66xx;
207 struct cvmx_agl_gmx_bad_reg_s cn68xx;
208 struct cvmx_agl_gmx_bad_reg_s cn68xxp1;
209};
210
211union cvmx_agl_gmx_bist {
212 uint64_t u64;
213 struct cvmx_agl_gmx_bist_s {
214#ifdef __BIG_ENDIAN_BITFIELD
215 uint64_t reserved_25_63:39;
216 uint64_t status:25;
217#else
218 uint64_t status:25;
219 uint64_t reserved_25_63:39;
220#endif
221 } s;
222 struct cvmx_agl_gmx_bist_cn52xx {
223#ifdef __BIG_ENDIAN_BITFIELD
224 uint64_t reserved_10_63:54;
225 uint64_t status:10;
226#else
227 uint64_t status:10;
228 uint64_t reserved_10_63:54;
229#endif
230 } cn52xx;
231 struct cvmx_agl_gmx_bist_cn52xx cn52xxp1;
232 struct cvmx_agl_gmx_bist_cn52xx cn56xx;
233 struct cvmx_agl_gmx_bist_cn52xx cn56xxp1;
234 struct cvmx_agl_gmx_bist_s cn61xx;
235 struct cvmx_agl_gmx_bist_s cn63xx;
236 struct cvmx_agl_gmx_bist_s cn63xxp1;
237 struct cvmx_agl_gmx_bist_s cn66xx;
238 struct cvmx_agl_gmx_bist_s cn68xx;
239 struct cvmx_agl_gmx_bist_s cn68xxp1;
240};
241
242union cvmx_agl_gmx_drv_ctl {
243 uint64_t u64;
244 struct cvmx_agl_gmx_drv_ctl_s {
245#ifdef __BIG_ENDIAN_BITFIELD
246 uint64_t reserved_49_63:15;
247 uint64_t byp_en1:1;
248 uint64_t reserved_45_47:3;
249 uint64_t pctl1:5;
250 uint64_t reserved_37_39:3;
251 uint64_t nctl1:5;
252 uint64_t reserved_17_31:15;
253 uint64_t byp_en:1;
254 uint64_t reserved_13_15:3;
255 uint64_t pctl:5;
256 uint64_t reserved_5_7:3;
257 uint64_t nctl:5;
258#else
259 uint64_t nctl:5;
260 uint64_t reserved_5_7:3;
261 uint64_t pctl:5;
262 uint64_t reserved_13_15:3;
263 uint64_t byp_en:1;
264 uint64_t reserved_17_31:15;
265 uint64_t nctl1:5;
266 uint64_t reserved_37_39:3;
267 uint64_t pctl1:5;
268 uint64_t reserved_45_47:3;
269 uint64_t byp_en1:1;
270 uint64_t reserved_49_63:15;
271#endif
272 } s;
273 struct cvmx_agl_gmx_drv_ctl_s cn52xx;
274 struct cvmx_agl_gmx_drv_ctl_s cn52xxp1;
275 struct cvmx_agl_gmx_drv_ctl_cn56xx {
276#ifdef __BIG_ENDIAN_BITFIELD
277 uint64_t reserved_17_63:47;
278 uint64_t byp_en:1;
279 uint64_t reserved_13_15:3;
280 uint64_t pctl:5;
281 uint64_t reserved_5_7:3;
282 uint64_t nctl:5;
283#else
284 uint64_t nctl:5;
285 uint64_t reserved_5_7:3;
286 uint64_t pctl:5;
287 uint64_t reserved_13_15:3;
288 uint64_t byp_en:1;
289 uint64_t reserved_17_63:47;
290#endif
291 } cn56xx;
292 struct cvmx_agl_gmx_drv_ctl_cn56xx cn56xxp1;
293};
294
295union cvmx_agl_gmx_inf_mode {
296 uint64_t u64;
297 struct cvmx_agl_gmx_inf_mode_s {
298#ifdef __BIG_ENDIAN_BITFIELD
299 uint64_t reserved_2_63:62;
300 uint64_t en:1;
301 uint64_t reserved_0_0:1;
302#else
303 uint64_t reserved_0_0:1;
304 uint64_t en:1;
305 uint64_t reserved_2_63:62;
306#endif
307 } s;
308 struct cvmx_agl_gmx_inf_mode_s cn52xx;
309 struct cvmx_agl_gmx_inf_mode_s cn52xxp1;
310 struct cvmx_agl_gmx_inf_mode_s cn56xx;
311 struct cvmx_agl_gmx_inf_mode_s cn56xxp1;
312};
313
314union cvmx_agl_gmx_prtx_cfg {
315 uint64_t u64;
316 struct cvmx_agl_gmx_prtx_cfg_s {
317#ifdef __BIG_ENDIAN_BITFIELD
318 uint64_t reserved_14_63:50;
319 uint64_t tx_idle:1;
320 uint64_t rx_idle:1;
321 uint64_t reserved_9_11:3;
322 uint64_t speed_msb:1;
323 uint64_t reserved_7_7:1;
324 uint64_t burst:1;
325 uint64_t tx_en:1;
326 uint64_t rx_en:1;
327 uint64_t slottime:1;
328 uint64_t duplex:1;
329 uint64_t speed:1;
330 uint64_t en:1;
331#else
332 uint64_t en:1;
333 uint64_t speed:1;
334 uint64_t duplex:1;
335 uint64_t slottime:1;
336 uint64_t rx_en:1;
337 uint64_t tx_en:1;
338 uint64_t burst:1;
339 uint64_t reserved_7_7:1;
340 uint64_t speed_msb:1;
341 uint64_t reserved_9_11:3;
342 uint64_t rx_idle:1;
343 uint64_t tx_idle:1;
344 uint64_t reserved_14_63:50;
345#endif
346 } s;
347 struct cvmx_agl_gmx_prtx_cfg_cn52xx {
348#ifdef __BIG_ENDIAN_BITFIELD
349 uint64_t reserved_6_63:58;
350 uint64_t tx_en:1;
351 uint64_t rx_en:1;
352 uint64_t slottime:1;
353 uint64_t duplex:1;
354 uint64_t speed:1;
355 uint64_t en:1;
356#else
357 uint64_t en:1;
358 uint64_t speed:1;
359 uint64_t duplex:1;
360 uint64_t slottime:1;
361 uint64_t rx_en:1;
362 uint64_t tx_en:1;
363 uint64_t reserved_6_63:58;
364#endif
365 } cn52xx;
366 struct cvmx_agl_gmx_prtx_cfg_cn52xx cn52xxp1;
367 struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xx;
368 struct cvmx_agl_gmx_prtx_cfg_cn52xx cn56xxp1;
369 struct cvmx_agl_gmx_prtx_cfg_s cn61xx;
370 struct cvmx_agl_gmx_prtx_cfg_s cn63xx;
371 struct cvmx_agl_gmx_prtx_cfg_s cn63xxp1;
372 struct cvmx_agl_gmx_prtx_cfg_s cn66xx;
373 struct cvmx_agl_gmx_prtx_cfg_s cn68xx;
374 struct cvmx_agl_gmx_prtx_cfg_s cn68xxp1;
375};
376
377union cvmx_agl_gmx_rxx_adr_cam0 {
378 uint64_t u64;
379 struct cvmx_agl_gmx_rxx_adr_cam0_s {
380#ifdef __BIG_ENDIAN_BITFIELD
381 uint64_t adr:64;
382#else
383 uint64_t adr:64;
384#endif
385 } s;
386 struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xx;
387 struct cvmx_agl_gmx_rxx_adr_cam0_s cn52xxp1;
388 struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xx;
389 struct cvmx_agl_gmx_rxx_adr_cam0_s cn56xxp1;
390 struct cvmx_agl_gmx_rxx_adr_cam0_s cn61xx;
391 struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xx;
392 struct cvmx_agl_gmx_rxx_adr_cam0_s cn63xxp1;
393 struct cvmx_agl_gmx_rxx_adr_cam0_s cn66xx;
394 struct cvmx_agl_gmx_rxx_adr_cam0_s cn68xx;
395 struct cvmx_agl_gmx_rxx_adr_cam0_s cn68xxp1;
396};
397
398union cvmx_agl_gmx_rxx_adr_cam1 {
399 uint64_t u64;
400 struct cvmx_agl_gmx_rxx_adr_cam1_s {
401#ifdef __BIG_ENDIAN_BITFIELD
402 uint64_t adr:64;
403#else
404 uint64_t adr:64;
405#endif
406 } s;
407 struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xx;
408 struct cvmx_agl_gmx_rxx_adr_cam1_s cn52xxp1;
409 struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xx;
410 struct cvmx_agl_gmx_rxx_adr_cam1_s cn56xxp1;
411 struct cvmx_agl_gmx_rxx_adr_cam1_s cn61xx;
412 struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xx;
413 struct cvmx_agl_gmx_rxx_adr_cam1_s cn63xxp1;
414 struct cvmx_agl_gmx_rxx_adr_cam1_s cn66xx;
415 struct cvmx_agl_gmx_rxx_adr_cam1_s cn68xx;
416 struct cvmx_agl_gmx_rxx_adr_cam1_s cn68xxp1;
417};
418
419union cvmx_agl_gmx_rxx_adr_cam2 {
420 uint64_t u64;
421 struct cvmx_agl_gmx_rxx_adr_cam2_s {
422#ifdef __BIG_ENDIAN_BITFIELD
423 uint64_t adr:64;
424#else
425 uint64_t adr:64;
426#endif
427 } s;
428 struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xx;
429 struct cvmx_agl_gmx_rxx_adr_cam2_s cn52xxp1;
430 struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xx;
431 struct cvmx_agl_gmx_rxx_adr_cam2_s cn56xxp1;
432 struct cvmx_agl_gmx_rxx_adr_cam2_s cn61xx;
433 struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xx;
434 struct cvmx_agl_gmx_rxx_adr_cam2_s cn63xxp1;
435 struct cvmx_agl_gmx_rxx_adr_cam2_s cn66xx;
436 struct cvmx_agl_gmx_rxx_adr_cam2_s cn68xx;
437 struct cvmx_agl_gmx_rxx_adr_cam2_s cn68xxp1;
438};
439
440union cvmx_agl_gmx_rxx_adr_cam3 {
441 uint64_t u64;
442 struct cvmx_agl_gmx_rxx_adr_cam3_s {
443#ifdef __BIG_ENDIAN_BITFIELD
444 uint64_t adr:64;
445#else
446 uint64_t adr:64;
447#endif
448 } s;
449 struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xx;
450 struct cvmx_agl_gmx_rxx_adr_cam3_s cn52xxp1;
451 struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xx;
452 struct cvmx_agl_gmx_rxx_adr_cam3_s cn56xxp1;
453 struct cvmx_agl_gmx_rxx_adr_cam3_s cn61xx;
454 struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xx;
455 struct cvmx_agl_gmx_rxx_adr_cam3_s cn63xxp1;
456 struct cvmx_agl_gmx_rxx_adr_cam3_s cn66xx;
457 struct cvmx_agl_gmx_rxx_adr_cam3_s cn68xx;
458 struct cvmx_agl_gmx_rxx_adr_cam3_s cn68xxp1;
459};
460
461union cvmx_agl_gmx_rxx_adr_cam4 {
462 uint64_t u64;
463 struct cvmx_agl_gmx_rxx_adr_cam4_s {
464#ifdef __BIG_ENDIAN_BITFIELD
465 uint64_t adr:64;
466#else
467 uint64_t adr:64;
468#endif
469 } s;
470 struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xx;
471 struct cvmx_agl_gmx_rxx_adr_cam4_s cn52xxp1;
472 struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xx;
473 struct cvmx_agl_gmx_rxx_adr_cam4_s cn56xxp1;
474 struct cvmx_agl_gmx_rxx_adr_cam4_s cn61xx;
475 struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xx;
476 struct cvmx_agl_gmx_rxx_adr_cam4_s cn63xxp1;
477 struct cvmx_agl_gmx_rxx_adr_cam4_s cn66xx;
478 struct cvmx_agl_gmx_rxx_adr_cam4_s cn68xx;
479 struct cvmx_agl_gmx_rxx_adr_cam4_s cn68xxp1;
480};
481
482union cvmx_agl_gmx_rxx_adr_cam5 {
483 uint64_t u64;
484 struct cvmx_agl_gmx_rxx_adr_cam5_s {
485#ifdef __BIG_ENDIAN_BITFIELD
486 uint64_t adr:64;
487#else
488 uint64_t adr:64;
489#endif
490 } s;
491 struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xx;
492 struct cvmx_agl_gmx_rxx_adr_cam5_s cn52xxp1;
493 struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xx;
494 struct cvmx_agl_gmx_rxx_adr_cam5_s cn56xxp1;
495 struct cvmx_agl_gmx_rxx_adr_cam5_s cn61xx;
496 struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xx;
497 struct cvmx_agl_gmx_rxx_adr_cam5_s cn63xxp1;
498 struct cvmx_agl_gmx_rxx_adr_cam5_s cn66xx;
499 struct cvmx_agl_gmx_rxx_adr_cam5_s cn68xx;
500 struct cvmx_agl_gmx_rxx_adr_cam5_s cn68xxp1;
501};
502
503union cvmx_agl_gmx_rxx_adr_cam_en {
504 uint64_t u64;
505 struct cvmx_agl_gmx_rxx_adr_cam_en_s {
506#ifdef __BIG_ENDIAN_BITFIELD
507 uint64_t reserved_8_63:56;
508 uint64_t en:8;
509#else
510 uint64_t en:8;
511 uint64_t reserved_8_63:56;
512#endif
513 } s;
514 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xx;
515 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn52xxp1;
516 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xx;
517 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn56xxp1;
518 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn61xx;
519 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xx;
520 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn63xxp1;
521 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn66xx;
522 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn68xx;
523 struct cvmx_agl_gmx_rxx_adr_cam_en_s cn68xxp1;
524};
525
526union cvmx_agl_gmx_rxx_adr_ctl {
527 uint64_t u64;
528 struct cvmx_agl_gmx_rxx_adr_ctl_s {
529#ifdef __BIG_ENDIAN_BITFIELD
530 uint64_t reserved_4_63:60;
531 uint64_t cam_mode:1;
532 uint64_t mcst:2;
533 uint64_t bcst:1;
534#else
535 uint64_t bcst:1;
536 uint64_t mcst:2;
537 uint64_t cam_mode:1;
538 uint64_t reserved_4_63:60;
539#endif
540 } s;
541 struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xx;
542 struct cvmx_agl_gmx_rxx_adr_ctl_s cn52xxp1;
543 struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xx;
544 struct cvmx_agl_gmx_rxx_adr_ctl_s cn56xxp1;
545 struct cvmx_agl_gmx_rxx_adr_ctl_s cn61xx;
546 struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xx;
547 struct cvmx_agl_gmx_rxx_adr_ctl_s cn63xxp1;
548 struct cvmx_agl_gmx_rxx_adr_ctl_s cn66xx;
549 struct cvmx_agl_gmx_rxx_adr_ctl_s cn68xx;
550 struct cvmx_agl_gmx_rxx_adr_ctl_s cn68xxp1;
551};
552
553union cvmx_agl_gmx_rxx_decision {
554 uint64_t u64;
555 struct cvmx_agl_gmx_rxx_decision_s {
556#ifdef __BIG_ENDIAN_BITFIELD
557 uint64_t reserved_5_63:59;
558 uint64_t cnt:5;
559#else
560 uint64_t cnt:5;
561 uint64_t reserved_5_63:59;
562#endif
563 } s;
564 struct cvmx_agl_gmx_rxx_decision_s cn52xx;
565 struct cvmx_agl_gmx_rxx_decision_s cn52xxp1;
566 struct cvmx_agl_gmx_rxx_decision_s cn56xx;
567 struct cvmx_agl_gmx_rxx_decision_s cn56xxp1;
568 struct cvmx_agl_gmx_rxx_decision_s cn61xx;
569 struct cvmx_agl_gmx_rxx_decision_s cn63xx;
570 struct cvmx_agl_gmx_rxx_decision_s cn63xxp1;
571 struct cvmx_agl_gmx_rxx_decision_s cn66xx;
572 struct cvmx_agl_gmx_rxx_decision_s cn68xx;
573 struct cvmx_agl_gmx_rxx_decision_s cn68xxp1;
574};
575
576union cvmx_agl_gmx_rxx_frm_chk {
577 uint64_t u64;
578 struct cvmx_agl_gmx_rxx_frm_chk_s {
579#ifdef __BIG_ENDIAN_BITFIELD
580 uint64_t reserved_10_63:54;
581 uint64_t niberr:1;
582 uint64_t skperr:1;
583 uint64_t rcverr:1;
584 uint64_t lenerr:1;
585 uint64_t alnerr:1;
586 uint64_t fcserr:1;
587 uint64_t jabber:1;
588 uint64_t maxerr:1;
589 uint64_t carext:1;
590 uint64_t minerr:1;
591#else
592 uint64_t minerr:1;
593 uint64_t carext:1;
594 uint64_t maxerr:1;
595 uint64_t jabber:1;
596 uint64_t fcserr:1;
597 uint64_t alnerr:1;
598 uint64_t lenerr:1;
599 uint64_t rcverr:1;
600 uint64_t skperr:1;
601 uint64_t niberr:1;
602 uint64_t reserved_10_63:54;
603#endif
604 } s;
605 struct cvmx_agl_gmx_rxx_frm_chk_cn52xx {
606#ifdef __BIG_ENDIAN_BITFIELD
607 uint64_t reserved_9_63:55;
608 uint64_t skperr:1;
609 uint64_t rcverr:1;
610 uint64_t lenerr:1;
611 uint64_t alnerr:1;
612 uint64_t fcserr:1;
613 uint64_t jabber:1;
614 uint64_t maxerr:1;
615 uint64_t reserved_1_1:1;
616 uint64_t minerr:1;
617#else
618 uint64_t minerr:1;
619 uint64_t reserved_1_1:1;
620 uint64_t maxerr:1;
621 uint64_t jabber:1;
622 uint64_t fcserr:1;
623 uint64_t alnerr:1;
624 uint64_t lenerr:1;
625 uint64_t rcverr:1;
626 uint64_t skperr:1;
627 uint64_t reserved_9_63:55;
628#endif
629 } cn52xx;
630 struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn52xxp1;
631 struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xx;
632 struct cvmx_agl_gmx_rxx_frm_chk_cn52xx cn56xxp1;
633 struct cvmx_agl_gmx_rxx_frm_chk_s cn61xx;
634 struct cvmx_agl_gmx_rxx_frm_chk_s cn63xx;
635 struct cvmx_agl_gmx_rxx_frm_chk_s cn63xxp1;
636 struct cvmx_agl_gmx_rxx_frm_chk_s cn66xx;
637 struct cvmx_agl_gmx_rxx_frm_chk_s cn68xx;
638 struct cvmx_agl_gmx_rxx_frm_chk_s cn68xxp1;
639};
640
641union cvmx_agl_gmx_rxx_frm_ctl {
642 uint64_t u64;
643 struct cvmx_agl_gmx_rxx_frm_ctl_s {
644#ifdef __BIG_ENDIAN_BITFIELD
645 uint64_t reserved_13_63:51;
646 uint64_t ptp_mode:1;
647 uint64_t reserved_11_11:1;
648 uint64_t null_dis:1;
649 uint64_t pre_align:1;
650 uint64_t pad_len:1;
651 uint64_t vlan_len:1;
652 uint64_t pre_free:1;
653 uint64_t ctl_smac:1;
654 uint64_t ctl_mcst:1;
655 uint64_t ctl_bck:1;
656 uint64_t ctl_drp:1;
657 uint64_t pre_strp:1;
658 uint64_t pre_chk:1;
659#else
660 uint64_t pre_chk:1;
661 uint64_t pre_strp:1;
662 uint64_t ctl_drp:1;
663 uint64_t ctl_bck:1;
664 uint64_t ctl_mcst:1;
665 uint64_t ctl_smac:1;
666 uint64_t pre_free:1;
667 uint64_t vlan_len:1;
668 uint64_t pad_len:1;
669 uint64_t pre_align:1;
670 uint64_t null_dis:1;
671 uint64_t reserved_11_11:1;
672 uint64_t ptp_mode:1;
673 uint64_t reserved_13_63:51;
674#endif
675 } s;
676 struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx {
677#ifdef __BIG_ENDIAN_BITFIELD
678 uint64_t reserved_10_63:54;
679 uint64_t pre_align:1;
680 uint64_t pad_len:1;
681 uint64_t vlan_len:1;
682 uint64_t pre_free:1;
683 uint64_t ctl_smac:1;
684 uint64_t ctl_mcst:1;
685 uint64_t ctl_bck:1;
686 uint64_t ctl_drp:1;
687 uint64_t pre_strp:1;
688 uint64_t pre_chk:1;
689#else
690 uint64_t pre_chk:1;
691 uint64_t pre_strp:1;
692 uint64_t ctl_drp:1;
693 uint64_t ctl_bck:1;
694 uint64_t ctl_mcst:1;
695 uint64_t ctl_smac:1;
696 uint64_t pre_free:1;
697 uint64_t vlan_len:1;
698 uint64_t pad_len:1;
699 uint64_t pre_align:1;
700 uint64_t reserved_10_63:54;
701#endif
702 } cn52xx;
703 struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn52xxp1;
704 struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xx;
705 struct cvmx_agl_gmx_rxx_frm_ctl_cn52xx cn56xxp1;
706 struct cvmx_agl_gmx_rxx_frm_ctl_s cn61xx;
707 struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xx;
708 struct cvmx_agl_gmx_rxx_frm_ctl_s cn63xxp1;
709 struct cvmx_agl_gmx_rxx_frm_ctl_s cn66xx;
710 struct cvmx_agl_gmx_rxx_frm_ctl_s cn68xx;
711 struct cvmx_agl_gmx_rxx_frm_ctl_s cn68xxp1;
712};
713
714union cvmx_agl_gmx_rxx_frm_max {
715 uint64_t u64;
716 struct cvmx_agl_gmx_rxx_frm_max_s {
717#ifdef __BIG_ENDIAN_BITFIELD
718 uint64_t reserved_16_63:48;
719 uint64_t len:16;
720#else
721 uint64_t len:16;
722 uint64_t reserved_16_63:48;
723#endif
724 } s;
725 struct cvmx_agl_gmx_rxx_frm_max_s cn52xx;
726 struct cvmx_agl_gmx_rxx_frm_max_s cn52xxp1;
727 struct cvmx_agl_gmx_rxx_frm_max_s cn56xx;
728 struct cvmx_agl_gmx_rxx_frm_max_s cn56xxp1;
729 struct cvmx_agl_gmx_rxx_frm_max_s cn61xx;
730 struct cvmx_agl_gmx_rxx_frm_max_s cn63xx;
731 struct cvmx_agl_gmx_rxx_frm_max_s cn63xxp1;
732 struct cvmx_agl_gmx_rxx_frm_max_s cn66xx;
733 struct cvmx_agl_gmx_rxx_frm_max_s cn68xx;
734 struct cvmx_agl_gmx_rxx_frm_max_s cn68xxp1;
735};
736
737union cvmx_agl_gmx_rxx_frm_min {
738 uint64_t u64;
739 struct cvmx_agl_gmx_rxx_frm_min_s {
740#ifdef __BIG_ENDIAN_BITFIELD
741 uint64_t reserved_16_63:48;
742 uint64_t len:16;
743#else
744 uint64_t len:16;
745 uint64_t reserved_16_63:48;
746#endif
747 } s;
748 struct cvmx_agl_gmx_rxx_frm_min_s cn52xx;
749 struct cvmx_agl_gmx_rxx_frm_min_s cn52xxp1;
750 struct cvmx_agl_gmx_rxx_frm_min_s cn56xx;
751 struct cvmx_agl_gmx_rxx_frm_min_s cn56xxp1;
752 struct cvmx_agl_gmx_rxx_frm_min_s cn61xx;
753 struct cvmx_agl_gmx_rxx_frm_min_s cn63xx;
754 struct cvmx_agl_gmx_rxx_frm_min_s cn63xxp1;
755 struct cvmx_agl_gmx_rxx_frm_min_s cn66xx;
756 struct cvmx_agl_gmx_rxx_frm_min_s cn68xx;
757 struct cvmx_agl_gmx_rxx_frm_min_s cn68xxp1;
758};
759
760union cvmx_agl_gmx_rxx_ifg {
761 uint64_t u64;
762 struct cvmx_agl_gmx_rxx_ifg_s {
763#ifdef __BIG_ENDIAN_BITFIELD
764 uint64_t reserved_4_63:60;
765 uint64_t ifg:4;
766#else
767 uint64_t ifg:4;
768 uint64_t reserved_4_63:60;
769#endif
770 } s;
771 struct cvmx_agl_gmx_rxx_ifg_s cn52xx;
772 struct cvmx_agl_gmx_rxx_ifg_s cn52xxp1;
773 struct cvmx_agl_gmx_rxx_ifg_s cn56xx;
774 struct cvmx_agl_gmx_rxx_ifg_s cn56xxp1;
775 struct cvmx_agl_gmx_rxx_ifg_s cn61xx;
776 struct cvmx_agl_gmx_rxx_ifg_s cn63xx;
777 struct cvmx_agl_gmx_rxx_ifg_s cn63xxp1;
778 struct cvmx_agl_gmx_rxx_ifg_s cn66xx;
779 struct cvmx_agl_gmx_rxx_ifg_s cn68xx;
780 struct cvmx_agl_gmx_rxx_ifg_s cn68xxp1;
781};
782
783union cvmx_agl_gmx_rxx_int_en {
784 uint64_t u64;
785 struct cvmx_agl_gmx_rxx_int_en_s {
786#ifdef __BIG_ENDIAN_BITFIELD
787 uint64_t reserved_20_63:44;
788 uint64_t pause_drp:1;
789 uint64_t phy_dupx:1;
790 uint64_t phy_spd:1;
791 uint64_t phy_link:1;
792 uint64_t ifgerr:1;
793 uint64_t coldet:1;
794 uint64_t falerr:1;
795 uint64_t rsverr:1;
796 uint64_t pcterr:1;
797 uint64_t ovrerr:1;
798 uint64_t niberr:1;
799 uint64_t skperr:1;
800 uint64_t rcverr:1;
801 uint64_t lenerr:1;
802 uint64_t alnerr:1;
803 uint64_t fcserr:1;
804 uint64_t jabber:1;
805 uint64_t maxerr:1;
806 uint64_t carext:1;
807 uint64_t minerr:1;
808#else
809 uint64_t minerr:1;
810 uint64_t carext:1;
811 uint64_t maxerr:1;
812 uint64_t jabber:1;
813 uint64_t fcserr:1;
814 uint64_t alnerr:1;
815 uint64_t lenerr:1;
816 uint64_t rcverr:1;
817 uint64_t skperr:1;
818 uint64_t niberr:1;
819 uint64_t ovrerr:1;
820 uint64_t pcterr:1;
821 uint64_t rsverr:1;
822 uint64_t falerr:1;
823 uint64_t coldet:1;
824 uint64_t ifgerr:1;
825 uint64_t phy_link:1;
826 uint64_t phy_spd:1;
827 uint64_t phy_dupx:1;
828 uint64_t pause_drp:1;
829 uint64_t reserved_20_63:44;
830#endif
831 } s;
832 struct cvmx_agl_gmx_rxx_int_en_cn52xx {
833#ifdef __BIG_ENDIAN_BITFIELD
834 uint64_t reserved_20_63:44;
835 uint64_t pause_drp:1;
836 uint64_t reserved_16_18:3;
837 uint64_t ifgerr:1;
838 uint64_t coldet:1;
839 uint64_t falerr:1;
840 uint64_t rsverr:1;
841 uint64_t pcterr:1;
842 uint64_t ovrerr:1;
843 uint64_t reserved_9_9:1;
844 uint64_t skperr:1;
845 uint64_t rcverr:1;
846 uint64_t lenerr:1;
847 uint64_t alnerr:1;
848 uint64_t fcserr:1;
849 uint64_t jabber:1;
850 uint64_t maxerr:1;
851 uint64_t reserved_1_1:1;
852 uint64_t minerr:1;
853#else
854 uint64_t minerr:1;
855 uint64_t reserved_1_1:1;
856 uint64_t maxerr:1;
857 uint64_t jabber:1;
858 uint64_t fcserr:1;
859 uint64_t alnerr:1;
860 uint64_t lenerr:1;
861 uint64_t rcverr:1;
862 uint64_t skperr:1;
863 uint64_t reserved_9_9:1;
864 uint64_t ovrerr:1;
865 uint64_t pcterr:1;
866 uint64_t rsverr:1;
867 uint64_t falerr:1;
868 uint64_t coldet:1;
869 uint64_t ifgerr:1;
870 uint64_t reserved_16_18:3;
871 uint64_t pause_drp:1;
872 uint64_t reserved_20_63:44;
873#endif
874 } cn52xx;
875 struct cvmx_agl_gmx_rxx_int_en_cn52xx cn52xxp1;
876 struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xx;
877 struct cvmx_agl_gmx_rxx_int_en_cn52xx cn56xxp1;
878 struct cvmx_agl_gmx_rxx_int_en_s cn61xx;
879 struct cvmx_agl_gmx_rxx_int_en_s cn63xx;
880 struct cvmx_agl_gmx_rxx_int_en_s cn63xxp1;
881 struct cvmx_agl_gmx_rxx_int_en_s cn66xx;
882 struct cvmx_agl_gmx_rxx_int_en_s cn68xx;
883 struct cvmx_agl_gmx_rxx_int_en_s cn68xxp1;
884};
885
886union cvmx_agl_gmx_rxx_int_reg {
887 uint64_t u64;
888 struct cvmx_agl_gmx_rxx_int_reg_s {
889#ifdef __BIG_ENDIAN_BITFIELD
890 uint64_t reserved_20_63:44;
891 uint64_t pause_drp:1;
892 uint64_t phy_dupx:1;
893 uint64_t phy_spd:1;
894 uint64_t phy_link:1;
895 uint64_t ifgerr:1;
896 uint64_t coldet:1;
897 uint64_t falerr:1;
898 uint64_t rsverr:1;
899 uint64_t pcterr:1;
900 uint64_t ovrerr:1;
901 uint64_t niberr:1;
902 uint64_t skperr:1;
903 uint64_t rcverr:1;
904 uint64_t lenerr:1;
905 uint64_t alnerr:1;
906 uint64_t fcserr:1;
907 uint64_t jabber:1;
908 uint64_t maxerr:1;
909 uint64_t carext:1;
910 uint64_t minerr:1;
911#else
912 uint64_t minerr:1;
913 uint64_t carext:1;
914 uint64_t maxerr:1;
915 uint64_t jabber:1;
916 uint64_t fcserr:1;
917 uint64_t alnerr:1;
918 uint64_t lenerr:1;
919 uint64_t rcverr:1;
920 uint64_t skperr:1;
921 uint64_t niberr:1;
922 uint64_t ovrerr:1;
923 uint64_t pcterr:1;
924 uint64_t rsverr:1;
925 uint64_t falerr:1;
926 uint64_t coldet:1;
927 uint64_t ifgerr:1;
928 uint64_t phy_link:1;
929 uint64_t phy_spd:1;
930 uint64_t phy_dupx:1;
931 uint64_t pause_drp:1;
932 uint64_t reserved_20_63:44;
933#endif
934 } s;
935 struct cvmx_agl_gmx_rxx_int_reg_cn52xx {
936#ifdef __BIG_ENDIAN_BITFIELD
937 uint64_t reserved_20_63:44;
938 uint64_t pause_drp:1;
939 uint64_t reserved_16_18:3;
940 uint64_t ifgerr:1;
941 uint64_t coldet:1;
942 uint64_t falerr:1;
943 uint64_t rsverr:1;
944 uint64_t pcterr:1;
945 uint64_t ovrerr:1;
946 uint64_t reserved_9_9:1;
947 uint64_t skperr:1;
948 uint64_t rcverr:1;
949 uint64_t lenerr:1;
950 uint64_t alnerr:1;
951 uint64_t fcserr:1;
952 uint64_t jabber:1;
953 uint64_t maxerr:1;
954 uint64_t reserved_1_1:1;
955 uint64_t minerr:1;
956#else
957 uint64_t minerr:1;
958 uint64_t reserved_1_1:1;
959 uint64_t maxerr:1;
960 uint64_t jabber:1;
961 uint64_t fcserr:1;
962 uint64_t alnerr:1;
963 uint64_t lenerr:1;
964 uint64_t rcverr:1;
965 uint64_t skperr:1;
966 uint64_t reserved_9_9:1;
967 uint64_t ovrerr:1;
968 uint64_t pcterr:1;
969 uint64_t rsverr:1;
970 uint64_t falerr:1;
971 uint64_t coldet:1;
972 uint64_t ifgerr:1;
973 uint64_t reserved_16_18:3;
974 uint64_t pause_drp:1;
975 uint64_t reserved_20_63:44;
976#endif
977 } cn52xx;
978 struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn52xxp1;
979 struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xx;
980 struct cvmx_agl_gmx_rxx_int_reg_cn52xx cn56xxp1;
981 struct cvmx_agl_gmx_rxx_int_reg_s cn61xx;
982 struct cvmx_agl_gmx_rxx_int_reg_s cn63xx;
983 struct cvmx_agl_gmx_rxx_int_reg_s cn63xxp1;
984 struct cvmx_agl_gmx_rxx_int_reg_s cn66xx;
985 struct cvmx_agl_gmx_rxx_int_reg_s cn68xx;
986 struct cvmx_agl_gmx_rxx_int_reg_s cn68xxp1;
987};
988
989union cvmx_agl_gmx_rxx_jabber {
990 uint64_t u64;
991 struct cvmx_agl_gmx_rxx_jabber_s {
992#ifdef __BIG_ENDIAN_BITFIELD
993 uint64_t reserved_16_63:48;
994 uint64_t cnt:16;
995#else
996 uint64_t cnt:16;
997 uint64_t reserved_16_63:48;
998#endif
999 } s;
1000 struct cvmx_agl_gmx_rxx_jabber_s cn52xx;
1001 struct cvmx_agl_gmx_rxx_jabber_s cn52xxp1;
1002 struct cvmx_agl_gmx_rxx_jabber_s cn56xx;
1003 struct cvmx_agl_gmx_rxx_jabber_s cn56xxp1;
1004 struct cvmx_agl_gmx_rxx_jabber_s cn61xx;
1005 struct cvmx_agl_gmx_rxx_jabber_s cn63xx;
1006 struct cvmx_agl_gmx_rxx_jabber_s cn63xxp1;
1007 struct cvmx_agl_gmx_rxx_jabber_s cn66xx;
1008 struct cvmx_agl_gmx_rxx_jabber_s cn68xx;
1009 struct cvmx_agl_gmx_rxx_jabber_s cn68xxp1;
1010};
1011
1012union cvmx_agl_gmx_rxx_pause_drop_time {
1013 uint64_t u64;
1014 struct cvmx_agl_gmx_rxx_pause_drop_time_s {
1015#ifdef __BIG_ENDIAN_BITFIELD
1016 uint64_t reserved_16_63:48;
1017 uint64_t status:16;
1018#else
1019 uint64_t status:16;
1020 uint64_t reserved_16_63:48;
1021#endif
1022 } s;
1023 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xx;
1024 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn52xxp1;
1025 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xx;
1026 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn56xxp1;
1027 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn61xx;
1028 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xx;
1029 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn63xxp1;
1030 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn66xx;
1031 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn68xx;
1032 struct cvmx_agl_gmx_rxx_pause_drop_time_s cn68xxp1;
1033};
1034
1035union cvmx_agl_gmx_rxx_rx_inbnd {
1036 uint64_t u64;
1037 struct cvmx_agl_gmx_rxx_rx_inbnd_s {
1038#ifdef __BIG_ENDIAN_BITFIELD
1039 uint64_t reserved_4_63:60;
1040 uint64_t duplex:1;
1041 uint64_t speed:2;
1042 uint64_t status:1;
1043#else
1044 uint64_t status:1;
1045 uint64_t speed:2;
1046 uint64_t duplex:1;
1047 uint64_t reserved_4_63:60;
1048#endif
1049 } s;
1050 struct cvmx_agl_gmx_rxx_rx_inbnd_s cn61xx;
1051 struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xx;
1052 struct cvmx_agl_gmx_rxx_rx_inbnd_s cn63xxp1;
1053 struct cvmx_agl_gmx_rxx_rx_inbnd_s cn66xx;
1054 struct cvmx_agl_gmx_rxx_rx_inbnd_s cn68xx;
1055 struct cvmx_agl_gmx_rxx_rx_inbnd_s cn68xxp1;
1056};
1057
1058union cvmx_agl_gmx_rxx_stats_ctl {
1059 uint64_t u64;
1060 struct cvmx_agl_gmx_rxx_stats_ctl_s {
1061#ifdef __BIG_ENDIAN_BITFIELD
1062 uint64_t reserved_1_63:63;
1063 uint64_t rd_clr:1;
1064#else
1065 uint64_t rd_clr:1;
1066 uint64_t reserved_1_63:63;
1067#endif
1068 } s;
1069 struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xx;
1070 struct cvmx_agl_gmx_rxx_stats_ctl_s cn52xxp1;
1071 struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xx;
1072 struct cvmx_agl_gmx_rxx_stats_ctl_s cn56xxp1;
1073 struct cvmx_agl_gmx_rxx_stats_ctl_s cn61xx;
1074 struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xx;
1075 struct cvmx_agl_gmx_rxx_stats_ctl_s cn63xxp1;
1076 struct cvmx_agl_gmx_rxx_stats_ctl_s cn66xx;
1077 struct cvmx_agl_gmx_rxx_stats_ctl_s cn68xx;
1078 struct cvmx_agl_gmx_rxx_stats_ctl_s cn68xxp1;
1079};
1080
1081union cvmx_agl_gmx_rxx_stats_octs {
1082 uint64_t u64;
1083 struct cvmx_agl_gmx_rxx_stats_octs_s {
1084#ifdef __BIG_ENDIAN_BITFIELD
1085 uint64_t reserved_48_63:16;
1086 uint64_t cnt:48;
1087#else
1088 uint64_t cnt:48;
1089 uint64_t reserved_48_63:16;
1090#endif
1091 } s;
1092 struct cvmx_agl_gmx_rxx_stats_octs_s cn52xx;
1093 struct cvmx_agl_gmx_rxx_stats_octs_s cn52xxp1;
1094 struct cvmx_agl_gmx_rxx_stats_octs_s cn56xx;
1095 struct cvmx_agl_gmx_rxx_stats_octs_s cn56xxp1;
1096 struct cvmx_agl_gmx_rxx_stats_octs_s cn61xx;
1097 struct cvmx_agl_gmx_rxx_stats_octs_s cn63xx;
1098 struct cvmx_agl_gmx_rxx_stats_octs_s cn63xxp1;
1099 struct cvmx_agl_gmx_rxx_stats_octs_s cn66xx;
1100 struct cvmx_agl_gmx_rxx_stats_octs_s cn68xx;
1101 struct cvmx_agl_gmx_rxx_stats_octs_s cn68xxp1;
1102};
1103
1104union cvmx_agl_gmx_rxx_stats_octs_ctl {
1105 uint64_t u64;
1106 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s {
1107#ifdef __BIG_ENDIAN_BITFIELD
1108 uint64_t reserved_48_63:16;
1109 uint64_t cnt:48;
1110#else
1111 uint64_t cnt:48;
1112 uint64_t reserved_48_63:16;
1113#endif
1114 } s;
1115 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xx;
1116 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn52xxp1;
1117 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xx;
1118 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn56xxp1;
1119 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn61xx;
1120 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xx;
1121 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn63xxp1;
1122 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn66xx;
1123 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn68xx;
1124 struct cvmx_agl_gmx_rxx_stats_octs_ctl_s cn68xxp1;
1125};
1126
1127union cvmx_agl_gmx_rxx_stats_octs_dmac {
1128 uint64_t u64;
1129 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s {
1130#ifdef __BIG_ENDIAN_BITFIELD
1131 uint64_t reserved_48_63:16;
1132 uint64_t cnt:48;
1133#else
1134 uint64_t cnt:48;
1135 uint64_t reserved_48_63:16;
1136#endif
1137 } s;
1138 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xx;
1139 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn52xxp1;
1140 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xx;
1141 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn56xxp1;
1142 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn61xx;
1143 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xx;
1144 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn63xxp1;
1145 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn66xx;
1146 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn68xx;
1147 struct cvmx_agl_gmx_rxx_stats_octs_dmac_s cn68xxp1;
1148};
1149
1150union cvmx_agl_gmx_rxx_stats_octs_drp {
1151 uint64_t u64;
1152 struct cvmx_agl_gmx_rxx_stats_octs_drp_s {
1153#ifdef __BIG_ENDIAN_BITFIELD
1154 uint64_t reserved_48_63:16;
1155 uint64_t cnt:48;
1156#else
1157 uint64_t cnt:48;
1158 uint64_t reserved_48_63:16;
1159#endif
1160 } s;
1161 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xx;
1162 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn52xxp1;
1163 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xx;
1164 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn56xxp1;
1165 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn61xx;
1166 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xx;
1167 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn63xxp1;
1168 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn66xx;
1169 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn68xx;
1170 struct cvmx_agl_gmx_rxx_stats_octs_drp_s cn68xxp1;
1171};
1172
1173union cvmx_agl_gmx_rxx_stats_pkts {
1174 uint64_t u64;
1175 struct cvmx_agl_gmx_rxx_stats_pkts_s {
1176#ifdef __BIG_ENDIAN_BITFIELD
1177 uint64_t reserved_32_63:32;
1178 uint64_t cnt:32;
1179#else
1180 uint64_t cnt:32;
1181 uint64_t reserved_32_63:32;
1182#endif
1183 } s;
1184 struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xx;
1185 struct cvmx_agl_gmx_rxx_stats_pkts_s cn52xxp1;
1186 struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xx;
1187 struct cvmx_agl_gmx_rxx_stats_pkts_s cn56xxp1;
1188 struct cvmx_agl_gmx_rxx_stats_pkts_s cn61xx;
1189 struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xx;
1190 struct cvmx_agl_gmx_rxx_stats_pkts_s cn63xxp1;
1191 struct cvmx_agl_gmx_rxx_stats_pkts_s cn66xx;
1192 struct cvmx_agl_gmx_rxx_stats_pkts_s cn68xx;
1193 struct cvmx_agl_gmx_rxx_stats_pkts_s cn68xxp1;
1194};
1195
1196union cvmx_agl_gmx_rxx_stats_pkts_bad {
1197 uint64_t u64;
1198 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s {
1199#ifdef __BIG_ENDIAN_BITFIELD
1200 uint64_t reserved_32_63:32;
1201 uint64_t cnt:32;
1202#else
1203 uint64_t cnt:32;
1204 uint64_t reserved_32_63:32;
1205#endif
1206 } s;
1207 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xx;
1208 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn52xxp1;
1209 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xx;
1210 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn56xxp1;
1211 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn61xx;
1212 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xx;
1213 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn63xxp1;
1214 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn66xx;
1215 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn68xx;
1216 struct cvmx_agl_gmx_rxx_stats_pkts_bad_s cn68xxp1;
1217};
1218
1219union cvmx_agl_gmx_rxx_stats_pkts_ctl {
1220 uint64_t u64;
1221 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s {
1222#ifdef __BIG_ENDIAN_BITFIELD
1223 uint64_t reserved_32_63:32;
1224 uint64_t cnt:32;
1225#else
1226 uint64_t cnt:32;
1227 uint64_t reserved_32_63:32;
1228#endif
1229 } s;
1230 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xx;
1231 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn52xxp1;
1232 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xx;
1233 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn56xxp1;
1234 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn61xx;
1235 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xx;
1236 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn63xxp1;
1237 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn66xx;
1238 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn68xx;
1239 struct cvmx_agl_gmx_rxx_stats_pkts_ctl_s cn68xxp1;
1240};
1241
1242union cvmx_agl_gmx_rxx_stats_pkts_dmac {
1243 uint64_t u64;
1244 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s {
1245#ifdef __BIG_ENDIAN_BITFIELD
1246 uint64_t reserved_32_63:32;
1247 uint64_t cnt:32;
1248#else
1249 uint64_t cnt:32;
1250 uint64_t reserved_32_63:32;
1251#endif
1252 } s;
1253 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xx;
1254 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn52xxp1;
1255 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xx;
1256 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn56xxp1;
1257 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn61xx;
1258 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xx;
1259 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn63xxp1;
1260 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn66xx;
1261 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn68xx;
1262 struct cvmx_agl_gmx_rxx_stats_pkts_dmac_s cn68xxp1;
1263};
1264
1265union cvmx_agl_gmx_rxx_stats_pkts_drp {
1266 uint64_t u64;
1267 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s {
1268#ifdef __BIG_ENDIAN_BITFIELD
1269 uint64_t reserved_32_63:32;
1270 uint64_t cnt:32;
1271#else
1272 uint64_t cnt:32;
1273 uint64_t reserved_32_63:32;
1274#endif
1275 } s;
1276 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xx;
1277 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn52xxp1;
1278 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xx;
1279 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn56xxp1;
1280 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn61xx;
1281 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xx;
1282 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn63xxp1;
1283 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn66xx;
1284 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn68xx;
1285 struct cvmx_agl_gmx_rxx_stats_pkts_drp_s cn68xxp1;
1286};
1287
1288union cvmx_agl_gmx_rxx_udd_skp {
1289 uint64_t u64;
1290 struct cvmx_agl_gmx_rxx_udd_skp_s {
1291#ifdef __BIG_ENDIAN_BITFIELD
1292 uint64_t reserved_9_63:55;
1293 uint64_t fcssel:1;
1294 uint64_t reserved_7_7:1;
1295 uint64_t len:7;
1296#else
1297 uint64_t len:7;
1298 uint64_t reserved_7_7:1;
1299 uint64_t fcssel:1;
1300 uint64_t reserved_9_63:55;
1301#endif
1302 } s;
1303 struct cvmx_agl_gmx_rxx_udd_skp_s cn52xx;
1304 struct cvmx_agl_gmx_rxx_udd_skp_s cn52xxp1;
1305 struct cvmx_agl_gmx_rxx_udd_skp_s cn56xx;
1306 struct cvmx_agl_gmx_rxx_udd_skp_s cn56xxp1;
1307 struct cvmx_agl_gmx_rxx_udd_skp_s cn61xx;
1308 struct cvmx_agl_gmx_rxx_udd_skp_s cn63xx;
1309 struct cvmx_agl_gmx_rxx_udd_skp_s cn63xxp1;
1310 struct cvmx_agl_gmx_rxx_udd_skp_s cn66xx;
1311 struct cvmx_agl_gmx_rxx_udd_skp_s cn68xx;
1312 struct cvmx_agl_gmx_rxx_udd_skp_s cn68xxp1;
1313};
1314
1315union cvmx_agl_gmx_rx_bp_dropx {
1316 uint64_t u64;
1317 struct cvmx_agl_gmx_rx_bp_dropx_s {
1318#ifdef __BIG_ENDIAN_BITFIELD
1319 uint64_t reserved_6_63:58;
1320 uint64_t mark:6;
1321#else
1322 uint64_t mark:6;
1323 uint64_t reserved_6_63:58;
1324#endif
1325 } s;
1326 struct cvmx_agl_gmx_rx_bp_dropx_s cn52xx;
1327 struct cvmx_agl_gmx_rx_bp_dropx_s cn52xxp1;
1328 struct cvmx_agl_gmx_rx_bp_dropx_s cn56xx;
1329 struct cvmx_agl_gmx_rx_bp_dropx_s cn56xxp1;
1330 struct cvmx_agl_gmx_rx_bp_dropx_s cn61xx;
1331 struct cvmx_agl_gmx_rx_bp_dropx_s cn63xx;
1332 struct cvmx_agl_gmx_rx_bp_dropx_s cn63xxp1;
1333 struct cvmx_agl_gmx_rx_bp_dropx_s cn66xx;
1334 struct cvmx_agl_gmx_rx_bp_dropx_s cn68xx;
1335 struct cvmx_agl_gmx_rx_bp_dropx_s cn68xxp1;
1336};
1337
1338union cvmx_agl_gmx_rx_bp_offx {
1339 uint64_t u64;
1340 struct cvmx_agl_gmx_rx_bp_offx_s {
1341#ifdef __BIG_ENDIAN_BITFIELD
1342 uint64_t reserved_6_63:58;
1343 uint64_t mark:6;
1344#else
1345 uint64_t mark:6;
1346 uint64_t reserved_6_63:58;
1347#endif
1348 } s;
1349 struct cvmx_agl_gmx_rx_bp_offx_s cn52xx;
1350 struct cvmx_agl_gmx_rx_bp_offx_s cn52xxp1;
1351 struct cvmx_agl_gmx_rx_bp_offx_s cn56xx;
1352 struct cvmx_agl_gmx_rx_bp_offx_s cn56xxp1;
1353 struct cvmx_agl_gmx_rx_bp_offx_s cn61xx;
1354 struct cvmx_agl_gmx_rx_bp_offx_s cn63xx;
1355 struct cvmx_agl_gmx_rx_bp_offx_s cn63xxp1;
1356 struct cvmx_agl_gmx_rx_bp_offx_s cn66xx;
1357 struct cvmx_agl_gmx_rx_bp_offx_s cn68xx;
1358 struct cvmx_agl_gmx_rx_bp_offx_s cn68xxp1;
1359};
1360
1361union cvmx_agl_gmx_rx_bp_onx {
1362 uint64_t u64;
1363 struct cvmx_agl_gmx_rx_bp_onx_s {
1364#ifdef __BIG_ENDIAN_BITFIELD
1365 uint64_t reserved_9_63:55;
1366 uint64_t mark:9;
1367#else
1368 uint64_t mark:9;
1369 uint64_t reserved_9_63:55;
1370#endif
1371 } s;
1372 struct cvmx_agl_gmx_rx_bp_onx_s cn52xx;
1373 struct cvmx_agl_gmx_rx_bp_onx_s cn52xxp1;
1374 struct cvmx_agl_gmx_rx_bp_onx_s cn56xx;
1375 struct cvmx_agl_gmx_rx_bp_onx_s cn56xxp1;
1376 struct cvmx_agl_gmx_rx_bp_onx_s cn61xx;
1377 struct cvmx_agl_gmx_rx_bp_onx_s cn63xx;
1378 struct cvmx_agl_gmx_rx_bp_onx_s cn63xxp1;
1379 struct cvmx_agl_gmx_rx_bp_onx_s cn66xx;
1380 struct cvmx_agl_gmx_rx_bp_onx_s cn68xx;
1381 struct cvmx_agl_gmx_rx_bp_onx_s cn68xxp1;
1382};
1383
1384union cvmx_agl_gmx_rx_prt_info {
1385 uint64_t u64;
1386 struct cvmx_agl_gmx_rx_prt_info_s {
1387#ifdef __BIG_ENDIAN_BITFIELD
1388 uint64_t reserved_18_63:46;
1389 uint64_t drop:2;
1390 uint64_t reserved_2_15:14;
1391 uint64_t commit:2;
1392#else
1393 uint64_t commit:2;
1394 uint64_t reserved_2_15:14;
1395 uint64_t drop:2;
1396 uint64_t reserved_18_63:46;
1397#endif
1398 } s;
1399 struct cvmx_agl_gmx_rx_prt_info_s cn52xx;
1400 struct cvmx_agl_gmx_rx_prt_info_s cn52xxp1;
1401 struct cvmx_agl_gmx_rx_prt_info_cn56xx {
1402#ifdef __BIG_ENDIAN_BITFIELD
1403 uint64_t reserved_17_63:47;
1404 uint64_t drop:1;
1405 uint64_t reserved_1_15:15;
1406 uint64_t commit:1;
1407#else
1408 uint64_t commit:1;
1409 uint64_t reserved_1_15:15;
1410 uint64_t drop:1;
1411 uint64_t reserved_17_63:47;
1412#endif
1413 } cn56xx;
1414 struct cvmx_agl_gmx_rx_prt_info_cn56xx cn56xxp1;
1415 struct cvmx_agl_gmx_rx_prt_info_s cn61xx;
1416 struct cvmx_agl_gmx_rx_prt_info_s cn63xx;
1417 struct cvmx_agl_gmx_rx_prt_info_s cn63xxp1;
1418 struct cvmx_agl_gmx_rx_prt_info_s cn66xx;
1419 struct cvmx_agl_gmx_rx_prt_info_s cn68xx;
1420 struct cvmx_agl_gmx_rx_prt_info_s cn68xxp1;
1421};
1422
1423union cvmx_agl_gmx_rx_tx_status {
1424 uint64_t u64;
1425 struct cvmx_agl_gmx_rx_tx_status_s {
1426#ifdef __BIG_ENDIAN_BITFIELD
1427 uint64_t reserved_6_63:58;
1428 uint64_t tx:2;
1429 uint64_t reserved_2_3:2;
1430 uint64_t rx:2;
1431#else
1432 uint64_t rx:2;
1433 uint64_t reserved_2_3:2;
1434 uint64_t tx:2;
1435 uint64_t reserved_6_63:58;
1436#endif
1437 } s;
1438 struct cvmx_agl_gmx_rx_tx_status_s cn52xx;
1439 struct cvmx_agl_gmx_rx_tx_status_s cn52xxp1;
1440 struct cvmx_agl_gmx_rx_tx_status_cn56xx {
1441#ifdef __BIG_ENDIAN_BITFIELD
1442 uint64_t reserved_5_63:59;
1443 uint64_t tx:1;
1444 uint64_t reserved_1_3:3;
1445 uint64_t rx:1;
1446#else
1447 uint64_t rx:1;
1448 uint64_t reserved_1_3:3;
1449 uint64_t tx:1;
1450 uint64_t reserved_5_63:59;
1451#endif
1452 } cn56xx;
1453 struct cvmx_agl_gmx_rx_tx_status_cn56xx cn56xxp1;
1454 struct cvmx_agl_gmx_rx_tx_status_s cn61xx;
1455 struct cvmx_agl_gmx_rx_tx_status_s cn63xx;
1456 struct cvmx_agl_gmx_rx_tx_status_s cn63xxp1;
1457 struct cvmx_agl_gmx_rx_tx_status_s cn66xx;
1458 struct cvmx_agl_gmx_rx_tx_status_s cn68xx;
1459 struct cvmx_agl_gmx_rx_tx_status_s cn68xxp1;
1460};
1461
1462union cvmx_agl_gmx_smacx {
1463 uint64_t u64;
1464 struct cvmx_agl_gmx_smacx_s {
1465#ifdef __BIG_ENDIAN_BITFIELD
1466 uint64_t reserved_48_63:16;
1467 uint64_t smac:48;
1468#else
1469 uint64_t smac:48;
1470 uint64_t reserved_48_63:16;
1471#endif
1472 } s;
1473 struct cvmx_agl_gmx_smacx_s cn52xx;
1474 struct cvmx_agl_gmx_smacx_s cn52xxp1;
1475 struct cvmx_agl_gmx_smacx_s cn56xx;
1476 struct cvmx_agl_gmx_smacx_s cn56xxp1;
1477 struct cvmx_agl_gmx_smacx_s cn61xx;
1478 struct cvmx_agl_gmx_smacx_s cn63xx;
1479 struct cvmx_agl_gmx_smacx_s cn63xxp1;
1480 struct cvmx_agl_gmx_smacx_s cn66xx;
1481 struct cvmx_agl_gmx_smacx_s cn68xx;
1482 struct cvmx_agl_gmx_smacx_s cn68xxp1;
1483};
1484
1485union cvmx_agl_gmx_stat_bp {
1486 uint64_t u64;
1487 struct cvmx_agl_gmx_stat_bp_s {
1488#ifdef __BIG_ENDIAN_BITFIELD
1489 uint64_t reserved_17_63:47;
1490 uint64_t bp:1;
1491 uint64_t cnt:16;
1492#else
1493 uint64_t cnt:16;
1494 uint64_t bp:1;
1495 uint64_t reserved_17_63:47;
1496#endif
1497 } s;
1498 struct cvmx_agl_gmx_stat_bp_s cn52xx;
1499 struct cvmx_agl_gmx_stat_bp_s cn52xxp1;
1500 struct cvmx_agl_gmx_stat_bp_s cn56xx;
1501 struct cvmx_agl_gmx_stat_bp_s cn56xxp1;
1502 struct cvmx_agl_gmx_stat_bp_s cn61xx;
1503 struct cvmx_agl_gmx_stat_bp_s cn63xx;
1504 struct cvmx_agl_gmx_stat_bp_s cn63xxp1;
1505 struct cvmx_agl_gmx_stat_bp_s cn66xx;
1506 struct cvmx_agl_gmx_stat_bp_s cn68xx;
1507 struct cvmx_agl_gmx_stat_bp_s cn68xxp1;
1508};
1509
1510union cvmx_agl_gmx_txx_append {
1511 uint64_t u64;
1512 struct cvmx_agl_gmx_txx_append_s {
1513#ifdef __BIG_ENDIAN_BITFIELD
1514 uint64_t reserved_4_63:60;
1515 uint64_t force_fcs:1;
1516 uint64_t fcs:1;
1517 uint64_t pad:1;
1518 uint64_t preamble:1;
1519#else
1520 uint64_t preamble:1;
1521 uint64_t pad:1;
1522 uint64_t fcs:1;
1523 uint64_t force_fcs:1;
1524 uint64_t reserved_4_63:60;
1525#endif
1526 } s;
1527 struct cvmx_agl_gmx_txx_append_s cn52xx;
1528 struct cvmx_agl_gmx_txx_append_s cn52xxp1;
1529 struct cvmx_agl_gmx_txx_append_s cn56xx;
1530 struct cvmx_agl_gmx_txx_append_s cn56xxp1;
1531 struct cvmx_agl_gmx_txx_append_s cn61xx;
1532 struct cvmx_agl_gmx_txx_append_s cn63xx;
1533 struct cvmx_agl_gmx_txx_append_s cn63xxp1;
1534 struct cvmx_agl_gmx_txx_append_s cn66xx;
1535 struct cvmx_agl_gmx_txx_append_s cn68xx;
1536 struct cvmx_agl_gmx_txx_append_s cn68xxp1;
1537};
1538
1539union cvmx_agl_gmx_txx_clk {
1540 uint64_t u64;
1541 struct cvmx_agl_gmx_txx_clk_s {
1542#ifdef __BIG_ENDIAN_BITFIELD
1543 uint64_t reserved_6_63:58;
1544 uint64_t clk_cnt:6;
1545#else
1546 uint64_t clk_cnt:6;
1547 uint64_t reserved_6_63:58;
1548#endif
1549 } s;
1550 struct cvmx_agl_gmx_txx_clk_s cn61xx;
1551 struct cvmx_agl_gmx_txx_clk_s cn63xx;
1552 struct cvmx_agl_gmx_txx_clk_s cn63xxp1;
1553 struct cvmx_agl_gmx_txx_clk_s cn66xx;
1554 struct cvmx_agl_gmx_txx_clk_s cn68xx;
1555 struct cvmx_agl_gmx_txx_clk_s cn68xxp1;
1556};
1557
1558union cvmx_agl_gmx_txx_ctl {
1559 uint64_t u64;
1560 struct cvmx_agl_gmx_txx_ctl_s {
1561#ifdef __BIG_ENDIAN_BITFIELD
1562 uint64_t reserved_2_63:62;
1563 uint64_t xsdef_en:1;
1564 uint64_t xscol_en:1;
1565#else
1566 uint64_t xscol_en:1;
1567 uint64_t xsdef_en:1;
1568 uint64_t reserved_2_63:62;
1569#endif
1570 } s;
1571 struct cvmx_agl_gmx_txx_ctl_s cn52xx;
1572 struct cvmx_agl_gmx_txx_ctl_s cn52xxp1;
1573 struct cvmx_agl_gmx_txx_ctl_s cn56xx;
1574 struct cvmx_agl_gmx_txx_ctl_s cn56xxp1;
1575 struct cvmx_agl_gmx_txx_ctl_s cn61xx;
1576 struct cvmx_agl_gmx_txx_ctl_s cn63xx;
1577 struct cvmx_agl_gmx_txx_ctl_s cn63xxp1;
1578 struct cvmx_agl_gmx_txx_ctl_s cn66xx;
1579 struct cvmx_agl_gmx_txx_ctl_s cn68xx;
1580 struct cvmx_agl_gmx_txx_ctl_s cn68xxp1;
1581};
1582
1583union cvmx_agl_gmx_txx_min_pkt {
1584 uint64_t u64;
1585 struct cvmx_agl_gmx_txx_min_pkt_s {
1586#ifdef __BIG_ENDIAN_BITFIELD
1587 uint64_t reserved_8_63:56;
1588 uint64_t min_size:8;
1589#else
1590 uint64_t min_size:8;
1591 uint64_t reserved_8_63:56;
1592#endif
1593 } s;
1594 struct cvmx_agl_gmx_txx_min_pkt_s cn52xx;
1595 struct cvmx_agl_gmx_txx_min_pkt_s cn52xxp1;
1596 struct cvmx_agl_gmx_txx_min_pkt_s cn56xx;
1597 struct cvmx_agl_gmx_txx_min_pkt_s cn56xxp1;
1598 struct cvmx_agl_gmx_txx_min_pkt_s cn61xx;
1599 struct cvmx_agl_gmx_txx_min_pkt_s cn63xx;
1600 struct cvmx_agl_gmx_txx_min_pkt_s cn63xxp1;
1601 struct cvmx_agl_gmx_txx_min_pkt_s cn66xx;
1602 struct cvmx_agl_gmx_txx_min_pkt_s cn68xx;
1603 struct cvmx_agl_gmx_txx_min_pkt_s cn68xxp1;
1604};
1605
1606union cvmx_agl_gmx_txx_pause_pkt_interval {
1607 uint64_t u64;
1608 struct cvmx_agl_gmx_txx_pause_pkt_interval_s {
1609#ifdef __BIG_ENDIAN_BITFIELD
1610 uint64_t reserved_16_63:48;
1611 uint64_t interval:16;
1612#else
1613 uint64_t interval:16;
1614 uint64_t reserved_16_63:48;
1615#endif
1616 } s;
1617 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xx;
1618 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn52xxp1;
1619 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xx;
1620 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn56xxp1;
1621 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn61xx;
1622 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xx;
1623 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn63xxp1;
1624 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn66xx;
1625 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn68xx;
1626 struct cvmx_agl_gmx_txx_pause_pkt_interval_s cn68xxp1;
1627};
1628
1629union cvmx_agl_gmx_txx_pause_pkt_time {
1630 uint64_t u64;
1631 struct cvmx_agl_gmx_txx_pause_pkt_time_s {
1632#ifdef __BIG_ENDIAN_BITFIELD
1633 uint64_t reserved_16_63:48;
1634 uint64_t time:16;
1635#else
1636 uint64_t time:16;
1637 uint64_t reserved_16_63:48;
1638#endif
1639 } s;
1640 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xx;
1641 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn52xxp1;
1642 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xx;
1643 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn56xxp1;
1644 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn61xx;
1645 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xx;
1646 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn63xxp1;
1647 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn66xx;
1648 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn68xx;
1649 struct cvmx_agl_gmx_txx_pause_pkt_time_s cn68xxp1;
1650};
1651
1652union cvmx_agl_gmx_txx_pause_togo {
1653 uint64_t u64;
1654 struct cvmx_agl_gmx_txx_pause_togo_s {
1655#ifdef __BIG_ENDIAN_BITFIELD
1656 uint64_t reserved_16_63:48;
1657 uint64_t time:16;
1658#else
1659 uint64_t time:16;
1660 uint64_t reserved_16_63:48;
1661#endif
1662 } s;
1663 struct cvmx_agl_gmx_txx_pause_togo_s cn52xx;
1664 struct cvmx_agl_gmx_txx_pause_togo_s cn52xxp1;
1665 struct cvmx_agl_gmx_txx_pause_togo_s cn56xx;
1666 struct cvmx_agl_gmx_txx_pause_togo_s cn56xxp1;
1667 struct cvmx_agl_gmx_txx_pause_togo_s cn61xx;
1668 struct cvmx_agl_gmx_txx_pause_togo_s cn63xx;
1669 struct cvmx_agl_gmx_txx_pause_togo_s cn63xxp1;
1670 struct cvmx_agl_gmx_txx_pause_togo_s cn66xx;
1671 struct cvmx_agl_gmx_txx_pause_togo_s cn68xx;
1672 struct cvmx_agl_gmx_txx_pause_togo_s cn68xxp1;
1673};
1674
1675union cvmx_agl_gmx_txx_pause_zero {
1676 uint64_t u64;
1677 struct cvmx_agl_gmx_txx_pause_zero_s {
1678#ifdef __BIG_ENDIAN_BITFIELD
1679 uint64_t reserved_1_63:63;
1680 uint64_t send:1;
1681#else
1682 uint64_t send:1;
1683 uint64_t reserved_1_63:63;
1684#endif
1685 } s;
1686 struct cvmx_agl_gmx_txx_pause_zero_s cn52xx;
1687 struct cvmx_agl_gmx_txx_pause_zero_s cn52xxp1;
1688 struct cvmx_agl_gmx_txx_pause_zero_s cn56xx;
1689 struct cvmx_agl_gmx_txx_pause_zero_s cn56xxp1;
1690 struct cvmx_agl_gmx_txx_pause_zero_s cn61xx;
1691 struct cvmx_agl_gmx_txx_pause_zero_s cn63xx;
1692 struct cvmx_agl_gmx_txx_pause_zero_s cn63xxp1;
1693 struct cvmx_agl_gmx_txx_pause_zero_s cn66xx;
1694 struct cvmx_agl_gmx_txx_pause_zero_s cn68xx;
1695 struct cvmx_agl_gmx_txx_pause_zero_s cn68xxp1;
1696};
1697
1698union cvmx_agl_gmx_txx_soft_pause {
1699 uint64_t u64;
1700 struct cvmx_agl_gmx_txx_soft_pause_s {
1701#ifdef __BIG_ENDIAN_BITFIELD
1702 uint64_t reserved_16_63:48;
1703 uint64_t time:16;
1704#else
1705 uint64_t time:16;
1706 uint64_t reserved_16_63:48;
1707#endif
1708 } s;
1709 struct cvmx_agl_gmx_txx_soft_pause_s cn52xx;
1710 struct cvmx_agl_gmx_txx_soft_pause_s cn52xxp1;
1711 struct cvmx_agl_gmx_txx_soft_pause_s cn56xx;
1712 struct cvmx_agl_gmx_txx_soft_pause_s cn56xxp1;
1713 struct cvmx_agl_gmx_txx_soft_pause_s cn61xx;
1714 struct cvmx_agl_gmx_txx_soft_pause_s cn63xx;
1715 struct cvmx_agl_gmx_txx_soft_pause_s cn63xxp1;
1716 struct cvmx_agl_gmx_txx_soft_pause_s cn66xx;
1717 struct cvmx_agl_gmx_txx_soft_pause_s cn68xx;
1718 struct cvmx_agl_gmx_txx_soft_pause_s cn68xxp1;
1719};
1720
1721union cvmx_agl_gmx_txx_stat0 {
1722 uint64_t u64;
1723 struct cvmx_agl_gmx_txx_stat0_s {
1724#ifdef __BIG_ENDIAN_BITFIELD
1725 uint64_t xsdef:32;
1726 uint64_t xscol:32;
1727#else
1728 uint64_t xscol:32;
1729 uint64_t xsdef:32;
1730#endif
1731 } s;
1732 struct cvmx_agl_gmx_txx_stat0_s cn52xx;
1733 struct cvmx_agl_gmx_txx_stat0_s cn52xxp1;
1734 struct cvmx_agl_gmx_txx_stat0_s cn56xx;
1735 struct cvmx_agl_gmx_txx_stat0_s cn56xxp1;
1736 struct cvmx_agl_gmx_txx_stat0_s cn61xx;
1737 struct cvmx_agl_gmx_txx_stat0_s cn63xx;
1738 struct cvmx_agl_gmx_txx_stat0_s cn63xxp1;
1739 struct cvmx_agl_gmx_txx_stat0_s cn66xx;
1740 struct cvmx_agl_gmx_txx_stat0_s cn68xx;
1741 struct cvmx_agl_gmx_txx_stat0_s cn68xxp1;
1742};
1743
1744union cvmx_agl_gmx_txx_stat1 {
1745 uint64_t u64;
1746 struct cvmx_agl_gmx_txx_stat1_s {
1747#ifdef __BIG_ENDIAN_BITFIELD
1748 uint64_t scol:32;
1749 uint64_t mcol:32;
1750#else
1751 uint64_t mcol:32;
1752 uint64_t scol:32;
1753#endif
1754 } s;
1755 struct cvmx_agl_gmx_txx_stat1_s cn52xx;
1756 struct cvmx_agl_gmx_txx_stat1_s cn52xxp1;
1757 struct cvmx_agl_gmx_txx_stat1_s cn56xx;
1758 struct cvmx_agl_gmx_txx_stat1_s cn56xxp1;
1759 struct cvmx_agl_gmx_txx_stat1_s cn61xx;
1760 struct cvmx_agl_gmx_txx_stat1_s cn63xx;
1761 struct cvmx_agl_gmx_txx_stat1_s cn63xxp1;
1762 struct cvmx_agl_gmx_txx_stat1_s cn66xx;
1763 struct cvmx_agl_gmx_txx_stat1_s cn68xx;
1764 struct cvmx_agl_gmx_txx_stat1_s cn68xxp1;
1765};
1766
1767union cvmx_agl_gmx_txx_stat2 {
1768 uint64_t u64;
1769 struct cvmx_agl_gmx_txx_stat2_s {
1770#ifdef __BIG_ENDIAN_BITFIELD
1771 uint64_t reserved_48_63:16;
1772 uint64_t octs:48;
1773#else
1774 uint64_t octs:48;
1775 uint64_t reserved_48_63:16;
1776#endif
1777 } s;
1778 struct cvmx_agl_gmx_txx_stat2_s cn52xx;
1779 struct cvmx_agl_gmx_txx_stat2_s cn52xxp1;
1780 struct cvmx_agl_gmx_txx_stat2_s cn56xx;
1781 struct cvmx_agl_gmx_txx_stat2_s cn56xxp1;
1782 struct cvmx_agl_gmx_txx_stat2_s cn61xx;
1783 struct cvmx_agl_gmx_txx_stat2_s cn63xx;
1784 struct cvmx_agl_gmx_txx_stat2_s cn63xxp1;
1785 struct cvmx_agl_gmx_txx_stat2_s cn66xx;
1786 struct cvmx_agl_gmx_txx_stat2_s cn68xx;
1787 struct cvmx_agl_gmx_txx_stat2_s cn68xxp1;
1788};
1789
1790union cvmx_agl_gmx_txx_stat3 {
1791 uint64_t u64;
1792 struct cvmx_agl_gmx_txx_stat3_s {
1793#ifdef __BIG_ENDIAN_BITFIELD
1794 uint64_t reserved_32_63:32;
1795 uint64_t pkts:32;
1796#else
1797 uint64_t pkts:32;
1798 uint64_t reserved_32_63:32;
1799#endif
1800 } s;
1801 struct cvmx_agl_gmx_txx_stat3_s cn52xx;
1802 struct cvmx_agl_gmx_txx_stat3_s cn52xxp1;
1803 struct cvmx_agl_gmx_txx_stat3_s cn56xx;
1804 struct cvmx_agl_gmx_txx_stat3_s cn56xxp1;
1805 struct cvmx_agl_gmx_txx_stat3_s cn61xx;
1806 struct cvmx_agl_gmx_txx_stat3_s cn63xx;
1807 struct cvmx_agl_gmx_txx_stat3_s cn63xxp1;
1808 struct cvmx_agl_gmx_txx_stat3_s cn66xx;
1809 struct cvmx_agl_gmx_txx_stat3_s cn68xx;
1810 struct cvmx_agl_gmx_txx_stat3_s cn68xxp1;
1811};
1812
1813union cvmx_agl_gmx_txx_stat4 {
1814 uint64_t u64;
1815 struct cvmx_agl_gmx_txx_stat4_s {
1816#ifdef __BIG_ENDIAN_BITFIELD
1817 uint64_t hist1:32;
1818 uint64_t hist0:32;
1819#else
1820 uint64_t hist0:32;
1821 uint64_t hist1:32;
1822#endif
1823 } s;
1824 struct cvmx_agl_gmx_txx_stat4_s cn52xx;
1825 struct cvmx_agl_gmx_txx_stat4_s cn52xxp1;
1826 struct cvmx_agl_gmx_txx_stat4_s cn56xx;
1827 struct cvmx_agl_gmx_txx_stat4_s cn56xxp1;
1828 struct cvmx_agl_gmx_txx_stat4_s cn61xx;
1829 struct cvmx_agl_gmx_txx_stat4_s cn63xx;
1830 struct cvmx_agl_gmx_txx_stat4_s cn63xxp1;
1831 struct cvmx_agl_gmx_txx_stat4_s cn66xx;
1832 struct cvmx_agl_gmx_txx_stat4_s cn68xx;
1833 struct cvmx_agl_gmx_txx_stat4_s cn68xxp1;
1834};
1835
1836union cvmx_agl_gmx_txx_stat5 {
1837 uint64_t u64;
1838 struct cvmx_agl_gmx_txx_stat5_s {
1839#ifdef __BIG_ENDIAN_BITFIELD
1840 uint64_t hist3:32;
1841 uint64_t hist2:32;
1842#else
1843 uint64_t hist2:32;
1844 uint64_t hist3:32;
1845#endif
1846 } s;
1847 struct cvmx_agl_gmx_txx_stat5_s cn52xx;
1848 struct cvmx_agl_gmx_txx_stat5_s cn52xxp1;
1849 struct cvmx_agl_gmx_txx_stat5_s cn56xx;
1850 struct cvmx_agl_gmx_txx_stat5_s cn56xxp1;
1851 struct cvmx_agl_gmx_txx_stat5_s cn61xx;
1852 struct cvmx_agl_gmx_txx_stat5_s cn63xx;
1853 struct cvmx_agl_gmx_txx_stat5_s cn63xxp1;
1854 struct cvmx_agl_gmx_txx_stat5_s cn66xx;
1855 struct cvmx_agl_gmx_txx_stat5_s cn68xx;
1856 struct cvmx_agl_gmx_txx_stat5_s cn68xxp1;
1857};
1858
1859union cvmx_agl_gmx_txx_stat6 {
1860 uint64_t u64;
1861 struct cvmx_agl_gmx_txx_stat6_s {
1862#ifdef __BIG_ENDIAN_BITFIELD
1863 uint64_t hist5:32;
1864 uint64_t hist4:32;
1865#else
1866 uint64_t hist4:32;
1867 uint64_t hist5:32;
1868#endif
1869 } s;
1870 struct cvmx_agl_gmx_txx_stat6_s cn52xx;
1871 struct cvmx_agl_gmx_txx_stat6_s cn52xxp1;
1872 struct cvmx_agl_gmx_txx_stat6_s cn56xx;
1873 struct cvmx_agl_gmx_txx_stat6_s cn56xxp1;
1874 struct cvmx_agl_gmx_txx_stat6_s cn61xx;
1875 struct cvmx_agl_gmx_txx_stat6_s cn63xx;
1876 struct cvmx_agl_gmx_txx_stat6_s cn63xxp1;
1877 struct cvmx_agl_gmx_txx_stat6_s cn66xx;
1878 struct cvmx_agl_gmx_txx_stat6_s cn68xx;
1879 struct cvmx_agl_gmx_txx_stat6_s cn68xxp1;
1880};
1881
1882union cvmx_agl_gmx_txx_stat7 {
1883 uint64_t u64;
1884 struct cvmx_agl_gmx_txx_stat7_s {
1885#ifdef __BIG_ENDIAN_BITFIELD
1886 uint64_t hist7:32;
1887 uint64_t hist6:32;
1888#else
1889 uint64_t hist6:32;
1890 uint64_t hist7:32;
1891#endif
1892 } s;
1893 struct cvmx_agl_gmx_txx_stat7_s cn52xx;
1894 struct cvmx_agl_gmx_txx_stat7_s cn52xxp1;
1895 struct cvmx_agl_gmx_txx_stat7_s cn56xx;
1896 struct cvmx_agl_gmx_txx_stat7_s cn56xxp1;
1897 struct cvmx_agl_gmx_txx_stat7_s cn61xx;
1898 struct cvmx_agl_gmx_txx_stat7_s cn63xx;
1899 struct cvmx_agl_gmx_txx_stat7_s cn63xxp1;
1900 struct cvmx_agl_gmx_txx_stat7_s cn66xx;
1901 struct cvmx_agl_gmx_txx_stat7_s cn68xx;
1902 struct cvmx_agl_gmx_txx_stat7_s cn68xxp1;
1903};
1904
1905union cvmx_agl_gmx_txx_stat8 {
1906 uint64_t u64;
1907 struct cvmx_agl_gmx_txx_stat8_s {
1908#ifdef __BIG_ENDIAN_BITFIELD
1909 uint64_t mcst:32;
1910 uint64_t bcst:32;
1911#else
1912 uint64_t bcst:32;
1913 uint64_t mcst:32;
1914#endif
1915 } s;
1916 struct cvmx_agl_gmx_txx_stat8_s cn52xx;
1917 struct cvmx_agl_gmx_txx_stat8_s cn52xxp1;
1918 struct cvmx_agl_gmx_txx_stat8_s cn56xx;
1919 struct cvmx_agl_gmx_txx_stat8_s cn56xxp1;
1920 struct cvmx_agl_gmx_txx_stat8_s cn61xx;
1921 struct cvmx_agl_gmx_txx_stat8_s cn63xx;
1922 struct cvmx_agl_gmx_txx_stat8_s cn63xxp1;
1923 struct cvmx_agl_gmx_txx_stat8_s cn66xx;
1924 struct cvmx_agl_gmx_txx_stat8_s cn68xx;
1925 struct cvmx_agl_gmx_txx_stat8_s cn68xxp1;
1926};
1927
1928union cvmx_agl_gmx_txx_stat9 {
1929 uint64_t u64;
1930 struct cvmx_agl_gmx_txx_stat9_s {
1931#ifdef __BIG_ENDIAN_BITFIELD
1932 uint64_t undflw:32;
1933 uint64_t ctl:32;
1934#else
1935 uint64_t ctl:32;
1936 uint64_t undflw:32;
1937#endif
1938 } s;
1939 struct cvmx_agl_gmx_txx_stat9_s cn52xx;
1940 struct cvmx_agl_gmx_txx_stat9_s cn52xxp1;
1941 struct cvmx_agl_gmx_txx_stat9_s cn56xx;
1942 struct cvmx_agl_gmx_txx_stat9_s cn56xxp1;
1943 struct cvmx_agl_gmx_txx_stat9_s cn61xx;
1944 struct cvmx_agl_gmx_txx_stat9_s cn63xx;
1945 struct cvmx_agl_gmx_txx_stat9_s cn63xxp1;
1946 struct cvmx_agl_gmx_txx_stat9_s cn66xx;
1947 struct cvmx_agl_gmx_txx_stat9_s cn68xx;
1948 struct cvmx_agl_gmx_txx_stat9_s cn68xxp1;
1949};
1950
1951union cvmx_agl_gmx_txx_stats_ctl {
1952 uint64_t u64;
1953 struct cvmx_agl_gmx_txx_stats_ctl_s {
1954#ifdef __BIG_ENDIAN_BITFIELD
1955 uint64_t reserved_1_63:63;
1956 uint64_t rd_clr:1;
1957#else
1958 uint64_t rd_clr:1;
1959 uint64_t reserved_1_63:63;
1960#endif
1961 } s;
1962 struct cvmx_agl_gmx_txx_stats_ctl_s cn52xx;
1963 struct cvmx_agl_gmx_txx_stats_ctl_s cn52xxp1;
1964 struct cvmx_agl_gmx_txx_stats_ctl_s cn56xx;
1965 struct cvmx_agl_gmx_txx_stats_ctl_s cn56xxp1;
1966 struct cvmx_agl_gmx_txx_stats_ctl_s cn61xx;
1967 struct cvmx_agl_gmx_txx_stats_ctl_s cn63xx;
1968 struct cvmx_agl_gmx_txx_stats_ctl_s cn63xxp1;
1969 struct cvmx_agl_gmx_txx_stats_ctl_s cn66xx;
1970 struct cvmx_agl_gmx_txx_stats_ctl_s cn68xx;
1971 struct cvmx_agl_gmx_txx_stats_ctl_s cn68xxp1;
1972};
1973
1974union cvmx_agl_gmx_txx_thresh {
1975 uint64_t u64;
1976 struct cvmx_agl_gmx_txx_thresh_s {
1977#ifdef __BIG_ENDIAN_BITFIELD
1978 uint64_t reserved_6_63:58;
1979 uint64_t cnt:6;
1980#else
1981 uint64_t cnt:6;
1982 uint64_t reserved_6_63:58;
1983#endif
1984 } s;
1985 struct cvmx_agl_gmx_txx_thresh_s cn52xx;
1986 struct cvmx_agl_gmx_txx_thresh_s cn52xxp1;
1987 struct cvmx_agl_gmx_txx_thresh_s cn56xx;
1988 struct cvmx_agl_gmx_txx_thresh_s cn56xxp1;
1989 struct cvmx_agl_gmx_txx_thresh_s cn61xx;
1990 struct cvmx_agl_gmx_txx_thresh_s cn63xx;
1991 struct cvmx_agl_gmx_txx_thresh_s cn63xxp1;
1992 struct cvmx_agl_gmx_txx_thresh_s cn66xx;
1993 struct cvmx_agl_gmx_txx_thresh_s cn68xx;
1994 struct cvmx_agl_gmx_txx_thresh_s cn68xxp1;
1995};
1996
1997union cvmx_agl_gmx_tx_bp {
1998 uint64_t u64;
1999 struct cvmx_agl_gmx_tx_bp_s {
2000#ifdef __BIG_ENDIAN_BITFIELD
2001 uint64_t reserved_2_63:62;
2002 uint64_t bp:2;
2003#else
2004 uint64_t bp:2;
2005 uint64_t reserved_2_63:62;
2006#endif
2007 } s;
2008 struct cvmx_agl_gmx_tx_bp_s cn52xx;
2009 struct cvmx_agl_gmx_tx_bp_s cn52xxp1;
2010 struct cvmx_agl_gmx_tx_bp_cn56xx {
2011#ifdef __BIG_ENDIAN_BITFIELD
2012 uint64_t reserved_1_63:63;
2013 uint64_t bp:1;
2014#else
2015 uint64_t bp:1;
2016 uint64_t reserved_1_63:63;
2017#endif
2018 } cn56xx;
2019 struct cvmx_agl_gmx_tx_bp_cn56xx cn56xxp1;
2020 struct cvmx_agl_gmx_tx_bp_s cn61xx;
2021 struct cvmx_agl_gmx_tx_bp_s cn63xx;
2022 struct cvmx_agl_gmx_tx_bp_s cn63xxp1;
2023 struct cvmx_agl_gmx_tx_bp_s cn66xx;
2024 struct cvmx_agl_gmx_tx_bp_s cn68xx;
2025 struct cvmx_agl_gmx_tx_bp_s cn68xxp1;
2026};
2027
2028union cvmx_agl_gmx_tx_col_attempt {
2029 uint64_t u64;
2030 struct cvmx_agl_gmx_tx_col_attempt_s {
2031#ifdef __BIG_ENDIAN_BITFIELD
2032 uint64_t reserved_5_63:59;
2033 uint64_t limit:5;
2034#else
2035 uint64_t limit:5;
2036 uint64_t reserved_5_63:59;
2037#endif
2038 } s;
2039 struct cvmx_agl_gmx_tx_col_attempt_s cn52xx;
2040 struct cvmx_agl_gmx_tx_col_attempt_s cn52xxp1;
2041 struct cvmx_agl_gmx_tx_col_attempt_s cn56xx;
2042 struct cvmx_agl_gmx_tx_col_attempt_s cn56xxp1;
2043 struct cvmx_agl_gmx_tx_col_attempt_s cn61xx;
2044 struct cvmx_agl_gmx_tx_col_attempt_s cn63xx;
2045 struct cvmx_agl_gmx_tx_col_attempt_s cn63xxp1;
2046 struct cvmx_agl_gmx_tx_col_attempt_s cn66xx;
2047 struct cvmx_agl_gmx_tx_col_attempt_s cn68xx;
2048 struct cvmx_agl_gmx_tx_col_attempt_s cn68xxp1;
2049};
2050
2051union cvmx_agl_gmx_tx_ifg {
2052 uint64_t u64;
2053 struct cvmx_agl_gmx_tx_ifg_s {
2054#ifdef __BIG_ENDIAN_BITFIELD
2055 uint64_t reserved_8_63:56;
2056 uint64_t ifg2:4;
2057 uint64_t ifg1:4;
2058#else
2059 uint64_t ifg1:4;
2060 uint64_t ifg2:4;
2061 uint64_t reserved_8_63:56;
2062#endif
2063 } s;
2064 struct cvmx_agl_gmx_tx_ifg_s cn52xx;
2065 struct cvmx_agl_gmx_tx_ifg_s cn52xxp1;
2066 struct cvmx_agl_gmx_tx_ifg_s cn56xx;
2067 struct cvmx_agl_gmx_tx_ifg_s cn56xxp1;
2068 struct cvmx_agl_gmx_tx_ifg_s cn61xx;
2069 struct cvmx_agl_gmx_tx_ifg_s cn63xx;
2070 struct cvmx_agl_gmx_tx_ifg_s cn63xxp1;
2071 struct cvmx_agl_gmx_tx_ifg_s cn66xx;
2072 struct cvmx_agl_gmx_tx_ifg_s cn68xx;
2073 struct cvmx_agl_gmx_tx_ifg_s cn68xxp1;
2074};
2075
2076union cvmx_agl_gmx_tx_int_en {
2077 uint64_t u64;
2078 struct cvmx_agl_gmx_tx_int_en_s {
2079#ifdef __BIG_ENDIAN_BITFIELD
2080 uint64_t reserved_22_63:42;
2081 uint64_t ptp_lost:2;
2082 uint64_t reserved_18_19:2;
2083 uint64_t late_col:2;
2084 uint64_t reserved_14_15:2;
2085 uint64_t xsdef:2;
2086 uint64_t reserved_10_11:2;
2087 uint64_t xscol:2;
2088 uint64_t reserved_4_7:4;
2089 uint64_t undflw:2;
2090 uint64_t reserved_1_1:1;
2091 uint64_t pko_nxa:1;
2092#else
2093 uint64_t pko_nxa:1;
2094 uint64_t reserved_1_1:1;
2095 uint64_t undflw:2;
2096 uint64_t reserved_4_7:4;
2097 uint64_t xscol:2;
2098 uint64_t reserved_10_11:2;
2099 uint64_t xsdef:2;
2100 uint64_t reserved_14_15:2;
2101 uint64_t late_col:2;
2102 uint64_t reserved_18_19:2;
2103 uint64_t ptp_lost:2;
2104 uint64_t reserved_22_63:42;
2105#endif
2106 } s;
2107 struct cvmx_agl_gmx_tx_int_en_cn52xx {
2108#ifdef __BIG_ENDIAN_BITFIELD
2109 uint64_t reserved_18_63:46;
2110 uint64_t late_col:2;
2111 uint64_t reserved_14_15:2;
2112 uint64_t xsdef:2;
2113 uint64_t reserved_10_11:2;
2114 uint64_t xscol:2;
2115 uint64_t reserved_4_7:4;
2116 uint64_t undflw:2;
2117 uint64_t reserved_1_1:1;
2118 uint64_t pko_nxa:1;
2119#else
2120 uint64_t pko_nxa:1;
2121 uint64_t reserved_1_1:1;
2122 uint64_t undflw:2;
2123 uint64_t reserved_4_7:4;
2124 uint64_t xscol:2;
2125 uint64_t reserved_10_11:2;
2126 uint64_t xsdef:2;
2127 uint64_t reserved_14_15:2;
2128 uint64_t late_col:2;
2129 uint64_t reserved_18_63:46;
2130#endif
2131 } cn52xx;
2132 struct cvmx_agl_gmx_tx_int_en_cn52xx cn52xxp1;
2133 struct cvmx_agl_gmx_tx_int_en_cn56xx {
2134#ifdef __BIG_ENDIAN_BITFIELD
2135 uint64_t reserved_17_63:47;
2136 uint64_t late_col:1;
2137 uint64_t reserved_13_15:3;
2138 uint64_t xsdef:1;
2139 uint64_t reserved_9_11:3;
2140 uint64_t xscol:1;
2141 uint64_t reserved_3_7:5;
2142 uint64_t undflw:1;
2143 uint64_t reserved_1_1:1;
2144 uint64_t pko_nxa:1;
2145#else
2146 uint64_t pko_nxa:1;
2147 uint64_t reserved_1_1:1;
2148 uint64_t undflw:1;
2149 uint64_t reserved_3_7:5;
2150 uint64_t xscol:1;
2151 uint64_t reserved_9_11:3;
2152 uint64_t xsdef:1;
2153 uint64_t reserved_13_15:3;
2154 uint64_t late_col:1;
2155 uint64_t reserved_17_63:47;
2156#endif
2157 } cn56xx;
2158 struct cvmx_agl_gmx_tx_int_en_cn56xx cn56xxp1;
2159 struct cvmx_agl_gmx_tx_int_en_s cn61xx;
2160 struct cvmx_agl_gmx_tx_int_en_s cn63xx;
2161 struct cvmx_agl_gmx_tx_int_en_s cn63xxp1;
2162 struct cvmx_agl_gmx_tx_int_en_s cn66xx;
2163 struct cvmx_agl_gmx_tx_int_en_s cn68xx;
2164 struct cvmx_agl_gmx_tx_int_en_s cn68xxp1;
2165};
2166
2167union cvmx_agl_gmx_tx_int_reg {
2168 uint64_t u64;
2169 struct cvmx_agl_gmx_tx_int_reg_s {
2170#ifdef __BIG_ENDIAN_BITFIELD
2171 uint64_t reserved_22_63:42;
2172 uint64_t ptp_lost:2;
2173 uint64_t reserved_18_19:2;
2174 uint64_t late_col:2;
2175 uint64_t reserved_14_15:2;
2176 uint64_t xsdef:2;
2177 uint64_t reserved_10_11:2;
2178 uint64_t xscol:2;
2179 uint64_t reserved_4_7:4;
2180 uint64_t undflw:2;
2181 uint64_t reserved_1_1:1;
2182 uint64_t pko_nxa:1;
2183#else
2184 uint64_t pko_nxa:1;
2185 uint64_t reserved_1_1:1;
2186 uint64_t undflw:2;
2187 uint64_t reserved_4_7:4;
2188 uint64_t xscol:2;
2189 uint64_t reserved_10_11:2;
2190 uint64_t xsdef:2;
2191 uint64_t reserved_14_15:2;
2192 uint64_t late_col:2;
2193 uint64_t reserved_18_19:2;
2194 uint64_t ptp_lost:2;
2195 uint64_t reserved_22_63:42;
2196#endif
2197 } s;
2198 struct cvmx_agl_gmx_tx_int_reg_cn52xx {
2199#ifdef __BIG_ENDIAN_BITFIELD
2200 uint64_t reserved_18_63:46;
2201 uint64_t late_col:2;
2202 uint64_t reserved_14_15:2;
2203 uint64_t xsdef:2;
2204 uint64_t reserved_10_11:2;
2205 uint64_t xscol:2;
2206 uint64_t reserved_4_7:4;
2207 uint64_t undflw:2;
2208 uint64_t reserved_1_1:1;
2209 uint64_t pko_nxa:1;
2210#else
2211 uint64_t pko_nxa:1;
2212 uint64_t reserved_1_1:1;
2213 uint64_t undflw:2;
2214 uint64_t reserved_4_7:4;
2215 uint64_t xscol:2;
2216 uint64_t reserved_10_11:2;
2217 uint64_t xsdef:2;
2218 uint64_t reserved_14_15:2;
2219 uint64_t late_col:2;
2220 uint64_t reserved_18_63:46;
2221#endif
2222 } cn52xx;
2223 struct cvmx_agl_gmx_tx_int_reg_cn52xx cn52xxp1;
2224 struct cvmx_agl_gmx_tx_int_reg_cn56xx {
2225#ifdef __BIG_ENDIAN_BITFIELD
2226 uint64_t reserved_17_63:47;
2227 uint64_t late_col:1;
2228 uint64_t reserved_13_15:3;
2229 uint64_t xsdef:1;
2230 uint64_t reserved_9_11:3;
2231 uint64_t xscol:1;
2232 uint64_t reserved_3_7:5;
2233 uint64_t undflw:1;
2234 uint64_t reserved_1_1:1;
2235 uint64_t pko_nxa:1;
2236#else
2237 uint64_t pko_nxa:1;
2238 uint64_t reserved_1_1:1;
2239 uint64_t undflw:1;
2240 uint64_t reserved_3_7:5;
2241 uint64_t xscol:1;
2242 uint64_t reserved_9_11:3;
2243 uint64_t xsdef:1;
2244 uint64_t reserved_13_15:3;
2245 uint64_t late_col:1;
2246 uint64_t reserved_17_63:47;
2247#endif
2248 } cn56xx;
2249 struct cvmx_agl_gmx_tx_int_reg_cn56xx cn56xxp1;
2250 struct cvmx_agl_gmx_tx_int_reg_s cn61xx;
2251 struct cvmx_agl_gmx_tx_int_reg_s cn63xx;
2252 struct cvmx_agl_gmx_tx_int_reg_s cn63xxp1;
2253 struct cvmx_agl_gmx_tx_int_reg_s cn66xx;
2254 struct cvmx_agl_gmx_tx_int_reg_s cn68xx;
2255 struct cvmx_agl_gmx_tx_int_reg_s cn68xxp1;
2256};
2257
2258union cvmx_agl_gmx_tx_jam {
2259 uint64_t u64;
2260 struct cvmx_agl_gmx_tx_jam_s {
2261#ifdef __BIG_ENDIAN_BITFIELD
2262 uint64_t reserved_8_63:56;
2263 uint64_t jam:8;
2264#else
2265 uint64_t jam:8;
2266 uint64_t reserved_8_63:56;
2267#endif
2268 } s;
2269 struct cvmx_agl_gmx_tx_jam_s cn52xx;
2270 struct cvmx_agl_gmx_tx_jam_s cn52xxp1;
2271 struct cvmx_agl_gmx_tx_jam_s cn56xx;
2272 struct cvmx_agl_gmx_tx_jam_s cn56xxp1;
2273 struct cvmx_agl_gmx_tx_jam_s cn61xx;
2274 struct cvmx_agl_gmx_tx_jam_s cn63xx;
2275 struct cvmx_agl_gmx_tx_jam_s cn63xxp1;
2276 struct cvmx_agl_gmx_tx_jam_s cn66xx;
2277 struct cvmx_agl_gmx_tx_jam_s cn68xx;
2278 struct cvmx_agl_gmx_tx_jam_s cn68xxp1;
2279};
2280
2281union cvmx_agl_gmx_tx_lfsr {
2282 uint64_t u64;
2283 struct cvmx_agl_gmx_tx_lfsr_s {
2284#ifdef __BIG_ENDIAN_BITFIELD
2285 uint64_t reserved_16_63:48;
2286 uint64_t lfsr:16;
2287#else
2288 uint64_t lfsr:16;
2289 uint64_t reserved_16_63:48;
2290#endif
2291 } s;
2292 struct cvmx_agl_gmx_tx_lfsr_s cn52xx;
2293 struct cvmx_agl_gmx_tx_lfsr_s cn52xxp1;
2294 struct cvmx_agl_gmx_tx_lfsr_s cn56xx;
2295 struct cvmx_agl_gmx_tx_lfsr_s cn56xxp1;
2296 struct cvmx_agl_gmx_tx_lfsr_s cn61xx;
2297 struct cvmx_agl_gmx_tx_lfsr_s cn63xx;
2298 struct cvmx_agl_gmx_tx_lfsr_s cn63xxp1;
2299 struct cvmx_agl_gmx_tx_lfsr_s cn66xx;
2300 struct cvmx_agl_gmx_tx_lfsr_s cn68xx;
2301 struct cvmx_agl_gmx_tx_lfsr_s cn68xxp1;
2302};
2303
2304union cvmx_agl_gmx_tx_ovr_bp {
2305 uint64_t u64;
2306 struct cvmx_agl_gmx_tx_ovr_bp_s {
2307#ifdef __BIG_ENDIAN_BITFIELD
2308 uint64_t reserved_10_63:54;
2309 uint64_t en:2;
2310 uint64_t reserved_6_7:2;
2311 uint64_t bp:2;
2312 uint64_t reserved_2_3:2;
2313 uint64_t ign_full:2;
2314#else
2315 uint64_t ign_full:2;
2316 uint64_t reserved_2_3:2;
2317 uint64_t bp:2;
2318 uint64_t reserved_6_7:2;
2319 uint64_t en:2;
2320 uint64_t reserved_10_63:54;
2321#endif
2322 } s;
2323 struct cvmx_agl_gmx_tx_ovr_bp_s cn52xx;
2324 struct cvmx_agl_gmx_tx_ovr_bp_s cn52xxp1;
2325 struct cvmx_agl_gmx_tx_ovr_bp_cn56xx {
2326#ifdef __BIG_ENDIAN_BITFIELD
2327 uint64_t reserved_9_63:55;
2328 uint64_t en:1;
2329 uint64_t reserved_5_7:3;
2330 uint64_t bp:1;
2331 uint64_t reserved_1_3:3;
2332 uint64_t ign_full:1;
2333#else
2334 uint64_t ign_full:1;
2335 uint64_t reserved_1_3:3;
2336 uint64_t bp:1;
2337 uint64_t reserved_5_7:3;
2338 uint64_t en:1;
2339 uint64_t reserved_9_63:55;
2340#endif
2341 } cn56xx;
2342 struct cvmx_agl_gmx_tx_ovr_bp_cn56xx cn56xxp1;
2343 struct cvmx_agl_gmx_tx_ovr_bp_s cn61xx;
2344 struct cvmx_agl_gmx_tx_ovr_bp_s cn63xx;
2345 struct cvmx_agl_gmx_tx_ovr_bp_s cn63xxp1;
2346 struct cvmx_agl_gmx_tx_ovr_bp_s cn66xx;
2347 struct cvmx_agl_gmx_tx_ovr_bp_s cn68xx;
2348 struct cvmx_agl_gmx_tx_ovr_bp_s cn68xxp1;
2349};
2350
2351union cvmx_agl_gmx_tx_pause_pkt_dmac {
2352 uint64_t u64;
2353 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s {
2354#ifdef __BIG_ENDIAN_BITFIELD
2355 uint64_t reserved_48_63:16;
2356 uint64_t dmac:48;
2357#else
2358 uint64_t dmac:48;
2359 uint64_t reserved_48_63:16;
2360#endif
2361 } s;
2362 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xx;
2363 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn52xxp1;
2364 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xx;
2365 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn56xxp1;
2366 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn61xx;
2367 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xx;
2368 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn63xxp1;
2369 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn66xx;
2370 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn68xx;
2371 struct cvmx_agl_gmx_tx_pause_pkt_dmac_s cn68xxp1;
2372};
2373
2374union cvmx_agl_gmx_tx_pause_pkt_type {
2375 uint64_t u64;
2376 struct cvmx_agl_gmx_tx_pause_pkt_type_s {
2377#ifdef __BIG_ENDIAN_BITFIELD
2378 uint64_t reserved_16_63:48;
2379 uint64_t type:16;
2380#else
2381 uint64_t type:16;
2382 uint64_t reserved_16_63:48;
2383#endif
2384 } s;
2385 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xx;
2386 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn52xxp1;
2387 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xx;
2388 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn56xxp1;
2389 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn61xx;
2390 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xx;
2391 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn63xxp1;
2392 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn66xx;
2393 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn68xx;
2394 struct cvmx_agl_gmx_tx_pause_pkt_type_s cn68xxp1;
2395};
2396
2397union cvmx_agl_prtx_ctl {
2398 uint64_t u64;
2399 struct cvmx_agl_prtx_ctl_s {
2400#ifdef __BIG_ENDIAN_BITFIELD
2401 uint64_t drv_byp:1;
2402 uint64_t reserved_62_62:1;
2403 uint64_t cmp_pctl:6;
2404 uint64_t reserved_54_55:2;
2405 uint64_t cmp_nctl:6;
2406 uint64_t reserved_46_47:2;
2407 uint64_t drv_pctl:6;
2408 uint64_t reserved_38_39:2;
2409 uint64_t drv_nctl:6;
2410 uint64_t reserved_29_31:3;
2411 uint64_t clk_set:5;
2412 uint64_t clkrx_byp:1;
2413 uint64_t reserved_21_22:2;
2414 uint64_t clkrx_set:5;
2415 uint64_t clktx_byp:1;
2416 uint64_t reserved_13_14:2;
2417 uint64_t clktx_set:5;
2418 uint64_t reserved_5_7:3;
2419 uint64_t dllrst:1;
2420 uint64_t comp:1;
2421 uint64_t enable:1;
2422 uint64_t clkrst:1;
2423 uint64_t mode:1;
2424#else
2425 uint64_t mode:1;
2426 uint64_t clkrst:1;
2427 uint64_t enable:1;
2428 uint64_t comp:1;
2429 uint64_t dllrst:1;
2430 uint64_t reserved_5_7:3;
2431 uint64_t clktx_set:5;
2432 uint64_t reserved_13_14:2;
2433 uint64_t clktx_byp:1;
2434 uint64_t clkrx_set:5;
2435 uint64_t reserved_21_22:2;
2436 uint64_t clkrx_byp:1;
2437 uint64_t clk_set:5;
2438 uint64_t reserved_29_31:3;
2439 uint64_t drv_nctl:6;
2440 uint64_t reserved_38_39:2;
2441 uint64_t drv_pctl:6;
2442 uint64_t reserved_46_47:2;
2443 uint64_t cmp_nctl:6;
2444 uint64_t reserved_54_55:2;
2445 uint64_t cmp_pctl:6;
2446 uint64_t reserved_62_62:1;
2447 uint64_t drv_byp:1;
2448#endif
2449 } s;
2450 struct cvmx_agl_prtx_ctl_s cn61xx;
2451 struct cvmx_agl_prtx_ctl_s cn63xx;
2452 struct cvmx_agl_prtx_ctl_s cn63xxp1;
2453 struct cvmx_agl_prtx_ctl_s cn66xx;
2454 struct cvmx_agl_prtx_ctl_s cn68xx;
2455 struct cvmx_agl_prtx_ctl_s cn68xxp1;
2456};
2457
2458#endif